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Linux 3.4.102
[linux/fpc-iii.git] / drivers / net / ethernet / 3com / 3c59x.c
blob5673d6e68da20a346a336888909b42c24db6db3e
1 /* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
2 /*
3 Written 1996-1999 by Donald Becker.
4
5 This software may be used and distributed according to the terms
6 of the GNU General Public License, incorporated herein by reference.
7
8 This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
9 Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
10 and the EtherLink XL 3c900 and 3c905 cards.
11
12 Problem reports and questions should be directed to
13 vortex@scyld.com
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
20 */
21
22 /*
23 * FIXME: This driver _could_ support MTU changing, but doesn't. See Don's hamachi.c implementation
24 * as well as other drivers
25 *
26 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
27 * due to dead code elimination. There will be some performance benefits from this due to
28 * elimination of all the tests and reduced cache footprint.
29 */
30
31
32 #define DRV_NAME "3c59x"
33
34
35
36 /* A few values that may be tweaked. */
37 /* Keep the ring sizes a power of two for efficiency. */
38 #define TX_RING_SIZE 16
39 #define RX_RING_SIZE 32
40 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
41
42 /* "Knobs" that adjust features and parameters. */
43 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
44 Setting to > 1512 effectively disables this feature. */
45 #ifndef __arm__
46 static int rx_copybreak = 200;
47 #else
48 /* ARM systems perform better by disregarding the bus-master
49 transfer capability of these cards. -- rmk */
50 static int rx_copybreak = 1513;
51 #endif
52 /* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
53 static const int mtu = 1500;
54 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55 static int max_interrupt_work = 32;
56 /* Tx timeout interval (millisecs) */
57 static int watchdog = 5000;
58
59 /* Allow aggregation of Tx interrupts. Saves CPU load at the cost
60 * of possible Tx stalls if the system is blocking interrupts
61 * somewhere else. Undefine this to disable.
62 */
63 #define tx_interrupt_mitigation 1
64
65 /* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
66 #define vortex_debug debug
67 #ifdef VORTEX_DEBUG
68 static int vortex_debug = VORTEX_DEBUG;
69 #else
70 static int vortex_debug = 1;
71 #endif
72
73 #include <linux/module.h>
74 #include <linux/kernel.h>
75 #include <linux/string.h>
76 #include <linux/timer.h>
77 #include <linux/errno.h>
78 #include <linux/in.h>
79 #include <linux/ioport.h>
80 #include <linux/interrupt.h>
81 #include <linux/pci.h>
82 #include <linux/mii.h>
83 #include <linux/init.h>
84 #include <linux/netdevice.h>
85 #include <linux/etherdevice.h>
86 #include <linux/skbuff.h>
87 #include <linux/ethtool.h>
88 #include <linux/highmem.h>
89 #include <linux/eisa.h>
90 #include <linux/bitops.h>
91 #include <linux/jiffies.h>
92 #include <linux/gfp.h>
93 #include <asm/irq.h> /* For nr_irqs only. */
94 #include <asm/io.h>
95 #include <asm/uaccess.h>
96
97 /* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
98 This is only in the support-all-kernels source code. */
99
100 #define RUN_AT(x) (jiffies + (x))
101
102 #include <linux/delay.h>
103
104
105 static const char version[] __devinitconst =
106 DRV_NAME ": Donald Becker and others.\n";
107
108 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
109 MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver ");
110 MODULE_LICENSE("GPL");
111
112
113 /* Operational parameter that usually are not changed. */
114
115 /* The Vortex size is twice that of the original EtherLinkIII series: the
116 runtime register window, window 1, is now always mapped in.
117 The Boomerang size is twice as large as the Vortex -- it has additional
118 bus master control registers. */
119 #define VORTEX_TOTAL_SIZE 0x20
120 #define BOOMERANG_TOTAL_SIZE 0x40
121
122 /* Set iff a MII transceiver on any interface requires mdio preamble.
123 This only set with the original DP83840 on older 3c905 boards, so the extra
124 code size of a per-interface flag is not worthwhile. */
125 static char mii_preamble_required;
126
127 #define PFX DRV_NAME ": "
128
129
130
131 /*
132 Theory of Operation
133
134 I. Board Compatibility
135
136 This device driver is designed for the 3Com FastEtherLink and FastEtherLink
137 XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs
138 versions of the FastEtherLink cards. The supported product IDs are
139 3c590, 3c592, 3c595, 3c597, 3c900, 3c905
140
141 The related ISA 3c515 is supported with a separate driver, 3c515.c, included
142 with the kernel source or available from
143 cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
144
145 II. Board-specific settings
146
147 PCI bus devices are configured by the system at boot time, so no jumpers
148 need to be set on the board. The system BIOS should be set to assign the
149 PCI INTA signal to an otherwise unused system IRQ line.
150
151 The EEPROM settings for media type and forced-full-duplex are observed.
152 The EEPROM media type should be left at the default "autoselect" unless using
153 10base2 or AUI connections which cannot be reliably detected.
154
155 III. Driver operation
156
157 The 3c59x series use an interface that's very similar to the previous 3c5x9
158 series. The primary interface is two programmed-I/O FIFOs, with an
159 alternate single-contiguous-region bus-master transfer (see next).
160
161 The 3c900 "Boomerang" series uses a full-bus-master interface with separate
162 lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
163 DEC Tulip and Intel Speedo3. The first chip version retains a compatible
164 programmed-I/O interface that has been removed in 'B' and subsequent board
165 revisions.
166
167 One extension that is advertised in a very large font is that the adapters
168 are capable of being bus masters. On the Vortex chip this capability was
169 only for a single contiguous region making it far less useful than the full
170 bus master capability. There is a significant performance impact of taking
171 an extra interrupt or polling for the completion of each transfer, as well
172 as difficulty sharing the single transfer engine between the transmit and
173 receive threads. Using DMA transfers is a win only with large blocks or
174 with the flawed versions of the Intel Orion motherboard PCI controller.
175
176 The Boomerang chip's full-bus-master interface is useful, and has the
177 currently-unused advantages over other similar chips that queued transmit
178 packets may be reordered and receive buffer groups are associated with a
179 single frame.
180
181 With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
182 Rather than a fixed intermediate receive buffer, this scheme allocates
183 full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as
184 the copying breakpoint: it is chosen to trade-off the memory wasted by
185 passing the full-sized skbuff to the queue layer for all frames vs. the
186 copying cost of copying a frame to a correctly-sized skbuff.
187
188 IIIC. Synchronization
189 The driver runs as two independent, single-threaded flows of control. One
190 is the send-packet routine, which enforces single-threaded use by the
191 dev->tbusy flag. The other thread is the interrupt handler, which is single
192 threaded by the hardware and other software.
193
194 IV. Notes
195
196 Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
197 3c590, 3c595, and 3c900 boards.
198 The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
199 the EISA version is called "Demon". According to Terry these names come
200 from rides at the local amusement park.
201
202 The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
203 This driver only supports ethernet packets because of the skbuff allocation
204 limit of 4K.
205 */
206
207 /* This table drives the PCI probe routines. It's mostly boilerplate in all
208 of the drivers, and will likely be provided by some future kernel.
209 */
210 enum pci_flags_bit {
211 PCI_USES_MASTER=4,
212 };
213
214 enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
215 EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
216 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
217 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
218 EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
219 EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
220
221 enum vortex_chips {
222 CH_3C590 = 0,
223 CH_3C592,
224 CH_3C597,
225 CH_3C595_1,
226 CH_3C595_2,
227
228 CH_3C595_3,
229 CH_3C900_1,
230 CH_3C900_2,
231 CH_3C900_3,
232 CH_3C900_4,
233
234 CH_3C900_5,
235 CH_3C900B_FL,
236 CH_3C905_1,
237 CH_3C905_2,
238 CH_3C905B_TX,
239 CH_3C905B_1,
240
241 CH_3C905B_2,
242 CH_3C905B_FX,
243 CH_3C905C,
244 CH_3C9202,
245 CH_3C980,
246 CH_3C9805,
247
248 CH_3CSOHO100_TX,
249 CH_3C555,
250 CH_3C556,
251 CH_3C556B,
252 CH_3C575,
253
254 CH_3C575_1,
255 CH_3CCFE575,
256 CH_3CCFE575CT,
257 CH_3CCFE656,
258 CH_3CCFEM656,
259
260 CH_3CCFEM656_1,
261 CH_3C450,
262 CH_3C920,
263 CH_3C982A,
264 CH_3C982B,
265
266 CH_905BT4,
267 CH_920B_EMB_WNM,
268 };
269
270
271 /* note: this array directly indexed by above enums, and MUST
272 * be kept in sync with both the enums above, and the PCI device
273 * table below
274 */
275 static struct vortex_chip_info {
276 const char *name;
277 int flags;
278 int drv_flags;
279 int io_size;
280 } vortex_info_tbl[] __devinitdata = {
281 {"3c590 Vortex 10Mbps",
282 PCI_USES_MASTER, IS_VORTEX, 32, },
283 {"3c592 EISA 10Mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
284 PCI_USES_MASTER, IS_VORTEX, 32, },
285 {"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
286 PCI_USES_MASTER, IS_VORTEX, 32, },
287 {"3c595 Vortex 100baseTx",
288 PCI_USES_MASTER, IS_VORTEX, 32, },
289 {"3c595 Vortex 100baseT4",
290 PCI_USES_MASTER, IS_VORTEX, 32, },
291
292 {"3c595 Vortex 100base-MII",
293 PCI_USES_MASTER, IS_VORTEX, 32, },
294 {"3c900 Boomerang 10baseT",
295 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
296 {"3c900 Boomerang 10Mbps Combo",
297 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
298 {"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */
299 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
300 {"3c900 Cyclone 10Mbps Combo",
301 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
302
303 {"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */
304 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
305 {"3c900B-FL Cyclone 10base-FL",
306 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
307 {"3c905 Boomerang 100baseTx",
308 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
309 {"3c905 Boomerang 100baseT4",
310 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
311 {"3C905B-TX Fast Etherlink XL PCI",
312 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
313 {"3c905B Cyclone 100baseTx",
314 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
315
316 {"3c905B Cyclone 10/100/BNC",
317 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
318 {"3c905B-FX Cyclone 100baseFx",
319 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
320 {"3c905C Tornado",
321 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
322 {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
323 PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
324 {"3c980 Cyclone",
325 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
326
327 {"3c980C Python-T",
328 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
329 {"3cSOHO100-TX Hurricane",
330 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
331 {"3c555 Laptop Hurricane",
332 PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
333 {"3c556 Laptop Tornado",
334 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
335 HAS_HWCKSM, 128, },
336 {"3c556B Laptop Hurricane",
337 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
338 WNO_XCVR_PWR|HAS_HWCKSM, 128, },
339
340 {"3c575 [Megahertz] 10/100 LAN CardBus",
341 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
342 {"3c575 Boomerang CardBus",
343 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
344 {"3CCFE575BT Cyclone CardBus",
345 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
346 INVERT_LED_PWR|HAS_HWCKSM, 128, },
347 {"3CCFE575CT Tornado CardBus",
348 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
349 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
350 {"3CCFE656 Cyclone CardBus",
351 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
352 INVERT_LED_PWR|HAS_HWCKSM, 128, },
353
354 {"3CCFEM656B Cyclone+Winmodem CardBus",
355 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
356 INVERT_LED_PWR|HAS_HWCKSM, 128, },
357 {"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */
358 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
359 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
360 {"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */
361 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
362 {"3c920 Tornado",
363 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
364 {"3c982 Hydra Dual Port A",
365 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
366
367 {"3c982 Hydra Dual Port B",
368 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
369 {"3c905B-T4",
370 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
371 {"3c920B-EMB-WNM Tornado",
372 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
373
374 {NULL,}, /* NULL terminated list. */
375 };
376
377
378 static DEFINE_PCI_DEVICE_TABLE(vortex_pci_tbl) = {
379 { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
380 { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
381 { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
382 { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
383 { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
384
385 { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
386 { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
387 { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
388 { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
389 { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
390
391 { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
392 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
393 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
394 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
395 { 0x10B7, 0x9054, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_TX },
396 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
397
398 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
399 { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
400 { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
401 { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
402 { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
403 { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
404
405 { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
406 { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
407 { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
408 { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
409 { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
410
411 { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
412 { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
413 { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
414 { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
415 { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
416
417 { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
418 { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
419 { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
420 { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
421 { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
422
423 { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
424 { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
425
426 {0,} /* 0 terminated list. */
427 };
428 MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
429
430
431 /* Operational definitions.
432 These are not used by other compilation units and thus are not
433 exported in a ".h" file.
434
435 First the windows. There are eight register windows, with the command
436 and status registers available in each.
437 */
438 #define EL3_CMD 0x0e
439 #define EL3_STATUS 0x0e
440
441 /* The top five bits written to EL3_CMD are a command, the lower
442 11 bits are the parameter, if applicable.
443 Note that 11 parameters bits was fine for ethernet, but the new chip
444 can handle FDDI length frames (~4500 octets) and now parameters count
445 32-bit 'Dwords' rather than octets. */
446
447 enum vortex_cmd {
448 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
449 RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
450 UpStall = 6<<11, UpUnstall = (6<<11)+1,
451 DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
452 RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
453 FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
454 SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
455 SetTxThreshold = 18<<11, SetTxStart = 19<<11,
456 StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
457 StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
458
459 /* The SetRxFilter command accepts the following classes: */
460 enum RxFilter {
461 RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
462
463 /* Bits in the general status register. */
464 enum vortex_status {
465 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
466 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
467 IntReq = 0x0040, StatsFull = 0x0080,
468 DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
469 DMAInProgress = 1<<11, /* DMA controller is still busy.*/
470 CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
471 };
472
473 /* Register window 1 offsets, the window used in normal operation.
474 On the Vortex this window is always mapped at offsets 0x10-0x1f. */
475 enum Window1 {
476 TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
477 RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
478 TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
479 };
480 enum Window0 {
481 Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
482 Wn0EepromData = 12, /* Window 0: EEPROM results register. */
483 IntrStatus=0x0E, /* Valid in all windows. */
484 };
485 enum Win0_EEPROM_bits {
486 EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
487 EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
488 EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
489 };
490 /* EEPROM locations. */
491 enum eeprom_offset {
492 PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
493 EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
494 NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
495 DriverTune=13, Checksum=15};
496
497 enum Window2 { /* Window 2. */
498 Wn2_ResetOptions=12,
499 };
500 enum Window3 { /* Window 3: MAC/config bits. */
501 Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,
502 };
503
504 #define BFEXT(value, offset, bitcount) \
505 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
506
507 #define BFINS(lhs, rhs, offset, bitcount) \
508 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
509 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
510
511 #define RAM_SIZE(v) BFEXT(v, 0, 3)
512 #define RAM_WIDTH(v) BFEXT(v, 3, 1)
513 #define RAM_SPEED(v) BFEXT(v, 4, 2)
514 #define ROM_SIZE(v) BFEXT(v, 6, 2)
515 #define RAM_SPLIT(v) BFEXT(v, 16, 2)
516 #define XCVR(v) BFEXT(v, 20, 4)
517 #define AUTOSELECT(v) BFEXT(v, 24, 1)
518
519 enum Window4 { /* Window 4: Xcvr/media bits. */
520 Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
521 };
522 enum Win4_Media_bits {
523 Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
524 Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
525 Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
526 Media_LnkBeat = 0x0800,
527 };
528 enum Window7 { /* Window 7: Bus Master control. */
529 Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,
530 Wn7_MasterStatus = 12,
531 };
532 /* Boomerang bus master control registers. */
533 enum MasterCtrl {
534 PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
535 TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
536 };
537
538 /* The Rx and Tx descriptor lists.
539 Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
540 alignment contraint on tx_ring[] and rx_ring[]. */
541 #define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
542 #define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
543 struct boom_rx_desc {
544 __le32 next; /* Last entry points to 0. */
545 __le32 status;
546 __le32 addr; /* Up to 63 addr/len pairs possible. */
547 __le32 length; /* Set LAST_FRAG to indicate last pair. */
548 };
549 /* Values for the Rx status entry. */
550 enum rx_desc_status {
551 RxDComplete=0x00008000, RxDError=0x4000,
552 /* See boomerang_rx() for actual error bits */
553 IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
554 IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
555 };
556
557 #ifdef MAX_SKB_FRAGS
558 #define DO_ZEROCOPY 1
559 #else
560 #define DO_ZEROCOPY 0
561 #endif
562
563 struct boom_tx_desc {
564 __le32 next; /* Last entry points to 0. */
565 __le32 status; /* bits 0:12 length, others see below. */
566 #if DO_ZEROCOPY
567 struct {
568 __le32 addr;
569 __le32 length;
570 } frag[1+MAX_SKB_FRAGS];
571 #else
572 __le32 addr;
573 __le32 length;
574 #endif
575 };
576
577 /* Values for the Tx status entry. */
578 enum tx_desc_status {
579 CRCDisable=0x2000, TxDComplete=0x8000,
580 AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
581 TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
582 };
583
584 /* Chip features we care about in vp->capabilities, read from the EEPROM. */
585 enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
586
587 struct vortex_extra_stats {
588 unsigned long tx_deferred;
589 unsigned long tx_max_collisions;
590 unsigned long tx_multiple_collisions;
591 unsigned long tx_single_collisions;
592 unsigned long rx_bad_ssd;
593 };
594
595 struct vortex_private {
596 /* The Rx and Tx rings should be quad-word-aligned. */
597 struct boom_rx_desc* rx_ring;
598 struct boom_tx_desc* tx_ring;
599 dma_addr_t rx_ring_dma;
600 dma_addr_t tx_ring_dma;
601 /* The addresses of transmit- and receive-in-place skbuffs. */
602 struct sk_buff* rx_skbuff[RX_RING_SIZE];
603 struct sk_buff* tx_skbuff[TX_RING_SIZE];
604 unsigned int cur_rx, cur_tx; /* The next free ring entry */
605 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
606 struct vortex_extra_stats xstats; /* NIC-specific extra stats */
607 struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
608 dma_addr_t tx_skb_dma; /* Allocated DMA address for bus master ctrl DMA. */
609
610 /* PCI configuration space information. */
611 struct device *gendev;
612 void __iomem *ioaddr; /* IO address space */
613 void __iomem *cb_fn_base; /* CardBus function status addr space. */
614
615 /* Some values here only for performance evaluation and path-coverage */
616 int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
617 int card_idx;
618
619 /* The remainder are related to chip state, mostly media selection. */
620 struct timer_list timer; /* Media selection timer. */
621 struct timer_list rx_oom_timer; /* Rx skb allocation retry timer */
622 int options; /* User-settable misc. driver options. */
623 unsigned int media_override:4, /* Passed-in media type. */
624 default_media:4, /* Read from the EEPROM/Wn3_Config. */
625 full_duplex:1, autoselect:1,
626 bus_master:1, /* Vortex can only do a fragment bus-m. */
627 full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */
628 flow_ctrl:1, /* Use 802.3x flow control (PAUSE only) */
629 partner_flow_ctrl:1, /* Partner supports flow control */
630 has_nway:1,
631 enable_wol:1, /* Wake-on-LAN is enabled */
632 pm_state_valid:1, /* pci_dev->saved_config_space has sane contents */
633 open:1,
634 medialock:1,
635 large_frames:1, /* accept large frames */
636 handling_irq:1; /* private in_irq indicator */
637 /* {get|set}_wol operations are already serialized by rtnl.
638 * no additional locking is required for the enable_wol and acpi_set_WOL()
639 */
640 int drv_flags;
641 u16 status_enable;
642 u16 intr_enable;
643 u16 available_media; /* From Wn3_Options. */
644 u16 capabilities, info1, info2; /* Various, from EEPROM. */
645 u16 advertising; /* NWay media advertisement */
646 unsigned char phys[2]; /* MII device addresses. */
647 u16 deferred; /* Resend these interrupts when we
648 * bale from the ISR */
649 u16 io_size; /* Size of PCI region (for release_region) */
650
651 /* Serialises access to hardware other than MII and variables below.
652 * The lock hierarchy is rtnl_lock > {lock, mii_lock} > window_lock. */
653 spinlock_t lock;
654
655 spinlock_t mii_lock; /* Serialises access to MII */
656 struct mii_if_info mii; /* MII lib hooks/info */
657 spinlock_t window_lock; /* Serialises access to windowed regs */
658 int window; /* Register window */
659 };
660
661 static void window_set(struct vortex_private *vp, int window)
662 {
663 if (window != vp->window) {
664 iowrite16(SelectWindow + window, vp->ioaddr + EL3_CMD);
665 vp->window = window;
666 }
667 }
668
669 #define DEFINE_WINDOW_IO(size) \
670 static u ## size \
671 window_read ## size(struct vortex_private *vp, int window, int addr) \
672 { \
673 unsigned long flags; \
674 u ## size ret; \
675 spin_lock_irqsave(&vp->window_lock, flags); \
676 window_set(vp, window); \
677 ret = ioread ## size(vp->ioaddr + addr); \
678 spin_unlock_irqrestore(&vp->window_lock, flags); \
679 return ret; \
680 } \
681 static void \
682 window_write ## size(struct vortex_private *vp, u ## size value, \
683 int window, int addr) \
684 { \
685 unsigned long flags; \
686 spin_lock_irqsave(&vp->window_lock, flags); \
687 window_set(vp, window); \
688 iowrite ## size(value, vp->ioaddr + addr); \
689 spin_unlock_irqrestore(&vp->window_lock, flags); \
690 }
691 DEFINE_WINDOW_IO(8)
692 DEFINE_WINDOW_IO(16)
693 DEFINE_WINDOW_IO(32)
694
695 #ifdef CONFIG_PCI
696 #define DEVICE_PCI(dev) (((dev)->bus == &pci_bus_type) ? to_pci_dev((dev)) : NULL)
697 #else
698 #define DEVICE_PCI(dev) NULL
699 #endif
700
701 #define VORTEX_PCI(vp) \
702 ((struct pci_dev *) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL))
703
704 #ifdef CONFIG_EISA
705 #define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
706 #else
707 #define DEVICE_EISA(dev) NULL
708 #endif
709
710 #define VORTEX_EISA(vp) \
711 ((struct eisa_device *) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL))
712
713 /* The action to take with a media selection timer tick.
714 Note that we deviate from the 3Com order by checking 10base2 before AUI.
715 */
716 enum xcvr_types {
717 XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
718 XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
719 };
720
721 static const struct media_table {
722 char *name;
723 unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
724 mask:8, /* The transceiver-present bit in Wn3_Config.*/
725 next:8; /* The media type to try next. */
726 int wait; /* Time before we check media status. */
727 } media_tbl[] = {
728 { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
729 { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
730 { "undefined", 0, 0x80, XCVR_10baseT, 10000},
731 { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
732 { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
733 { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
734 { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
735 { "undefined", 0, 0x01, XCVR_10baseT, 10000},
736 { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
737 { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
738 { "Default", 0, 0xFF, XCVR_10baseT, 10000},
739 };
740
741 static struct {
742 const char str[ETH_GSTRING_LEN];
743 } ethtool_stats_keys[] = {
744 { "tx_deferred" },
745 { "tx_max_collisions" },
746 { "tx_multiple_collisions" },
747 { "tx_single_collisions" },
748 { "rx_bad_ssd" },
749 };
750
751 /* number of ETHTOOL_GSTATS u64's */
752 #define VORTEX_NUM_STATS 5
753
754 static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
755 int chip_idx, int card_idx);
756 static int vortex_up(struct net_device *dev);
757 static void vortex_down(struct net_device *dev, int final);
758 static int vortex_open(struct net_device *dev);
759 static void mdio_sync(struct vortex_private *vp, int bits);
760 static int mdio_read(struct net_device *dev, int phy_id, int location);
761 static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
762 static void vortex_timer(unsigned long arg);
763 static void rx_oom_timer(unsigned long arg);
764 static netdev_tx_t vortex_start_xmit(struct sk_buff *skb,
765 struct net_device *dev);
766 static netdev_tx_t boomerang_start_xmit(struct sk_buff *skb,
767 struct net_device *dev);
768 static int vortex_rx(struct net_device *dev);
769 static int boomerang_rx(struct net_device *dev);
770 static irqreturn_t vortex_interrupt(int irq, void *dev_id);
771 static irqreturn_t boomerang_interrupt(int irq, void *dev_id);
772 static int vortex_close(struct net_device *dev);
773 static void dump_tx_ring(struct net_device *dev);
774 static void update_stats(void __iomem *ioaddr, struct net_device *dev);
775 static struct net_device_stats *vortex_get_stats(struct net_device *dev);
776 static void set_rx_mode(struct net_device *dev);
777 #ifdef CONFIG_PCI
778 static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
779 #endif
780 static void vortex_tx_timeout(struct net_device *dev);
781 static void acpi_set_WOL(struct net_device *dev);
782 static const struct ethtool_ops vortex_ethtool_ops;
783 static void set_8021q_mode(struct net_device *dev, int enable);
784
785 /* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
786 /* Option count limit only -- unlimited interfaces are supported. */
787 #define MAX_UNITS 8
788 static int options[MAX_UNITS] = { [0 ... MAX_UNITS-1] = -1 };
789 static int full_duplex[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
790 static int hw_checksums[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
791 static int flow_ctrl[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
792 static int enable_wol[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
793 static int use_mmio[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
794 static int global_options = -1;
795 static int global_full_duplex = -1;
796 static int global_enable_wol = -1;
797 static int global_use_mmio = -1;
798
799 /* Variables to work-around the Compaq PCI BIOS32 problem. */
800 static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
801 static struct net_device *compaq_net_device;
802
803 static int vortex_cards_found;
804
805 module_param(debug, int, 0);
806 module_param(global_options, int, 0);
807 module_param_array(options, int, NULL, 0);
808 module_param(global_full_duplex, int, 0);
809 module_param_array(full_duplex, int, NULL, 0);
810 module_param_array(hw_checksums, int, NULL, 0);
811 module_param_array(flow_ctrl, int, NULL, 0);
812 module_param(global_enable_wol, int, 0);
813 module_param_array(enable_wol, int, NULL, 0);
814 module_param(rx_copybreak, int, 0);
815 module_param(max_interrupt_work, int, 0);
816 module_param(compaq_ioaddr, int, 0);
817 module_param(compaq_irq, int, 0);
818 module_param(compaq_device_id, int, 0);
819 module_param(watchdog, int, 0);
820 module_param(global_use_mmio, int, 0);
821 module_param_array(use_mmio, int, NULL, 0);
822 MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
823 MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
824 MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
825 MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
826 MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if full_duplex is unset");
827 MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
828 MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
829 MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
830 MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if enable_wol is unset");
831 MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
832 MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
833 MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
834 MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
835 MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
836 MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
837 MODULE_PARM_DESC(global_use_mmio, "3c59x: same as use_mmio, but applies to all NICs if options is unset");
838 MODULE_PARM_DESC(use_mmio, "3c59x: use memory-mapped PCI I/O resource (0-1)");
839
840 #ifdef CONFIG_NET_POLL_CONTROLLER
841 static void poll_vortex(struct net_device *dev)
842 {
843 struct vortex_private *vp = netdev_priv(dev);
844 unsigned long flags;
845 local_irq_save(flags);
846 (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev);
847 local_irq_restore(flags);
848 }
849 #endif
850
851 #ifdef CONFIG_PM
852
853 static int vortex_suspend(struct device *dev)
854 {
855 struct pci_dev *pdev = to_pci_dev(dev);
856 struct net_device *ndev = pci_get_drvdata(pdev);
857
858 if (!ndev || !netif_running(ndev))
859 return 0;
860
861 netif_device_detach(ndev);
862 vortex_down(ndev, 1);
863
864 return 0;
865 }
866
867 static int vortex_resume(struct device *dev)
868 {
869 struct pci_dev *pdev = to_pci_dev(dev);
870 struct net_device *ndev = pci_get_drvdata(pdev);
871 int err;
872
873 if (!ndev || !netif_running(ndev))
874 return 0;
875
876 err = vortex_up(ndev);
877 if (err)
878 return err;
879
880 netif_device_attach(ndev);
881
882 return 0;
883 }
884
885 static const struct dev_pm_ops vortex_pm_ops = {
886 .suspend = vortex_suspend,
887 .resume = vortex_resume,
888 .freeze = vortex_suspend,
889 .thaw = vortex_resume,
890 .poweroff = vortex_suspend,
891 .restore = vortex_resume,
892 };
893
894 #define VORTEX_PM_OPS (&vortex_pm_ops)
895
896 #else /* !CONFIG_PM */
897
898 #define VORTEX_PM_OPS NULL
899
900 #endif /* !CONFIG_PM */
901
902 #ifdef CONFIG_EISA
903 static struct eisa_device_id vortex_eisa_ids[] = {
904 { "TCM5920", CH_3C592 },
905 { "TCM5970", CH_3C597 },
906 { "" }
907 };
908 MODULE_DEVICE_TABLE(eisa, vortex_eisa_ids);
909
910 static int __init vortex_eisa_probe(struct device *device)
911 {
912 void __iomem *ioaddr;
913 struct eisa_device *edev;
914
915 edev = to_eisa_device(device);
916
917 if (!request_region(edev->base_addr, VORTEX_TOTAL_SIZE, DRV_NAME))
918 return -EBUSY;
919
920 ioaddr = ioport_map(edev->base_addr, VORTEX_TOTAL_SIZE);
921
922 if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12,
923 edev->id.driver_data, vortex_cards_found)) {
924 release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
925 return -ENODEV;
926 }
927
928 vortex_cards_found++;
929
930 return 0;
931 }
932
933 static int __devexit vortex_eisa_remove(struct device *device)
934 {
935 struct eisa_device *edev;
936 struct net_device *dev;
937 struct vortex_private *vp;
938 void __iomem *ioaddr;
939
940 edev = to_eisa_device(device);
941 dev = eisa_get_drvdata(edev);
942
943 if (!dev) {
944 pr_err("vortex_eisa_remove called for Compaq device!\n");
945 BUG();
946 }
947
948 vp = netdev_priv(dev);
949 ioaddr = vp->ioaddr;
950
951 unregister_netdev(dev);
952 iowrite16(TotalReset|0x14, ioaddr + EL3_CMD);
953 release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
954
955 free_netdev(dev);
956 return 0;
957 }
958
959 static struct eisa_driver vortex_eisa_driver = {
960 .id_table = vortex_eisa_ids,
961 .driver = {
962 .name = "3c59x",
963 .probe = vortex_eisa_probe,
964 .remove = __devexit_p(vortex_eisa_remove)
965 }
966 };
967
968 #endif /* CONFIG_EISA */
969
970 /* returns count found (>= 0), or negative on error */
971 static int __init vortex_eisa_init(void)
972 {
973 int eisa_found = 0;
974 int orig_cards_found = vortex_cards_found;
975
976 #ifdef CONFIG_EISA
977 int err;
978
979 err = eisa_driver_register (&vortex_eisa_driver);
980 if (!err) {
981 /*
982 * Because of the way EISA bus is probed, we cannot assume
983 * any device have been found when we exit from
984 * eisa_driver_register (the bus root driver may not be
985 * initialized yet). So we blindly assume something was
986 * found, and let the sysfs magic happened...
987 */
988 eisa_found = 1;
989 }
990 #endif
991
992 /* Special code to work-around the Compaq PCI BIOS32 problem. */
993 if (compaq_ioaddr) {
994 vortex_probe1(NULL, ioport_map(compaq_ioaddr, VORTEX_TOTAL_SIZE),
995 compaq_irq, compaq_device_id, vortex_cards_found++);
996 }
997
998 return vortex_cards_found - orig_cards_found + eisa_found;
999 }
1000
1001 /* returns count (>= 0), or negative on error */
1002 static int __devinit vortex_init_one(struct pci_dev *pdev,
1003 const struct pci_device_id *ent)
1004 {
1005 int rc, unit, pci_bar;
1006 struct vortex_chip_info *vci;
1007 void __iomem *ioaddr;
1008
1009 /* wake up and enable device */
1010 rc = pci_enable_device(pdev);
1011 if (rc < 0)
1012 goto out;
1013
1014 rc = pci_request_regions(pdev, DRV_NAME);
1015 if (rc < 0) {
1016 pci_disable_device(pdev);
1017 goto out;
1018 }
1019
1020 unit = vortex_cards_found;
1021
1022 if (global_use_mmio < 0 && (unit >= MAX_UNITS || use_mmio[unit] < 0)) {
1023 /* Determine the default if the user didn't override us */
1024 vci = &vortex_info_tbl[ent->driver_data];
1025 pci_bar = vci->drv_flags & (IS_CYCLONE | IS_TORNADO) ? 1 : 0;
1026 } else if (unit < MAX_UNITS && use_mmio[unit] >= 0)
1027 pci_bar = use_mmio[unit] ? 1 : 0;
1028 else
1029 pci_bar = global_use_mmio ? 1 : 0;
1030
1031 ioaddr = pci_iomap(pdev, pci_bar, 0);
1032 if (!ioaddr) /* If mapping fails, fall-back to BAR 0... */
1033 ioaddr = pci_iomap(pdev, 0, 0);
1034 if (!ioaddr) {
1035 pci_release_regions(pdev);
1036 pci_disable_device(pdev);
1037 rc = -ENOMEM;
1038 goto out;
1039 }
1040
1041 rc = vortex_probe1(&pdev->dev, ioaddr, pdev->irq,
1042 ent->driver_data, unit);
1043 if (rc < 0) {
1044 pci_iounmap(pdev, ioaddr);
1045 pci_release_regions(pdev);
1046 pci_disable_device(pdev);
1047 goto out;
1048 }
1049
1050 vortex_cards_found++;
1051
1052 out:
1053 return rc;
1054 }
1055
1056 static const struct net_device_ops boomrang_netdev_ops = {
1057 .ndo_open = vortex_open,
1058 .ndo_stop = vortex_close,
1059 .ndo_start_xmit = boomerang_start_xmit,
1060 .ndo_tx_timeout = vortex_tx_timeout,
1061 .ndo_get_stats = vortex_get_stats,
1062 #ifdef CONFIG_PCI
1063 .ndo_do_ioctl = vortex_ioctl,
1064 #endif
1065 .ndo_set_rx_mode = set_rx_mode,
1066 .ndo_change_mtu = eth_change_mtu,
1067 .ndo_set_mac_address = eth_mac_addr,
1068 .ndo_validate_addr = eth_validate_addr,
1069 #ifdef CONFIG_NET_POLL_CONTROLLER
1070 .ndo_poll_controller = poll_vortex,
1071 #endif
1072 };
1073
1074 static const struct net_device_ops vortex_netdev_ops = {
1075 .ndo_open = vortex_open,
1076 .ndo_stop = vortex_close,
1077 .ndo_start_xmit = vortex_start_xmit,
1078 .ndo_tx_timeout = vortex_tx_timeout,
1079 .ndo_get_stats = vortex_get_stats,
1080 #ifdef CONFIG_PCI
1081 .ndo_do_ioctl = vortex_ioctl,
1082 #endif
1083 .ndo_set_rx_mode = set_rx_mode,
1084 .ndo_change_mtu = eth_change_mtu,
1085 .ndo_set_mac_address = eth_mac_addr,
1086 .ndo_validate_addr = eth_validate_addr,
1087 #ifdef CONFIG_NET_POLL_CONTROLLER
1088 .ndo_poll_controller = poll_vortex,
1089 #endif
1090 };
1091
1092 /*
1093 * Start up the PCI/EISA device which is described by *gendev.
1094 * Return 0 on success.
1095 *
1096 * NOTE: pdev can be NULL, for the case of a Compaq device
1097 */
1098 static int __devinit vortex_probe1(struct device *gendev,
1099 void __iomem *ioaddr, int irq,
1100 int chip_idx, int card_idx)
1101 {
1102 struct vortex_private *vp;
1103 int option;
1104 unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
1105 int i, step;
1106 struct net_device *dev;
1107 static int printed_version;
1108 int retval, print_info;
1109 struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
1110 const char *print_name = "3c59x";
1111 struct pci_dev *pdev = NULL;
1112 struct eisa_device *edev = NULL;
1113
1114 if (!printed_version) {
1115 pr_info("%s", version);
1116 printed_version = 1;
1117 }
1118
1119 if (gendev) {
1120 if ((pdev = DEVICE_PCI(gendev))) {
1121 print_name = pci_name(pdev);
1122 }
1123
1124 if ((edev = DEVICE_EISA(gendev))) {
1125 print_name = dev_name(&edev->dev);
1126 }
1127 }
1128
1129 dev = alloc_etherdev(sizeof(*vp));
1130 retval = -ENOMEM;
1131 if (!dev)
1132 goto out;
1133
1134 SET_NETDEV_DEV(dev, gendev);
1135 vp = netdev_priv(dev);
1136
1137 option = global_options;
1138
1139 /* The lower four bits are the media type. */
1140 if (dev->mem_start) {
1141 /*
1142 * The 'options' param is passed in as the third arg to the
1143 * LILO 'ether=' argument for non-modular use
1144 */
1145 option = dev->mem_start;
1146 }
1147 else if (card_idx < MAX_UNITS) {
1148 if (options[card_idx] >= 0)
1149 option = options[card_idx];
1150 }
1151
1152 if (option > 0) {
1153 if (option & 0x8000)
1154 vortex_debug = 7;
1155 if (option & 0x4000)
1156 vortex_debug = 2;
1157 if (option & 0x0400)
1158 vp->enable_wol = 1;
1159 }
1160
1161 print_info = (vortex_debug > 1);
1162 if (print_info)
1163 pr_info("See Documentation/networking/vortex.txt\n");
1164
1165 pr_info("%s: 3Com %s %s at %p.\n",
1166 print_name,
1167 pdev ? "PCI" : "EISA",
1168 vci->name,
1169 ioaddr);
1170
1171 dev->base_addr = (unsigned long)ioaddr;
1172 dev->irq = irq;
1173 dev->mtu = mtu;
1174 vp->ioaddr = ioaddr;
1175 vp->large_frames = mtu > 1500;
1176 vp->drv_flags = vci->drv_flags;
1177 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1178 vp->io_size = vci->io_size;
1179 vp->card_idx = card_idx;
1180 vp->window = -1;
1181
1182 /* module list only for Compaq device */
1183 if (gendev == NULL) {
1184 compaq_net_device = dev;
1185 }
1186
1187 /* PCI-only startup logic */
1188 if (pdev) {
1189 /* enable bus-mastering if necessary */
1190 if (vci->flags & PCI_USES_MASTER)
1191 pci_set_master(pdev);
1192
1193 if (vci->drv_flags & IS_VORTEX) {
1194 u8 pci_latency;
1195 u8 new_latency = 248;
1196
1197 /* Check the PCI latency value. On the 3c590 series the latency timer
1198 must be set to the maximum value to avoid data corruption that occurs
1199 when the timer expires during a transfer. This bug exists the Vortex
1200 chip only. */
1201 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
1202 if (pci_latency < new_latency) {
1203 pr_info("%s: Overriding PCI latency timer (CFLT) setting of %d, new value is %d.\n",
1204 print_name, pci_latency, new_latency);
1205 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
1206 }
1207 }
1208 }
1209
1210 spin_lock_init(&vp->lock);
1211 spin_lock_init(&vp->mii_lock);
1212 spin_lock_init(&vp->window_lock);
1213 vp->gendev = gendev;
1214 vp->mii.dev = dev;
1215 vp->mii.mdio_read = mdio_read;
1216 vp->mii.mdio_write = mdio_write;
1217 vp->mii.phy_id_mask = 0x1f;
1218 vp->mii.reg_num_mask = 0x1f;
1219
1220 /* Makes sure rings are at least 16 byte aligned. */
1221 vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1222 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1223 &vp->rx_ring_dma);
1224 retval = -ENOMEM;
1225 if (!vp->rx_ring)
1226 goto free_device;
1227
1228 vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1229 vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1230
1231 /* if we are a PCI driver, we store info in pdev->driver_data
1232 * instead of a module list */
1233 if (pdev)
1234 pci_set_drvdata(pdev, dev);
1235 if (edev)
1236 eisa_set_drvdata(edev, dev);
1237
1238 vp->media_override = 7;
1239 if (option >= 0) {
1240 vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
1241 if (vp->media_override != 7)
1242 vp->medialock = 1;
1243 vp->full_duplex = (option & 0x200) ? 1 : 0;
1244 vp->bus_master = (option & 16) ? 1 : 0;
1245 }
1246
1247 if (global_full_duplex > 0)
1248 vp->full_duplex = 1;
1249 if (global_enable_wol > 0)
1250 vp->enable_wol = 1;
1251
1252 if (card_idx < MAX_UNITS) {
1253 if (full_duplex[card_idx] > 0)
1254 vp->full_duplex = 1;
1255 if (flow_ctrl[card_idx] > 0)
1256 vp->flow_ctrl = 1;
1257 if (enable_wol[card_idx] > 0)
1258 vp->enable_wol = 1;
1259 }
1260
1261 vp->mii.force_media = vp->full_duplex;
1262 vp->options = option;
1263 /* Read the station address from the EEPROM. */
1264 {
1265 int base;
1266
1267 if (vci->drv_flags & EEPROM_8BIT)
1268 base = 0x230;
1269 else if (vci->drv_flags & EEPROM_OFFSET)
1270 base = EEPROM_Read + 0x30;
1271 else
1272 base = EEPROM_Read;
1273
1274 for (i = 0; i < 0x40; i++) {
1275 int timer;
1276 window_write16(vp, base + i, 0, Wn0EepromCmd);
1277 /* Pause for at least 162 us. for the read to take place. */
1278 for (timer = 10; timer >= 0; timer--) {
1279 udelay(162);
1280 if ((window_read16(vp, 0, Wn0EepromCmd) &
1281 0x8000) == 0)
1282 break;
1283 }
1284 eeprom[i] = window_read16(vp, 0, Wn0EepromData);
1285 }
1286 }
1287 for (i = 0; i < 0x18; i++)
1288 checksum ^= eeprom[i];
1289 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1290 if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */
1291 while (i < 0x21)
1292 checksum ^= eeprom[i++];
1293 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1294 }
1295 if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
1296 pr_cont(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1297 for (i = 0; i < 3; i++)
1298 ((__be16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
1299 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1300 if (print_info)
1301 pr_cont(" %pM", dev->dev_addr);
1302 /* Unfortunately an all zero eeprom passes the checksum and this
1303 gets found in the wild in failure cases. Crypto is hard 8) */
1304 if (!is_valid_ether_addr(dev->dev_addr)) {
1305 retval = -EINVAL;
1306 pr_err("*** EEPROM MAC address is invalid.\n");
1307 goto free_ring; /* With every pack */
1308 }
1309 for (i = 0; i < 6; i++)
1310 window_write8(vp, dev->dev_addr[i], 2, i);
1311
1312 if (print_info)
1313 pr_cont(", IRQ %d\n", dev->irq);
1314 /* Tell them about an invalid IRQ. */
1315 if (dev->irq <= 0 || dev->irq >= nr_irqs)
1316 pr_warning(" *** Warning: IRQ %d is unlikely to work! ***\n",
1317 dev->irq);
1318
1319 step = (window_read8(vp, 4, Wn4_NetDiag) & 0x1e) >> 1;
1320 if (print_info) {
1321 pr_info(" product code %02x%02x rev %02x.%d date %02d-%02d-%02d\n",
1322 eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1323 step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1324 }
1325
1326
1327 if (pdev && vci->drv_flags & HAS_CB_FNS) {
1328 unsigned short n;
1329
1330 vp->cb_fn_base = pci_iomap(pdev, 2, 0);
1331 if (!vp->cb_fn_base) {
1332 retval = -ENOMEM;
1333 goto free_ring;
1334 }
1335
1336 if (print_info) {
1337 pr_info("%s: CardBus functions mapped %16.16llx->%p\n",
1338 print_name,
1339 (unsigned long long)pci_resource_start(pdev, 2),
1340 vp->cb_fn_base);
1341 }
1342
1343 n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010;
1344 if (vp->drv_flags & INVERT_LED_PWR)
1345 n |= 0x10;
1346 if (vp->drv_flags & INVERT_MII_PWR)
1347 n |= 0x4000;
1348 window_write16(vp, n, 2, Wn2_ResetOptions);
1349 if (vp->drv_flags & WNO_XCVR_PWR) {
1350 window_write16(vp, 0x0800, 0, 0);
1351 }
1352 }
1353
1354 /* Extract our information from the EEPROM data. */
1355 vp->info1 = eeprom[13];
1356 vp->info2 = eeprom[15];
1357 vp->capabilities = eeprom[16];
1358
1359 if (vp->info1 & 0x8000) {
1360 vp->full_duplex = 1;
1361 if (print_info)
1362 pr_info("Full duplex capable\n");
1363 }
1364
1365 {
1366 static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1367 unsigned int config;
1368 vp->available_media = window_read16(vp, 3, Wn3_Options);
1369 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
1370 vp->available_media = 0x40;
1371 config = window_read32(vp, 3, Wn3_Config);
1372 if (print_info) {
1373 pr_debug(" Internal config register is %4.4x, transceivers %#x.\n",
1374 config, window_read16(vp, 3, Wn3_Options));
1375 pr_info(" %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1376 8 << RAM_SIZE(config),
1377 RAM_WIDTH(config) ? "word" : "byte",
1378 ram_split[RAM_SPLIT(config)],
1379 AUTOSELECT(config) ? "autoselect/" : "",
1380 XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1381 media_tbl[XCVR(config)].name);
1382 }
1383 vp->default_media = XCVR(config);
1384 if (vp->default_media == XCVR_NWAY)
1385 vp->has_nway = 1;
1386 vp->autoselect = AUTOSELECT(config);
1387 }
1388
1389 if (vp->media_override != 7) {
1390 pr_info("%s: Media override to transceiver type %d (%s).\n",
1391 print_name, vp->media_override,
1392 media_tbl[vp->media_override].name);
1393 dev->if_port = vp->media_override;
1394 } else
1395 dev->if_port = vp->default_media;
1396
1397 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1398 dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1399 int phy, phy_idx = 0;
1400 mii_preamble_required++;
1401 if (vp->drv_flags & EXTRA_PREAMBLE)
1402 mii_preamble_required++;
1403 mdio_sync(vp, 32);
1404 mdio_read(dev, 24, MII_BMSR);
1405 for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1406 int mii_status, phyx;
1407
1408 /*
1409 * For the 3c905CX we look at index 24 first, because it bogusly
1410 * reports an external PHY at all indices
1411 */
1412 if (phy == 0)
1413 phyx = 24;
1414 else if (phy <= 24)
1415 phyx = phy - 1;
1416 else
1417 phyx = phy;
1418 mii_status = mdio_read(dev, phyx, MII_BMSR);
1419 if (mii_status && mii_status != 0xffff) {
1420 vp->phys[phy_idx++] = phyx;
1421 if (print_info) {
1422 pr_info(" MII transceiver found at address %d, status %4x.\n",
1423 phyx, mii_status);
1424 }
1425 if ((mii_status & 0x0040) == 0)
1426 mii_preamble_required++;
1427 }
1428 }
1429 mii_preamble_required--;
1430 if (phy_idx == 0) {
1431 pr_warning(" ***WARNING*** No MII transceivers found!\n");
1432 vp->phys[0] = 24;
1433 } else {
1434 vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE);
1435 if (vp->full_duplex) {
1436 /* Only advertise the FD media types. */
1437 vp->advertising &= ~0x02A0;
1438 mdio_write(dev, vp->phys[0], 4, vp->advertising);
1439 }
1440 }
1441 vp->mii.phy_id = vp->phys[0];
1442 }
1443
1444 if (vp->capabilities & CapBusMaster) {
1445 vp->full_bus_master_tx = 1;
1446 if (print_info) {
1447 pr_info(" Enabling bus-master transmits and %s receives.\n",
1448 (vp->info2 & 1) ? "early" : "whole-frame" );
1449 }
1450 vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1451 vp->bus_master = 0; /* AKPM: vortex only */
1452 }
1453
1454 /* The 3c59x-specific entries in the device structure. */
1455 if (vp->full_bus_master_tx) {
1456 dev->netdev_ops = &boomrang_netdev_ops;
1457 /* Actually, it still should work with iommu. */
1458 if (card_idx < MAX_UNITS &&
1459 ((hw_checksums[card_idx] == -1 && (vp->drv_flags & HAS_HWCKSM)) ||
1460 hw_checksums[card_idx] == 1)) {
1461 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
1462 }
1463 } else
1464 dev->netdev_ops = &vortex_netdev_ops;
1465
1466 if (print_info) {
1467 pr_info("%s: scatter/gather %sabled. h/w checksums %sabled\n",
1468 print_name,
1469 (dev->features & NETIF_F_SG) ? "en":"dis",
1470 (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
1471 }
1472
1473 dev->ethtool_ops = &vortex_ethtool_ops;
1474 dev->watchdog_timeo = (watchdog * HZ) / 1000;
1475
1476 if (pdev) {
1477 vp->pm_state_valid = 1;
1478 pci_save_state(VORTEX_PCI(vp));
1479 acpi_set_WOL(dev);
1480 }
1481 retval = register_netdev(dev);
1482 if (retval == 0)
1483 return 0;
1484
1485 free_ring:
1486 pci_free_consistent(pdev,
1487 sizeof(struct boom_rx_desc) * RX_RING_SIZE
1488 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1489 vp->rx_ring,
1490 vp->rx_ring_dma);
1491 free_device:
1492 free_netdev(dev);
1493 pr_err(PFX "vortex_probe1 fails. Returns %d\n", retval);
1494 out:
1495 return retval;
1496 }
1497
1498 static void
1499 issue_and_wait(struct net_device *dev, int cmd)
1500 {
1501 struct vortex_private *vp = netdev_priv(dev);
1502 void __iomem *ioaddr = vp->ioaddr;
1503 int i;
1504
1505 iowrite16(cmd, ioaddr + EL3_CMD);
1506 for (i = 0; i < 2000; i++) {
1507 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1508 return;
1509 }
1510
1511 /* OK, that didn't work. Do it the slow way. One second */
1512 for (i = 0; i < 100000; i++) {
1513 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) {
1514 if (vortex_debug > 1)
1515 pr_info("%s: command 0x%04x took %d usecs\n",
1516 dev->name, cmd, i * 10);
1517 return;
1518 }
1519 udelay(10);
1520 }
1521 pr_err("%s: command 0x%04x did not complete! Status=0x%x\n",
1522 dev->name, cmd, ioread16(ioaddr + EL3_STATUS));
1523 }
1524
1525 static void
1526 vortex_set_duplex(struct net_device *dev)
1527 {
1528 struct vortex_private *vp = netdev_priv(dev);
1529
1530 pr_info("%s: setting %s-duplex.\n",
1531 dev->name, (vp->full_duplex) ? "full" : "half");
1532
1533 /* Set the full-duplex bit. */
1534 window_write16(vp,
1535 ((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1536 (vp->large_frames ? 0x40 : 0) |
1537 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ?
1538 0x100 : 0),
1539 3, Wn3_MAC_Ctrl);
1540 }
1541
1542 static void vortex_check_media(struct net_device *dev, unsigned int init)
1543 {
1544 struct vortex_private *vp = netdev_priv(dev);
1545 unsigned int ok_to_print = 0;
1546
1547 if (vortex_debug > 3)
1548 ok_to_print = 1;
1549
1550 if (mii_check_media(&vp->mii, ok_to_print, init)) {
1551 vp->full_duplex = vp->mii.full_duplex;
1552 vortex_set_duplex(dev);
1553 } else if (init) {
1554 vortex_set_duplex(dev);
1555 }
1556 }
1557
1558 static int
1559 vortex_up(struct net_device *dev)
1560 {
1561 struct vortex_private *vp = netdev_priv(dev);
1562 void __iomem *ioaddr = vp->ioaddr;
1563 unsigned int config;
1564 int i, mii_reg1, mii_reg5, err = 0;
1565
1566 if (VORTEX_PCI(vp)) {
1567 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
1568 if (vp->pm_state_valid)
1569 pci_restore_state(VORTEX_PCI(vp));
1570 err = pci_enable_device(VORTEX_PCI(vp));
1571 if (err) {
1572 pr_warning("%s: Could not enable device\n",
1573 dev->name);
1574 goto err_out;
1575 }
1576 }
1577
1578 /* Before initializing select the active media port. */
1579 config = window_read32(vp, 3, Wn3_Config);
1580
1581 if (vp->media_override != 7) {
1582 pr_info("%s: Media override to transceiver %d (%s).\n",
1583 dev->name, vp->media_override,
1584 media_tbl[vp->media_override].name);
1585 dev->if_port = vp->media_override;
1586 } else if (vp->autoselect) {
1587 if (vp->has_nway) {
1588 if (vortex_debug > 1)
1589 pr_info("%s: using NWAY device table, not %d\n",
1590 dev->name, dev->if_port);
1591 dev->if_port = XCVR_NWAY;
1592 } else {
1593 /* Find first available media type, starting with 100baseTx. */
1594 dev->if_port = XCVR_100baseTx;
1595 while (! (vp->available_media & media_tbl[dev->if_port].mask))
1596 dev->if_port = media_tbl[dev->if_port].next;
1597 if (vortex_debug > 1)
1598 pr_info("%s: first available media type: %s\n",
1599 dev->name, media_tbl[dev->if_port].name);
1600 }
1601 } else {
1602 dev->if_port = vp->default_media;
1603 if (vortex_debug > 1)
1604 pr_info("%s: using default media %s\n",
1605 dev->name, media_tbl[dev->if_port].name);
1606 }
1607
1608 init_timer(&vp->timer);
1609 vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait);
1610 vp->timer.data = (unsigned long)dev;
1611 vp->timer.function = vortex_timer; /* timer handler */
1612 add_timer(&vp->timer);
1613
1614 init_timer(&vp->rx_oom_timer);
1615 vp->rx_oom_timer.data = (unsigned long)dev;
1616 vp->rx_oom_timer.function = rx_oom_timer;
1617
1618 if (vortex_debug > 1)
1619 pr_debug("%s: Initial media type %s.\n",
1620 dev->name, media_tbl[dev->if_port].name);
1621
1622 vp->full_duplex = vp->mii.force_media;
1623 config = BFINS(config, dev->if_port, 20, 4);
1624 if (vortex_debug > 6)
1625 pr_debug("vortex_up(): writing 0x%x to InternalConfig\n", config);
1626 window_write32(vp, config, 3, Wn3_Config);
1627
1628 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1629 mii_reg1 = mdio_read(dev, vp->phys[0], MII_BMSR);
1630 mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA);
1631 vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
1632 vp->mii.full_duplex = vp->full_duplex;
1633
1634 vortex_check_media(dev, 1);
1635 }
1636 else
1637 vortex_set_duplex(dev);
1638
1639 issue_and_wait(dev, TxReset);
1640 /*
1641 * Don't reset the PHY - that upsets autonegotiation during DHCP operations.
1642 */
1643 issue_and_wait(dev, RxReset|0x04);
1644
1645
1646 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1647
1648 if (vortex_debug > 1) {
1649 pr_debug("%s: vortex_up() irq %d media status %4.4x.\n",
1650 dev->name, dev->irq, window_read16(vp, 4, Wn4_Media));
1651 }
1652
1653 /* Set the station address and mask in window 2 each time opened. */
1654 for (i = 0; i < 6; i++)
1655 window_write8(vp, dev->dev_addr[i], 2, i);
1656 for (; i < 12; i+=2)
1657 window_write16(vp, 0, 2, i);
1658
1659 if (vp->cb_fn_base) {
1660 unsigned short n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010;
1661 if (vp->drv_flags & INVERT_LED_PWR)
1662 n |= 0x10;
1663 if (vp->drv_flags & INVERT_MII_PWR)
1664 n |= 0x4000;
1665 window_write16(vp, n, 2, Wn2_ResetOptions);
1666 }
1667
1668 if (dev->if_port == XCVR_10base2)
1669 /* Start the thinnet transceiver. We should really wait 50ms...*/
1670 iowrite16(StartCoax, ioaddr + EL3_CMD);
1671 if (dev->if_port != XCVR_NWAY) {
1672 window_write16(vp,
1673 (window_read16(vp, 4, Wn4_Media) &
1674 ~(Media_10TP|Media_SQE)) |
1675 media_tbl[dev->if_port].media_bits,
1676 4, Wn4_Media);
1677 }
1678
1679 /* Switch to the stats window, and clear all stats by reading. */
1680 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1681 for (i = 0; i < 10; i++)
1682 window_read8(vp, 6, i);
1683 window_read16(vp, 6, 10);
1684 window_read16(vp, 6, 12);
1685 /* New: On the Vortex we must also clear the BadSSD counter. */
1686 window_read8(vp, 4, 12);
1687 /* ..and on the Boomerang we enable the extra statistics bits. */
1688 window_write16(vp, 0x0040, 4, Wn4_NetDiag);
1689
1690 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1691 vp->cur_rx = vp->dirty_rx = 0;
1692 /* Initialize the RxEarly register as recommended. */
1693 iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1694 iowrite32(0x0020, ioaddr + PktStatus);
1695 iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr);
1696 }
1697 if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
1698 vp->cur_tx = vp->dirty_tx = 0;
1699 if (vp->drv_flags & IS_BOOMERANG)
1700 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
1701 /* Clear the Rx, Tx rings. */
1702 for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */
1703 vp->rx_ring[i].status = 0;
1704 for (i = 0; i < TX_RING_SIZE; i++)
1705 vp->tx_skbuff[i] = NULL;
1706 iowrite32(0, ioaddr + DownListPtr);
1707 }
1708 /* Set receiver mode: presumably accept b-case and phys addr only. */
1709 set_rx_mode(dev);
1710 /* enable 802.1q tagged frames */
1711 set_8021q_mode(dev, 1);
1712 iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1713
1714 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1715 iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1716 /* Allow status bits to be seen. */
1717 vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1718 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1719 (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1720 (vp->bus_master ? DMADone : 0);
1721 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1722 (vp->full_bus_master_rx ? 0 : RxComplete) |
1723 StatsFull | HostError | TxComplete | IntReq
1724 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
1725 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1726 /* Ack all pending events, and set active indicator mask. */
1727 iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1728 ioaddr + EL3_CMD);
1729 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1730 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
1731 iowrite32(0x8000, vp->cb_fn_base + 4);
1732 netif_start_queue (dev);
1733 err_out:
1734 return err;
1735 }
1736
1737 static int
1738 vortex_open(struct net_device *dev)
1739 {
1740 struct vortex_private *vp = netdev_priv(dev);
1741 int i;
1742 int retval;
1743
1744 /* Use the now-standard shared IRQ implementation. */
1745 if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ?
1746 boomerang_interrupt : vortex_interrupt, IRQF_SHARED, dev->name, dev))) {
1747 pr_err("%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
1748 goto err;
1749 }
1750
1751 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1752 if (vortex_debug > 2)
1753 pr_debug("%s: Filling in the Rx ring.\n", dev->name);
1754 for (i = 0; i < RX_RING_SIZE; i++) {
1755 struct sk_buff *skb;
1756 vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1757 vp->rx_ring[i].status = 0; /* Clear complete bit. */
1758 vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
1759
1760 skb = __netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN,
1761 GFP_KERNEL);
1762 vp->rx_skbuff[i] = skb;
1763 if (skb == NULL)
1764 break; /* Bad news! */
1765
1766 skb_reserve(skb, NET_IP_ALIGN); /* Align IP on 16 byte boundaries */
1767 vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1768 }
1769 if (i != RX_RING_SIZE) {
1770 int j;
1771 pr_emerg("%s: no memory for rx ring\n", dev->name);
1772 for (j = 0; j < i; j++) {
1773 if (vp->rx_skbuff[j]) {
1774 dev_kfree_skb(vp->rx_skbuff[j]);
1775 vp->rx_skbuff[j] = NULL;
1776 }
1777 }
1778 retval = -ENOMEM;
1779 goto err_free_irq;
1780 }
1781 /* Wrap the ring. */
1782 vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1783 }
1784
1785 retval = vortex_up(dev);
1786 if (!retval)
1787 goto out;
1788
1789 err_free_irq:
1790 free_irq(dev->irq, dev);
1791 err:
1792 if (vortex_debug > 1)
1793 pr_err("%s: vortex_open() fails: returning %d\n", dev->name, retval);
1794 out:
1795 return retval;
1796 }
1797
1798 static void
1799 vortex_timer(unsigned long data)
1800 {
1801 struct net_device *dev = (struct net_device *)data;
1802 struct vortex_private *vp = netdev_priv(dev);
1803 void __iomem *ioaddr = vp->ioaddr;
1804 int next_tick = 60*HZ;
1805 int ok = 0;
1806 int media_status;
1807
1808 if (vortex_debug > 2) {
1809 pr_debug("%s: Media selection timer tick happened, %s.\n",
1810 dev->name, media_tbl[dev->if_port].name);
1811 pr_debug("dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1812 }
1813
1814 media_status = window_read16(vp, 4, Wn4_Media);
1815 switch (dev->if_port) {
1816 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1817 if (media_status & Media_LnkBeat) {
1818 netif_carrier_on(dev);
1819 ok = 1;
1820 if (vortex_debug > 1)
1821 pr_debug("%s: Media %s has link beat, %x.\n",
1822 dev->name, media_tbl[dev->if_port].name, media_status);
1823 } else {
1824 netif_carrier_off(dev);
1825 if (vortex_debug > 1) {
1826 pr_debug("%s: Media %s has no link beat, %x.\n",
1827 dev->name, media_tbl[dev->if_port].name, media_status);
1828 }
1829 }
1830 break;
1831 case XCVR_MII: case XCVR_NWAY:
1832 {
1833 ok = 1;
1834 vortex_check_media(dev, 0);
1835 }
1836 break;
1837 default: /* Other media types handled by Tx timeouts. */
1838 if (vortex_debug > 1)
1839 pr_debug("%s: Media %s has no indication, %x.\n",
1840 dev->name, media_tbl[dev->if_port].name, media_status);
1841 ok = 1;
1842 }
1843
1844 if (dev->flags & IFF_SLAVE || !netif_carrier_ok(dev))
1845 next_tick = 5*HZ;
1846
1847 if (vp->medialock)
1848 goto leave_media_alone;
1849
1850 if (!ok) {
1851 unsigned int config;
1852
1853 spin_lock_irq(&vp->lock);
1854
1855 do {
1856 dev->if_port = media_tbl[dev->if_port].next;
1857 } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1858 if (dev->if_port == XCVR_Default) { /* Go back to default. */
1859 dev->if_port = vp->default_media;
1860 if (vortex_debug > 1)
1861 pr_debug("%s: Media selection failing, using default %s port.\n",
1862 dev->name, media_tbl[dev->if_port].name);
1863 } else {
1864 if (vortex_debug > 1)
1865 pr_debug("%s: Media selection failed, now trying %s port.\n",
1866 dev->name, media_tbl[dev->if_port].name);
1867 next_tick = media_tbl[dev->if_port].wait;
1868 }
1869 window_write16(vp,
1870 (media_status & ~(Media_10TP|Media_SQE)) |
1871 media_tbl[dev->if_port].media_bits,
1872 4, Wn4_Media);
1873
1874 config = window_read32(vp, 3, Wn3_Config);
1875 config = BFINS(config, dev->if_port, 20, 4);
1876 window_write32(vp, config, 3, Wn3_Config);
1877
1878 iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1879 ioaddr + EL3_CMD);
1880 if (vortex_debug > 1)
1881 pr_debug("wrote 0x%08x to Wn3_Config\n", config);
1882 /* AKPM: FIXME: Should reset Rx & Tx here. P60 of 3c90xc.pdf */
1883
1884 spin_unlock_irq(&vp->lock);
1885 }
1886
1887 leave_media_alone:
1888 if (vortex_debug > 2)
1889 pr_debug("%s: Media selection timer finished, %s.\n",
1890 dev->name, media_tbl[dev->if_port].name);
1891
1892 mod_timer(&vp->timer, RUN_AT(next_tick));
1893 if (vp->deferred)
1894 iowrite16(FakeIntr, ioaddr + EL3_CMD);
1895 }
1896
1897 static void vortex_tx_timeout(struct net_device *dev)
1898 {
1899 struct vortex_private *vp = netdev_priv(dev);
1900 void __iomem *ioaddr = vp->ioaddr;
1901
1902 pr_err("%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
1903 dev->name, ioread8(ioaddr + TxStatus),
1904 ioread16(ioaddr + EL3_STATUS));
1905 pr_err(" diagnostics: net %04x media %04x dma %08x fifo %04x\n",
1906 window_read16(vp, 4, Wn4_NetDiag),
1907 window_read16(vp, 4, Wn4_Media),
1908 ioread32(ioaddr + PktStatus),
1909 window_read16(vp, 4, Wn4_FIFODiag));
1910 /* Slight code bloat to be user friendly. */
1911 if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88)
1912 pr_err("%s: Transmitter encountered 16 collisions --"
1913 " network cable problem?\n", dev->name);
1914 if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
1915 pr_err("%s: Interrupt posted but not delivered --"
1916 " IRQ blocked by another device?\n", dev->name);
1917 /* Bad idea here.. but we might as well handle a few events. */
1918 {
1919 /*
1920 * Block interrupts because vortex_interrupt does a bare spin_lock()
1921 */
1922 unsigned long flags;
1923 local_irq_save(flags);
1924 if (vp->full_bus_master_tx)
1925 boomerang_interrupt(dev->irq, dev);
1926 else
1927 vortex_interrupt(dev->irq, dev);
1928 local_irq_restore(flags);
1929 }
1930 }
1931
1932 if (vortex_debug > 0)
1933 dump_tx_ring(dev);
1934
1935 issue_and_wait(dev, TxReset);
1936
1937 dev->stats.tx_errors++;
1938 if (vp->full_bus_master_tx) {
1939 pr_debug("%s: Resetting the Tx ring pointer.\n", dev->name);
1940 if (vp->cur_tx - vp->dirty_tx > 0 && ioread32(ioaddr + DownListPtr) == 0)
1941 iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
1942 ioaddr + DownListPtr);
1943 if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE)
1944 netif_wake_queue (dev);
1945 if (vp->drv_flags & IS_BOOMERANG)
1946 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
1947 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1948 } else {
1949 dev->stats.tx_dropped++;
1950 netif_wake_queue(dev);
1951 }
1952
1953 /* Issue Tx Enable */
1954 iowrite16(TxEnable, ioaddr + EL3_CMD);
1955 dev->trans_start = jiffies; /* prevent tx timeout */
1956 }
1957
1958 /*
1959 * Handle uncommon interrupt sources. This is a separate routine to minimize
1960 * the cache impact.
1961 */
1962 static void
1963 vortex_error(struct net_device *dev, int status)
1964 {
1965 struct vortex_private *vp = netdev_priv(dev);
1966 void __iomem *ioaddr = vp->ioaddr;
1967 int do_tx_reset = 0, reset_mask = 0;
1968 unsigned char tx_status = 0;
1969
1970 if (vortex_debug > 2) {
1971 pr_err("%s: vortex_error(), status=0x%x\n", dev->name, status);
1972 }
1973
1974 if (status & TxComplete) { /* Really "TxError" for us. */
1975 tx_status = ioread8(ioaddr + TxStatus);
1976 /* Presumably a tx-timeout. We must merely re-enable. */
1977 if (vortex_debug > 2 ||
1978 (tx_status != 0x88 && vortex_debug > 0)) {
1979 pr_err("%s: Transmit error, Tx status register %2.2x.\n",
1980 dev->name, tx_status);
1981 if (tx_status == 0x82) {
1982 pr_err("Probably a duplex mismatch. See "
1983 "Documentation/networking/vortex.txt\n");
1984 }
1985 dump_tx_ring(dev);
1986 }
1987 if (tx_status & 0x14) dev->stats.tx_fifo_errors++;
1988 if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
1989 if (tx_status & 0x08) vp->xstats.tx_max_collisions++;
1990 iowrite8(0, ioaddr + TxStatus);
1991 if (tx_status & 0x30) { /* txJabber or txUnderrun */
1992 do_tx_reset = 1;
1993 } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) { /* maxCollisions */
1994 do_tx_reset = 1;
1995 reset_mask = 0x0108; /* Reset interface logic, but not download logic */
1996 } else { /* Merely re-enable the transmitter. */
1997 iowrite16(TxEnable, ioaddr + EL3_CMD);
1998 }
1999 }
2000
2001 if (status & RxEarly) /* Rx early is unused. */
2002 iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
2003
2004 if (status & StatsFull) { /* Empty statistics. */
2005 static int DoneDidThat;
2006 if (vortex_debug > 4)
2007 pr_debug("%s: Updating stats.\n", dev->name);
2008 update_stats(ioaddr, dev);
2009 /* HACK: Disable statistics as an interrupt source. */
2010 /* This occurs when we have the wrong media type! */
2011 if (DoneDidThat == 0 &&
2012 ioread16(ioaddr + EL3_STATUS) & StatsFull) {
2013 pr_warning("%s: Updating statistics failed, disabling "
2014 "stats as an interrupt source.\n", dev->name);
2015 iowrite16(SetIntrEnb |
2016 (window_read16(vp, 5, 10) & ~StatsFull),
2017 ioaddr + EL3_CMD);
2018 vp->intr_enable &= ~StatsFull;
2019 DoneDidThat++;
2020 }
2021 }
2022 if (status & IntReq) { /* Restore all interrupt sources. */
2023 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
2024 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
2025 }
2026 if (status & HostError) {
2027 u16 fifo_diag;
2028 fifo_diag = window_read16(vp, 4, Wn4_FIFODiag);
2029 pr_err("%s: Host error, FIFO diagnostic register %4.4x.\n",
2030 dev->name, fifo_diag);
2031 /* Adapter failure requires Tx/Rx reset and reinit. */
2032 if (vp->full_bus_master_tx) {
2033 int bus_status = ioread32(ioaddr + PktStatus);
2034 /* 0x80000000 PCI master abort. */
2035 /* 0x40000000 PCI target abort. */
2036 if (vortex_debug)
2037 pr_err("%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
2038
2039 /* In this case, blow the card away */
2040 /* Must not enter D3 or we can't legally issue the reset! */
2041 vortex_down(dev, 0);
2042 issue_and_wait(dev, TotalReset | 0xff);
2043 vortex_up(dev); /* AKPM: bug. vortex_up() assumes that the rx ring is full. It may not be. */
2044 } else if (fifo_diag & 0x0400)
2045 do_tx_reset = 1;
2046 if (fifo_diag & 0x3000) {
2047 /* Reset Rx fifo and upload logic */
2048 issue_and_wait(dev, RxReset|0x07);
2049 /* Set the Rx filter to the current state. */
2050 set_rx_mode(dev);
2051 /* enable 802.1q VLAN tagged frames */
2052 set_8021q_mode(dev, 1);
2053 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
2054 iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
2055 }
2056 }
2057
2058 if (do_tx_reset) {
2059 issue_and_wait(dev, TxReset|reset_mask);
2060 iowrite16(TxEnable, ioaddr + EL3_CMD);
2061 if (!vp->full_bus_master_tx)
2062 netif_wake_queue(dev);
2063 }
2064 }
2065
2066 static netdev_tx_t
2067 vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
2068 {
2069 struct vortex_private *vp = netdev_priv(dev);
2070 void __iomem *ioaddr = vp->ioaddr;
2071
2072 /* Put out the doubleword header... */
2073 iowrite32(skb->len, ioaddr + TX_FIFO);
2074 if (vp->bus_master) {
2075 /* Set the bus-master controller to transfer the packet. */
2076 int len = (skb->len + 3) & ~3;
2077 vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len,
2078 PCI_DMA_TODEVICE);
2079 spin_lock_irq(&vp->window_lock);
2080 window_set(vp, 7);
2081 iowrite32(vp->tx_skb_dma, ioaddr + Wn7_MasterAddr);
2082 iowrite16(len, ioaddr + Wn7_MasterLen);
2083 spin_unlock_irq(&vp->window_lock);
2084 vp->tx_skb = skb;
2085 iowrite16(StartDMADown, ioaddr + EL3_CMD);
2086 /* netif_wake_queue() will be called at the DMADone interrupt. */
2087 } else {
2088 /* ... and the packet rounded to a doubleword. */
2089 iowrite32_rep(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
2090 dev_kfree_skb (skb);
2091 if (ioread16(ioaddr + TxFree) > 1536) {
2092 netif_start_queue (dev); /* AKPM: redundant? */
2093 } else {
2094 /* Interrupt us when the FIFO has room for max-sized packet. */
2095 netif_stop_queue(dev);
2096 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2097 }
2098 }
2099
2100
2101 /* Clear the Tx status stack. */
2102 {
2103 int tx_status;
2104 int i = 32;
2105
2106 while (--i > 0 && (tx_status = ioread8(ioaddr + TxStatus)) > 0) {
2107 if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
2108 if (vortex_debug > 2)
2109 pr_debug("%s: Tx error, status %2.2x.\n",
2110 dev->name, tx_status);
2111 if (tx_status & 0x04) dev->stats.tx_fifo_errors++;
2112 if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
2113 if (tx_status & 0x30) {
2114 issue_and_wait(dev, TxReset);
2115 }
2116 iowrite16(TxEnable, ioaddr + EL3_CMD);
2117 }
2118 iowrite8(0x00, ioaddr + TxStatus); /* Pop the status stack. */
2119 }
2120 }
2121 return NETDEV_TX_OK;
2122 }
2123
2124 static netdev_tx_t
2125 boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2126 {
2127 struct vortex_private *vp = netdev_priv(dev);
2128 void __iomem *ioaddr = vp->ioaddr;
2129 /* Calculate the next Tx descriptor entry. */
2130 int entry = vp->cur_tx % TX_RING_SIZE;
2131 struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2132 unsigned long flags;
2133
2134 if (vortex_debug > 6) {
2135 pr_debug("boomerang_start_xmit()\n");
2136 pr_debug("%s: Trying to send a packet, Tx index %d.\n",
2137 dev->name, vp->cur_tx);
2138 }
2139
2140 /*
2141 * We can't allow a recursion from our interrupt handler back into the
2142 * tx routine, as they take the same spin lock, and that causes
2143 * deadlock. Just return NETDEV_TX_BUSY and let the stack try again in
2144 * a bit
2145 */
2146 if (vp->handling_irq)
2147 return NETDEV_TX_BUSY;
2148
2149 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2150 if (vortex_debug > 0)
2151 pr_warning("%s: BUG! Tx Ring full, refusing to send buffer.\n",
2152 dev->name);
2153 netif_stop_queue(dev);
2154 return NETDEV_TX_BUSY;
2155 }
2156
2157 vp->tx_skbuff[entry] = skb;
2158
2159 vp->tx_ring[entry].next = 0;
2160 #if DO_ZEROCOPY
2161 if (skb->ip_summed != CHECKSUM_PARTIAL)
2162 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2163 else
2164 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2165
2166 if (!skb_shinfo(skb)->nr_frags) {
2167 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2168 skb->len, PCI_DMA_TODEVICE));
2169 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2170 } else {
2171 int i;
2172
2173 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2174 skb_headlen(skb), PCI_DMA_TODEVICE));
2175 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb_headlen(skb));
2176
2177 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2178 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2179
2180 vp->tx_ring[entry].frag[i+1].addr =
2181 cpu_to_le32(pci_map_single(
2182 VORTEX_PCI(vp),
2183 (void *)skb_frag_address(frag),
2184 skb_frag_size(frag), PCI_DMA_TODEVICE));
2185
2186 if (i == skb_shinfo(skb)->nr_frags-1)
2187 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(skb_frag_size(frag)|LAST_FRAG);
2188 else
2189 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(skb_frag_size(frag));
2190 }
2191 }
2192 #else
2193 vp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, skb->len, PCI_DMA_TODEVICE));
2194 vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2195 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2196 #endif
2197
2198 spin_lock_irqsave(&vp->lock, flags);
2199 /* Wait for the stall to complete. */
2200 issue_and_wait(dev, DownStall);
2201 prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
2202 if (ioread32(ioaddr + DownListPtr) == 0) {
2203 iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
2204 vp->queued_packet++;
2205 }
2206
2207 vp->cur_tx++;
2208 if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2209 netif_stop_queue (dev);
2210 } else { /* Clear previous interrupt enable. */
2211 #if defined(tx_interrupt_mitigation)
2212 /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef
2213 * were selected, this would corrupt DN_COMPLETE. No?
2214 */
2215 prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
2216 #endif
2217 }
2218 iowrite16(DownUnstall, ioaddr + EL3_CMD);
2219 spin_unlock_irqrestore(&vp->lock, flags);
2220 return NETDEV_TX_OK;
2221 }
2222
2223 /* The interrupt handler does all of the Rx thread work and cleans up
2224 after the Tx thread. */
2225
2226 /*
2227 * This is the ISR for the vortex series chips.
2228 * full_bus_master_tx == 0 && full_bus_master_rx == 0
2229 */
2230
2231 static irqreturn_t
2232 vortex_interrupt(int irq, void *dev_id)
2233 {
2234 struct net_device *dev = dev_id;
2235 struct vortex_private *vp = netdev_priv(dev);
2236 void __iomem *ioaddr;
2237 int status;
2238 int work_done = max_interrupt_work;
2239 int handled = 0;
2240
2241 ioaddr = vp->ioaddr;
2242 spin_lock(&vp->lock);
2243
2244 status = ioread16(ioaddr + EL3_STATUS);
2245
2246 if (vortex_debug > 6)
2247 pr_debug("vortex_interrupt(). status=0x%4x\n", status);
2248
2249 if ((status & IntLatch) == 0)
2250 goto handler_exit; /* No interrupt: shared IRQs cause this */
2251 handled = 1;
2252
2253 if (status & IntReq) {
2254 status |= vp->deferred;
2255 vp->deferred = 0;
2256 }
2257
2258 if (status == 0xffff) /* h/w no longer present (hotplug)? */
2259 goto handler_exit;
2260
2261 if (vortex_debug > 4)
2262 pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
2263 dev->name, status, ioread8(ioaddr + Timer));
2264
2265 spin_lock(&vp->window_lock);
2266 window_set(vp, 7);
2267
2268 do {
2269 if (vortex_debug > 5)
2270 pr_debug("%s: In interrupt loop, status %4.4x.\n",
2271 dev->name, status);
2272 if (status & RxComplete)
2273 vortex_rx(dev);
2274
2275 if (status & TxAvailable) {
2276 if (vortex_debug > 5)
2277 pr_debug(" TX room bit was handled.\n");
2278 /* There's room in the FIFO for a full-sized packet. */
2279 iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
2280 netif_wake_queue (dev);
2281 }
2282
2283 if (status & DMADone) {
2284 if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) {
2285 iowrite16(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
2286 pci_unmap_single(VORTEX_PCI(vp), vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE);
2287 dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */
2288 if (ioread16(ioaddr + TxFree) > 1536) {
2289 /*
2290 * AKPM: FIXME: I don't think we need this. If the queue was stopped due to
2291 * insufficient FIFO room, the TxAvailable test will succeed and call
2292 * netif_wake_queue()
2293 */
2294 netif_wake_queue(dev);
2295 } else { /* Interrupt when FIFO has room for max-sized packet. */
2296 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2297 netif_stop_queue(dev);
2298 }
2299 }
2300 }
2301 /* Check for all uncommon interrupts at once. */
2302 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
2303 if (status == 0xffff)
2304 break;
2305 if (status & RxEarly)
2306 vortex_rx(dev);
2307 spin_unlock(&vp->window_lock);
2308 vortex_error(dev, status);
2309 spin_lock(&vp->window_lock);
2310 window_set(vp, 7);
2311 }
2312
2313 if (--work_done < 0) {
2314 pr_warning("%s: Too much work in interrupt, status %4.4x.\n",
2315 dev->name, status);
2316 /* Disable all pending interrupts. */
2317 do {
2318 vp->deferred |= status;
2319 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
2320 ioaddr + EL3_CMD);
2321 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2322 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2323 /* The timer will reenable interrupts. */
2324 mod_timer(&vp->timer, jiffies + 1*HZ);
2325 break;
2326 }
2327 /* Acknowledge the IRQ. */
2328 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2329 } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
2330
2331 spin_unlock(&vp->window_lock);
2332
2333 if (vortex_debug > 4)
2334 pr_debug("%s: exiting interrupt, status %4.4x.\n",
2335 dev->name, status);
2336 handler_exit:
2337 spin_unlock(&vp->lock);
2338 return IRQ_RETVAL(handled);
2339 }
2340
2341 /*
2342 * This is the ISR for the boomerang series chips.
2343 * full_bus_master_tx == 1 && full_bus_master_rx == 1
2344 */
2345
2346 static irqreturn_t
2347 boomerang_interrupt(int irq, void *dev_id)
2348 {
2349 struct net_device *dev = dev_id;
2350 struct vortex_private *vp = netdev_priv(dev);
2351 void __iomem *ioaddr;
2352 int status;
2353 int work_done = max_interrupt_work;
2354
2355 ioaddr = vp->ioaddr;
2356
2357
2358 /*
2359 * It seems dopey to put the spinlock this early, but we could race against vortex_tx_timeout
2360 * and boomerang_start_xmit
2361 */
2362 spin_lock(&vp->lock);
2363 vp->handling_irq = 1;
2364
2365 status = ioread16(ioaddr + EL3_STATUS);
2366
2367 if (vortex_debug > 6)
2368 pr_debug("boomerang_interrupt. status=0x%4x\n", status);
2369
2370 if ((status & IntLatch) == 0)
2371 goto handler_exit; /* No interrupt: shared IRQs can cause this */
2372
2373 if (status == 0xffff) { /* h/w no longer present (hotplug)? */
2374 if (vortex_debug > 1)
2375 pr_debug("boomerang_interrupt(1): status = 0xffff\n");
2376 goto handler_exit;
2377 }
2378
2379 if (status & IntReq) {
2380 status |= vp->deferred;
2381 vp->deferred = 0;
2382 }
2383
2384 if (vortex_debug > 4)
2385 pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
2386 dev->name, status, ioread8(ioaddr + Timer));
2387 do {
2388 if (vortex_debug > 5)
2389 pr_debug("%s: In interrupt loop, status %4.4x.\n",
2390 dev->name, status);
2391 if (status & UpComplete) {
2392 iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
2393 if (vortex_debug > 5)
2394 pr_debug("boomerang_interrupt->boomerang_rx\n");
2395 boomerang_rx(dev);
2396 }
2397
2398 if (status & DownComplete) {
2399 unsigned int dirty_tx = vp->dirty_tx;
2400
2401 iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
2402 while (vp->cur_tx - dirty_tx > 0) {
2403 int entry = dirty_tx % TX_RING_SIZE;
2404 #if 1 /* AKPM: the latter is faster, but cyclone-only */
2405 if (ioread32(ioaddr + DownListPtr) ==
2406 vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2407 break; /* It still hasn't been processed. */
2408 #else
2409 if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2410 break; /* It still hasn't been processed. */
2411 #endif
2412
2413 if (vp->tx_skbuff[entry]) {
2414 struct sk_buff *skb = vp->tx_skbuff[entry];
2415 #if DO_ZEROCOPY
2416 int i;
2417 for (i=0; i<=skb_shinfo(skb)->nr_frags; i++)
2418 pci_unmap_single(VORTEX_PCI(vp),
2419 le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2420 le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2421 PCI_DMA_TODEVICE);
2422 #else
2423 pci_unmap_single(VORTEX_PCI(vp),
2424 le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE);
2425 #endif
2426 dev_kfree_skb_irq(skb);
2427 vp->tx_skbuff[entry] = NULL;
2428 } else {
2429 pr_debug("boomerang_interrupt: no skb!\n");
2430 }
2431 /* dev->stats.tx_packets++; Counted below. */
2432 dirty_tx++;
2433 }
2434 vp->dirty_tx = dirty_tx;
2435 if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2436 if (vortex_debug > 6)
2437 pr_debug("boomerang_interrupt: wake queue\n");
2438 netif_wake_queue (dev);
2439 }
2440 }
2441
2442 /* Check for all uncommon interrupts at once. */
2443 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2444 vortex_error(dev, status);
2445
2446 if (--work_done < 0) {
2447 pr_warning("%s: Too much work in interrupt, status %4.4x.\n",
2448 dev->name, status);
2449 /* Disable all pending interrupts. */
2450 do {
2451 vp->deferred |= status;
2452 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
2453 ioaddr + EL3_CMD);
2454 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2455 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2456 /* The timer will reenable interrupts. */
2457 mod_timer(&vp->timer, jiffies + 1*HZ);
2458 break;
2459 }
2460 /* Acknowledge the IRQ. */
2461 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2462 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
2463 iowrite32(0x8000, vp->cb_fn_base + 4);
2464
2465 } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);
2466
2467 if (vortex_debug > 4)
2468 pr_debug("%s: exiting interrupt, status %4.4x.\n",
2469 dev->name, status);
2470 handler_exit:
2471 vp->handling_irq = 0;
2472 spin_unlock(&vp->lock);
2473 return IRQ_HANDLED;
2474 }
2475
2476 static int vortex_rx(struct net_device *dev)
2477 {
2478 struct vortex_private *vp = netdev_priv(dev);
2479 void __iomem *ioaddr = vp->ioaddr;
2480 int i;
2481 short rx_status;
2482
2483 if (vortex_debug > 5)
2484 pr_debug("vortex_rx(): status %4.4x, rx_status %4.4x.\n",
2485 ioread16(ioaddr+EL3_STATUS), ioread16(ioaddr+RxStatus));
2486 while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) {
2487 if (rx_status & 0x4000) { /* Error, update stats. */
2488 unsigned char rx_error = ioread8(ioaddr + RxErrors);
2489 if (vortex_debug > 2)
2490 pr_debug(" Rx error: status %2.2x.\n", rx_error);
2491 dev->stats.rx_errors++;
2492 if (rx_error & 0x01) dev->stats.rx_over_errors++;
2493 if (rx_error & 0x02) dev->stats.rx_length_errors++;
2494 if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2495 if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2496 if (rx_error & 0x10) dev->stats.rx_length_errors++;
2497 } else {
2498 /* The packet length: up to 4.5K!. */
2499 int pkt_len = rx_status & 0x1fff;
2500 struct sk_buff *skb;
2501
2502 skb = netdev_alloc_skb(dev, pkt_len + 5);
2503 if (vortex_debug > 4)
2504 pr_debug("Receiving packet size %d status %4.4x.\n",
2505 pkt_len, rx_status);
2506 if (skb != NULL) {
2507 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2508 /* 'skb_put()' points to the start of sk_buff data area. */
2509 if (vp->bus_master &&
2510 ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) {
2511 dma_addr_t dma = pci_map_single(VORTEX_PCI(vp), skb_put(skb, pkt_len),
2512 pkt_len, PCI_DMA_FROMDEVICE);
2513 iowrite32(dma, ioaddr + Wn7_MasterAddr);
2514 iowrite16((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2515 iowrite16(StartDMAUp, ioaddr + EL3_CMD);
2516 while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)
2517 ;
2518 pci_unmap_single(VORTEX_PCI(vp), dma, pkt_len, PCI_DMA_FROMDEVICE);
2519 } else {
2520 ioread32_rep(ioaddr + RX_FIFO,
2521 skb_put(skb, pkt_len),
2522 (pkt_len + 3) >> 2);
2523 }
2524 iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
2525 skb->protocol = eth_type_trans(skb, dev);
2526 netif_rx(skb);
2527 dev->stats.rx_packets++;
2528 /* Wait a limited time to go to next packet. */
2529 for (i = 200; i >= 0; i--)
2530 if ( ! (ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
2531 break;
2532 continue;
2533 } else if (vortex_debug > 0)
2534 pr_notice("%s: No memory to allocate a sk_buff of size %d.\n",
2535 dev->name, pkt_len);
2536 dev->stats.rx_dropped++;
2537 }
2538 issue_and_wait(dev, RxDiscard);
2539 }
2540
2541 return 0;
2542 }
2543
2544 static int
2545 boomerang_rx(struct net_device *dev)
2546 {
2547 struct vortex_private *vp = netdev_priv(dev);
2548 int entry = vp->cur_rx % RX_RING_SIZE;
2549 void __iomem *ioaddr = vp->ioaddr;
2550 int rx_status;
2551 int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx;
2552
2553 if (vortex_debug > 5)
2554 pr_debug("boomerang_rx(): status %4.4x\n", ioread16(ioaddr+EL3_STATUS));
2555
2556 while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2557 if (--rx_work_limit < 0)
2558 break;
2559 if (rx_status & RxDError) { /* Error, update stats. */
2560 unsigned char rx_error = rx_status >> 16;
2561 if (vortex_debug > 2)
2562 pr_debug(" Rx error: status %2.2x.\n", rx_error);
2563 dev->stats.rx_errors++;
2564 if (rx_error & 0x01) dev->stats.rx_over_errors++;
2565 if (rx_error & 0x02) dev->stats.rx_length_errors++;
2566 if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2567 if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2568 if (rx_error & 0x10) dev->stats.rx_length_errors++;
2569 } else {
2570 /* The packet length: up to 4.5K!. */
2571 int pkt_len = rx_status & 0x1fff;
2572 struct sk_buff *skb;
2573 dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2574
2575 if (vortex_debug > 4)
2576 pr_debug("Receiving packet size %d status %4.4x.\n",
2577 pkt_len, rx_status);
2578
2579 /* Check if the packet is long enough to just accept without
2580 copying to a properly sized skbuff. */
2581 if (pkt_len < rx_copybreak &&
2582 (skb = netdev_alloc_skb(dev, pkt_len + 2)) != NULL) {
2583 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2584 pci_dma_sync_single_for_cpu(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2585 /* 'skb_put()' points to the start of sk_buff data area. */
2586 memcpy(skb_put(skb, pkt_len),
2587 vp->rx_skbuff[entry]->data,
2588 pkt_len);
2589 pci_dma_sync_single_for_device(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2590 vp->rx_copy++;
2591 } else {
2592 /* Pass up the skbuff already on the Rx ring. */
2593 skb = vp->rx_skbuff[entry];
2594 vp->rx_skbuff[entry] = NULL;
2595 skb_put(skb, pkt_len);
2596 pci_unmap_single(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2597 vp->rx_nocopy++;
2598 }
2599 skb->protocol = eth_type_trans(skb, dev);
2600 { /* Use hardware checksum info. */
2601 int csum_bits = rx_status & 0xee000000;
2602 if (csum_bits &&
2603 (csum_bits == (IPChksumValid | TCPChksumValid) ||
2604 csum_bits == (IPChksumValid | UDPChksumValid))) {
2605 skb->ip_summed = CHECKSUM_UNNECESSARY;
2606 vp->rx_csumhits++;
2607 }
2608 }
2609 netif_rx(skb);
2610 dev->stats.rx_packets++;
2611 }
2612 entry = (++vp->cur_rx) % RX_RING_SIZE;
2613 }
2614 /* Refill the Rx ring buffers. */
2615 for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
2616 struct sk_buff *skb;
2617 entry = vp->dirty_rx % RX_RING_SIZE;
2618 if (vp->rx_skbuff[entry] == NULL) {
2619 skb = netdev_alloc_skb_ip_align(dev, PKT_BUF_SZ);
2620 if (skb == NULL) {
2621 static unsigned long last_jif;
2622 if (time_after(jiffies, last_jif + 10 * HZ)) {
2623 pr_warning("%s: memory shortage\n", dev->name);
2624 last_jif = jiffies;
2625 }
2626 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE)
2627 mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1));
2628 break; /* Bad news! */
2629 }
2630
2631 vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
2632 vp->rx_skbuff[entry] = skb;
2633 }
2634 vp->rx_ring[entry].status = 0; /* Clear complete bit. */
2635 iowrite16(UpUnstall, ioaddr + EL3_CMD);
2636 }
2637 return 0;
2638 }
2639
2640 /*
2641 * If we've hit a total OOM refilling the Rx ring we poll once a second
2642 * for some memory. Otherwise there is no way to restart the rx process.
2643 */
2644 static void
2645 rx_oom_timer(unsigned long arg)
2646 {
2647 struct net_device *dev = (struct net_device *)arg;
2648 struct vortex_private *vp = netdev_priv(dev);
2649
2650 spin_lock_irq(&vp->lock);
2651 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */
2652 boomerang_rx(dev);
2653 if (vortex_debug > 1) {
2654 pr_debug("%s: rx_oom_timer %s\n", dev->name,
2655 ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying");
2656 }
2657 spin_unlock_irq(&vp->lock);
2658 }
2659
2660 static void
2661 vortex_down(struct net_device *dev, int final_down)
2662 {
2663 struct vortex_private *vp = netdev_priv(dev);
2664 void __iomem *ioaddr = vp->ioaddr;
2665
2666 netif_stop_queue (dev);
2667
2668 del_timer_sync(&vp->rx_oom_timer);
2669 del_timer_sync(&vp->timer);
2670
2671 /* Turn off statistics ASAP. We update dev->stats below. */
2672 iowrite16(StatsDisable, ioaddr + EL3_CMD);
2673
2674 /* Disable the receiver and transmitter. */
2675 iowrite16(RxDisable, ioaddr + EL3_CMD);
2676 iowrite16(TxDisable, ioaddr + EL3_CMD);
2677
2678 /* Disable receiving 802.1q tagged frames */
2679 set_8021q_mode(dev, 0);
2680
2681 if (dev->if_port == XCVR_10base2)
2682 /* Turn off thinnet power. Green! */
2683 iowrite16(StopCoax, ioaddr + EL3_CMD);
2684
2685 iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
2686
2687 update_stats(ioaddr, dev);
2688 if (vp->full_bus_master_rx)
2689 iowrite32(0, ioaddr + UpListPtr);
2690 if (vp->full_bus_master_tx)
2691 iowrite32(0, ioaddr + DownListPtr);
2692
2693 if (final_down && VORTEX_PCI(vp)) {
2694 vp->pm_state_valid = 1;
2695 pci_save_state(VORTEX_PCI(vp));
2696 acpi_set_WOL(dev);
2697 }
2698 }
2699
2700 static int
2701 vortex_close(struct net_device *dev)
2702 {
2703 struct vortex_private *vp = netdev_priv(dev);
2704 void __iomem *ioaddr = vp->ioaddr;
2705 int i;
2706
2707 if (netif_device_present(dev))
2708 vortex_down(dev, 1);
2709
2710 if (vortex_debug > 1) {
2711 pr_debug("%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
2712 dev->name, ioread16(ioaddr + EL3_STATUS), ioread8(ioaddr + TxStatus));
2713 pr_debug("%s: vortex close stats: rx_nocopy %d rx_copy %d"
2714 " tx_queued %d Rx pre-checksummed %d.\n",
2715 dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2716 }
2717
2718 #if DO_ZEROCOPY
2719 if (vp->rx_csumhits &&
2720 (vp->drv_flags & HAS_HWCKSM) == 0 &&
2721 (vp->card_idx >= MAX_UNITS || hw_checksums[vp->card_idx] == -1)) {
2722 pr_warning("%s supports hardware checksums, and we're not using them!\n", dev->name);
2723 }
2724 #endif
2725
2726 free_irq(dev->irq, dev);
2727
2728 if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
2729 for (i = 0; i < RX_RING_SIZE; i++)
2730 if (vp->rx_skbuff[i]) {
2731 pci_unmap_single( VORTEX_PCI(vp), le32_to_cpu(vp->rx_ring[i].addr),
2732 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2733 dev_kfree_skb(vp->rx_skbuff[i]);
2734 vp->rx_skbuff[i] = NULL;
2735 }
2736 }
2737 if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
2738 for (i = 0; i < TX_RING_SIZE; i++) {
2739 if (vp->tx_skbuff[i]) {
2740 struct sk_buff *skb = vp->tx_skbuff[i];
2741 #if DO_ZEROCOPY
2742 int k;
2743
2744 for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
2745 pci_unmap_single(VORTEX_PCI(vp),
2746 le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2747 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2748 PCI_DMA_TODEVICE);
2749 #else
2750 pci_unmap_single(VORTEX_PCI(vp), le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE);
2751 #endif
2752 dev_kfree_skb(skb);
2753 vp->tx_skbuff[i] = NULL;
2754 }
2755 }
2756 }
2757
2758 return 0;
2759 }
2760
2761 static void
2762 dump_tx_ring(struct net_device *dev)
2763 {
2764 if (vortex_debug > 0) {
2765 struct vortex_private *vp = netdev_priv(dev);
2766 void __iomem *ioaddr = vp->ioaddr;
2767
2768 if (vp->full_bus_master_tx) {
2769 int i;
2770 int stalled = ioread32(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */
2771
2772 pr_err(" Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
2773 vp->full_bus_master_tx,
2774 vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2775 vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
2776 pr_err(" Transmit list %8.8x vs. %p.\n",
2777 ioread32(ioaddr + DownListPtr),
2778 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2779 issue_and_wait(dev, DownStall);
2780 for (i = 0; i < TX_RING_SIZE; i++) {
2781 unsigned int length;
2782
2783 #if DO_ZEROCOPY
2784 length = le32_to_cpu(vp->tx_ring[i].frag[0].length);
2785 #else
2786 length = le32_to_cpu(vp->tx_ring[i].length);
2787 #endif
2788 pr_err(" %d: @%p length %8.8x status %8.8x\n",
2789 i, &vp->tx_ring[i], length,
2790 le32_to_cpu(vp->tx_ring[i].status));
2791 }
2792 if (!stalled)
2793 iowrite16(DownUnstall, ioaddr + EL3_CMD);
2794 }
2795 }
2796 }
2797
2798 static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2799 {
2800 struct vortex_private *vp = netdev_priv(dev);
2801 void __iomem *ioaddr = vp->ioaddr;
2802 unsigned long flags;
2803
2804 if (netif_device_present(dev)) { /* AKPM: Used to be netif_running */
2805 spin_lock_irqsave (&vp->lock, flags);
2806 update_stats(ioaddr, dev);
2807 spin_unlock_irqrestore (&vp->lock, flags);
2808 }
2809 return &dev->stats;
2810 }
2811
2812 /* Update statistics.
2813 Unlike with the EL3 we need not worry about interrupts changing
2814 the window setting from underneath us, but we must still guard
2815 against a race condition with a StatsUpdate interrupt updating the
2816 table. This is done by checking that the ASM (!) code generated uses
2817 atomic updates with '+='.
2818 */
2819 static void update_stats(void __iomem *ioaddr, struct net_device *dev)
2820 {
2821 struct vortex_private *vp = netdev_priv(dev);
2822
2823 /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
2824 /* Switch to the stats window, and read everything. */
2825 dev->stats.tx_carrier_errors += window_read8(vp, 6, 0);
2826 dev->stats.tx_heartbeat_errors += window_read8(vp, 6, 1);
2827 dev->stats.tx_window_errors += window_read8(vp, 6, 4);
2828 dev->stats.rx_fifo_errors += window_read8(vp, 6, 5);
2829 dev->stats.tx_packets += window_read8(vp, 6, 6);
2830 dev->stats.tx_packets += (window_read8(vp, 6, 9) &
2831 0x30) << 4;
2832 /* Rx packets */ window_read8(vp, 6, 7); /* Must read to clear */
2833 /* Don't bother with register 9, an extension of registers 6&7.
2834 If we do use the 6&7 values the atomic update assumption above
2835 is invalid. */
2836 dev->stats.rx_bytes += window_read16(vp, 6, 10);
2837 dev->stats.tx_bytes += window_read16(vp, 6, 12);
2838 /* Extra stats for get_ethtool_stats() */
2839 vp->xstats.tx_multiple_collisions += window_read8(vp, 6, 2);
2840 vp->xstats.tx_single_collisions += window_read8(vp, 6, 3);
2841 vp->xstats.tx_deferred += window_read8(vp, 6, 8);
2842 vp->xstats.rx_bad_ssd += window_read8(vp, 4, 12);
2843
2844 dev->stats.collisions = vp->xstats.tx_multiple_collisions
2845 + vp->xstats.tx_single_collisions
2846 + vp->xstats.tx_max_collisions;
2847
2848 {
2849 u8 up = window_read8(vp, 4, 13);
2850 dev->stats.rx_bytes += (up & 0x0f) << 16;
2851 dev->stats.tx_bytes += (up & 0xf0) << 12;
2852 }
2853 }
2854
2855 static int vortex_nway_reset(struct net_device *dev)
2856 {
2857 struct vortex_private *vp = netdev_priv(dev);
2858
2859 return mii_nway_restart(&vp->mii);
2860 }
2861
2862 static int vortex_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2863 {
2864 struct vortex_private *vp = netdev_priv(dev);
2865
2866 return mii_ethtool_gset(&vp->mii, cmd);
2867 }
2868
2869 static int vortex_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2870 {
2871 struct vortex_private *vp = netdev_priv(dev);
2872
2873 return mii_ethtool_sset(&vp->mii, cmd);
2874 }
2875
2876 static u32 vortex_get_msglevel(struct net_device *dev)
2877 {
2878 return vortex_debug;
2879 }
2880
2881 static void vortex_set_msglevel(struct net_device *dev, u32 dbg)
2882 {
2883 vortex_debug = dbg;
2884 }
2885
2886 static int vortex_get_sset_count(struct net_device *dev, int sset)
2887 {
2888 switch (sset) {
2889 case ETH_SS_STATS:
2890 return VORTEX_NUM_STATS;
2891 default:
2892 return -EOPNOTSUPP;
2893 }
2894 }
2895
2896 static void vortex_get_ethtool_stats(struct net_device *dev,
2897 struct ethtool_stats *stats, u64 *data)
2898 {
2899 struct vortex_private *vp = netdev_priv(dev);
2900 void __iomem *ioaddr = vp->ioaddr;
2901 unsigned long flags;
2902
2903 spin_lock_irqsave(&vp->lock, flags);
2904 update_stats(ioaddr, dev);
2905 spin_unlock_irqrestore(&vp->lock, flags);
2906
2907 data[0] = vp->xstats.tx_deferred;
2908 data[1] = vp->xstats.tx_max_collisions;
2909 data[2] = vp->xstats.tx_multiple_collisions;
2910 data[3] = vp->xstats.tx_single_collisions;
2911 data[4] = vp->xstats.rx_bad_ssd;
2912 }
2913
2914
2915 static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2916 {
2917 switch (stringset) {
2918 case ETH_SS_STATS:
2919 memcpy(data, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
2920 break;
2921 default:
2922 WARN_ON(1);
2923 break;
2924 }
2925 }
2926
2927 static void vortex_get_drvinfo(struct net_device *dev,
2928 struct ethtool_drvinfo *info)
2929 {
2930 struct vortex_private *vp = netdev_priv(dev);
2931
2932 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2933 if (VORTEX_PCI(vp)) {
2934 strlcpy(info->bus_info, pci_name(VORTEX_PCI(vp)),
2935 sizeof(info->bus_info));
2936 } else {
2937 if (VORTEX_EISA(vp))
2938 strlcpy(info->bus_info, dev_name(vp->gendev),
2939 sizeof(info->bus_info));
2940 else
2941 snprintf(info->bus_info, sizeof(info->bus_info),
2942 "EISA 0x%lx %d", dev->base_addr, dev->irq);
2943 }
2944 }
2945
2946 static void vortex_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2947 {
2948 struct vortex_private *vp = netdev_priv(dev);
2949
2950 if (!VORTEX_PCI(vp))
2951 return;
2952
2953 wol->supported = WAKE_MAGIC;
2954
2955 wol->wolopts = 0;
2956 if (vp->enable_wol)
2957 wol->wolopts |= WAKE_MAGIC;
2958 }
2959
2960 static int vortex_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2961 {
2962 struct vortex_private *vp = netdev_priv(dev);
2963
2964 if (!VORTEX_PCI(vp))
2965 return -EOPNOTSUPP;
2966
2967 if (wol->wolopts & ~WAKE_MAGIC)
2968 return -EINVAL;
2969
2970 if (wol->wolopts & WAKE_MAGIC)
2971 vp->enable_wol = 1;
2972 else
2973 vp->enable_wol = 0;
2974 acpi_set_WOL(dev);
2975
2976 return 0;
2977 }
2978
2979 static const struct ethtool_ops vortex_ethtool_ops = {
2980 .get_drvinfo = vortex_get_drvinfo,
2981 .get_strings = vortex_get_strings,
2982 .get_msglevel = vortex_get_msglevel,
2983 .set_msglevel = vortex_set_msglevel,
2984 .get_ethtool_stats = vortex_get_ethtool_stats,
2985 .get_sset_count = vortex_get_sset_count,
2986 .get_settings = vortex_get_settings,
2987 .set_settings = vortex_set_settings,
2988 .get_link = ethtool_op_get_link,
2989 .nway_reset = vortex_nway_reset,
2990 .get_wol = vortex_get_wol,
2991 .set_wol = vortex_set_wol,
2992 };
2993
2994 #ifdef CONFIG_PCI
2995 /*
2996 * Must power the device up to do MDIO operations
2997 */
2998 static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2999 {
3000 int err;
3001 struct vortex_private *vp = netdev_priv(dev);
3002 pci_power_t state = 0;
3003
3004 if(VORTEX_PCI(vp))
3005 state = VORTEX_PCI(vp)->current_state;
3006
3007 /* The kernel core really should have pci_get_power_state() */
3008
3009 if(state != 0)
3010 pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
3011 err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
3012 if(state != 0)
3013 pci_set_power_state(VORTEX_PCI(vp), state);
3014
3015 return err;
3016 }
3017 #endif
3018
3019
3020 /* Pre-Cyclone chips have no documented multicast filter, so the only
3021 multicast setting is to receive all multicast frames. At least
3022 the chip has a very clean way to set the mode, unlike many others. */
3023 static void set_rx_mode(struct net_device *dev)
3024 {
3025 struct vortex_private *vp = netdev_priv(dev);
3026 void __iomem *ioaddr = vp->ioaddr;
3027 int new_mode;
3028
3029 if (dev->flags & IFF_PROMISC) {
3030 if (vortex_debug > 3)
3031 pr_notice("%s: Setting promiscuous mode.\n", dev->name);
3032 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
3033 } else if (!netdev_mc_empty(dev) || dev->flags & IFF_ALLMULTI) {
3034 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
3035 } else
3036 new_mode = SetRxFilter | RxStation | RxBroadcast;
3037
3038 iowrite16(new_mode, ioaddr + EL3_CMD);
3039 }
3040
3041 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
3042 /* Setup the card so that it can receive frames with an 802.1q VLAN tag.
3043 Note that this must be done after each RxReset due to some backwards
3044 compatibility logic in the Cyclone and Tornado ASICs */
3045
3046 /* The Ethernet Type used for 802.1q tagged frames */
3047 #define VLAN_ETHER_TYPE 0x8100
3048
3049 static void set_8021q_mode(struct net_device *dev, int enable)
3050 {
3051 struct vortex_private *vp = netdev_priv(dev);
3052 int mac_ctrl;
3053
3054 if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
3055 /* cyclone and tornado chipsets can recognize 802.1q
3056 * tagged frames and treat them correctly */
3057
3058 int max_pkt_size = dev->mtu+14; /* MTU+Ethernet header */
3059 if (enable)
3060 max_pkt_size += 4; /* 802.1Q VLAN tag */
3061
3062 window_write16(vp, max_pkt_size, 3, Wn3_MaxPktSize);
3063
3064 /* set VlanEtherType to let the hardware checksumming
3065 treat tagged frames correctly */
3066 window_write16(vp, VLAN_ETHER_TYPE, 7, Wn7_VlanEtherType);
3067 } else {
3068 /* on older cards we have to enable large frames */
3069
3070 vp->large_frames = dev->mtu > 1500 || enable;
3071
3072 mac_ctrl = window_read16(vp, 3, Wn3_MAC_Ctrl);
3073 if (vp->large_frames)
3074 mac_ctrl |= 0x40;
3075 else
3076 mac_ctrl &= ~0x40;
3077 window_write16(vp, mac_ctrl, 3, Wn3_MAC_Ctrl);
3078 }
3079 }
3080 #else
3081
3082 static void set_8021q_mode(struct net_device *dev, int enable)
3083 {
3084 }
3085
3086
3087 #endif
3088
3089 /* MII transceiver control section.
3090 Read and write the MII registers using software-generated serial
3091 MDIO protocol. See the MII specifications or DP83840A data sheet
3092 for details. */
3093
3094 /* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
3095 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
3096 "overclocking" issues. */
3097 static void mdio_delay(struct vortex_private *vp)
3098 {
3099 window_read32(vp, 4, Wn4_PhysicalMgmt);
3100 }
3101
3102 #define MDIO_SHIFT_CLK 0x01
3103 #define MDIO_DIR_WRITE 0x04
3104 #define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
3105 #define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
3106 #define MDIO_DATA_READ 0x02
3107 #define MDIO_ENB_IN 0x00
3108
3109 /* Generate the preamble required for initial synchronization and
3110 a few older transceivers. */
3111 static void mdio_sync(struct vortex_private *vp, int bits)
3112 {
3113 /* Establish sync by sending at least 32 logic ones. */
3114 while (-- bits >= 0) {
3115 window_write16(vp, MDIO_DATA_WRITE1, 4, Wn4_PhysicalMgmt);
3116 mdio_delay(vp);
3117 window_write16(vp, MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK,
3118 4, Wn4_PhysicalMgmt);
3119 mdio_delay(vp);
3120 }
3121 }
3122
3123 static int mdio_read(struct net_device *dev, int phy_id, int location)
3124 {
3125 int i;
3126 struct vortex_private *vp = netdev_priv(dev);
3127 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
3128 unsigned int retval = 0;
3129
3130 spin_lock_bh(&vp->mii_lock);
3131
3132 if (mii_preamble_required)
3133 mdio_sync(vp, 32);
3134
3135 /* Shift the read command bits out. */
3136 for (i = 14; i >= 0; i--) {
3137 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3138 window_write16(vp, dataval, 4, Wn4_PhysicalMgmt);
3139 mdio_delay(vp);
3140 window_write16(vp, dataval | MDIO_SHIFT_CLK,
3141 4, Wn4_PhysicalMgmt);
3142 mdio_delay(vp);
3143 }
3144 /* Read the two transition, 16 data, and wire-idle bits. */
3145 for (i = 19; i > 0; i--) {
3146 window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt);
3147 mdio_delay(vp);
3148 retval = (retval << 1) |
3149 ((window_read16(vp, 4, Wn4_PhysicalMgmt) &
3150 MDIO_DATA_READ) ? 1 : 0);
3151 window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK,
3152 4, Wn4_PhysicalMgmt);
3153 mdio_delay(vp);
3154 }
3155
3156 spin_unlock_bh(&vp->mii_lock);
3157
3158 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3159 }
3160
3161 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3162 {
3163 struct vortex_private *vp = netdev_priv(dev);
3164 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
3165 int i;
3166
3167 spin_lock_bh(&vp->mii_lock);
3168
3169 if (mii_preamble_required)
3170 mdio_sync(vp, 32);
3171
3172 /* Shift the command bits out. */
3173 for (i = 31; i >= 0; i--) {
3174 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3175 window_write16(vp, dataval, 4, Wn4_PhysicalMgmt);
3176 mdio_delay(vp);
3177 window_write16(vp, dataval | MDIO_SHIFT_CLK,
3178 4, Wn4_PhysicalMgmt);
3179 mdio_delay(vp);
3180 }
3181 /* Leave the interface idle. */
3182 for (i = 1; i >= 0; i--) {
3183 window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt);
3184 mdio_delay(vp);
3185 window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK,
3186 4, Wn4_PhysicalMgmt);
3187 mdio_delay(vp);
3188 }
3189
3190 spin_unlock_bh(&vp->mii_lock);
3191 }
3192
3193 /* ACPI: Advanced Configuration and Power Interface. */
3194 /* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */
3195 static void acpi_set_WOL(struct net_device *dev)
3196 {
3197 struct vortex_private *vp = netdev_priv(dev);
3198 void __iomem *ioaddr = vp->ioaddr;
3199
3200 device_set_wakeup_enable(vp->gendev, vp->enable_wol);
3201
3202 if (vp->enable_wol) {
3203 /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
3204 window_write16(vp, 2, 7, 0x0c);
3205 /* The RxFilter must accept the WOL frames. */
3206 iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3207 iowrite16(RxEnable, ioaddr + EL3_CMD);
3208
3209 if (pci_enable_wake(VORTEX_PCI(vp), PCI_D3hot, 1)) {
3210 pr_info("%s: WOL not supported.\n", pci_name(VORTEX_PCI(vp)));
3211
3212 vp->enable_wol = 0;
3213 return;
3214 }
3215
3216 if (VORTEX_PCI(vp)->current_state < PCI_D3hot)
3217 return;
3218
3219 /* Change the power state to D3; RxEnable doesn't take effect. */
3220 pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
3221 }
3222 }
3223
3224
3225 static void __devexit vortex_remove_one(struct pci_dev *pdev)
3226 {
3227 struct net_device *dev = pci_get_drvdata(pdev);
3228 struct vortex_private *vp;
3229
3230 if (!dev) {
3231 pr_err("vortex_remove_one called for Compaq device!\n");
3232 BUG();
3233 }
3234
3235 vp = netdev_priv(dev);
3236
3237 if (vp->cb_fn_base)
3238 pci_iounmap(VORTEX_PCI(vp), vp->cb_fn_base);
3239
3240 unregister_netdev(dev);
3241
3242 if (VORTEX_PCI(vp)) {
3243 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3244 if (vp->pm_state_valid)
3245 pci_restore_state(VORTEX_PCI(vp));
3246 pci_disable_device(VORTEX_PCI(vp));
3247 }
3248 /* Should really use issue_and_wait() here */
3249 iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14),
3250 vp->ioaddr + EL3_CMD);
3251
3252 pci_iounmap(VORTEX_PCI(vp), vp->ioaddr);
3253
3254 pci_free_consistent(pdev,
3255 sizeof(struct boom_rx_desc) * RX_RING_SIZE
3256 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
3257 vp->rx_ring,
3258 vp->rx_ring_dma);
3259
3260 pci_release_regions(pdev);
3261
3262 free_netdev(dev);
3263 }
3264
3265
3266 static struct pci_driver vortex_driver = {
3267 .name = "3c59x",
3268 .probe = vortex_init_one,
3269 .remove = __devexit_p(vortex_remove_one),
3270 .id_table = vortex_pci_tbl,
3271 .driver.pm = VORTEX_PM_OPS,
3272 };
3273
3274
3275 static int vortex_have_pci;
3276 static int vortex_have_eisa;
3277
3278
3279 static int __init vortex_init(void)
3280 {
3281 int pci_rc, eisa_rc;
3282
3283 pci_rc = pci_register_driver(&vortex_driver);
3284 eisa_rc = vortex_eisa_init();
3285
3286 if (pci_rc == 0)
3287 vortex_have_pci = 1;
3288 if (eisa_rc > 0)
3289 vortex_have_eisa = 1;
3290
3291 return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
3292 }
3293
3294
3295 static void __exit vortex_eisa_cleanup(void)
3296 {
3297 struct vortex_private *vp;
3298 void __iomem *ioaddr;
3299
3300 #ifdef CONFIG_EISA
3301 /* Take care of the EISA devices */
3302 eisa_driver_unregister(&vortex_eisa_driver);
3303 #endif
3304
3305 if (compaq_net_device) {
3306 vp = netdev_priv(compaq_net_device);
3307 ioaddr = ioport_map(compaq_net_device->base_addr,
3308 VORTEX_TOTAL_SIZE);
3309
3310 unregister_netdev(compaq_net_device);
3311 iowrite16(TotalReset, ioaddr + EL3_CMD);
3312 release_region(compaq_net_device->base_addr,
3313 VORTEX_TOTAL_SIZE);
3314
3315 free_netdev(compaq_net_device);
3316 }
3317 }
3318
3319
3320 static void __exit vortex_cleanup(void)
3321 {
3322 if (vortex_have_pci)
3323 pci_unregister_driver(&vortex_driver);
3324 if (vortex_have_eisa)
3325 vortex_eisa_cleanup();
3326 }
3327
3328
3329 module_init(vortex_init);
3330 module_exit(vortex_cleanup);
Linux with added FPC-III support