drivers/net/ethernet/amd/ni65.h

   1 /* am7990 (lance) definitions
   2  *
   3  * This is an extension to the Linux operating system, and is covered by
   4  * same GNU General Public License that covers that work.
   5  *
   6  * Michael Hipp
   7  * email: mhipp@student.uni-tuebingen.de
   8  *
   9  * sources: (mail me or ask archie if you need them)
  10  *    crynwr-packet-driver
  11  */
  12
  13 /*
  14  *      Control and Status Register 0 (CSR0) bit definitions
  15  * (R=Readable) (W=Writeable) (S=Set on write) (C-Clear on write)
  16  *
  17  */
  18
  19 #define CSR0_ERR        0x8000  /* Error summary (R) */
  20 #define CSR0_BABL       0x4000  /* Babble transmitter timeout error (RC) */
  21 #define CSR0_CERR       0x2000  /* Collision Error (RC) */
  22 #define CSR0_MISS       0x1000  /* Missed packet (RC) */
  23 #define CSR0_MERR       0x0800  /* Memory Error (RC) */
  24 #define CSR0_RINT       0x0400  /* Receiver Interrupt (RC) */
  25 #define CSR0_TINT       0x0200  /* Transmit Interrupt (RC) */
  26 #define CSR0_IDON       0x0100  /* Initialization Done (RC) */
  27 #define CSR0_INTR       0x0080  /* Interrupt Flag (R) */
  28 #define CSR0_INEA       0x0040  /* Interrupt Enable (RW) */
  29 #define CSR0_RXON       0x0020  /* Receiver on (R) */
  30 #define CSR0_TXON       0x0010  /* Transmitter on (R) */
  31 #define CSR0_TDMD       0x0008  /* Transmit Demand (RS) */
  32 #define CSR0_STOP       0x0004  /* Stop (RS) */
  33 #define CSR0_STRT       0x0002  /* Start (RS) */
  34 #define CSR0_INIT       0x0001  /* Initialize (RS) */
  35
  36 #define CSR0_CLRALL    0x7f00   /* mask for all clearable bits */
  37 /*
  38  *      Initialization Block  Mode operation Bit Definitions.
  39  */
  40
  41 #define M_PROM          0x8000  /* Promiscuous Mode */
  42 #define M_INTL          0x0040  /* Internal Loopback */
  43 #define M_DRTY          0x0020  /* Disable Retry */
  44 #define M_COLL          0x0010  /* Force Collision */
  45 #define M_DTCR          0x0008  /* Disable Transmit CRC) */
  46 #define M_LOOP          0x0004  /* Loopback */
  47 #define M_DTX           0x0002  /* Disable the Transmitter */
  48 #define M_DRX           0x0001  /* Disable the Receiver */
  49
  50
  51 /*
  52  *      Receive message descriptor bit definitions.
  53  */
  54
  55 #define RCV_OWN         0x80    /* owner bit 0 = host, 1 = lance */
  56 #define RCV_ERR         0x40    /* Error Summary */
  57 #define RCV_FRAM        0x20    /* Framing Error */
  58 #define RCV_OFLO        0x10    /* Overflow Error */
  59 #define RCV_CRC         0x08    /* CRC Error */
  60 #define RCV_BUF_ERR     0x04    /* Buffer Error */
  61 #define RCV_START       0x02    /* Start of Packet */
  62 #define RCV_END         0x01    /* End of Packet */
  63
  64
  65 /*
  66  *      Transmit  message descriptor bit definitions.
  67  */
  68
  69 #define XMIT_OWN        0x80    /* owner bit 0 = host, 1 = lance */
  70 #define XMIT_ERR        0x40    /* Error Summary */
  71 #define XMIT_RETRY      0x10    /* more the 1 retry needed to Xmit */
  72 #define XMIT_1_RETRY    0x08    /* one retry needed to Xmit */
  73 #define XMIT_DEF        0x04    /* Deferred */
  74 #define XMIT_START      0x02    /* Start of Packet */
  75 #define XMIT_END        0x01    /* End of Packet */
  76
  77 /*
  78  * transmit status (2) (valid if XMIT_ERR == 1)
  79  */
  80
  81 #define XMIT_TDRMASK    0x03ff  /* time-domain-reflectometer-value */
  82 #define XMIT_RTRY       0x0400  /* Failed after 16 retransmissions  */
  83 #define XMIT_LCAR       0x0800  /* Loss of Carrier */
  84 #define XMIT_LCOL       0x1000  /* Late collision */
  85 #define XMIT_RESERV     0x2000  /* Reserved */
  86 #define XMIT_UFLO       0x4000  /* Underflow (late memory) */
  87 #define XMIT_BUFF       0x8000  /* Buffering error (no ENP) */
  88
  89 struct init_block {
  90         unsigned short mode;
  91         unsigned char eaddr[6];
  92         unsigned char filter[8];
  93         /* bit 29-31: number of rmd's (power of 2) */
  94         u32 rrp;                /* receive ring pointer (align 8) */
  95         /* bit 29-31: number of tmd's (power of 2) */
  96         u32 trp;                /* transmit ring pointer (align 8) */
  97 };
  98
  99 struct rmd {                    /* Receive Message Descriptor */
 100         union {
 101                 volatile u32 buffer;
 102                 struct {
 103                         volatile unsigned char dummy[3];
 104                         volatile unsigned char status;
 105                 } s;
 106         } u;
 107         volatile short blen;
 108         volatile unsigned short mlen;
 109 };
 110
 111 struct tmd {
 112         union {
 113                 volatile u32 buffer;
 114                 struct {
 115                         volatile unsigned char dummy[3];
 116                         volatile unsigned char status;
 117                 } s;
 118         } u;
 119         volatile unsigned short blen;
 120         volatile unsigned short status2;
 121 };