| blob | 64392ec410a3898b3b4372523db4a19d3614b390 |
1 /* Copyright 2008-2012 Broadcom Corporation
2 *
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
7 *
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
11 * consent.
12 *
13 * Written by Yaniv Rosner
14 *
15 */
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/delay.h>
24 #include <linux/ethtool.h>
25 #include <linux/mutex.h>
30 /********************************************************/
31 #define ETH_HLEN 14
32 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
33 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
34 #define ETH_MIN_PACKET_SIZE 60
35 #define ETH_MAX_PACKET_SIZE 1500
36 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
37 #define MDIO_ACCESS_TIMEOUT 1000
38 #define WC_LANE_MAX 4
39 #define I2C_SWITCH_WIDTH 2
40 #define I2C_BSC0 0
41 #define I2C_BSC1 1
42 #define I2C_WA_RETRY_CNT 3
43 #define MCPR_IMC_COMMAND_READ_OP 1
44 #define MCPR_IMC_COMMAND_WRITE_OP 2
46 /* LED Blink rate that will achieve ~15.9Hz */
47 #define LED_BLINK_RATE_VAL_E3 354
48 #define LED_BLINK_RATE_VAL_E1X_E2 480
49 /***********************************************************/
50 /* Shortcut definitions */
51 /***********************************************************/
53 #define NIG_LATCH_BC_ENABLE_MI_INT 0
55 #define NIG_STATUS_EMAC0_MI_INT \
56 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
57 #define NIG_STATUS_XGXS0_LINK10G \
58 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
59 #define NIG_STATUS_XGXS0_LINK_STATUS \
60 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
61 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
62 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
63 #define NIG_STATUS_SERDES0_LINK_STATUS \
64 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
65 #define NIG_MASK_MI_INT \
66 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
67 #define NIG_MASK_XGXS0_LINK10G \
68 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
69 #define NIG_MASK_XGXS0_LINK_STATUS \
70 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
71 #define NIG_MASK_SERDES0_LINK_STATUS \
72 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
74 #define MDIO_AN_CL73_OR_37_COMPLETE \
75 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
76 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
78 #define XGXS_RESET_BITS \
79 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
80 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
81 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
82 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
83 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
85 #define SERDES_RESET_BITS \
86 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
87 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
88 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
89 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
91 #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
92 #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
93 #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
94 #define AUTONEG_PARALLEL \
95 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
96 #define AUTONEG_SGMII_FIBER_AUTODET \
97 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
98 #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
100 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
101 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
102 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
103 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
104 #define GP_STATUS_SPEED_MASK \
105 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
106 #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
107 #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
108 #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
109 #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
110 #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
111 #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
112 #define GP_STATUS_10G_HIG \
113 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
114 #define GP_STATUS_10G_CX4 \
115 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
116 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
117 #define GP_STATUS_10G_KX4 \
118 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
119 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
120 #define GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
121 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
122 #define GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
123 #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
124 #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
125 #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
126 #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
127 #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
128 #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
129 #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
130 #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
131 #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
132 #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
133 #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
134 #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
135 #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
136 #define LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
137 #define LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
141 /* */
142 #define SFP_EEPROM_CON_TYPE_ADDR 0x2
143 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
144 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
147 #define SFP_EEPROM_COMP_CODE_ADDR 0x3
148 #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
149 #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
150 #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
152 #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
153 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
154 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
156 #define SFP_EEPROM_OPTIONS_ADDR 0x40
157 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
158 #define SFP_EEPROM_OPTIONS_SIZE 2
160 #define EDC_MODE_LINEAR 0x0022
161 #define EDC_MODE_LIMITING 0x0044
162 #define EDC_MODE_PASSIVE_DAC 0x0055
164 /* BRB default for class 0 E2 */
165 #define DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR 170
166 #define DEFAULT0_E2_BRB_MAC_PAUSE_XON_THR 250
167 #define DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR 10
168 #define DEFAULT0_E2_BRB_MAC_FULL_XON_THR 50
170 /* BRB thresholds for E2*/
171 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE 170
172 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
174 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE 250
175 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
177 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE 10
178 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 90
180 #define PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE 50
181 #define PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE 250
183 /* BRB default for class 0 E3A0 */
184 #define DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR 290
185 #define DEFAULT0_E3A0_BRB_MAC_PAUSE_XON_THR 410
186 #define DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR 10
187 #define DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR 50
189 /* BRB thresholds for E3A0 */
190 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE 290
191 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
193 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE 410
194 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
196 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE 10
197 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 170
199 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE 50
200 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE 410
202 /* BRB default for E3B0 */
203 #define DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR 330
204 #define DEFAULT0_E3B0_BRB_MAC_PAUSE_XON_THR 490
205 #define DEFAULT0_E3B0_BRB_MAC_FULL_XOFF_THR 15
206 #define DEFAULT0_E3B0_BRB_MAC_FULL_XON_THR 55
208 /* BRB thresholds for E3B0 2 port mode*/
209 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 1025
210 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
212 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE 1025
213 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
215 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE 10
216 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 1025
218 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE 50
219 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE 1025
221 /* only for E3B0*/
222 #define PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR 1025
223 #define PFC_E3B0_2P_BRB_FULL_LB_XON_THR 1025
225 /* Lossy +Lossless GUARANTIED == GUART */
226 #define PFC_E3B0_2P_MIX_PAUSE_LB_GUART 284
227 /* Lossless +Lossless*/
228 #define PFC_E3B0_2P_PAUSE_LB_GUART 236
229 /* Lossy +Lossy*/
230 #define PFC_E3B0_2P_NON_PAUSE_LB_GUART 342
232 /* Lossy +Lossless*/
233 #define PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART 284
234 /* Lossless +Lossless*/
235 #define PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART 236
236 /* Lossy +Lossy*/
237 #define PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART 336
238 #define PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST 80
240 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART 0
241 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST 0
243 /* BRB thresholds for E3B0 4 port mode */
244 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 304
245 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
247 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE 384
248 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
250 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE 10
251 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 304
253 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE 50
254 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE 384
256 /* only for E3B0*/
257 #define PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR 304
258 #define PFC_E3B0_4P_BRB_FULL_LB_XON_THR 384
259 #define PFC_E3B0_4P_LB_GUART 120
261 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART 120
262 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST 80
264 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART 80
265 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST 120
267 /* Pause defines*/
268 #define DEFAULT_E3B0_BRB_FULL_LB_XOFF_THR 330
269 #define DEFAULT_E3B0_BRB_FULL_LB_XON_THR 490
270 #define DEFAULT_E3B0_LB_GUART 40
272 #define DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART 40
273 #define DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART_HYST 0
275 #define DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART 40
276 #define DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART_HYST 0
278 /* ETS defines*/
279 #define DCBX_INVALID_COS (0xFF)
281 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
282 #define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000)
283 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360)
284 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720)
285 #define ETS_E3B0_PBF_MIN_W_VAL (10000)
287 #define MAX_PACKET_SIZE (9700)
288 #define WC_UC_TIMEOUT 100
289 #define MAX_KR_LINK_RETRY 4
291 /**********************************************************/
292 /* INTERFACE */
293 /**********************************************************/
295 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
296 bnx2x_cl45_write(_bp, _phy, \
297 (_phy)->def_md_devad, \
298 (_bank + (_addr & 0xf)), \
299 _val)
301 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
302 bnx2x_cl45_read(_bp, _phy, \
303 (_phy)->def_md_devad, \
304 (_bank + (_addr & 0xf)), \
305 _val)
308 {
314 }
317 {
323 }
325 /******************************************************************/
326 /* EPIO/GPIO section */
327 /******************************************************************/
329 {
332 /* Sanity check */
336 }
339 /* Set this EPIO to output */
344 }
346 {
349 /* Sanity check */
353 }
356 /* Set this EPIO to output */
360 else
365 /* Set the value for this EPIO */
368 }
371 {
380 }
381 }
384 {
393 }
396 }
397 /******************************************************************/
398 /* ETS section */
399 /******************************************************************/
401 {
402 /* ETS disabled configuration*/
407 /*
408 * mapping between entry priority to client number (0,1,2 -debug and
409 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
410 * 3bits client num.
411 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
412 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000
413 */
416 /*
417 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
418 * as strict. Bits 0,1,2 - debug and management entries, 3 -
419 * COS0 entry, 4 - COS1 entry.
420 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
421 * bit4 bit3 bit2 bit1 bit0
422 * MCP and debug are strict
423 */
426 /* defines which entries (clients) are subjected to WFQ arbitration */
428 /*
429 * For strict priority entries defines the number of consecutive
430 * slots for the highest priority.
431 */
433 /*
434 * mapping between the CREDIT_WEIGHT registers and actual client
435 * numbers
436 */
444 /* ETS mode disable */
446 /*
447 * If ETS mode is enabled (there is no strict priority) defines a WFQ
448 * weight for COS0/COS1.
449 */
452 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
455 /* Defines the number of consecutive slots for the strict priority */
457 }
458 /******************************************************************************
459 * Description:
460 * Getting min_w_val will be set according to line speed .
461 *.
462 ******************************************************************************/
464 {
466 /* Calculate min_w_val.*/
470 else
474 /**
475 * If the link isn't up (static configuration for example ) The
476 * link will be according to 20GBPS.
477 */
479 }
480 /******************************************************************************
481 * Description:
482 * Getting credit upper bound form min_w_val.
483 *.
484 ******************************************************************************/
486 {
488 MAX_PACKET_SIZE);
490 }
491 /******************************************************************************
492 * Description:
493 * Set credit upper bound for NIG.
494 *.
495 ******************************************************************************/
499 {
520 credit_upper_bound);
522 credit_upper_bound);
524 credit_upper_bound);
525 }
526 }
527 /******************************************************************************
528 * Description:
529 * Will return the NIG ETS registers to init values.Except
530 * credit_upper_bound.
531 * That isn't used in this configuration (No WFQ is enabled) and will be
532 * configured acording to spec
533 *.
534 ******************************************************************************/
537 {
541 /**
542 * mapping between entry priority to client number (0,1,2 -debug and
543 * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
544 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
545 * reset value or init tool
546 */
553 }
554 /**
555 * For strict priority entries defines the number of consecutive
556 * slots for the highest priority.
557 */
558 /* TODO_ETS - Should be done by reset value or init tool */
561 /**
562 * mapping between the CREDIT_WEIGHT registers and actual client
563 * numbers
564 */
565 /* TODO_ETS - Should be done by reset value or init tool */
567 /*Port 1 has 6 COS*/
571 /*Port 0 has 9 COS*/
575 }
577 /**
578 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
579 * as strict. Bits 0,1,2 - debug and management entries, 3 -
580 * COS0 entry, 4 - COS1 entry.
581 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
582 * bit4 bit3 bit2 bit1 bit0
583 * MCP and debug are strict
584 */
587 else
589 /* defines which entries (clients) are subjected to WFQ arbitration */
593 /**
594 * Please notice the register address are note continuous and a
595 * for here is note appropriate.In 2 port mode port0 only COS0-5
596 * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
597 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
598 * are never used for WFQ
599 */
616 }
619 }
620 /******************************************************************************
621 * Description:
622 * Set credit upper bound for PBF.
623 *.
624 ******************************************************************************/
628 {
636 /**
637 * In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
638 * port mode port1 has COS0-2 that can be used for WFQ.
639 */
646 }
650 }
652 /******************************************************************************
653 * Description:
654 * Will return the PBF ETS registers to init values.Except
655 * credit_upper_bound.
656 * That isn't used in this configuration (No WFQ is enabled) and will be
657 * configured acording to spec
658 *.
659 ******************************************************************************/
661 {
669 /**
670 * mapping between entry priority to client number 0 - COS0
671 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
672 * TODO_ETS - Should be done by reset value or init tool
673 */
675 /* 0x688 (|011|0 10|00 1|000) */
677 else
678 /* (10 1|100 |011|0 10|00 1|000) */
681 /* TODO_ETS - Should be done by reset value or init tool */
683 /* 0x688 (|011|0 10|00 1|000)*/
685 else
686 /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
698 /**
699 * In 2 port mode port0 has COS0-5 that can be used for WFQ.
700 * In 4 port mode port1 has COS0-2 that can be used for WFQ.
701 */
708 }
714 }
715 /******************************************************************************
716 * Description:
717 * E3B0 disable will return basicly the values to init values.
718 *.
719 ******************************************************************************/
722 {
729 }
736 }
738 /******************************************************************************
739 * Description:
740 * Disable will return basicly the values to init values.
741 *.
742 ******************************************************************************/
745 {
756 }
759 }
761 /******************************************************************************
762 * Description
763 * Set the COS mappimg to SP and BW until this point all the COS are not
764 * set as SP or BW.
765 ******************************************************************************/
770 {
785 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
786 nig_cli_subject2wfq_bitmap);
789 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
790 pbf_cli_subject2wfq_bitmap);
793 }
795 /******************************************************************************
796 * Description:
797 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
798 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
799 ******************************************************************************/
807 {
810 /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
816 nig_reg_adress_crd_weight =
818 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
824 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
825 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
831 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
832 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
840 nig_reg_adress_crd_weight =
841 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
842 pbf_reg_adress_crd_weight =
843 PBF_REG_COS3_WEIGHT_P0;
848 nig_reg_adress_crd_weight =
849 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
855 nig_reg_adress_crd_weight =
856 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
859 }
866 }
867 /******************************************************************************
868 * Description:
869 * Calculate the total BW.A value of 0 isn't legal.
870 *.
871 ******************************************************************************/
876 {
883 /* Calculate total BW requested */
890 /*
891 * This is to prevent a state when ramrods
892 * can't be sent
893 */
896 }
899 }
900 }
902 /* Check total BW is valid */
908 }
911 /*
912 * We can handle a case whre the BW isn't 100 this can happen
913 * if the TC are joined.
914 */
915 }
917 }
919 /******************************************************************************
920 * Description:
921 * Invalidate all the sp_pri_to_cos.
922 *.
923 ******************************************************************************/
925 {
929 }
930 /******************************************************************************
931 * Description:
932 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
933 * according to sp_pri_to_cos.
934 *.
935 ******************************************************************************/
939 {
943 DCBX_E3B0_MAX_NUM_COS_PORT0;
949 }
953 "parameter There can't be two COS's with "
956 }
961 }
963 /******************************************************************************
964 * Description:
965 * Returns the correct value according to COS and priority in
966 * the sp_pri_cli register.
967 *.
968 ******************************************************************************/
973 {
979 }
980 /******************************************************************************
981 * Description:
982 * Returns the correct value according to COS and priority in the
983 * sp_pri_cli register for NIG.
984 *.
985 ******************************************************************************/
987 {
988 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
995 }
996 /******************************************************************************
997 * Description:
998 * Returns the correct value according to COS and priority in the
999 * sp_pri_cli register for PBF.
1000 *.
1001 ******************************************************************************/
1003 {
1010 }
1012 /******************************************************************************
1013 * Description:
1014 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
1015 * according to sp_pri_to_cos.(which COS has higher priority)
1016 *.
1017 ******************************************************************************/
1020 {
1024 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1030 DCBX_E3B0_MAX_NUM_COS_PORT0;
1034 /* Set all the strict priority first */
1039 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1042 }
1050 /* COS is used remove it from bitmap.*/
1053 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1054 "invalid There can't be two COS's with"
1057 }
1059 pri_set++;
1060 }
1061 }
1063 /* Set all the Non strict priority i= COS*/
1066 /* Check if COS was already used for SP */
1068 /* COS wasn't used for SP */
1074 /* COS is used remove it from bitmap.*/
1076 pri_set++;
1077 }
1078 }
1084 }
1087 /* Only 6 usable clients*/
1093 /* Only 9 usable clients*/
1098 pri_cli_nig_lsb);
1100 pri_cli_nig_msb);
1103 }
1105 }
1107 /******************************************************************************
1108 * Description:
1109 * Configure the COS to ETS according to BW and SP settings.
1110 ******************************************************************************/
1114 {
1125 DCBX_E3B0_MAX_NUM_COS_PORT0;
1132 }
1138 }
1140 /* Prepare sp strict priority parameters*/
1143 /* Prepare BW parameters*/
1150 }
1152 /*
1153 * Upper bound is set according to current link speed (min_w_val
1154 * should be the same for upper bound and COS credit val).
1155 */
1163 /*
1164 * The function also sets the BW in HW(not the mappin
1165 * yet)
1166 */
1169 total_bw,
1171 port);
1177 params,
1178 sp_pri_to_cos,
1180 cos_entry);
1186 }
1191 }
1192 }
1194 /* Set SP register (which COS has higher priority) */
1196 sp_pri_to_cos);
1202 }
1204 /* Set client mapping of BW and strict */
1206 cos_sp_bitmap,
1207 cos_bw_bitmap);
1212 }
1214 }
1216 {
1217 /* ETS disabled configuration */
1220 /*
1221 * defines which entries (clients) are subjected to WFQ arbitration
1222 * COS0 0x8
1223 * COS1 0x10
1224 */
1226 /*
1227 * mapping between the ARB_CREDIT_WEIGHT registers and actual
1228 * client numbers (WEIGHT_0 does not actually have to represent
1229 * client 0)
1230 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1231 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010
1232 */
1236 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1238 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1240 /* ETS mode enabled*/
1243 /* Defines the number of consecutive slots for the strict priority */
1245 /*
1246 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
1247 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0
1248 * entry, 4 - COS1 entry.
1249 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1250 * bit4 bit3 bit2 bit1 bit0
1251 * MCP and debug are strict
1252 */
1255 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1257 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1259 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1260 }
1264 {
1265 /* ETS disabled configuration*/
1278 }
1281 total_bw;
1283 total_bw;
1292 }
1295 {
1296 /* ETS disabled configuration*/
1301 /*
1302 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
1303 * as strict. Bits 0,1,2 - debug and management entries,
1304 * 3 - COS0 entry, 4 - COS1 entry.
1305 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1306 * bit4 bit3 bit2 bit1 bit0
1307 * MCP and debug are strict
1308 */
1310 /*
1311 * For strict priority entries defines the number of consecutive slots
1312 * for the highest priority.
1313 */
1315 /* ETS mode disable */
1317 /* Defines the number of consecutive slots for the strict priority */
1320 /* Defines the number of consecutive slots for the strict priority */
1323 /*
1324 * mapping between entry priority to client number (0,1,2 -debug and
1325 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1326 * 3bits client num.
1327 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1328 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000
1329 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000
1330 */
1335 }
1336 /******************************************************************/
1337 /* PFC section */
1338 /******************************************************************/
1341 u8 is_lb)
1342 {
1344 u32 xmac_base;
1347 /* XMAC base adrr */
1350 /* Initialize pause and pfc registers */
1355 /* No PFC support */
1357 FEATURE_CONFIG_PFC_ENABLED)) {
1359 /*
1360 * RX flow control - Process pause frame in receive direction
1361 */
1365 /*
1366 * TX flow control - Send pause packet when buffer is full
1367 */
1372 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1373 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1374 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
1375 XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1376 /* Write pause and PFC registers */
1382 }
1384 /* Write pause and PFC registers */
1390 /* Set MAC address for source TX Pause/PFC frames */
1401 }
1407 {
1408 /* Read pfc statistic */
1416 /* PFC received frames */
1418 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
1425 /* PFC received sent */
1427 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
1433 }
1435 /* Read pfc statistic*/
1439 {
1440 /* Read pfc statistic */
1451 pfc_frames_received);
1452 }
1453 }
1454 /******************************************************************/
1455 /* MAC/PBF section */
1456 /******************************************************************/
1458 {
1460 /**
1461 * Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1462 * (a value of 49==0x31) and make sure that the AUTO poll is off
1463 */
1467 else
1471 EMAC_MDIO_MODE_CLOCK_CNT);
1474 else
1481 }
1483 {
1484 u32 port4mode_ovwr_val;
1485 /* Check 4-port override enabled */
1488 /* Return 4-port mode override value */
1490 }
1491 /* Return 4-port mode from input pin */
1493 }
1497 {
1498 /* reset and unreset the emac core */
1502 u32 val;
1503 u16 timeout;
1511 /* init emac - use read-modify-write */
1512 /* self clear reset */
1523 }
1524 timeout--;
1527 /* Set mac address */
1537 }
1540 u16 tx_pause_en,
1541 u8 enable)
1542 {
1546 enable);
1548 enable);
1551 }
1554 {
1561 /* Disable RX and TX */
1563 }
1567 {
1568 u32 val;
1571 /* Reset UMAC */
1581 /**
1582 * This register determines on which events the MAC will assert
1583 * error on the i/f to the NIG along w/ EOP.
1584 */
1586 /**
1587 * BD REG_WR(bp, NIG_REG_P0_MAC_RSV_ERR_MASK +
1588 * params->port*0x14, 0xfffff.
1589 */
1590 /* This register opens the gate for the UMAC despite its name */
1594 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1595 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1596 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1614 }
1627 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1637 /* Enable RX and TX */
1640 UMAC_COMMAND_CONFIG_REG_RX_ENA;
1644 /* Remove SW Reset */
1647 /* Check loopback mode */
1652 /*
1653 * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1654 * length used by the MAC receive logic to check frames.
1655 */
1661 }
1663 /* Define the XMAC mode */
1665 {
1669 /*
1670 * In 4-port mode, need to set the mode only once, so if XMAC is
1671 * already out of reset, it means the mode has already been set,
1672 * and it must not* reset the XMAC again, since it controls both
1673 * ports of the path
1674 */
1678 MISC_REGISTERS_RESET_REG_2_XMAC)) {
1682 }
1684 /* Hard reset */
1686 MISC_REGISTERS_RESET_REG_2_XMAC);
1690 MISC_REGISTERS_RESET_REG_2_XMAC);
1694 /* Set the number of ports on the system side to up to 2 */
1697 /* Set the number of ports on the Warp Core to 10G */
1700 /* Set the number of ports on the system side to 1 */
1705 /* Set the number of ports on the Warp Core to 10G */
1710 /* Set the number of ports on the Warp Core to 20G */
1712 }
1713 }
1714 /* Soft reset */
1716 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1720 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1722 }
1725 {
1731 MISC_REGISTERS_RESET_REG_2_XMAC) {
1732 /*
1733 * Send an indication to change the state in the NIG back to XON
1734 * Clearing this bit enables the next set of this bit to get
1735 * rising edge
1736 */
1744 }
1745 }
1749 {
1758 /*
1759 * This register determines on which events the MAC will assert
1760 * error on the i/f to the NIG along w/ EOP.
1761 */
1763 /*
1764 * This register tells the NIG whether to send traffic to UMAC
1765 * or XMAC
1766 */
1769 /* Set Max packet size */
1772 /* CRC append for Tx packets */
1775 /* update PFC */
1778 /* Enable TX and RX */
1781 /* Check loopback mode */
1791 }
1795 {
1799 u32 val;
1803 /* Disable BMAC */
1807 /* enable emac and not bmac */
1810 /* ASIC */
1813 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1814 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1817 /* select the master lanes (out of 0-3) */
1819 /* select XGXS */
1824 /* select SerDes */
1826 }
1829 EMAC_RX_MODE_RESET);
1831 EMAC_TX_MODE_RESET);
1834 /* config GMII mode */
1838 /* pause enable/disable */
1840 EMAC_RX_MODE_FLOW_EN);
1844 EMAC_TX_MODE_FLOW_EN));
1846 FEATURE_CONFIG_PFC_ENABLED)) {
1849 EMAC_REG_EMAC_RX_MODE,
1850 EMAC_RX_MODE_FLOW_EN);
1854 EMAC_REG_EMAC_TX_MODE,
1856 EMAC_TX_MODE_FLOW_EN));
1859 EMAC_TX_MODE_FLOW_EN);
1860 }
1862 /* KEEP_VLAN_TAG, promiscuous */
1866 /*
1867 * Setting this bit causes MAC control frames (except for pause
1868 * frames) to be passed on for processing. This setting has no
1869 * affect on the operation of the pause frames. This bit effects
1870 * all packets regardless of RX Parser packet sorting logic.
1871 * Turn the PFC off to make sure we are in Xon state before
1872 * enabling it.
1873 */
1877 /* Enable PFC again */
1879 EMAC_REG_RX_PFC_MODE_RX_EN |
1880 EMAC_REG_RX_PFC_MODE_TX_EN |
1881 EMAC_REG_RX_PFC_MODE_PRIORITIES);
1885 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1887 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1889 }
1892 /* Set Loopback */
1896 else
1900 /* enable emac */
1903 /* enable emac for jumbo packets */
1908 /* strip CRC */
1911 /* disable the NIG in/out to the bmac */
1916 /* enable the NIG in/out to the emac */
1920 FEATURE_CONFIG_PFC_ENABLED) ||
1931 }
1935 {
1939 NIG_REG_INGRESS_BMAC0_MEM;
1943 FEATURE_CONFIG_PFC_ENABLED)) &&
1945 /* Enable BigMAC to react on received Pause packets */
1951 /* tx control */
1954 FEATURE_CONFIG_PFC_ENABLED) &&
1960 }
1964 u8 is_lb)
1965 {
1966 /*
1967 * Set rx control: Strip CRC and enable BigMAC to relay
1968 * control packets to the system as well
1969 */
1973 NIG_REG_INGRESS_BMAC0_MEM;
1977 FEATURE_CONFIG_PFC_ENABLED)) &&
1979 /* Enable BigMAC to react on received Pause packets */
1986 /* Tx control */
1989 FEATURE_CONFIG_PFC_ENABLED) &&
1998 /* Enable PFC RX & TX & STATS and set 8 COS */
2008 /* Clear the force Xon */
2012 /* disable PFC RX & TX & STATS and set 8 COS */
2015 }
2019 /*
2020 * Set Time (based unit is 512 bit time) between automatic
2021 * re-sending of PP packets amd enable automatic re-send of
2022 * Per-Priroity Packet as long as pp_gen is asserted and
2023 * pp_disable is low.
2024 */
2034 /* mac control */
2039 }
2040 /* When PFC enabled, Pass pause frames towards the NIG. */
2047 }
2049 /* PFC BRB internal port configuration params */
2051 u32 pause_xoff;
2052 u32 pause_xon;
2053 u32 full_xoff;
2054 u32 full_xon;
2055 };
2058 u32 per_class_guaranty_mode;
2059 u32 lb_guarantied_hyst;
2060 u32 full_lb_xoff_th;
2061 u32 full_lb_xon_threshold;
2062 u32 lb_guarantied;
2063 u32 mac_0_class_t_guarantied;
2064 u32 mac_0_class_t_guarantied_hyst;
2065 u32 mac_1_class_t_guarantied;
2066 u32 mac_1_class_t_guarantied_hyst;
2067 };
2075 };
2079 {
2089 /* class0 defaults */
2091 DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR;
2093 DEFAULT0_E2_BRB_MAC_PAUSE_XON_THR;
2095 DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR;
2097 DEFAULT0_E2_BRB_MAC_FULL_XON_THR;
2098 /* pause able*/
2100 PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2102 PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE;
2104 PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE;
2106 PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE;
2107 /* non pause able*/
2109 PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2111 PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2113 PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2115 PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2117 /* class0 defaults */
2119 DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR;
2121 DEFAULT0_E3A0_BRB_MAC_PAUSE_XON_THR;
2123 DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR;
2125 DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR;
2126 /* pause able */
2128 PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2130 PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE;
2132 PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE;
2134 PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE;
2135 /* non pause able*/
2137 PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2139 PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2141 PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2143 PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2145 /* class0 defaults */
2147 DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR;
2149 DEFAULT0_E3B0_BRB_MAC_PAUSE_XON_THR;
2151 DEFAULT0_E3B0_BRB_MAC_FULL_XOFF_THR;
2153 DEFAULT0_E3B0_BRB_MAC_FULL_XON_THR;
2156 FLAGS_4_PORT_MODE) {
2158 PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2160 PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2162 PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2164 PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE;
2165 /* non pause able*/
2167 PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2169 PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2171 PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2173 PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2176 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2178 PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2180 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2182 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE;
2183 /* non pause able*/
2185 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2187 PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2189 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2191 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2192 }
2197 }
2201 struct bnx2x_pfc_brb_e3b0_val
2205 {
2211 FLAGS_4_PORT_MODE) {
2213 PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR;
2215 PFC_E3B0_4P_BRB_FULL_LB_XON_THR;
2217 PFC_E3B0_4P_LB_GUART;
2219 PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART;
2221 PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST;
2223 PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART;
2225 PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST;
2228 PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR;
2230 PFC_E3B0_2P_BRB_FULL_LB_XON_THR;
2232 PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST;
2234 PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART;
2236 PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST;
2240 /* nonpauseable= Lossy + pauseable = Lossless*/
2242 PFC_E3B0_2P_MIX_PAUSE_LB_GUART;
2244 PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART;
2246 /* Lossless +Lossless*/
2248 PFC_E3B0_2P_PAUSE_LB_GUART;
2250 PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART;
2252 /* Lossy +Lossy*/
2254 PFC_E3B0_2P_NON_PAUSE_LB_GUART;
2256 PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART;
2257 }
2258 }
2263 DEFAULT_E3B0_BRB_FULL_LB_XOFF_THR;
2265 DEFAULT_E3B0_BRB_FULL_LB_XON_THR;
2267 DEFAULT_E3B0_LB_GUART;
2269 DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART;
2271 DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART_HYST;
2273 DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART;
2275 DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART_HYST;
2276 }
2277 }
2280 struct bnx2x_nig_brb_pfc_port_params
2282 {
2289 FEATURE_CONFIG_PFC_ENABLED;
2294 /* default - pause configuration */
2301 /* First COS */
2304 else
2308 /*
2309 * The number of free blocks below which the pause signal to class 0
2310 * of MAC #n is asserted. n=0,1
2311 */
2313 BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 ,
2315 /*
2316 * The number of free blocks above which the pause signal to class 0
2317 * of MAC #n is de-asserted. n=0,1
2318 */
2321 /*
2322 * The number of free blocks below which the full signal to class 0
2323 * of MAC #n is asserted. n=0,1
2324 */
2327 /*
2328 * The number of free blocks above which the full signal to class 0
2329 * of MAC #n is de-asserted. n=0,1
2330 */
2335 /* Second COS */
2338 else
2342 /*
2343 * The number of free blocks below which the pause signal to
2344 * class 1 of MAC #n is asserted. n=0,1
2345 */
2347 BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0,
2350 /*
2351 * The number of free blocks above which the pause signal to
2352 * class 1 of MAC #n is de-asserted. n=0,1
2353 */
2355 BRB1_REG_PAUSE_1_XON_THRESHOLD_0,
2357 /*
2358 * The number of free blocks below which the full signal to
2359 * class 1 of MAC #n is asserted. n=0,1
2360 */
2362 BRB1_REG_FULL_1_XOFF_THRESHOLD_0,
2364 /*
2365 * The number of free blocks above which the full signal to
2366 * class 1 of MAC #n is de-asserted. n=0,1
2367 */
2369 BRB1_REG_FULL_1_XON_THRESHOLD_0,
2374 params,
2376 pfc_params,
2377 pfc_enabled);
2382 /*
2383 * The hysteresis on the guarantied buffer space for the Lb
2384 * port before signaling XON.
2385 */
2389 /*
2390 * The number of free blocks below which the full signal to the
2391 * LB port is asserted.
2392 */
2395 /*
2396 * The number of free blocks above which the full signal to the
2397 * LB port is de-asserted.
2398 */
2401 /*
2402 * The number of blocks guarantied for the MAC #n port. n=0,1
2403 */
2405 /* The number of blocks guarantied for the LB port.*/
2409 /*
2410 * The number of blocks guarantied for the MAC #n port.
2411 */
2416 /*
2417 * The number of blocks guarantied for class #t in MAC0. t=0,1
2418 */
2423 /*
2424 * The hysteresis on the guarantied buffer space for class in
2425 * MAC0. t=0,1
2426 */
2432 /*
2433 * The number of blocks guarantied for class #t in MAC1.t=0,1
2434 */
2439 /*
2440 * The hysteresis on the guarantied buffer space for class #t
2441 * in MAC1. t=0,1
2442 */
2447 }
2450 }
2452 /******************************************************************************
2453 * Description:
2454 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2455 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2456 ******************************************************************************/
2458 u8 cos_entry,
2460 {
2466 NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2467 NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2471 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2472 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2476 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2477 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2494 }
2499 }
2501 {
2507 }
2512 {
2520 FEATURE_CONFIG_PFC_ENABLED;
2523 /*
2524 * When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2525 * MAC control frames (that are not pause packets)
2526 * will be forwarded to the XCM.
2527 */
2529 NIG_REG_LLH0_XCM_MASK);
2530 /*
2531 * nig params will override non PFC params, since it's possible to
2532 * do transition from PFC to SAFC
2533 */
2540 else
2543 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2555 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2557 }
2578 /* output enable for RX_XCM # IF */
2582 /* HW PFC TX enable */
2595 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2599 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2601 }
2603 NIG_REG_P0_PKT_PRIORITY_TO_COS,
2604 pkt_priority_to_cos);
2605 }
2610 {
2611 /*
2612 * The PFC and pause are orthogonal to one another, meaning when
2613 * PFC is enabled, the pause are disabled, and when PFC is
2614 * disabled, pause are set according to the pause result.
2615 */
2616 u32 val;
2623 else
2628 /* update NIG params */
2631 /* update BRB params */
2650 }
2653 else
2658 FEATURE_CONFIG_PFC_ENABLED) ||
2662 }
2664 }
2669 u8 is_lb)
2670 {
2674 NIG_REG_INGRESS_BMAC0_MEM;
2676 u32 val;
2680 /* XGXS control */
2686 /* tx MAC SA */
2695 /* mac control */
2700 }
2705 /* set rx mtu */
2712 /* set tx mtu */
2717 /* set cnt max size */
2722 /* configure safc */
2729 }
2733 u8 is_lb)
2734 {
2738 NIG_REG_INGRESS_BMAC0_MEM;
2748 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2756 /* tx MAC SA */
2768 /* Configure SAFC */
2775 /* set rx mtu */
2781 /* set tx mtu */
2786 /* set cnt max size */
2794 }
2798 u8 is_lb)
2799 {
2803 u32 val;
2804 /* reset and unreset the BigMac */
2812 /* enable access for bmac registers */
2815 /* Enable BMAC according to BMAC type*/
2818 else
2825 FEATURE_CONFIG_PFC_ENABLED) ||
2837 }
2840 {
2842 NIG_REG_INGRESS_BMAC0_MEM;
2846 /* Only if the bmac is out of reset */
2849 nig_bmac_enable) {
2852 /* Clear Rx Enable bit in BMAC_CONTROL register */
2854 BIGMAC2_REGISTER_BMAC_CONTROL,
2858 BIGMAC2_REGISTER_BMAC_CONTROL,
2861 /* Clear Rx Enable bit in BMAC_CONTROL register */
2863 BIGMAC_REGISTER_BMAC_CONTROL,
2867 BIGMAC_REGISTER_BMAC_CONTROL,
2869 }
2871 }
2872 }
2875 u32 line_speed)
2876 {
2882 /* disable port */
2885 /* wait for init credit */
2894 count--;
2895 }
2901 }
2909 /* update threshold */
2911 /* update init credit */
2918 /* update threshold */
2920 /* update init credit */
2927 line_speed);
2929 }
2930 }
2935 /* probe the credit changes */
2940 /* enable port */
2943 }
2945 /**
2946 * bnx2x_get_emac_base - retrive emac base address
2947 *
2948 * @bp: driver handle
2949 * @mdc_mdio_access: access type
2950 * @port: port id
2951 *
2952 * This function selects the MDC/MDIO access (through emac0 or
2953 * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2954 * phy has a default access mode, which could also be overridden
2955 * by nvram configuration. This parameter, whether this is the
2956 * default phy configuration, or the nvram overrun
2957 * configuration, is passed here as mdc_mdio_access and selects
2958 * the emac_base for the CL45 read/writes operations
2959 */
2962 {
2970 else
2976 else
2987 }
2990 }
2992 /******************************************************************/
2993 /* CL22 access functions */
2994 /******************************************************************/
2998 {
3000 u8 i;
3002 /* Switch to CL22 */
3007 /* address */
3009 EMAC_MDIO_COMM_COMMAND_WRITE_22 |
3010 EMAC_MDIO_COMM_START_BUSY);
3020 }
3021 }
3025 }
3028 }
3033 {
3035 u16 i;
3038 /* Switch to CL22 */
3043 /* address */
3045 EMAC_MDIO_COMM_COMMAND_READ_22 |
3046 EMAC_MDIO_COMM_START_BUSY);
3057 }
3058 }
3064 }
3067 }
3069 /******************************************************************/
3070 /* CL45 access functions */
3071 /******************************************************************/
3074 {
3075 u32 val;
3076 u16 i;
3080 EMAC_MDIO_STATUS_10MB);
3081 /* address */
3083 EMAC_MDIO_COMM_COMMAND_ADDRESS |
3084 EMAC_MDIO_COMM_START_BUSY);
3094 }
3095 }
3102 /* data */
3104 EMAC_MDIO_COMM_COMMAND_READ_45 |
3105 EMAC_MDIO_COMM_START_BUSY);
3112 EMAC_REG_EMAC_MDIO_COMM);
3116 }
3117 }
3123 }
3124 }
3125 /* Work around for E3 A0 */
3129 u16 temp_val;
3131 }
3132 }
3136 EMAC_MDIO_STATUS_10MB);
3138 }
3142 {
3143 u32 tmp;
3144 u8 i;
3148 EMAC_MDIO_STATUS_10MB);
3150 /* address */
3153 EMAC_MDIO_COMM_COMMAND_ADDRESS |
3154 EMAC_MDIO_COMM_START_BUSY);
3164 }
3165 }
3171 /* data */
3173 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
3174 EMAC_MDIO_COMM_START_BUSY);
3181 EMAC_REG_EMAC_MDIO_COMM);
3185 }
3186 }
3191 }
3192 }
3193 /* Work around for E3 A0 */
3197 u16 temp_val;
3199 }
3200 }
3203 EMAC_MDIO_STATUS_10MB);
3205 }
3206 /******************************************************************/
3207 /* BSC access functions from E3 */
3208 /******************************************************************/
3210 {
3216 /* Read I2C output PINs */
3222 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3224 /* Read I2C output value */
3233 }
3237 u8 sl_devid,
3238 u16 sl_addr,
3239 u8 lc_addr,
3240 u8 xfer_cnt,
3242 {
3250 }
3254 xfer_cnt);
3256 }
3261 /* enable the engine */
3266 /* program slave device ID */
3270 /* start xfer with 0 byte to update the address pointer ???*/
3273 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3277 /* poll for completion */
3285 i);
3288 }
3289 }
3293 /* start xfer with read op */
3296 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3301 /* poll for completion */
3311 }
3312 }
3318 #ifdef __BIG_ENDIAN
3323 #endif
3324 }
3326 }
3330 {
3331 u16 val;
3334 }
3338 {
3339 u8 phy_index;
3340 /*
3341 * Probe for the phy according to the given phy_addr, and execute
3342 * the read request on it
3343 */
3349 }
3350 }
3352 }
3356 {
3357 u8 phy_index;
3358 /*
3359 * Probe for the phy according to the given phy_addr, and execute
3360 * the write request on it
3361 */
3367 }
3368 }
3370 }
3373 {
3385 /*figure out path swap value */
3389 else
3395 /*figure out port swap value */
3399 else
3408 /*figure out path swap value */
3409 path_swap_ovr =
3414 path_swap =
3416 }
3421 }
3423 }
3427 {
3428 u32 ser_lane;
3432 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3433 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3440 /*
3441 * In Dual-lane mode, two lanes are joined together,
3442 * so in order to configure them, the AER broadcast method is
3443 * used here.
3444 * 0x200 is the broadcast address for lanes 0,1
3445 * 0x201 is the broadcast address for lanes 2,3
3446 */
3451 else
3457 }
3459 /******************************************************************/
3460 /* Internal phy section */
3461 /******************************************************************/
3464 {
3467 /* Set Clause 22 */
3473 /* Set Clause 45 */
3475 }
3478 {
3479 u32 val;
3485 /* reset and unreset the SerDes/XGXS */
3493 DEFAULT_PHY_DEV_ADDR);
3494 }
3497 {
3499 u8 port;
3500 u32 val;
3506 /* reset and unreset the SerDes/XGXS */
3514 }
3518 {
3521 /**
3522 * resolve pause mode and advertisement Please refer to Table
3523 * 28B-3 of the 802.3ab-1999 spec
3524 */
3530 else
3532 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3548 }
3550 }
3554 {
3558 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3560 phy_index++) {
3568 }
3582 SPEED_AUTO_NEG)
3590 }
3591 }
3596 {
3597 u16 val;
3599 /* read modify write pause advertizing */
3604 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3607 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3608 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3610 }
3612 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3613 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3615 }
3618 }
3640 }
3645 }
3650 {
3653 u16 pause_result;
3666 MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
3667 lane;
3679 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3682 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3684 }
3687 MDIO_AN_DEVAD,
3690 MDIO_AN_DEVAD,
3692 }
3700 }
3704 {
3708 /* Update the advertised flow-controled of LD/LP in AN */
3711 /* But set the flow-control result as the requested one */
3718 }
3720 }
3721 /******************************************************************/
3722 /* Warpcore section */
3723 /******************************************************************/
3724 /* The init_internal_warpcore should mirror the xgxs,
3725 * i.e. reset the lane (if needed), set aer for the
3726 * init configuration, and set/clear SGMII flag. Internal
3727 * phy init is done purely in phy_init stage.
3728 */
3735 /* Set to default registers that may be overriden by 10G force */
3752 /* Disable Autoneg: re-enable it after adv is done. */
3756 /* Check adding advertisement for 1G KX */
3760 u16 sd_digital;
3763 /* Enable CL37 1G Parallel Detect */
3767 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3771 }
3775 /* Check adding advertisement for 10G KR */
3777 /* Enable 10G Parallel Detect */
3782 }
3784 /* Set Transmit PMD settings */
3792 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3795 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3798 /* Advertised speeds */
3802 /* Advertised and set FEC (Forward Error Correction) */
3804 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
3806 MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
3808 /* Enable CL37 BAM */
3812 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3818 }
3820 /* Advertise pause */
3823 /*
3824 * Set KR Autoneg Work-Around flag for Warpcore version older than D108
3825 */
3831 }
3839 /* Over 1G - AN local device user page 1 */
3843 /* Enable Autoneg */
3847 }
3852 {
3854 u16 val;
3856 /* Disable Autoneg */
3878 /* Disable CL36 PCS Tx */
3882 /* Double Wide Single Data Rate @ pll rate */
3886 /* Leave cl72 training enable, needed for KR */
3888 MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150,
3891 /* Leave CL72 enabled */
3893 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3896 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3899 /* Set speed via PMA/PMD register */
3906 /*Enable encoded forced speed */
3910 /* Turn TX scramble payload only the 64/66 scrambler */
3914 /* Turn RX scramble payload only the 64/66 scrambler */
3918 /* set and clear loopback to cause a reset to 64/66 decoder */
3924 }
3928 u8 is_xfi)
3929 {
3932 /* Hold rxSeqStart */
3938 /* Hold tx_fifo_reset */
3944 /* Disable CL73 AN */
3947 /* Disable 100FX Enable and Auto-Detect */
3953 /* Disable 100FX Idle detect */
3959 /* Set Block address to Remote PHY & Clear forced_speed[5] */
3965 /* Turn off auto-detect & fiber mode */
3969 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3972 /* Set filter_force_link, disable_false_link and parallel_detect */
3976 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3979 /* Set XFI / SFI */
3990 tx_driver_val =
4000 tx_driver_val =
4004 }
4008 /* Set Transmit PMD settings */
4011 MDIO_WC_REG_TX_FIR_TAP,
4015 tx_driver_val);
4017 /* Enable fiber mode, enable and invert sig_det */
4023 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
4029 /* 10G XFI Full Duplex */
4033 /* Release tx_fifo_reset */
4039 /* Release rxSeqStart */
4044 }
4048 {
4050 }
4054 u16 lane)
4055 {
4056 /* Rx0 anaRxControl1G */
4060 /* Rx2 anaRxControl1G */
4088 /* Serdes Digital Misc1 */
4092 /* Serdes Digital4 Misc3 */
4096 /* Set Transmit PMD settings */
4098 MDIO_WC_REG_TX_FIR_TAP,
4102 MDIO_WC_REG_TX_FIR_TAP_ENABLE));
4108 }
4112 u8 fiber_mode,
4113 u8 always_autoneg)
4114 {
4118 /* Clear XFI clock comp in non-10G single lane mode. */
4125 /* SGMII Autoneg */
4129 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4149 }
4162 }
4164 /* SGMII Slave mode and disable signal detect */
4169 else
4173 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4174 digctrl_kx1);
4176 /* Turn off parallel detect */
4180 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4183 /* Re-enable parallel detect */
4185 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4188 /* Enable autodet */
4190 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4192 }
4196 u8 reset)
4197 {
4198 u16 val;
4199 /* Take lane out of reset after configuration is finished */
4204 else
4210 }
4211 /* Clear SFI/XFI link settings registers */
4214 u16 lane)
4215 {
4217 u16 val16;
4219 /* Set XFI clock comp as default. */
4251 }
4254 u32 chip_id,
4257 {
4258 u32 cfg_pin;
4265 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4266 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4268 /*
4269 * Should not happen. This function called upon interrupt
4270 * triggered by GPIO ( since EPIO can only generate interrupts
4271 * to MCP).
4272 * So if this function was called and none of the GPIOs was set,
4273 * it means the shit hit the fan.
4274 */
4279 cfg_pin);
4281 }
4288 }
4291 }
4295 {
4298 u32 gpio_val;
4305 /* Call the handling function in case module is detected */
4308 else
4310 }
4313 {
4323 }
4328 {
4330 u32 serdes_net_if;
4339 /* return if there is no link partner */
4343 }
4349 PORT_HW_CFG_NET_SERDES_IF_MASK);
4353 /* Do we get link yet? */
4357 /*10G KR*/
4369 /*reset the lane to see if link comes up.*/
4373 /* restart Autoneg */
4380 }
4385 }
4389 }
4394 {
4396 u32 serdes_net_if;
4397 u8 fiber_mode;
4402 PORT_HW_CFG_NET_SERDES_IF_MASK);
4420 /* Enable KR Auto Neg */
4426 }
4441 }
4443 params,
4444 fiber_mode,
4446 }
4460 }
4461 /* Issue Module detection */
4470 }
4473 /* Issue Module detection */
4482 }
4490 serdes_net_if);
4492 }
4493 }
4495 /* Take lane out of reset after configuration is finished */
4498 }
4502 u8 tx_en)
4503 {
4505 u32 cfg_pin;
4511 PORT_HW_CFG_TX_LASER_MASK;
4512 /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4514 /* For 20G, the expected pin to be used is 3 pins after the current */
4519 }
4523 {
4525 u16 val16;
4529 /* Global register */
4532 /* Clear loopback settings (if any) */
4533 /* 10G & 20G */
4545 /* Update those 1-copy registers */
4548 /* Enable 1G MDIO (1-copy) */
4550 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4553 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4559 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4562 }
4566 {
4568 u16 val16;
4569 u32 lane;
4574 /* 10/100/1000 */
4576 /* Update those 1-copy registers */
4579 /* Enable 1G MDIO (1-copy) */
4581 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4584 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4586 /* Set 1G loopback based on lane (1-copy) */
4591 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4594 /* Switch back to 4-copy registers */
4597 /* 10G & 20G */
4608 }
4609 }
4614 {
4616 u8 link_10g_plus;
4626 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4629 /* fall thru */
4636 /* fall thru */
4644 /* fall thru */
4651 /* fall thru */
4664 }
4681 }
4686 /* anything 10 and over uses the bmac */
4692 else
4697 else
4699 }
4709 /* indicate no mac active */
4713 }
4714 }
4718 {
4722 /* Update PHY configuration */
4731 /* Sync media type */
4739 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4742 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4745 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4748 /* Sync AEU offset */
4755 /* Sync PFC status */
4758 FEATURE_CONFIG_PFC_ENABLED;
4759 else
4767 }
4771 {
4775 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4776 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4778 /* set the master_ln for AN */
4780 MDIO_REG_BANK_XGXS_BLOCK2,
4781 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4785 MDIO_REG_BANK_XGXS_BLOCK2 ,
4786 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4788 }
4792 u8 set_serdes)
4793 {
4795 u16 mii_control;
4796 u16 i;
4798 MDIO_REG_BANK_COMBO_IEEE0,
4801 /* reset the unicore */
4803 MDIO_REG_BANK_COMBO_IEEE0,
4804 MDIO_COMBO_IEEE0_MII_CONTROL,
4806 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4810 /* wait for the reset to self clear */
4814 /* the reset erased the previous bank value */
4816 MDIO_REG_BANK_COMBO_IEEE0,
4817 MDIO_COMBO_IEEE0_MII_CONTROL,
4823 }
4824 }
4832 }
4836 {
4838 /*
4839 * Each two bits represents a lane number:
4840 * No swap is 0123 => 0x1b no need to enable the swap
4841 */
4845 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4846 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4848 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4849 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4853 MDIO_REG_BANK_XGXS_BLOCK2,
4854 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4856 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4857 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4860 MDIO_REG_BANK_XGXS_BLOCK2,
4862 }
4866 MDIO_REG_BANK_XGXS_BLOCK2,
4867 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4869 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4872 MDIO_REG_BANK_XGXS_BLOCK2,
4874 }
4875 }
4879 {
4881 u16 control2;
4883 MDIO_REG_BANK_SERDES_DIGITAL,
4884 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4888 else
4893 MDIO_REG_BANK_SERDES_DIGITAL,
4894 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4895 control2);
4899 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4903 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4904 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
4905 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
4908 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4909 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4913 control2 |=
4914 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
4917 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4918 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4919 control2);
4921 /* Disable parallel detection of HiG */
4923 MDIO_REG_BANK_XGXS_BLOCK2,
4924 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
4925 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
4926 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
4927 }
4928 }
4933 u8 enable_cl73)
4934 {
4936 u16 reg_val;
4938 /* CL37 Autoneg */
4940 MDIO_REG_BANK_COMBO_IEEE0,
4943 /* CL37 Autoneg Enabled */
4948 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
4951 MDIO_REG_BANK_COMBO_IEEE0,
4954 /* Enable/Disable Autodetection */
4957 MDIO_REG_BANK_SERDES_DIGITAL,
4960 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
4964 else
4968 MDIO_REG_BANK_SERDES_DIGITAL,
4971 /* Enable TetonII and BAM autoneg */
4973 MDIO_REG_BANK_BAM_NEXT_PAGE,
4974 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
4977 /* Enable BAM aneg Mode and TetonII aneg Mode */
4979 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4981 /* TetonII and BAM Autoneg Disabled */
4983 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4984 }
4986 MDIO_REG_BANK_BAM_NEXT_PAGE,
4987 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
4988 reg_val);
4991 /* Enable Cl73 FSM status bits */
4993 MDIO_REG_BANK_CL73_USERB0,
4994 MDIO_CL73_USERB0_CL73_UCTRL,
4997 /* Enable BAM Station Manager*/
4999 MDIO_REG_BANK_CL73_USERB0,
5000 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
5001 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
5002 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
5003 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
5005 /* Advertise CL73 link speeds */
5007 MDIO_REG_BANK_CL73_IEEEB1,
5008 MDIO_CL73_IEEEB1_AN_ADV2,
5011 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5014 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5018 MDIO_REG_BANK_CL73_IEEEB1,
5019 MDIO_CL73_IEEEB1_AN_ADV2,
5020 reg_val);
5022 /* CL73 Autoneg Enabled */
5029 MDIO_REG_BANK_CL73_IEEEB0,
5031 }
5033 /* program SerDes, forced speed */
5037 {
5039 u16 reg_val;
5041 /* program duplex, disable autoneg and sgmii*/
5043 MDIO_REG_BANK_COMBO_IEEE0,
5046 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5047 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
5051 MDIO_REG_BANK_COMBO_IEEE0,
5054 /*
5055 * program speed
5056 * - needed only if the speed is greater than 1G (2.5G or 10G)
5057 */
5059 MDIO_REG_BANK_SERDES_DIGITAL,
5061 /* clearing the speed value before setting the right speed */
5065 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5072 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5074 reg_val |=
5075 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
5076 }
5079 MDIO_REG_BANK_SERDES_DIGITAL,
5082 }
5086 {
5090 /* configure the 48 bits for BAM AN */
5092 /* set extended capabilities */
5098 MDIO_REG_BANK_OVER_1G,
5102 MDIO_REG_BANK_OVER_1G,
5104 }
5108 u16 ieee_fc)
5109 {
5111 u16 val;
5112 /* for AN, we are always publishing full duplex */
5115 MDIO_REG_BANK_COMBO_IEEE0,
5118 MDIO_REG_BANK_CL73_IEEEB1,
5123 MDIO_REG_BANK_CL73_IEEEB1,
5125 }
5129 u8 enable_cl73)
5130 {
5132 u16 mii_control;
5135 /* Enable and restart BAM/CL37 aneg */
5139 MDIO_REG_BANK_CL73_IEEEB0,
5140 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5144 MDIO_REG_BANK_CL73_IEEEB0,
5145 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5147 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
5148 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
5152 MDIO_REG_BANK_COMBO_IEEE0,
5153 MDIO_COMBO_IEEE0_MII_CONTROL,
5157 mii_control);
5159 MDIO_REG_BANK_COMBO_IEEE0,
5160 MDIO_COMBO_IEEE0_MII_CONTROL,
5162 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5163 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
5164 }
5165 }
5170 {
5172 u16 control1;
5174 /* in SGMII mode, the unicore is always slave */
5177 MDIO_REG_BANK_SERDES_DIGITAL,
5178 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5181 /* set sgmii mode (and not fiber) */
5183 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
5184 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
5186 MDIO_REG_BANK_SERDES_DIGITAL,
5187 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5188 control1);
5190 /* if forced speed */
5192 /* set speed, disable autoneg */
5193 u16 mii_control;
5196 MDIO_REG_BANK_COMBO_IEEE0,
5197 MDIO_COMBO_IEEE0_MII_CONTROL,
5200 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
5201 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
5205 mii_control |=
5206 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
5209 mii_control |=
5210 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
5213 /* there is nothing to set for 10M */
5216 /* invalid speed for SGMII */
5220 }
5222 /* setting the full duplex */
5224 mii_control |=
5225 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5227 MDIO_REG_BANK_COMBO_IEEE0,
5228 MDIO_COMBO_IEEE0_MII_CONTROL,
5229 mii_control);
5232 /* enable and restart AN */
5234 }
5235 }
5238 /*
5239 * link management
5240 */
5244 {
5250 MDIO_REG_BANK_SERDES_DIGITAL,
5251 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5254 MDIO_REG_BANK_SERDES_DIGITAL,
5255 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5261 }
5264 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5265 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
5272 }
5274 }
5279 u32 gp_status)
5280 {
5283 u16 pause_result;
5287 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5289 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5292 MDIO_REG_BANK_CL73_IEEEB1,
5293 MDIO_CL73_IEEEB1_AN_ADV1,
5296 MDIO_REG_BANK_CL73_IEEEB1,
5297 MDIO_CL73_IEEEB1_AN_LP_ADV1,
5306 MDIO_REG_BANK_COMBO_IEEE0,
5307 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5310 MDIO_REG_BANK_COMBO_IEEE0,
5311 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5318 }
5321 }
5326 u32 gp_status)
5327 {
5331 /* resolve from gp_status in case of AN complete and not sgmii */
5333 /* Update the advertised flow-controled of LD/LP in AN */
5336 /* But set the flow-control result as the requested one */
5345 }
5347 }
5349 }
5353 {
5357 /* Step 1: Make sure signal is detected */
5359 MDIO_REG_BANK_RX0,
5360 MDIO_RX0_RX_STATUS,
5367 MDIO_REG_BANK_CL73_IEEEB0,
5368 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5369 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5371 }
5372 /* Step 2: Check CL73 state machine */
5374 MDIO_REG_BANK_CL73_USERB0,
5375 MDIO_CL73_USERB0_CL73_USTAT1,
5379 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5381 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5385 }
5386 /*
5387 * Step 3: Check CL37 Message Pages received to indicate LP
5388 * supports only CL37
5389 */
5391 MDIO_REG_BANK_REMOTE_PHY,
5392 MDIO_REMOTE_PHY_MISC_RX_STATUS,
5396 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5398 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5401 cl37_fsm_received);
5403 }
5404 /*
5405 * The combined cl37/cl73 fsm state information indicating that
5406 * we are connected to a device which does not support cl73, but
5407 * does support cl37 BAM. In this case we disable cl73 and
5408 * restart cl37 auto-neg
5409 */
5411 /* Disable CL73 */
5413 MDIO_REG_BANK_CL73_IEEEB0,
5414 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5416 /* Restart CL37 autoneg */
5419 }
5424 u32 gp_status)
5425 {
5428 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5432 LINK_STATUS_PARALLEL_DETECTION_USED;
5433 }
5437 u16 is_link_up,
5438 u16 speed_mask,
5439 u16 is_duplex)
5440 {
5455 else
5463 else
5472 else
5480 else
5488 speed_mask);
5507 speed_mask);
5509 }
5518 }
5522 }
5527 {
5533 /* Read gp_status */
5535 MDIO_REG_BANK_GP_STATUS,
5536 MDIO_GP_STATUS_TOP_AN_STATUS1,
5546 duplex);
5555 gp_status);
5556 }
5560 /* Check signal is detected */
5562 }
5563 }
5565 /* Read LP advertised speeds*/
5568 u16 val;
5575 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5577 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5579 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5586 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5589 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5590 }
5595 }
5600 {
5602 u8 lane;
5606 /* Read gp_status */
5608 u16 temp_link_up;
5622 /* Check for either KR or generic link up. */
5629 /* Check Autoneg complete */
5631 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5635 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5637 /* Check parallel detect used */
5639 MDIO_WC_REG_PAR_DET_10G_STATUS,
5643 LINK_STATUS_PARALLEL_DETECTION_USED;
5644 }
5646 }
5647 }
5651 u16 val;
5658 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5660 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5662 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5669 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5672 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5674 }
5683 }
5692 duplex);
5697 }
5699 {
5702 u16 lp_up2;
5703 u16 tx_driver;
5704 u16 bank;
5706 /* read precomp */
5708 MDIO_REG_BANK_OVER_1G,
5711 /* bits [10:7] at lp_up2, positioned at [15:12] */
5713 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5714 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5722 bank,
5725 /* replace tx_driver bits [15:12] */
5731 bank,
5733 }
5734 }
5735 }
5739 {
5746 EMAC_REG_EMAC_MODE,
5748 EMAC_MODE_PORT_MII_10M |
5749 EMAC_MODE_HALF_DUPLEX));
5768 /* 10G not valid for EMAC */
5772 }
5778 mode);
5782 }
5786 {
5794 bank,
5795 MDIO_RX0_RX_EQ_BOOST,
5797 }
5802 bank,
5803 MDIO_TX0_TX_DRIVER,
5805 }
5806 }
5811 {
5818 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5821 /* forced speed requested? */
5827 /* disable autoneg */
5830 /* program speed and duplex */
5836 /* AN enabled */
5839 /* program duplex & pause advertisement (for aneg) */
5843 /* enable autoneg */
5846 /* enable and restart AN */
5848 }
5854 }
5855 }
5860 {
5868 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5870 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5873 else
5882 /* reset the SerDes and wait for reset bit return low */
5887 /* setting the masterLn_def again after the reset */
5891 }
5894 }
5899 {
5901 /* Wait for soft reset to get cleared up to 1 sec */
5906 else
5908 MDIO_PMA_DEVAD,
5913 }
5921 }
5924 {
5926 u32 mask;
5929 /* Setting the status to report on link up for either XGXS or SerDes */
5936 NIG_MASK_XGXS0_LINK_STATUS);
5940 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
5943 }
5950 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
5953 }
5954 }
5957 mask);
5969 }
5972 u8 exp_mi_int)
5973 {
5976 /*
5977 * Disable the MI INT ( external phy int ) by writing 1 to the
5978 * status register. Link down indication is high-active-signal,
5979 * so in this case we need to write the status to clear the XOR
5980 */
5981 /* Read Latched signals */
5985 /* Handle only those with latched-signal=up.*/
5988 NIG_REG_STATUS_INTERRUPT_PORT0
5990 NIG_STATUS_EMAC0_MI_INT);
5991 else
5993 NIG_REG_STATUS_INTERRUPT_PORT0
5995 NIG_STATUS_EMAC0_MI_INT);
5999 /* For all latched-signal=up : Re-Arm Latch signals */
6002 }
6003 /* For all latched-signal=up,Write original_signal to status */
6004 }
6008 {
6011 u32 mask;
6012 /*
6013 * First reset all status we assume only one line will be
6014 * change at a time
6015 */
6018 NIG_STATUS_XGXS0_LINK_STATUS |
6019 NIG_STATUS_SERDES0_LINK_STATUS));
6027 /*
6028 * Disable the link interrupt by writing 1 to
6029 * the relevant lane in the status register
6030 */
6031 u32 ser_lane =
6033 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
6034 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
6036 NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
6039 }
6041 mask);
6044 mask);
6045 }
6046 }
6049 {
6053 u8 digit;
6056 /* Need more than 10chars for this format */
6060 }
6070 else
6073 str_ptr++;
6078 str_ptr++;
6081 }
6082 }
6084 }
6088 {
6092 }
6095 u16 len)
6096 {
6106 /* Extract first external phy*/
6112 ver_p,
6115 }
6121 ver_p++;
6122 remain_len--;
6124 spirom_ver,
6125 ver_p,
6128 }
6129 }
6132 }
6136 {
6146 /* change the uni_phy_addr in the nig */
6152 }
6166 /* set aer mmd back */
6170 /* and md_devad */
6172 md_devad);
6173 }
6175 u16 mii_ctrl;
6184 mii_ctrl |
6185 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
6186 }
6187 }
6191 {
6195 u8 phy_idx;
6196 u32 tmp;
6202 /* In case */
6207 }
6208 }
6215 SHARED_HW_CFG_LED_MAC1);
6219 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6221 EMAC_LED_100MB_OVERRIDE |
6222 EMAC_LED_10MB_OVERRIDE);
6223 else
6230 /*
6231 * For all other phys, OPER mode is same as ON, so in case
6232 * link is down, do nothing
6233 */
6238 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
6240 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
6242 /*
6243 * This is a work-around for E2+8727 Configurations
6244 */
6253 /*
6254 * return here without enabling traffic
6255 * LED blink and setting rate in ON mode.
6256 * In oper mode, enabling LED blink
6257 * and setting rate is needed.
6258 */
6261 }
6263 /*
6264 * This is a work-around for HW issue found when link
6265 * is up in CL73
6266 */
6276 else
6278 hw_led_mode);
6280 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
6286 /* Break here; otherwise, it'll disable the
6287 * intended override.
6288 */
6292 hw_led_mode);
6295 /* Set blinking rate to ~15.9Hz */
6298 LED_BLINK_RATE_VAL_E3);
6299 else
6301 LED_BLINK_RATE_VAL_E1X_E2);
6313 /*
6314 * On Everest 1 Ax chip versions for speeds less than
6315 * 10G LED scheme is different
6316 */
6323 }
6329 mode);
6331 }
6334 }
6336 /*
6337 * This function comes to reflect the actual link state read DIRECTLY from the
6338 * HW
6339 */
6341 u8 is_serdes)
6342 {
6350 u16 link_up;
6353 /* Check 20G link */
6360 /* Check 10G link and below*/
6363 MDIO_WC_REG_GP2_STATUS_GP_2_1,
6368 }
6373 MDIO_REG_BANK_GP_STATUS,
6374 MDIO_GP_STATUS_TOP_AN_STATUS1,
6376 /* link is up only if both local phy and external phy are up */
6379 }
6380 /* In XGXS loopback mode, do not check external PHY */
6386 /* No external PHY */
6395 phy_index++) {
6397 ETH_PHY_SFP_FIBER) ||
6399 ETH_PHY_XFP_FIBER) ||
6401 ETH_PHY_DA_TWINAX));
6406 ext_phy_link_up |=
6410 }
6411 }
6413 }
6417 }
6421 {
6425 /*
6426 * In case of external phy existence, the line speed would be the
6427 * line speed linked up by the external phy. In case it is direct
6428 * only, then the line_speed during initialization will be
6429 * equal to the req_line_speed
6430 */
6433 /*
6434 * Initialize the internal phy in case this is a direct board
6435 * (no external phys), or this board has external phy which requires
6436 * to first.
6437 */
6440 /* init ext phy and enable link state int */
6454 params,
6455 vars);
6456 }
6458 /* Init external phy*/
6461 SUPPORTED_FIBRE)
6465 phy_index++) {
6466 /*
6467 * No need to initialize second phy in case of first
6468 * phy only selection. In case of second phy, we do
6469 * need to initialize the first phy, since they are
6470 * connected.
6471 */
6473 SUPPORTED_FIBRE)
6478 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6482 }
6486 }
6487 }
6488 /* Reset the interrupt indication after phy was initialized */
6492 NIG_STATUS_XGXS0_LINK_STATUS |
6493 NIG_STATUS_SERDES0_LINK_STATUS |
6494 NIG_MASK_MI_INT));
6497 }
6501 {
6502 /* reset the SerDes/XGXS */
6505 }
6509 {
6511 u8 gpio_port;
6512 /* HW reset */
6515 else
6518 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6519 gpio_port);
6521 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6522 gpio_port);
6524 }
6528 {
6535 /* indicate no mac active */
6538 /* update shared memory */
6540 LINK_STATUS_LINK_UP |
6541 LINK_STATUS_PHYSICAL_LINK_FLAG |
6542 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE |
6543 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK |
6544 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK |
6545 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK |
6546 LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE |
6547 LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE);
6551 /* activate nig drain */
6554 /* disable emac */
6559 /* reset BigMac/Xmac */
6564 MISC_REGISTERS_RESET_REG_2_CLEAR,
6566 }
6570 }
6573 }
6577 u8 link_10g)
6578 {
6584 LINK_STATUS_PHYSICAL_LINK_FLAG);
6589 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6593 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6602 }
6607 }
6617 }
6625 /* AN complete? */
6627 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6631 }
6632 }
6634 /* PBF - link up */
6639 /* disable drain */
6642 /* update shared memory */
6646 }
6647 /*
6648 * The bnx2x_link_update function should be called upon link
6649 * interrupt.
6650 * Link is considered up as follows:
6651 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6652 * to be up
6653 * - SINGLE_MEDIA - The link between the 577xx and the external
6654 * phy (XGXS) need to up as well as the external link of the
6655 * phy (PHY_EXT1)
6656 * - DUAL_MEDIA - The link between the 577xx and the first
6657 * external phy needs to be up, and at least one of the 2
6658 * external phy link must be up.
6659 */
6661 {
6673 phy_index++) {
6681 }
6694 is_mi_int,
6701 /* disable emac */
6705 /*
6706 * Step 1:
6707 * Check external link change only for external phys, and apply
6708 * priority selection between them in case the link on both phys
6709 * is up. Note that instead of the common vars, a temporary
6710 * vars argument is used since each phy may have different link/
6711 * speed/duplex result
6712 */
6714 phy_index++) {
6718 /* Read link status and params of this ext phy */
6723 phy_index);
6726 phy_index);
6728 }
6737 /*
6738 * In this option, the first PHY makes sure to pass the
6739 * traffic through itself only.
6740 * Its not clear how to reset the link on the second phy
6741 */
6745 /*
6746 * In this option, the first PHY makes sure to pass the
6747 * traffic through the second PHY.
6748 */
6752 /*
6753 * Link indication on both PHYs with the following cases
6754 * is invalid:
6755 * - FIRST_PHY means that second phy wasn't initialized,
6756 * hence its link is expected to be down
6757 * - SECOND_PHY means that first phy should not be able
6758 * to link up by itself (using configuration)
6759 * - DEFAULT should be overriden during initialiazation
6760 */
6766 }
6767 }
6768 }
6770 /*
6771 * Step 2:
6772 * Read the status of the internal phy. In case of
6773 * DIRECT_SINGLE_MEDIA board, this link is the external link,
6774 * otherwise this is the link between the 577xx and the first
6775 * external phy
6776 */
6781 /*
6782 * The INT_PHY flow control reside in the vars. This include the
6783 * case where the speed or flow control are not set to AUTO.
6784 * Otherwise, the active external phy flow control result is set
6785 * to the vars. The ext_phy_line_speed is needed to check if the
6786 * speed is different between the internal phy and external phy.
6787 * This case may be result of intermediate link speed change.
6788 */
6791 /*
6792 * Link speed is taken from the XGXS. AN and FC result from
6793 * the external phy.
6794 */
6797 /*
6798 * if active_external_phy is first PHY and link is up - disable
6799 * disable TX on second external PHY
6800 */
6808 }
6809 }
6814 SUPPORTED_FIBRE)
6816 else
6819 active_external_phy);
6820 }
6823 phy_index++) {
6825 FLAGS_REARM_LATCH_SIGNAL) {
6827 phy_index ==
6828 active_external_phy);
6830 }
6831 }
6835 /*
6836 * Upon link speed change set the NIG into drain mode. Comes to
6837 * deals with possible FIFO glitch due to clk change when speed
6838 * is decreased without link down indicator
6839 */
6845 " different than the external"
6847 ext_phy_line_speed);
6853 }
6854 }
6856 /* anything 10 and over uses the bmac */
6861 /*
6862 * In case external phy link is up, and internal link is down
6863 * (not initialized yet probably after link initialization, it
6864 * needs to be initialized.
6865 * Note that after link down-up as result of cable plug, the xgxs
6866 * link would probably become up again without the need
6867 * initialize it
6868 */
6874 FLAGS_INIT_XGXS_FIRST);
6876 FLAGS_INIT_XGXS_FIRST)
6881 else
6887 vars);
6888 }
6889 }
6890 /*
6891 * Link is up only if both local phy and external phy (in case of
6892 * non-direct board) are up and no fault detected on active PHY.
6893 */
6899 /* Update the PFC configuration in case it was changed */
6902 else
6907 else
6911 }
6913 /*****************************************************************************/
6914 /* External Phy section */
6915 /*****************************************************************************/
6917 {
6923 }
6927 {
6933 }
6937 u8 port)
6938 {
6947 }
6952 {
6953 u16 val;
6955 MDIO_AN_DEVAD,
6958 MDIO_AN_DEVAD,
6964 }
6966 /******************************************************************/
6967 /* common BCM8073/BCM8727 PHY SECTION */
6968 /******************************************************************/
6972 {
6978 }
6982 u16 pause_result;
6986 MDIO_AN_DEVAD,
6990 MDIO_AN_DEVAD,
6999 pause_result);
7000 }
7001 }
7004 u8 port)
7005 {
7010 /* Boot port from external ROM */
7011 /* EDC grst */
7013 MDIO_PMA_DEVAD,
7014 MDIO_PMA_REG_GEN_CTRL,
7017 /* ucode reboot and rst */
7019 MDIO_PMA_DEVAD,
7020 MDIO_PMA_REG_GEN_CTRL,
7024 MDIO_PMA_DEVAD,
7027 /* Reset internal microprocessor */
7029 MDIO_PMA_DEVAD,
7030 MDIO_PMA_REG_GEN_CTRL,
7031 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
7033 /* Release srst bit */
7035 MDIO_PMA_DEVAD,
7036 MDIO_PMA_REG_GEN_CTRL,
7037 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
7039 /* Delay 100ms per the PHY specifications */
7042 /* 8073 sometimes taking longer to download */
7044 count++;
7047 "bnx2x_8073_8727_external_rom_boot port %x:"
7052 }
7055 MDIO_PMA_DEVAD,
7058 MDIO_PMA_DEVAD,
7064 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
7066 /* Clear ser_boot_ctl bit */
7068 MDIO_PMA_DEVAD,
7073 "bnx2x_8073_8727_external_rom_boot port %x:"
7078 }
7080 /******************************************************************/
7081 /* BCM8073 PHY SECTION */
7082 /******************************************************************/
7084 {
7085 /* This is only required for 8073A1, version 102 only */
7086 u16 val;
7088 /* Read 8073 HW revision*/
7090 MDIO_PMA_DEVAD,
7094 /* No need to workaround in 8073 A1 */
7096 }
7099 MDIO_PMA_DEVAD,
7102 /* SNR should be applied only for version 0x102 */
7107 }
7110 {
7114 MDIO_PMA_DEVAD,
7118 /* No need to workaround in 8073 A1 */
7120 }
7121 /* XAUI workaround in 8073 A0: */
7123 /*
7124 * After loading the boot ROM and restarting Autoneg, poll
7125 * Dev1, Reg $C820:
7126 */
7130 MDIO_PMA_DEVAD,
7131 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7133 /*
7134 * If bit [14] = 0 or bit [13] = 0, continue on with
7135 * system initialization (XAUI work-around not required, as
7136 * these bits indicate 2.5G or 1G link up).
7137 */
7143 /*
7144 * If bit 15 is 0, then poll Dev1, Reg $C841 until it's
7145 * MSB (bit15) goes to 1 (indicating that the XAUI
7146 * workaround has completed), then continue on with
7147 * system initialization.
7148 */
7151 MDIO_PMA_DEVAD,
7157 }
7159 }
7161 }
7163 }
7166 }
7169 {
7170 /* Force KR or KX */
7179 }
7184 {
7185 u16 cl37_val;
7191 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
7194 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
7195 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
7197 }
7199 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
7200 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
7202 }
7204 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
7205 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
7207 }
7214 }
7219 {
7222 u8 gpio_port;
7227 else
7229 /* Restore normal power mode*/
7236 /* enable LASI */
7252 /* Swap polarity if required - Must be done only in non-1G mode */
7254 /* Configure the 8073 to swap _P and _N of the KR lines */
7256 /* 10G Rx/Tx and 1G Tx signal polarity swap */
7258 MDIO_PMA_DEVAD,
7261 MDIO_PMA_DEVAD,
7262 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
7264 }
7267 /* Enable CL37 BAM */
7271 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
7274 MDIO_AN_DEVAD,
7277 MDIO_AN_DEVAD,
7280 }
7288 }
7294 /*
7295 * Note that 2.5G works only when used with 1G
7296 * advertisement
7297 */
7303 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
7306 /* Note that 2.5G works only when used with 1G advertisement */
7309 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
7312 }
7320 u16 phy_ver;
7321 /* Allow 2.5G for A1 and above */
7328 else
7333 }
7336 /* Add support for CL37 (passive mode) II */
7343 /* Add support for CL37 (passive mode) III */
7346 /*
7347 * The SNR will improve about 2db by changing BW and FEE main
7348 * tap. Rest commands are executed after link is up
7349 * Change FFE main cursor to 5 in EDC register
7350 */
7356 /* Enable FEC (Forware Error Correction) Request in the AN */
7363 /* Restart autoneg */
7369 }
7374 {
7386 /* clear the interrupt LASI status register */
7392 /* Clear MSG-OUT */
7396 /* Check the LASI */
7402 /* Check the link status */
7418 }
7424 /* Check the link status on 1.1.2 */
7434 /*
7435 * The SNR will improve about 2dbby changing the BW and FEE main
7436 * tap. The 1st write to change FFE main tap is set before
7437 * restart AN. Change PLL Bandwidth in EDC register
7438 */
7443 /* Change CDR Bandwidth in EDC register */
7447 }
7452 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7472 }
7475 /* Swap polarity if required */
7477 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7478 /* Configure the 8073 to swap P and N of the KR lines */
7480 MDIO_XS_DEVAD,
7482 /*
7483 * Set bit 3 to invert Rx in 1G mode and clear this bit
7484 * when it`s in 10G mode.
7485 */
7494 MDIO_XS_DEVAD,
7495 MDIO_XS_REG_8073_RX_CTRL_PCIE,
7496 val1);
7497 }
7501 }
7509 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
7512 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
7513 }
7516 }
7520 {
7522 u8 gpio_port;
7525 else
7528 gpio_port);
7530 MISC_REGISTERS_GPIO_OUTPUT_LOW,
7531 gpio_port);
7532 }
7534 /******************************************************************/
7535 /* BCM8705 PHY SECTION */
7536 /******************************************************************/
7540 {
7543 /* Restore normal power mode*/
7546 /* HW reset */
7559 /* BCM8705 doesn't have microcode, hence the 0 */
7562 }
7567 {
7593 }
7595 }
7597 /******************************************************************/
7598 /* SFP+ module Section */
7599 /******************************************************************/
7602 u8 pmd_dis)
7603 {
7605 /*
7606 * Disable transmitter only for bootcodes which can enable it afterwards
7607 * (for D3 link)
7608 */
7611 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED)
7616 }
7620 MDIO_PMA_DEVAD,
7622 }
7625 {
7626 u8 gpio_port;
7631 else
7636 }
7640 u8 tx_en)
7641 {
7642 u16 val;
7645 u32 tx_en_mode;
7647 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
7651 PORT_HW_CFG_TX_LASER_MASK;
7658 MDIO_PMA_DEVAD,
7659 MDIO_PMA_REG_PHY_IDENTIFIER,
7664 else
7668 MDIO_PMA_DEVAD,
7669 MDIO_PMA_REG_PHY_IDENTIFIER,
7670 val);
7676 {
7677 u16 gpio_pin;
7681 else
7688 }
7692 }
7693 }
7697 u8 tx_en)
7698 {
7703 else
7705 }
7710 {
7713 u16 i;
7718 }
7719 /* Set the read command byte count */
7724 /* Set the read command address */
7727 addr);
7729 /* Activate read command */
7734 /* Wait up to 500us for command complete status */
7737 MDIO_PMA_DEVAD,
7740 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7743 }
7746 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7751 }
7753 /* Read the buffer */
7756 MDIO_PMA_DEVAD,
7759 }
7763 MDIO_PMA_DEVAD,
7766 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7769 }
7771 }
7777 {
7781 u16 addr32;
7783 /*DP(NETIF_MSG_LINK, "bnx2x_direct_read_sfp_module_eeprom:"
7784 " addr %d, cnt %d\n",
7785 addr, byte_cnt);*/
7790 }
7792 /* 4 byte aligned address */
7796 data_array);
7802 j++;
7803 }
7804 }
7807 }
7812 {
7820 }
7822 /* Need to read from 1.8000 to clear it */
7824 MDIO_PMA_DEVAD,
7825 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7828 /* Set the read command byte count */
7830 MDIO_PMA_DEVAD,
7831 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7834 /* Set the read command address */
7836 MDIO_PMA_DEVAD,
7837 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7838 addr);
7839 /* Set the destination address */
7841 MDIO_PMA_DEVAD,
7843 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
7845 /* Activate read command */
7847 MDIO_PMA_DEVAD,
7848 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7850 /*
7851 * Wait appropriate time for two-wire command to finish before
7852 * polling the status register
7853 */
7856 /* Wait up to 500us for command complete status */
7859 MDIO_PMA_DEVAD,
7862 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7865 }
7868 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7873 }
7875 /* Read the buffer */
7878 MDIO_PMA_DEVAD,
7881 }
7885 MDIO_PMA_DEVAD,
7888 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7891 }
7894 }
7899 {
7915 }
7917 }
7922 {
7929 /* First check for copper cable */
7931 params,
7932 SFP_EEPROM_CON_TYPE_ADDR,
7937 }
7941 {
7942 u8 copper_module_type;
7944 /*
7945 * Check if its active cable (includes SFP+ module)
7946 * of passive cable
7947 */
7949 params,
7950 SFP_EEPROM_FC_TX_TECH_ADDR,
7954 "Failed to read copper-cable-type"
7957 }
7960 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
7964 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
7968 EDC_MODE_PASSIVE_DAC;
7972 copper_module_type);
7974 }
7976 }
7984 val);
7986 }
7991 /* Update media type for non-PMF sync */
7997 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
8000 }
8001 }
8006 params,
8007 SFP_EEPROM_OPTIONS_ADDR,
8008 SFP_EEPROM_OPTIONS_SIZE,
8013 }
8016 else
8018 }
8021 }
8022 /*
8023 * This function read the relevant field from the module (SFP+), and verify it
8024 * is compliant with this board
8025 */
8028 {
8039 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
8042 }
8045 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
8046 /* Use specific phy request */
8049 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
8050 /* Use first phy request only in case of non-dual media*/
8055 }
8058 /* No support in OPT MDL detection */
8062 }
8069 }
8071 /* format the warning message */
8073 params,
8074 SFP_EEPROM_VENDOR_NAME_ADDR,
8075 SFP_EEPROM_VENDOR_NAME_SIZE,
8078 else
8081 params,
8082 SFP_EEPROM_PART_NO_ADDR,
8083 SFP_EEPROM_PART_NO_SIZE,
8086 else
8093 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)
8096 }
8101 {
8102 u8 val;
8104 u16 timeout;
8105 /*
8106 * Initialization time after hot-plug may take up to 300ms for
8107 * some phys type ( e.g. JDSU )
8108 */
8117 }
8119 }
8121 }
8125 u8 is_power_up) {
8126 /* Make sure GPIOs are not using for LED mode */
8127 u16 val;
8128 /*
8129 * In the GPIO register, bit 4 is use to determine if the GPIOs are
8130 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
8131 * output
8132 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
8133 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
8134 * where the 1st bit is the over-current(only input), and 2nd bit is
8135 * for power( only output )
8136 *
8137 * In case of NOC feature is disabled and power is up, set GPIO control
8138 * as input to enable listening of over-current indication
8139 */
8144 else
8145 /*
8146 * Set GPIO control to OUTPUT, and set the power bit
8147 * to according to the is_power_up
8148 */
8152 MDIO_PMA_DEVAD,
8153 MDIO_PMA_REG_8727_GPIO_CTRL,
8154 val);
8155 }
8159 u16 edc_mode)
8160 {
8161 u16 cur_limiting_mode;
8164 MDIO_PMA_DEVAD,
8165 MDIO_PMA_REG_ROM_VER2,
8168 cur_limiting_mode);
8173 MDIO_PMA_DEVAD,
8174 MDIO_PMA_REG_ROM_VER2,
8175 EDC_MODE_LIMITING);
8180 /*
8181 * Changing to LRM mode takes quite few seconds. So do it only
8182 * if current mode is limiting (default is LRM)
8183 */
8188 MDIO_PMA_DEVAD,
8189 MDIO_PMA_REG_LRM_MODE,
8192 MDIO_PMA_DEVAD,
8193 MDIO_PMA_REG_ROM_VER2,
8196 MDIO_PMA_DEVAD,
8197 MDIO_PMA_REG_MISC_CTRL0,
8200 MDIO_PMA_DEVAD,
8201 MDIO_PMA_REG_LRM_MODE,
8203 }
8205 }
8209 u16 edc_mode)
8210 {
8211 u16 phy_identifier;
8212 u16 rom_ver2_val;
8214 MDIO_PMA_DEVAD,
8215 MDIO_PMA_REG_PHY_IDENTIFIER,
8219 MDIO_PMA_DEVAD,
8220 MDIO_PMA_REG_PHY_IDENTIFIER,
8224 MDIO_PMA_DEVAD,
8225 MDIO_PMA_REG_ROM_VER2,
8227 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
8229 MDIO_PMA_DEVAD,
8230 MDIO_PMA_REG_ROM_VER2,
8234 MDIO_PMA_DEVAD,
8235 MDIO_PMA_REG_PHY_IDENTIFIER,
8239 }
8243 u32 action)
8244 {
8257 action);
8259 }
8260 }
8263 u8 gpio_mode)
8264 {
8270 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
8278 {
8281 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
8286 }
8290 fault_led_gpio);
8291 }
8292 }
8295 u8 gpio_mode)
8296 {
8297 u32 pin_cfg;
8303 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
8304 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
8308 }
8311 u8 gpio_mode)
8312 {
8316 /*
8317 * Low ==> if SFP+ module is supported otherwise
8318 * High ==> if SFP+ module is not on the approved vendor list
8319 */
8323 }
8327 u8 power)
8328 {
8329 u32 pin_cfg;
8335 PORT_HW_CFG_E3_PWR_DIS_MASK) >>
8336 PORT_HW_CFG_E3_PWR_DIS_SHIFT;
8342 /*
8343 * Low ==> corresponding SFP+ module is powered
8344 * high ==> the SFP+ module is powered down
8345 */
8347 }
8351 {
8354 /* Put Warpcore in low power mode */
8357 /* Put LCPLL in low power mode */
8361 }
8365 u8 power)
8366 {
8380 }
8381 }
8384 u16 edc_mode)
8385 {
8391 /* This is a global register which controls all lanes */
8406 }
8411 /* A must read */
8415 /* Restart microcode to re-read the new mode */
8419 }
8423 u16 edc_mode)
8424 {
8436 }
8437 }
8441 {
8443 u16 edc_mode;
8452 /* Power up module */
8458 /* check SFP+ module compatibility */
8461 /* Turn on fault module-detected led */
8463 MISC_REGISTERS_GPIO_HIGH);
8465 /* Check if need to power down the SFP+ module */
8467 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8471 }
8473 /* Turn off fault module-detected led */
8475 }
8477 /*
8478 * Check and set limiting mode / LRM mode on 8726. On 8727 it
8479 * is done automatically
8480 */
8483 /*
8484 * Enable transmit for this module if the module is approved, or
8485 * if unapproved modules should also enable the Tx laser
8486 */
8489 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8491 else
8495 }
8498 {
8501 u32 gpio_val;
8505 else
8513 }
8515 /* Set valid module led off */
8518 /* Get current gpio val reflecting module plugged in / out*/
8521 /* Call the handling function in case module is detected */
8525 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8526 gpio_port);
8529 else
8535 config));
8537 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8538 gpio_port);
8539 /*
8540 * Module was plugged out.
8541 * Disable transmit for this module
8542 */
8545 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) ||
8548 }
8549 }
8551 /******************************************************************/
8552 /* Used by 8706 and 8727 */
8553 /******************************************************************/
8556 u16 alarm_status_offset,
8557 u16 alarm_ctrl_offset)
8558 {
8566 /* Mask or enable the fault event. */
8570 else
8573 }
8574 /******************************************************************/
8575 /* common BCM8706/BCM8726 PHY SECTION */
8576 /******************************************************************/
8580 {
8585 /* Clear RX Alarm*/
8590 MDIO_PMA_LASI_TXCTRL);
8592 /* clear LASI indication*/
8610 /*
8611 * link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8612 * are set, or if the autoneg bit 1 is set
8613 */
8618 else
8622 }
8624 /* Capture 10G link fault. Read twice to clear stale value. */
8632 }
8635 }
8637 /******************************************************************/
8638 /* BCM8706 PHY SECTION */
8639 /******************************************************************/
8643 {
8644 u32 tx_en_mode;
8650 /* HW reset */
8655 /* Wait until fw is loaded */
8662 }
8665 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8666 u8 i;
8667 u16 reg;
8671 MDIO_XS_8706_REG_BANK_RX0);
8673 /* Clear first 3 bits of the control */
8675 /* Set control bits according to configuration */
8680 }
8681 }
8682 /* Force speed */
8687 MDIO_PMA_DEVAD,
8692 /* Arm LASI for link and Tx fault. */
8696 /* Force 1Gbps using autoneg with 1G advertisement */
8698 /* Allow CL37 through CL73 */
8703 /* Enable Full-Duplex advertisement on CL37 */
8706 /* Enable CL37 AN */
8709 /* 1G support */
8713 /* Enable clause 73 AN */
8722 }
8725 /*
8726 * If TX Laser is controlled by GPIO_0, do not let PHY go into low
8727 * power mode, if TX Laser is disabled
8728 */
8742 }
8745 }
8750 {
8752 }
8754 /******************************************************************/
8755 /* BCM8726 PHY SECTION */
8756 /******************************************************************/
8759 {
8763 }
8767 {
8769 /* Need to wait 100ms after reset */
8772 /* Micro controller re-boot */
8776 /* Set soft reset */
8778 MDIO_PMA_DEVAD,
8779 MDIO_PMA_REG_GEN_CTRL,
8780 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
8783 MDIO_PMA_DEVAD,
8787 MDIO_PMA_DEVAD,
8788 MDIO_PMA_REG_GEN_CTRL,
8789 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
8791 /* wait for 150ms for microcode load */
8794 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8796 MDIO_PMA_DEVAD,
8801 }
8806 {
8808 u16 val1;
8818 }
8819 }
8821 }
8827 {
8836 /*
8837 * Need to call module detected on initialization since the module
8838 * detection triggered by actual module insertion might occur before
8839 * driver is loaded, and when driver is loaded, it reset all
8840 * registers, including the transmitter
8841 */
8857 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
8859 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8860 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8862 /* Set Flow control */
8874 /*
8875 * Enable RX-ALARM control to receive interrupt for 1G speed
8876 * change
8877 */
8887 }
8889 /* Set TX PreEmphasis if needed */
8891 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8897 MDIO_PMA_DEVAD,
8898 MDIO_PMA_REG_8726_TX_CTRL1,
8902 MDIO_PMA_DEVAD,
8903 MDIO_PMA_REG_8726_TX_CTRL2,
8905 }
8909 }
8913 {
8916 /* Set serial boot control for external load */
8918 MDIO_PMA_DEVAD,
8920 }
8922 /******************************************************************/
8923 /* BCM8727 PHY SECTION */
8924 /******************************************************************/
8928 {
8932 u16 val;
8933 /* Only NOC flavor requires to set the LED specifically */
8950 }
8952 MDIO_PMA_DEVAD,
8953 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8958 MDIO_PMA_DEVAD,
8959 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8960 val);
8962 MDIO_PMA_DEVAD,
8963 MDIO_PMA_REG_8727_GPIO_CTRL,
8968 MDIO_PMA_DEVAD,
8969 MDIO_PMA_REG_8727_GPIO_CTRL,
8970 val);
8971 }
8975 u8 port;
8976 /*
8977 * The PHY reset is controlled by GPIO 1. Fake the port number
8978 * to cancel the swap done in set_gpio()
8979 */
8986 }
8991 {
8992 u32 tx_en_mode;
8994 u16 rx_alarm_ctrl_val;
8995 u16 lasi_ctrl_val;
8997 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
9001 /* Should be 0x6 to enable XS on Tx side. */
9005 /* enable LASI */
9008 rx_alarm_ctrl_val);
9015 /*
9016 * Initially configure MOD_ABS to interrupt when module is
9017 * presence( bit 8)
9018 */
9021 /*
9022 * Set EDC off by setting OPTXLOS signal input to low (bit 9).
9023 * When the EDC is off it locks onto a reference clock and avoids
9024 * becoming 'lost'
9025 */
9033 /* Enable/Disable PHY transmitter output */
9036 /* Make MOD_ABS give interrupt on change */
9043 /*
9044 * Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
9045 * status which reflect SFP+ module over-current
9046 */
9060 /* Set option 1G speed */
9070 /*
9071 * Power down the XAUI until link is up in case of dual-media
9072 * and 1G
9073 */
9076 MDIO_PMA_DEVAD,
9080 MDIO_PMA_DEVAD,
9082 }
9085 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
9087 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9088 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9096 /*
9097 * Since the 8727 has only single reset pin, need to set the 10G
9098 * registers although it is default
9099 */
9110 }
9112 /*
9113 * Set 2-wire transfer rate of SFP+ module EEPROM
9114 * to 100Khz since some DACs(direct attached cables) do
9115 * not work at 400Khz.
9116 */
9121 /* Set TX PreEmphasis if needed */
9123 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9134 }
9136 /*
9137 * If TX Laser is controlled by GPIO_0, do not let PHY go into low
9138 * power mode, if TX Laser is disabled
9139 */
9160 }
9163 }
9167 {
9173 config));
9175 MDIO_PMA_DEVAD,
9179 /* Module is absent */
9183 /*
9184 * 1. Set mod_abs to detect next module
9185 * presence event
9186 * 2. Set EDC off by setting OPTXLOS signal input to low
9187 * (bit 9).
9188 * When the EDC is off it locks onto a reference clock and
9189 * avoids becoming 'lost'.
9190 */
9195 MDIO_PMA_DEVAD,
9198 /*
9199 * Clear RX alarm since it stays up as long as
9200 * the mod_abs wasn't changed
9201 */
9203 MDIO_PMA_DEVAD,
9207 /* Module is present */
9210 /*
9211 * First disable transmitter, and if the module is ok, the
9212 * module_detection will enable it
9213 * 1. Set mod_abs to detect next module absent event ( bit 8)
9214 * 2. Restore the default polarity of the OPRXLOS signal and
9215 * this signal will then correctly indicate the presence or
9216 * absence of the Rx signal. (bit 9)
9217 */
9222 MDIO_PMA_DEVAD,
9225 /*
9226 * Clear RX alarm since it stays up as long as the mod_abs
9227 * wasn't changed. This is need to be done before calling the
9228 * module detection, otherwise it will clear* the link update
9229 * alarm
9230 */
9232 MDIO_PMA_DEVAD,
9237 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
9242 else
9244 }
9247 rx_alarm_status);
9248 /* No need to check link status in case of module plugged in/out */
9249 }
9255 {
9261 /* If PHY is not initialized, do not check link status */
9268 /* Check the LASI on Rx */
9276 MDIO_PMA_LASI_TXCTRL);
9283 /* Clear MSG-OUT */
9287 /*
9288 * If a module is present and there is need to check
9289 * for over current
9290 */
9292 /* Check over-current using 8727 GPIO0 input*/
9302 oc_port);
9304 "been detected and the power to "
9305 "that SFP+ module has been removed "
9306 "to prevent failure of the card. "
9307 "Please remove the SFP+ module and "
9308 "restart the system to clear this "
9310 oc_port);
9311 /* Disable all RX_ALARMs except for mod_abs */
9313 MDIO_PMA_DEVAD,
9317 MDIO_PMA_DEVAD,
9319 /* Wait for module_absent_event */
9322 MDIO_PMA_DEVAD,
9324 /* Clear RX alarm */
9326 MDIO_PMA_DEVAD,
9329 }
9332 /* When module absent bit is set, check module */
9335 /* Enable all mod_abs and link detection bits */
9339 }
9347 }
9350 MDIO_PMA_DEVAD,
9353 /*
9354 * Bits 0..2 --> speed detected,
9355 * Bits 13..15--> link is down
9356 */
9371 }
9373 /* Capture 10G link fault. */
9383 }
9384 }
9390 }
9395 MDIO_PMA_DEVAD,
9397 /*
9398 * In case of dual-media board and 1G, power up the XAUI side,
9399 * otherwise power it down. For 10G it is done automatically
9400 */
9403 else
9406 MDIO_PMA_DEVAD,
9408 }
9410 }
9414 {
9417 /* Enable/Disable PHY transmitter output */
9420 /* Disable Transmitter */
9422 /* Clear LASI */
9425 }
9427 /******************************************************************/
9428 /* BCM8481/BCM84823/BCM84833 PHY SECTION */
9429 /******************************************************************/
9432 u8 port)
9433 {
9441 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
9442 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9454 }
9461 }
9464 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9473 }
9480 }
9482 /* lower 16 bits of the register SPI_FW_STATUS */
9484 /* upper 16 bits of register SPI_FW_STATUS */
9489 }
9491 }
9494 {
9497 /* PHYC_CTL_LED_CTL */
9499 MDIO_PMA_DEVAD,
9505 MDIO_PMA_DEVAD,
9509 MDIO_PMA_DEVAD,
9510 MDIO_PMA_REG_8481_LED1_MASK,
9514 MDIO_PMA_DEVAD,
9515 MDIO_PMA_REG_8481_LED2_MASK,
9518 /* Select activity source by Tx and Rx, as suggested by PHY AE */
9520 MDIO_PMA_DEVAD,
9521 MDIO_PMA_REG_8481_LED3_MASK,
9524 /* Select the closest activity blink rate to that in 10/100/1000 */
9526 MDIO_PMA_DEVAD,
9527 MDIO_PMA_REG_8481_LED3_BLINK,
9530 /* Configure the blink rate to ~15.9 Hz */
9532 MDIO_PMA_DEVAD,
9533 MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
9534 MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ);
9538 else
9547 /* 'Interrupt Mask' */
9549 MDIO_AN_DEVAD,
9551 }
9556 {
9561 /* Save spirom version */
9563 }
9564 /*
9565 * This phy uses the NIG latch mechanism since link indication
9566 * arrives through its LED4 and not via its LASI signal, so we
9567 * get steady signal instead of clear on read
9568 */
9577 /* set 1000 speed advertisement */
9584 MDIO_AN_DEVAD,
9585 MDIO_AN_REG_8481_LEGACY_AN_ADV,
9590 /* Disable forced speed */
9596 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9608 an_1000_val);
9610 /* set 100 speed advertisement */
9614 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))) {
9616 /* Enable autoneg and restart autoneg for legacy speeds */
9622 }
9623 /* set 10 speed advertisement */
9627 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) &&
9630 SUPPORTED_10baseT_Full)))) {
9636 }
9638 /* Only 10/100 are allowed to work in FORCE mode */
9642 SUPPORTED_100baseT_Full))) {
9644 /* Enabled AUTO-MDIX when autoneg is disabled */
9648 /* The PHY needs this set even for forced link. */
9651 }
9655 SUPPORTED_10baseT_Full))) {
9656 /* Enabled AUTO-MDIX when autoneg is disabled */
9661 }
9665 an_10_100_val);
9670 /*
9671 * Always write this if this is not 84833.
9672 * For 84833, write it only when it's a forced speed.
9673 */
9677 MDIO_AN_DEVAD,
9682 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9685 /* Restart autoneg for 10G*/
9688 MDIO_AN_DEVAD,
9689 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9692 MDIO_AN_DEVAD,
9693 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9700 MDIO_AN_DEVAD,
9701 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9705 }
9710 {
9712 /* Restore normal power mode*/
9716 /* HW reset */
9722 }
9724 #define PHY84833_CMDHDLR_WAIT 300
9725 #define PHY84833_CMDHDLR_MAX_ARGS 5
9728 u16 fw_cmd,
9729 u16 cmd_args[])
9730 {
9731 u32 idx;
9732 u16 val;
9734 /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9736 MDIO_84833_CMD_HDLR_STATUS,
9737 PHY84833_STATUS_CMD_OPEN_OVERRIDE);
9744 }
9748 }
9750 /* Prepare argument(s) and issue command */
9755 }
9765 }
9770 }
9771 /* Gather returning data */
9776 }
9778 MDIO_84833_CMD_HDLR_STATUS,
9779 PHY84833_STATUS_CMD_CLEAR_COMPLETE);
9781 }
9787 {
9788 u32 pair_swap;
9793 /* Check for configuration. */
9797 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
9802 /* Only the second argument is used for this command */
9811 }
9814 u32 shmem_base_path[],
9815 u32 chip_id)
9816 {
9818 u32 idx;
9819 u8 reset_gpios;
9821 /* Assume that these will be GPIOs, not EPIOs. */
9823 /* Map config param to register bit. */
9828 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9829 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9832 }
9835 /* E2, look from diff place of shmem. */
9844 }
9846 }
9849 }
9853 {
9855 u8 reset_gpios;
9858 other_shmem_base_addr));
9862 /* Work around for 84833 LED failure inside RESET status */
9864 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9865 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
9867 MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
9868 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
9879 reset_gpios);
9882 }
9884 #define PHY84833_CONSTANT_LATENCY 1193
9888 {
9891 u16 val;
9900 else
9905 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
9906 port);
9908 /* MDIO reset */
9910 MDIO_PMA_DEVAD,
9912 }
9916 /* Wait for GPHY to come out of reset */
9919 /*
9920 * BCM84823 requires that XGXS links up first @ 10G for normal
9921 * behavior.
9922 */
9923 u16 temp;
9929 }
9934 MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
9935 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
9936 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
9937 MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
9941 MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
9944 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
9945 }
9951 /* Do nothing. Essentially this is like the priority copper */
9960 /* Do nothing here. The first PHY won't be initialized at all */
9966 }
9978 /* Keep AutogrEEEn disabled. */
9987 }
9990 else
9992 /* 84833 PHY has a better feature and doesn't need to support this. */
9997 PORT_HW_CFG_ENABLE_CMS_MASK;
10003 else
10007 }
10010 /* Bring PHY out of super isolate mode as the final step. */
10012 MDIO_CTL_DEVAD,
10016 MDIO_CTL_DEVAD,
10018 }
10020 }
10025 {
10031 /* Check 10G-BaseT link status */
10032 /* Check PMD signal ok */
10040 /* Check link 10G */
10049 /* Enable expansion register 0x42 (Operation mode status) */
10051 MDIO_AN_DEVAD,
10054 /* Get legacy speed operation status */
10056 MDIO_AN_DEVAD,
10057 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
10061 legacy_status);
10076 else
10083 /* Check legacy speed AN resolution */
10085 MDIO_AN_DEVAD,
10086 MDIO_AN_REG_8481_LEGACY_MII_STATUS,
10090 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10092 MDIO_AN_DEVAD,
10093 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
10097 LINK_STATUS_PARALLEL_DETECTION_USED;
10098 }
10099 }
10105 /* Read LP advertised speeds */
10110 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10113 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10116 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10119 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10122 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10129 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
10132 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
10139 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
10140 }
10143 }
10147 {
10149 u32 spirom_ver;
10153 }
10157 {
10162 }
10166 {
10171 }
10175 {
10177 u8 port;
10178 u16 val16;
10182 else
10187 MISC_REGISTERS_GPIO_OUTPUT_LOW,
10188 port);
10191 MDIO_CTL_DEVAD,
10195 MDIO_CTL_DEVAD,
10197 }
10198 }
10202 {
10204 u16 val;
10205 u8 port;
10209 else
10218 SHARED_HW_CFG_LED_EXTPHY1) {
10220 /* Set LED masks */
10222 MDIO_PMA_DEVAD,
10223 MDIO_PMA_REG_8481_LED1_MASK,
10227 MDIO_PMA_DEVAD,
10228 MDIO_PMA_REG_8481_LED2_MASK,
10232 MDIO_PMA_DEVAD,
10233 MDIO_PMA_REG_8481_LED3_MASK,
10237 MDIO_PMA_DEVAD,
10238 MDIO_PMA_REG_8481_LED5_MASK,
10243 MDIO_PMA_DEVAD,
10244 MDIO_PMA_REG_8481_LED1_MASK,
10246 }
10251 port);
10254 SHARED_HW_CFG_LED_EXTPHY1) {
10256 /* Set LED masks */
10258 MDIO_PMA_DEVAD,
10259 MDIO_PMA_REG_8481_LED1_MASK,
10263 MDIO_PMA_DEVAD,
10264 MDIO_PMA_REG_8481_LED2_MASK,
10268 MDIO_PMA_DEVAD,
10269 MDIO_PMA_REG_8481_LED3_MASK,
10273 MDIO_PMA_DEVAD,
10274 MDIO_PMA_REG_8481_LED5_MASK,
10279 MDIO_PMA_DEVAD,
10280 MDIO_PMA_REG_8481_LED1_MASK,
10282 }
10289 SHARED_HW_CFG_LED_EXTPHY1) {
10290 /* Set control reg */
10292 MDIO_PMA_DEVAD,
10293 MDIO_PMA_REG_8481_LINK_SIGNAL,
10299 MDIO_PMA_DEVAD,
10300 MDIO_PMA_REG_8481_LINK_SIGNAL,
10301 val);
10303 /* Set LED masks */
10305 MDIO_PMA_DEVAD,
10306 MDIO_PMA_REG_8481_LED1_MASK,
10310 MDIO_PMA_DEVAD,
10311 MDIO_PMA_REG_8481_LED2_MASK,
10315 MDIO_PMA_DEVAD,
10316 MDIO_PMA_REG_8481_LED3_MASK,
10320 MDIO_PMA_DEVAD,
10321 MDIO_PMA_REG_8481_LED5_MASK,
10325 MDIO_PMA_DEVAD,
10326 MDIO_PMA_REG_8481_LED1_MASK,
10328 }
10336 SHARED_HW_CFG_LED_EXTPHY1) {
10338 /* Set control reg */
10340 MDIO_PMA_DEVAD,
10341 MDIO_PMA_REG_8481_LINK_SIGNAL,
10345 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
10349 MDIO_PMA_DEVAD,
10350 MDIO_PMA_REG_8481_LINK_SIGNAL,
10352 }
10354 /* Set LED masks */
10356 MDIO_PMA_DEVAD,
10357 MDIO_PMA_REG_8481_LED1_MASK,
10361 MDIO_PMA_DEVAD,
10362 MDIO_PMA_REG_8481_LED2_MASK,
10366 MDIO_PMA_DEVAD,
10367 MDIO_PMA_REG_8481_LED3_MASK,
10371 MDIO_PMA_DEVAD,
10372 MDIO_PMA_REG_8481_LED5_MASK,
10377 MDIO_PMA_DEVAD,
10378 MDIO_PMA_REG_8481_LED1_MASK,
10381 /* Tell LED3 to blink on source */
10383 MDIO_PMA_DEVAD,
10384 MDIO_PMA_REG_8481_LINK_SIGNAL,
10389 MDIO_PMA_DEVAD,
10390 MDIO_PMA_REG_8481_LINK_SIGNAL,
10391 val);
10392 }
10394 }
10396 /*
10397 * This is a workaround for E3+84833 until autoneg
10398 * restart is fixed in f/w
10399 */
10403 }
10404 }
10406 /******************************************************************/
10407 /* 54618SE PHY SECTION */
10408 /******************************************************************/
10412 {
10414 u8 port;
10416 u32 cfg_pin;
10421 /*
10422 * This works with E3 only, no need to check the chip
10423 * before determining the port.
10424 */
10430 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10431 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10433 /* Drive pin high to bring the GPHY out of reset. */
10436 /* wait for GPHY to reset */
10439 /* reset phy */
10444 /*wait for GPHY to reset */
10447 /* Configure LED4: set to INTR (0x6). */
10448 /* Accessing shadow register 0xe. */
10450 MDIO_REG_GPHY_SHADOW,
10451 MDIO_REG_GPHY_SHADOW_LED_SEL2);
10453 MDIO_REG_GPHY_SHADOW,
10458 MDIO_REG_GPHY_SHADOW,
10460 /* Configure INTR based on link status change. */
10462 MDIO_REG_INTR_MASK,
10465 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10467 MDIO_REG_GPHY_SHADOW,
10468 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
10470 MDIO_REG_GPHY_SHADOW,
10474 MDIO_REG_GPHY_SHADOW,
10477 /* Set up fc */
10478 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10482 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
10486 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10489 /* read all advertisement */
10499 MDIO_PMA_REG_CTRL,
10502 /* Disable forced speed */
10509 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10521 an_1000_val);
10526 /* set 100 speed advertisement */
10530 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
10532 /* Enable autoneg and restart autoneg for legacy speeds */
10538 }
10540 /* set 10 speed advertisement */
10544 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
10550 }
10552 /* Only 10/100 are allowed to work in FORCE mode */
10555 /* Enabled AUTO-MDIX when autoneg is disabled */
10560 }
10562 /* Enabled AUTO-MDIX when autoneg is disabled */
10567 }
10569 /* Check if we should turn on Auto-GrEEEn */
10573 FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
10579 }
10583 MDIO_REG_GPHY_CL45_DATA_REG,
10584 MDIO_REG_GPHY_EEE_ADV);
10586 MDIO_REG_GPHY_CL45_ADDR_REG,
10589 MDIO_REG_GPHY_CL45_DATA_REG,
10590 temp);
10591 }
10604 }
10609 {
10611 u16 temp;
10614 MDIO_REG_GPHY_SHADOW,
10615 MDIO_REG_GPHY_SHADOW_LED_SEL1);
10617 MDIO_REG_GPHY_SHADOW,
10635 }
10637 MDIO_REG_GPHY_SHADOW,
10640 }
10645 {
10647 u32 cfg_pin;
10648 u8 port;
10650 /*
10651 * In case of no EPIO routed to reset the GPHY, put it
10652 * in low power mode.
10653 */
10655 /*
10656 * This works with E3 only, no need to check the chip
10657 * before determining the port.
10658 */
10663 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10664 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10666 /* Drive pin low to put GPHY in reset. */
10668 }
10673 {
10675 u16 val;
10679 /* Get speed operation status */
10685 /* Read status to clear the PHY interrupt. */
10687 MDIO_REG_INTR_STATUS,
10703 }
10704 /* Omitting 100Base-T4 for now */
10722 /* Check legacy speed AN resolution */
10728 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10734 LINK_STATUS_PARALLEL_DETECTION_USED;
10739 /* Report whether EEE is resolved. */
10743 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
10747 MDIO_REG_GPHY_CL45_ADDR_REG,
10748 MDIO_AN_DEVAD);
10750 MDIO_REG_GPHY_CL45_DATA_REG,
10751 MDIO_REG_GPHY_EEE_RESOLVED);
10753 MDIO_REG_GPHY_CL45_ADDR_REG,
10756 MDIO_REG_GPHY_CL45_DATA_REG,
10758 }
10760 }
10765 /* report LP advertised speeds */
10770 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10773 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10776 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10779 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10782 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10787 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
10790 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
10791 }
10792 }
10794 }
10798 {
10800 u16 val;
10805 /* Enable master/slave manual mmode and set to master */
10806 /* mii write 9 [bits set 11 12] */
10809 /* forced 1G and disable autoneg */
10810 /* set val [mii read 0] */
10811 /* set val [expr $val & [bits clear 6 12 13]] */
10812 /* set val [expr $val | [bits set 6 8]] */
10813 /* mii write 0 $val */
10819 /* Set external loopback and Tx using 6dB coding */
10820 /* mii write 0x18 7 */
10821 /* set val [mii read 0x18] */
10822 /* mii write 0x18 [expr $val | [bits set 10 15]] */
10827 /* This register opens the gate for the UMAC despite its name */
10830 /*
10831 * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
10832 * length used by the MAC receive logic to check frames.
10833 */
10835 }
10837 /******************************************************************/
10838 /* SFX7101 PHY SECTION */
10839 /******************************************************************/
10842 {
10844 /* SFX7101_XGXS_TEST1 */
10847 }
10852 {
10857 /* Restore normal power mode*/
10860 /* HW reset */
10871 /* Restart autoneg */
10878 /* Save spirom version */
10887 }
10892 {
10894 u8 link_up;
10909 /* if link is up print the AN outcome of the SFX7101 PHY */
10921 /* read LP advertised speeds */
10924 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
10925 }
10927 }
10930 {
10940 }
10943 {
10947 MDIO_PMA_DEVAD,
10952 /* Writes a self-clearing reset */
10954 MDIO_PMA_DEVAD,
10955 MDIO_PMA_REG_7101_RESET,
10957 /* Wait for clear */
10959 MDIO_PMA_DEVAD,
10964 }
10965 }
10969 /* Low power mode is controlled by GPIO 2 */
10972 /* The PHY reset is controlled by GPIO 1 */
10975 }
10979 {
10993 }
10995 MDIO_PMA_DEVAD,
10996 MDIO_PMA_REG_7107_LINK_LED_CNTL,
10997 val);
10998 }
11000 /******************************************************************/
11001 /* STATIC PHY DECLARATION */
11002 /******************************************************************/
11028 };
11039 SUPPORTED_10baseT_Full |
11040 SUPPORTED_100baseT_Half |
11041 SUPPORTED_100baseT_Full |
11042 SUPPORTED_1000baseT_Full |
11043 SUPPORTED_2500baseX_Full |
11044 SUPPORTED_TP |
11045 SUPPORTED_Autoneg |
11046 SUPPORTED_Pause |
11047 SUPPORTED_Asym_Pause),
11063 };
11074 SUPPORTED_10baseT_Full |
11075 SUPPORTED_100baseT_Half |
11076 SUPPORTED_100baseT_Full |
11077 SUPPORTED_1000baseT_Full |
11078 SUPPORTED_2500baseX_Full |
11079 SUPPORTED_10000baseT_Full |
11080 SUPPORTED_FIBRE |
11081 SUPPORTED_Autoneg |
11082 SUPPORTED_Pause |
11083 SUPPORTED_Asym_Pause),
11099 };
11109 SUPPORTED_10baseT_Full |
11110 SUPPORTED_100baseT_Half |
11111 SUPPORTED_100baseT_Full |
11112 SUPPORTED_1000baseT_Full |
11113 SUPPORTED_10000baseT_Full |
11114 SUPPORTED_20000baseKR2_Full |
11115 SUPPORTED_20000baseMLD2_Full |
11116 SUPPORTED_FIBRE |
11117 SUPPORTED_Autoneg |
11118 SUPPORTED_Pause |
11119 SUPPORTED_Asym_Pause),
11135 };
11147 SUPPORTED_TP |
11148 SUPPORTED_Autoneg |
11149 SUPPORTED_Pause |
11150 SUPPORTED_Asym_Pause),
11166 };
11176 SUPPORTED_2500baseX_Full |
11177 SUPPORTED_1000baseT_Full |
11178 SUPPORTED_FIBRE |
11179 SUPPORTED_Autoneg |
11180 SUPPORTED_Pause |
11181 SUPPORTED_Asym_Pause),
11197 };
11207 SUPPORTED_FIBRE |
11208 SUPPORTED_Pause |
11209 SUPPORTED_Asym_Pause),
11225 };
11235 SUPPORTED_1000baseT_Full |
11236 SUPPORTED_FIBRE |
11237 SUPPORTED_Pause |
11238 SUPPORTED_Asym_Pause),
11254 };
11261 FLAGS_INIT_XGXS_FIRST),
11266 SUPPORTED_1000baseT_Full |
11267 SUPPORTED_Autoneg |
11268 SUPPORTED_FIBRE |
11269 SUPPORTED_Pause |
11270 SUPPORTED_Asym_Pause),
11286 };
11297 SUPPORTED_1000baseT_Full |
11298 SUPPORTED_FIBRE |
11299 SUPPORTED_Pause |
11300 SUPPORTED_Asym_Pause),
11316 };
11322 FLAGS_REARM_LATCH_SIGNAL,
11327 SUPPORTED_10baseT_Full |
11328 SUPPORTED_100baseT_Half |
11329 SUPPORTED_100baseT_Full |
11330 SUPPORTED_1000baseT_Full |
11331 SUPPORTED_10000baseT_Full |
11332 SUPPORTED_TP |
11333 SUPPORTED_Autoneg |
11334 SUPPORTED_Pause |
11335 SUPPORTED_Asym_Pause),
11351 };
11358 FLAGS_REARM_LATCH_SIGNAL,
11363 SUPPORTED_10baseT_Full |
11364 SUPPORTED_100baseT_Half |
11365 SUPPORTED_100baseT_Full |
11366 SUPPORTED_1000baseT_Full |
11367 SUPPORTED_10000baseT_Full |
11368 SUPPORTED_TP |
11369 SUPPORTED_Autoneg |
11370 SUPPORTED_Pause |
11371 SUPPORTED_Asym_Pause),
11387 };
11394 FLAGS_REARM_LATCH_SIGNAL,
11399 SUPPORTED_100baseT_Full |
11400 SUPPORTED_1000baseT_Full |
11401 SUPPORTED_10000baseT_Full |
11402 SUPPORTED_TP |
11403 SUPPORTED_Autoneg |
11404 SUPPORTED_Pause |
11405 SUPPORTED_Asym_Pause),
11421 };
11432 SUPPORTED_10baseT_Full |
11433 SUPPORTED_100baseT_Half |
11434 SUPPORTED_100baseT_Full |
11435 SUPPORTED_1000baseT_Full |
11436 SUPPORTED_TP |
11437 SUPPORTED_Autoneg |
11438 SUPPORTED_Pause |
11439 SUPPORTED_Asym_Pause),
11455 };
11456 /*****************************************************************/
11457 /* */
11458 /* Populate the phy according. Main function: bnx2x_populate_phy */
11459 /* */
11460 /*****************************************************************/
11464 u8 phy_index)
11465 {
11466 /* Get the 4 lanes xgxs config rx and tx */
11469 /*
11470 * INT_PHY and EXT_PHY1 share the same value location in the
11471 * shmem. When num_phys is greater than 1, than this value
11472 * applies only to EXT_PHY1
11473 */
11490 }
11497 }
11498 }
11502 {
11518 }
11521 }
11524 {
11525 u32 phy_addr;
11526 u32 chip_id;
11530 PORT_FEATURE_CONNECTED_SWITCH_MASK);
11536 u32 serdes_net_if;
11538 MISC_REG_WC0_CTRL_PHY_ADDR);
11542 else
11544 /* Check Dual mode */
11548 PORT_HW_CFG_NET_SERDES_IF_MASK);
11549 /*
11550 * Set the appropriate supported and flags indications per
11551 * interface type of the chip
11552 */
11556 SUPPORTED_10baseT_Full |
11557 SUPPORTED_100baseT_Half |
11558 SUPPORTED_100baseT_Full |
11559 SUPPORTED_1000baseT_Full |
11560 SUPPORTED_FIBRE |
11561 SUPPORTED_Autoneg |
11562 SUPPORTED_Pause |
11563 SUPPORTED_Asym_Pause);
11571 SUPPORTED_10000baseT_Full |
11572 SUPPORTED_FIBRE |
11573 SUPPORTED_Pause |
11574 SUPPORTED_Asym_Pause);
11580 SUPPORTED_10000baseT_Full |
11581 SUPPORTED_FIBRE |
11582 SUPPORTED_Autoneg |
11583 SUPPORTED_Pause |
11584 SUPPORTED_Asym_Pause);
11590 SUPPORTED_FIBRE |
11591 SUPPORTED_Pause |
11592 SUPPORTED_Asym_Pause);
11598 SUPPORTED_FIBRE |
11599 SUPPORTED_Pause |
11600 SUPPORTED_Asym_Pause);
11604 serdes_net_if);
11606 }
11608 /*
11609 * Enable MDC/MDIO work-around for E3 A0 since free running MDC
11610 * was not set as expected. For B0, ECO will be enabled so there
11611 * won't be an issue there
11612 */
11615 else
11621 NIG_REG_SERDES0_CTRL_PHY_ADDR +
11627 NIG_REG_XGXS0_CTRL_PHY_ADDR +
11634 }
11635 }
11638 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
11639 port);
11642 else
11650 }
11653 u8 phy_index,
11654 u32 shmem_base,
11655 u32 shmem2_base,
11656 u8 port,
11658 {
11664 /* Select the phy type */
11681 /* BCM8727_NOC => BCM8727 no over current */
11712 /* In case external PHY wasn't found */
11717 }
11722 /*
11723 * The shmem address of the phy version is located on different
11724 * structures. In case this structure is too old, do not set
11725 * the address
11726 */
11733 /* Check specific mdc mdio settings */
11736 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
11745 }
11746 /* Check specific mdc mdio settings */
11749 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
11751 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
11752 }
11757 /*
11758 * Remove 100Mb link supported for BCM84833 when phy fw
11759 * version lower than or equal to 1.39
11760 */
11765 SUPPORTED_100baseT_Full);
11766 }
11768 /*
11769 * In case mdc/mdio_access of the external phy is different than the
11770 * mdc/mdio access of the XGXS, a HW lock must be taken in each access
11771 * to prevent one port interfere with another port's CL45 operations.
11772 */
11780 }
11784 {
11792 }
11796 u8 phy_index)
11797 {
11799 u32 link_config;
11800 /* Populate the default phy configuration for MF mode */
11807 dev_info.
11815 dev_info.
11817 }
11846 }
11864 }
11865 }
11868 {
11873 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11876 PORT_HW_CFG_PHY_SELECTION_MASK;
11892 }
11897 }
11901 {
11909 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11912 phy_index++) {
11919 }
11929 phy_index);
11932 phy_index++)
11935 }
11944 /*
11945 * Update media type for non-PMF sync only for the first time
11946 * In case the media type changes afterwards, it will be updated
11947 * using the update_status function
11948 */
11953 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
11955 actual_phy_idx));
11956 }
11961 }
11965 }
11969 {
11981 /* set bmac loopback */
11985 }
11989 {
12000 /* set bmac loopback */
12004 }
12008 {
12013 else
12019 /*
12020 * Set WC to loopback mode since link is required to provide clock
12021 * to the XMAC in 20G mode
12022 */
12027 params);
12031 }
12035 {
12046 }
12050 {
12057 else
12070 }
12074 else
12076 }
12079 /* set 10G XGXS loopback */
12082 params);
12085 /* set external phy loopback */
12086 u8 phy_index;
12092 params);
12093 }
12094 }
12098 }
12101 {
12117 /* disable attentions */
12120 NIG_MASK_XGXS0_LINK10G |
12121 NIG_MASK_SERDES0_LINK_STATUS |
12122 NIG_MASK_MI_INT));
12132 }
12157 else
12159 }
12164 }
12166 }
12169 u8 reset_ext_phy)
12170 {
12174 /* disable attentions */
12179 NIG_MASK_XGXS0_LINK10G |
12180 NIG_MASK_SERDES0_LINK_STATUS |
12181 NIG_MASK_MI_INT));
12183 /* activate nig drain */
12186 /* disable nig egress interface */
12190 }
12192 /* Stop BigMac rx */
12198 }
12199 /* disable emac */
12204 /* The PHY reset is controlled by GPIO 1
12205 * Hold it as vars low
12206 */
12207 /* clear link led */
12213 phy_index++) {
12219 params);
12220 }
12222 FLAGS_REARM_LATCH_SIGNAL)
12224 }
12225 }
12228 /* Clear latching indication */
12232 }
12237 /* disable nig ingress interface */
12239 /* reset BigMac */
12248 MISC_REGISTERS_RESET_REG_2_XMAC)
12250 XMAC_CTRL_REG_SOFT_RESET);
12251 }
12255 }
12257 /****************************************************************************/
12258 /* Common function */
12259 /****************************************************************************/
12261 u32 shmem_base_path[],
12263 u32 chip_id)
12264 {
12267 u16 val;
12275 /* PART1 - Reset both phys */
12278 /* In E2, same phy is using for port0 of the two paths */
12287 }
12289 /* Extract the ext phy address for the port */
12295 }
12296 /* disable attentions */
12300 NIG_MASK_XGXS0_LINK10G |
12301 NIG_MASK_SERDES0_LINK_STATUS |
12302 NIG_MASK_MI_INT));
12304 /* Need to take the phy out of low power mode in order
12305 to write to access its registers */
12307 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12308 port);
12310 /* Reset the phy */
12312 MDIO_PMA_DEVAD,
12313 MDIO_PMA_REG_CTRL,
12315 }
12317 /* Add delay of 150ms after reset */
12326 }
12328 /* PART2 - Download firmware to both phys */
12332 else
12338 port_of_path))
12341 /* Only set bit 10 = 1 (Tx power down) */
12343 MDIO_PMA_DEVAD,
12346 /* Phase1 of TX_POWER_DOWN reset */
12348 MDIO_PMA_DEVAD,
12349 MDIO_PMA_REG_TX_POWER_DOWN,
12351 }
12353 /*
12354 * Toggle Transmitter: Power down and then up with 600ms delay
12355 * between
12356 */
12359 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
12361 /* Phase2 of POWER_DOWN_RESET */
12362 /* Release bit 10 (Release Tx power down) */
12364 MDIO_PMA_DEVAD,
12368 MDIO_PMA_DEVAD,
12372 /* Read modify write the SPI-ROM version select register */
12374 MDIO_PMA_DEVAD,
12377 MDIO_PMA_DEVAD,
12380 /* set GPIO2 back to LOW */
12383 }
12385 }
12387 u32 shmem_base_path[],
12389 u32 chip_id)
12390 {
12391 u32 val;
12392 s8 port;
12394 /* Use port1 because of the static port-swap */
12395 /* Enable the module detection interrupt */
12406 /* In E2, same phy is using for port0 of the two paths */
12413 }
12414 /* Extract the ext phy address for the port */
12420 }
12422 /* Reset phy*/
12427 /* Set fault module detected LED on */
12429 MISC_REGISTERS_GPIO_HIGH,
12430 port);
12431 }
12434 }
12437 {
12476 /* Don't override the io_gpio and io_port */
12478 }
12479 }
12482 u32 shmem_base_path[],
12484 u32 chip_id)
12485 {
12490 s8 port_of_path;
12497 /*
12498 * Retrieve the reset gpio/port which control the reset.
12499 * Default is GPIO1, PORT1
12500 */
12504 /* Calculate the port based on port swap */
12507 /* Initiate PHY reset*/
12509 port);
12512 port);
12516 /* PART1 - Reset both phys */
12520 /* In E2, same phy is using for port0 of the two paths */
12529 }
12531 /* Extract the ext phy address for the port */
12537 }
12538 /* disable attentions */
12542 NIG_MASK_XGXS0_LINK10G |
12543 NIG_MASK_SERDES0_LINK_STATUS |
12544 NIG_MASK_MI_INT));
12547 /* Reset the phy */
12550 }
12552 /* Add delay of 150ms after reset */
12560 }
12561 /* PART2 - Download firmware to both phys */
12565 else
12570 port_of_path))
12572 /* Disable PHY transmitter output */
12574 MDIO_PMA_DEVAD,
12577 }
12579 }
12582 u32 shmem_base_path[],
12583 u32 shmem2_base_path[],
12584 u8 phy_index,
12585 u32 chip_id)
12586 {
12587 u8 reset_gpios;
12593 reset_gpios);
12595 }
12599 {
12601 /* Wait for FW completing its initialization. */
12604 MDIO_PMA_DEVAD,
12609 }
12613 }
12615 /* Put the port in super isolate mode. */
12617 MDIO_CTL_DEVAD,
12621 MDIO_CTL_DEVAD,
12624 /* Save spirom version */
12627 }
12630 u32 shmem_base,
12631 u32 shmem2_base,
12632 u32 chip_id)
12633 {
12641 }
12648 }
12650 }
12655 {
12661 shmem2_base_path,
12668 shmem2_base_path,
12673 /*
12674 * GPIO1 affects both ports, so there's need to pull
12675 * it for single port alone
12676 */
12678 shmem2_base_path,
12682 /*
12683 * GPIO3's are linked, and so both need to be toggled
12684 * to obtain required 2us pulse.
12685 */
12687 shmem2_base_path,
12696 ext_phy_type);
12698 }
12705 }
12709 {
12718 /* Enable EPIO */
12721 }
12722 /* Check if common init was already done */
12728 phy_ver);
12730 }
12732 /* Read the ext_phy_type for arbitrary port(0) */
12734 phy_index++) {
12740 shmem2_base_path,
12742 chip_id);
12743 }
12745 }
12749 {
12751 u32 cfg_pin;
12753 u32 pin_val;
12758 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
12759 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
12761 /* Ignore check if no external input PIN available */
12768 " been detected and the power to "
12769 "that SFP+ module has been removed"
12770 " to prevent failure of the card."
12771 " Please remove the SFP+ module and"
12772 " restart the system to clear this"
12776 }
12779 }
12783 {
12785 /* Compare new value with previous value */
12786 u8 led_mode;
12792 /* If values differ */
12796 /*
12797 * a. Update shmem->link_status accordingly
12798 * b. Update link_vars->link_up
12799 */
12805 /*
12806 * Set LED mode to off since the PHY doesn't know about these
12807 * errors
12808 */
12816 }
12817 /* Update the LED according to the link state */
12820 /* Update link status in the shared memory */
12823 /* C. Trigger General Attention */
12826 }
12828 /******************************************************************************
12829 * Description:
12830 * This function checks for half opened connection change indication.
12831 * When such change occurs, it calls the bnx2x_analyze_link_error
12832 * to check if Remote Fault is set or cleared. Reception of remote fault
12833 * status message in the MAC indicates that the peer's MAC has detected
12834 * a fault, for example, due to break in the TX side of fiber.
12835 *
12836 ******************************************************************************/
12839 {
12842 u32 mac_base;
12843 /* In case link status is physically up @ 10G do */
12850 /* Check E3 XMAC */
12851 /*
12852 * Note that link speed cannot be queried here, since it may be
12853 * zero while link is down. In case UMAC is active, LSS will
12854 * simply not be set
12855 */
12858 /* Clear stick bits (Requires rising edge) */
12861 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
12862 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
12869 /* Check E1X / E2 BMAC */
12870 u32 lss_status_reg;
12873 NIG_REG_INGRESS_BMAC0_MEM;
12874 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */
12877 else
12884 }
12885 }
12888 {
12890 u16 phy_idx;
12896 }
12897 }
12904 }
12906 }
12909 {
12910 u8 phy_index;
12913 phy_index++) {
12918 }
12922 }
12924 }
12927 u32 shmem_base,
12928 u32 shmem2_base,
12929 u8 port)
12930 {
12934 phy_index++) {
12940 }
12942 FLAGS_FAN_FAILURE_DET_REQ);
12943 }
12945 }
12948 {
12949 u8 phy_index;
12954 NIG_MASK_XGXS0_LINK10G |
12955 NIG_MASK_SERDES0_LINK_STATUS |
12956 NIG_MASK_MI_INT));
12959 phy_index++) {
12963 params);
12965 }
12966 }
12967 }
12971 u8 port)
12972 {
12974 u32 val;
12978 shmem_base,
12979 port,
12986 phy_index++) {
12992 }
12997 }
12998 }
12999 }
13004 /* Set GPIO3 to trigger SFP+ module insertion/removal */
13024 else
13027 /* Open appropriate AEU for interrupts */
13032 /* Enable the GPIO to trigger interrupt */
13036 }