drivers/net/ethernet/cadence/at91_ether.h

   1 /*
   2  * Ethernet driver for the Atmel AT91RM9200 (Thunder)
   3  *
   4  *  Copyright (C) SAN People (Pty) Ltd
   5  *
   6  * Based on an earlier Atmel EMAC macrocell driver by Atmel and Lineo Inc.
   7  * Initial version by Rick Bronson.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14
  15 #ifndef AT91_ETHERNET
  16 #define AT91_ETHERNET
  17
  18
  19 /* Davicom 9161 PHY */
  20 #define MII_DM9161_ID           0x0181b880
  21 #define MII_DM9161A_ID          0x0181b8a0
  22 #define MII_DSCR_REG            16
  23 #define MII_DSCSR_REG           17
  24 #define MII_DSINTR_REG          21
  25
  26 /* Intel LXT971A PHY */
  27 #define MII_LXT971A_ID          0x001378E0
  28 #define MII_ISINTE_REG          18
  29 #define MII_ISINTS_REG          19
  30 #define MII_LEDCTRL_REG         20
  31
  32 /* Realtek RTL8201 PHY */
  33 #define MII_RTL8201_ID          0x00008200
  34
  35 /* Broadcom BCM5221 PHY */
  36 #define MII_BCM5221_ID          0x004061e0
  37 #define MII_BCMINTR_REG         26
  38
  39 /* National Semiconductor DP83847 */
  40 #define MII_DP83847_ID          0x20005c30
  41
  42 /* National Semiconductor DP83848 */
  43 #define MII_DP83848_ID          0x20005c90
  44 #define MII_DPPHYSTS_REG        16
  45 #define MII_DPMICR_REG          17
  46 #define MII_DPMISR_REG          18
  47
  48 /* Altima AC101L PHY */
  49 #define MII_AC101L_ID           0x00225520
  50
  51 /* Micrel KS8721 PHY */
  52 #define MII_KS8721_ID           0x00221610
  53
  54 /* Teridian 78Q2123/78Q2133 */
  55 #define MII_T78Q21x3_ID         0x000e7230
  56 #define MII_T78Q21INT_REG       17
  57
  58 /* SMSC LAN83C185 */
  59 #define MII_LAN83C185_ID        0x0007C0A0
  60
  61 /* ........................................................................ */
  62
  63 #define MAX_RBUFF_SZ    0x600           /* 1518 rounded up */
  64 #define MAX_RX_DESCR    9               /* max number of receive buffers */
  65
  66 #define EMAC_DESC_DONE  0x00000001      /* bit for if DMA is done */
  67 #define EMAC_DESC_WRAP  0x00000002      /* bit for wrap */
  68
  69 #define EMAC_BROADCAST  0x80000000      /* broadcast address */
  70 #define EMAC_MULTICAST  0x40000000      /* multicast address */
  71 #define EMAC_UNICAST    0x20000000      /* unicast address */
  72
  73 struct rbf_t
  74 {
  75         unsigned int addr;
  76         unsigned long size;
  77 };
  78
  79 struct recv_desc_bufs
  80 {
  81         struct rbf_t descriptors[MAX_RX_DESCR];         /* must be on sizeof (rbf_t) boundary */
  82         char recv_buf[MAX_RX_DESCR][MAX_RBUFF_SZ];      /* must be on long boundary */
  83 };
  84
  85 struct at91_private
  86 {
  87         struct mii_if_info mii;                 /* ethtool support */
  88         struct macb_platform_data board_data;   /* board-specific
  89                                                  * configuration (shared with
  90                                                  * macb for common data */
  91         struct clk *ether_clk;                  /* clock */
  92
  93         /* PHY */
  94         unsigned long phy_type;                 /* type of PHY (PHY_ID) */
  95         spinlock_t lock;                        /* lock for MDI interface */
  96         short phy_media;                        /* media interface type */
  97         unsigned short phy_address;             /* 5-bit MDI address of PHY (0..31) */
  98         struct timer_list check_timer;          /* Poll link status */
  99
 100         /* Transmit */
 101         struct sk_buff *skb;                    /* holds skb until xmit interrupt completes */
 102         dma_addr_t skb_physaddr;                /* phys addr from pci_map_single */
 103         int skb_length;                         /* saved skb length for pci_unmap_single */
 104
 105         /* Receive */
 106         int rxBuffIndex;                        /* index into receive descriptor list */
 107         struct recv_desc_bufs *dlist;           /* descriptor list address */
 108         struct recv_desc_bufs *dlist_phys;      /* descriptor list physical address */
 109 };
 110
 111 #endif