drivers/net/ethernet/dec/ewrk3.h

   1 /*
   2     Written 1994 by David C. Davies.
   3
   4     Copyright 1994 Digital Equipment Corporation.
   5
   6     This software may be used and distributed according to  the terms of the
   7     GNU General Public License, incorporated herein by reference.
   8
   9     The author may    be  reached as davies@wanton.lkg.dec.com  or   Digital
  10     Equipment Corporation, 550 King Street, Littleton MA 01460.
  11
  12     =========================================================================
  13 */
  14
  15 /*
  16 ** I/O Address Register Map
  17 */
  18 #define EWRK3_CSR    iobase+0x00   /* Control and Status Register */
  19 #define EWRK3_CR     iobase+0x01   /* Control Register */
  20 #define EWRK3_ICR    iobase+0x02   /* Interrupt Control Register */
  21 #define EWRK3_TSR    iobase+0x03   /* Transmit Status Register */
  22 #define EWRK3_RSVD1  iobase+0x04   /* RESERVED */
  23 #define EWRK3_RSVD2  iobase+0x05   /* RESERVED */
  24 #define EWRK3_FMQ    iobase+0x06   /* Free Memory Queue */
  25 #define EWRK3_FMQC   iobase+0x07   /* Free Memory Queue Counter */
  26 #define EWRK3_RQ     iobase+0x08   /* Receive Queue */
  27 #define EWRK3_RQC    iobase+0x09   /* Receive Queue Counter */
  28 #define EWRK3_TQ     iobase+0x0a   /* Transmit Queue */
  29 #define EWRK3_TQC    iobase+0x0b   /* Transmit Queue Counter */
  30 #define EWRK3_TDQ    iobase+0x0c   /* Transmit Done Queue */
  31 #define EWRK3_TDQC   iobase+0x0d   /* Transmit Done Queue Counter */
  32 #define EWRK3_PIR1   iobase+0x0e   /* Page Index Register 1 */
  33 #define EWRK3_PIR2   iobase+0x0f   /* Page Index Register 2 */
  34 #define EWRK3_DATA   iobase+0x10   /* Data Register */
  35 #define EWRK3_IOPR   iobase+0x11   /* I/O Page Register */
  36 #define EWRK3_IOBR   iobase+0x12   /* I/O Base Register */
  37 #define EWRK3_MPR    iobase+0x13   /* Memory Page Register */
  38 #define EWRK3_MBR    iobase+0x14   /* Memory Base Register */
  39 #define EWRK3_APROM  iobase+0x15   /* Address PROM */
  40 #define EWRK3_EPROM1 iobase+0x16   /* EEPROM Data Register 1 */
  41 #define EWRK3_EPROM2 iobase+0x17   /* EEPROM Data Register 2 */
  42 #define EWRK3_PAR0   iobase+0x18   /* Physical Address Register 0 */
  43 #define EWRK3_PAR1   iobase+0x19   /* Physical Address Register 1 */
  44 #define EWRK3_PAR2   iobase+0x1a   /* Physical Address Register 2 */
  45 #define EWRK3_PAR3   iobase+0x1b   /* Physical Address Register 3 */
  46 #define EWRK3_PAR4   iobase+0x1c   /* Physical Address Register 4 */
  47 #define EWRK3_PAR5   iobase+0x1d   /* Physical Address Register 5 */
  48 #define EWRK3_CMR    iobase+0x1e   /* Configuration/Management Register */
  49
  50 /*
  51 ** Control Page Map
  52 */
  53 #define PAGE0_FMQ     0x000         /* Free Memory Queue */
  54 #define PAGE0_RQ      0x080         /* Receive Queue */
  55 #define PAGE0_TQ      0x100         /* Transmit Queue */
  56 #define PAGE0_TDQ     0x180         /* Transmit Done Queue */
  57 #define PAGE0_HTE     0x200         /* Hash Table Entries */
  58 #define PAGE0_RSVD    0x240         /* RESERVED */
  59 #define PAGE0_USRD    0x600         /* User Data */
  60
  61 /*
  62 ** Control and Status Register bit definitions (EWRK3_CSR)
  63 */
  64 #define CSR_RA          0x80        /* Runt Accept */
  65 #define CSR_PME         0x40        /* Promiscuous Mode Enable */
  66 #define CSR_MCE         0x20        /* Multicast Enable */
  67 #define CSR_TNE         0x08        /* TX Done Queue Not Empty */
  68 #define CSR_RNE         0x04        /* RX Queue Not Empty */
  69 #define CSR_TXD         0x02        /* TX Disable */
  70 #define CSR_RXD         0x01        /* RX Disable */
  71
  72 /*
  73 ** Control Register bit definitions (EWRK3_CR)
  74 */
  75 #define CR_APD          0x80    /* Auto Port Disable */
  76 #define CR_PSEL         0x40    /* Port Select (0->TP port) */
  77 #define CR_LBCK         0x20    /* LoopBaCK enable */
  78 #define CR_FDUP         0x10    /* Full DUPlex enable */
  79 #define CR_FBUS         0x08    /* Fast BUS enable (ISA clk > 8.33MHz) */
  80 #define CR_EN_16        0x04    /* ENable 16 bit memory accesses */
  81 #define CR_LED          0x02    /* LED (1-> turn on) */
  82
  83 /*
  84 ** Interrupt Control Register bit definitions (EWRK3_ICR)
  85 */
  86 #define ICR_IE          0x80    /* Interrupt Enable */
  87 #define ICR_IS          0x60    /* Interrupt Selected */
  88 #define ICR_TNEM        0x08    /* TNE Mask (0->mask) */
  89 #define ICR_RNEM        0x04    /* RNE Mask (0->mask) */
  90 #define ICR_TXDM        0x02    /* TXD Mask (0->mask) */
  91 #define ICR_RXDM        0x01    /* RXD Mask (0->mask) */
  92
  93 /*
  94 ** Transmit Status Register bit definitions (EWRK3_TSR)
  95 */
  96 #define TSR_NCL         0x80    /* No Carrier Loopback */
  97 #define TSR_ID          0x40    /* Initially Deferred */
  98 #define TSR_LCL         0x20    /* Late CoLlision */
  99 #define TSR_ECL         0x10    /* Excessive CoLlisions */
 100 #define TSR_RCNTR       0x0f    /* Retries CouNTeR */
 101
 102 /*
 103 ** I/O Page Register bit definitions (EWRK3_IOPR)
 104 */
 105 #define EEPROM_INIT     0xc0    /* EEPROM INIT command */
 106 #define EEPROM_WR_EN    0xc8    /* EEPROM WRITE ENABLE command */
 107 #define EEPROM_WR       0xd0    /* EEPROM WRITE command */
 108 #define EEPROM_WR_DIS   0xd8    /* EEPROM WRITE DISABLE command */
 109 #define EEPROM_RD       0xe0    /* EEPROM READ command */
 110
 111 /*
 112 ** I/O Base Register bit definitions (EWRK3_IOBR)
 113 */
 114 #define EISA_REGS_EN    0x20    /* Enable EISA ID and Control Registers */
 115 #define EISA_IOB        0x1f    /* Compare bits for I/O Base Address */
 116
 117 /*
 118 ** I/O Configuration/Management Register bit definitions (EWRK3_CMR)
 119 */
 120 #define CMR_RA          0x80    /* Read Ahead */
 121 #define CMR_WB          0x40    /* Write Behind */
 122 #define CMR_LINK        0x20    /* 0->TP */
 123 #define CMR_POLARITY    0x10    /* Informational */
 124 #define CMR_NO_EEPROM   0x0c    /* NO_EEPROM<1:0> pin status */
 125 #define CMR_HS          0x08    /* Hard Strapped pin status (LeMAC2) */
 126 #define CMR_PNP         0x04    /* Plug 'n Play */
 127 #define CMR_DRAM        0x02    /* 0-> 1DRAM, 1-> 2 DRAM on board */
 128 #define CMR_0WS         0x01    /* Zero Wait State */
 129
 130 /*
 131 ** MAC Receive Status Register bit definitions
 132 */
 133
 134 #define R_ROK           0x80    /* Receive OK summary */
 135 #define R_IAM           0x10    /* Individual Address Match */
 136 #define R_MCM           0x08    /* MultiCast Match */
 137 #define R_DBE           0x04    /* Dribble Bit Error */
 138 #define R_CRC           0x02    /* CRC error */
 139 #define R_PLL           0x01    /* Phase Lock Lost */
 140
 141 /*
 142 ** MAC Transmit Control Register bit definitions
 143 */
 144
 145 #define TCR_SQEE        0x40    /* SQE Enable - look for heartbeat  */
 146 #define TCR_SED         0x20    /* Stop when Error Detected */
 147 #define TCR_QMODE       0x10    /* Q_MODE */
 148 #define TCR_LAB         0x08    /* Less Aggressive Backoff */
 149 #define TCR_PAD         0x04    /* PAD Runt Packets */
 150 #define TCR_IFC         0x02    /* Insert Frame Check */
 151 #define TCR_ISA         0x01    /* Insert Source Address */
 152
 153 /*
 154 ** MAC Transmit Status Register bit definitions
 155 */
 156
 157 #define T_VSTS          0x80    /* Valid STatuS */
 158 #define T_CTU           0x40    /* Cut Through Used */
 159 #define T_SQE           0x20    /* Signal Quality Error */
 160 #define T_NCL           0x10    /* No Carrier Loopback */
 161 #define T_LCL           0x08    /* Late Collision */
 162 #define T_ID            0x04    /* Initially Deferred */
 163 #define T_COLL          0x03    /* COLLision status */
 164 #define T_XCOLL         0x03    /* Excessive Collisions */
 165 #define T_MCOLL         0x02    /* Multiple Collisions */
 166 #define T_OCOLL         0x01    /* One Collision */
 167 #define T_NOCOLL        0x00    /* No Collisions */
 168 #define T_XUR           0x03    /* Excessive Underruns */
 169 #define T_TXE           0x7f    /* TX Errors */
 170
 171 /*
 172 ** EISA Configuration Register bit definitions
 173 */
 174
 175 #define EISA_ID       iobase + 0x0c80  /* EISA ID Registers */
 176 #define EISA_ID0      iobase + 0x0c80  /* EISA ID Register 0 */
 177 #define EISA_ID1      iobase + 0x0c81  /* EISA ID Register 1 */
 178 #define EISA_ID2      iobase + 0x0c82  /* EISA ID Register 2 */
 179 #define EISA_ID3      iobase + 0x0c83  /* EISA ID Register 3 */
 180 #define EISA_CR       iobase + 0x0c84  /* EISA Control Register */
 181
 182 /*
 183 ** EEPROM BYTES
 184 */
 185 #define EEPROM_MEMB     0x00
 186 #define EEPROM_IOB      0x01
 187 #define EEPROM_EISA_ID0 0x02
 188 #define EEPROM_EISA_ID1 0x03
 189 #define EEPROM_EISA_ID2 0x04
 190 #define EEPROM_EISA_ID3 0x05
 191 #define EEPROM_MISC0    0x06
 192 #define EEPROM_MISC1    0x07
 193 #define EEPROM_PNAME7   0x08
 194 #define EEPROM_PNAME6   0x09
 195 #define EEPROM_PNAME5   0x0a
 196 #define EEPROM_PNAME4   0x0b
 197 #define EEPROM_PNAME3   0x0c
 198 #define EEPROM_PNAME2   0x0d
 199 #define EEPROM_PNAME1   0x0e
 200 #define EEPROM_PNAME0   0x0f
 201 #define EEPROM_SWFLAGS  0x10
 202 #define EEPROM_HWCAT    0x11
 203 #define EEPROM_NETMAN2  0x12
 204 #define EEPROM_REVLVL   0x13
 205 #define EEPROM_NETMAN0  0x14
 206 #define EEPROM_NETMAN1  0x15
 207 #define EEPROM_CHIPVER  0x16
 208 #define EEPROM_SETUP    0x17
 209 #define EEPROM_PADDR0   0x18
 210 #define EEPROM_PADDR1   0x19
 211 #define EEPROM_PADDR2   0x1a
 212 #define EEPROM_PADDR3   0x1b
 213 #define EEPROM_PADDR4   0x1c
 214 #define EEPROM_PADDR5   0x1d
 215 #define EEPROM_PA_CRC   0x1e
 216 #define EEPROM_CHKSUM   0x1f
 217
 218 /*
 219 ** EEPROM bytes for checksumming
 220 */
 221 #define EEPROM_MAX      32             /* bytes */
 222
 223 /*
 224 ** EEPROM MISCELLANEOUS FLAGS
 225 */
 226 #define RBE_SHADOW      0x0100  /* Remote Boot Enable Shadow */
 227 #define READ_AHEAD      0x0080  /* Read Ahead feature */
 228 #define IRQ_SEL2        0x0070  /* IRQ line selection (LeMAC2) */
 229 #define IRQ_SEL         0x0060  /* IRQ line selection */
 230 #define FAST_BUS        0x0008  /* ISA Bus speeds > 8.33MHz */
 231 #define ENA_16          0x0004  /* Enables 16 bit memory transfers */
 232 #define WRITE_BEHIND    0x0002  /* Write Behind feature */
 233 #define _0WS_ENA        0x0001  /* Zero Wait State Enable */
 234
 235 /*
 236 ** EEPROM NETWORK MANAGEMENT FLAGS
 237 */
 238 #define NETMAN_POL      0x04    /* Polarity defeat */
 239 #define NETMAN_LINK     0x02    /* Link defeat */
 240 #define NETMAN_CCE      0x01    /* Custom Counters Enable */
 241
 242 /*
 243 ** EEPROM SW FLAGS
 244 */
 245 #define SW_SQE          0x10    /* Signal Quality Error */
 246 #define SW_LAB          0x08    /* Less Aggressive Backoff */
 247 #define SW_INIT         0x04    /* Initialized */
 248 #define SW_TIMEOUT      0x02    /* 0:2.5 mins, 1: 30 secs */
 249 #define SW_REMOTE       0x01    /* Remote Boot Enable -> 1 */
 250
 251 /*
 252 ** EEPROM SETUP FLAGS
 253 */
 254 #define SETUP_APD       0x80    /* AutoPort Disable */
 255 #define SETUP_PS        0x40    /* Port Select */
 256 #define SETUP_MP        0x20    /* MultiPort */
 257 #define SETUP_1TP       0x10    /* 1 port, TP */
 258 #define SETUP_1COAX     0x00    /* 1 port, Coax */
 259 #define SETUP_DRAM      0x02    /* Number of DRAMS on board */
 260
 261 /*
 262 ** EEPROM MANAGEMENT FLAGS
 263 */
 264 #define MGMT_CCE        0x01    /* Custom Counters Enable */
 265
 266 /*
 267 ** EEPROM VERSIONS
 268 */
 269 #define LeMAC           0x11
 270 #define LeMAC2          0x12
 271
 272 /*
 273 ** Miscellaneous
 274 */
 275
 276 #define EEPROM_WAIT_TIME 1000    /* Number of microseconds */
 277 #define EISA_EN         0x0001   /* Enable EISA bus buffers */
 278
 279 #define HASH_TABLE_LEN   512     /* Bits */
 280
 281 #define XCT 0x80                 /* Transmit Cut Through */
 282 #define PRELOAD 16               /* 4 long words */
 283
 284 #define MASK_INTERRUPTS   1
 285 #define UNMASK_INTERRUPTS 0
 286
 287 #define EEPROM_OFFSET(a) ((u_short)((u_long)(a)))
 288
 289 /*
 290 ** Include the IOCTL stuff
 291 */
 292 #include <linux/sockios.h>
 293
 294 #define EWRK3IOCTL      SIOCDEVPRIVATE
 295
 296 struct ewrk3_ioctl {
 297         unsigned short cmd;                /* Command to run */
 298         unsigned short len;                /* Length of the data buffer */
 299         unsigned char  __user *data;       /* Pointer to the data buffer */
 300 };
 301
 302 /*
 303 ** Recognised commands for the driver
 304 */
 305 #define EWRK3_GET_HWADDR        0x01 /* Get the hardware address */
 306 #define EWRK3_SET_HWADDR        0x02 /* Get the hardware address */
 307 #define EWRK3_SET_PROM          0x03 /* Set Promiscuous Mode */
 308 #define EWRK3_CLR_PROM          0x04 /* Clear Promiscuous Mode */
 309 #define EWRK3_SAY_BOO           0x05 /* Say "Boo!" to the kernel log file */
 310 #define EWRK3_GET_MCA           0x06 /* Get a multicast address */
 311 #define EWRK3_SET_MCA           0x07 /* Set a multicast address */
 312 #define EWRK3_CLR_MCA           0x08 /* Clear a multicast address */
 313 #define EWRK3_MCA_EN            0x09 /* Enable a multicast address group */
 314 #define EWRK3_GET_STATS         0x0a /* Get the driver statistics */
 315 #define EWRK3_CLR_STATS         0x0b /* Zero out the driver statistics */
 316 #define EWRK3_GET_CSR           0x0c /* Get the CSR Register contents */
 317 #define EWRK3_SET_CSR           0x0d /* Set the CSR Register contents */
 318 #define EWRK3_GET_EEPROM        0x0e /* Get the EEPROM contents */
 319 #define EWRK3_SET_EEPROM        0x0f /* Set the EEPROM contents */
 320 #define EWRK3_GET_CMR           0x10 /* Get the CMR Register contents */
 321 #define EWRK3_CLR_TX_CUT_THRU   0x11 /* Clear the TX cut through mode */
 322 #define EWRK3_SET_TX_CUT_THRU   0x12 /* Set the TX cut through mode */