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Linux 3.4.102
[linux/fpc-iii.git] / drivers / net / ethernet / fealnx.c
blob1637b986229269b4c3f7b7dcc8f1eeac62b4a915
1 /*
2 Written 1998-2000 by Donald Becker.
3
4 This software may be used and distributed according to the terms of
5 the GNU General Public License (GPL), incorporated herein by reference.
6 Drivers based on or derived from this code fall under the GPL and must
7 retain the authorship, copyright and license notice. This file is not
8 a complete program and may only be used when the entire operating
9 system is licensed under the GPL.
10
11 The author may be reached as becker@scyld.com, or C/O
12 Scyld Computing Corporation
13 410 Severn Ave., Suite 210
14 Annapolis MD 21403
15
16 Support information and updates available at
17 http://www.scyld.com/network/pci-skeleton.html
18
19 Linux kernel updates:
20
21 Version 2.51, Nov 17, 2001 (jgarzik):
22 - Add ethtool support
23 - Replace some MII-related magic numbers with constants
24
25 */
26
27 #define DRV_NAME "fealnx"
28 #define DRV_VERSION "2.52"
29 #define DRV_RELDATE "Sep-11-2006"
30
31 static int debug; /* 1-> print debug message */
32 static int max_interrupt_work = 20;
33
34 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). */
35 static int multicast_filter_limit = 32;
36
37 /* Set the copy breakpoint for the copy-only-tiny-frames scheme. */
38 /* Setting to > 1518 effectively disables this feature. */
39 static int rx_copybreak;
40
41 /* Used to pass the media type, etc. */
42 /* Both 'options[]' and 'full_duplex[]' should exist for driver */
43 /* interoperability. */
44 /* The media type is usually passed in 'options[]'. */
45 #define MAX_UNITS 8 /* More are supported, limit only on options */
46 static int options[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
47 static int full_duplex[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
48
49 /* Operational parameters that are set at compile time. */
50 /* Keep the ring sizes a power of two for compile efficiency. */
51 /* The compiler will convert <unsigned>'%'<2^N> into a bit mask. */
52 /* Making the Tx ring too large decreases the effectiveness of channel */
53 /* bonding and packet priority. */
54 /* There are no ill effects from too-large receive rings. */
55 // 88-12-9 modify,
56 // #define TX_RING_SIZE 16
57 // #define RX_RING_SIZE 32
58 #define TX_RING_SIZE 6
59 #define RX_RING_SIZE 12
60 #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct fealnx_desc)
61 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct fealnx_desc)
62
63 /* Operational parameters that usually are not changed. */
64 /* Time in jiffies before concluding the transmitter is hung. */
65 #define TX_TIMEOUT (2*HZ)
66
67 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */
68
69
70 /* Include files, designed to support most kernel versions 2.0.0 and later. */
71 #include <linux/module.h>
72 #include <linux/kernel.h>
73 #include <linux/string.h>
74 #include <linux/timer.h>
75 #include <linux/errno.h>
76 #include <linux/ioport.h>
77 #include <linux/interrupt.h>
78 #include <linux/pci.h>
79 #include <linux/netdevice.h>
80 #include <linux/etherdevice.h>
81 #include <linux/skbuff.h>
82 #include <linux/init.h>
83 #include <linux/mii.h>
84 #include <linux/ethtool.h>
85 #include <linux/crc32.h>
86 #include <linux/delay.h>
87 #include <linux/bitops.h>
88
89 #include <asm/processor.h> /* Processor type for cache alignment. */
90 #include <asm/io.h>
91 #include <asm/uaccess.h>
92 #include <asm/byteorder.h>
93
94 /* These identify the driver base version and may not be removed. */
95 static const char version[] __devinitconst =
96 KERN_INFO DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE "\n";
97
98
99 /* This driver was written to use PCI memory space, however some x86 systems
100 work only with I/O space accesses. */
101 #ifndef __alpha__
102 #define USE_IO_OPS
103 #endif
104
105 /* Kernel compatibility defines, some common to David Hinds' PCMCIA package. */
106 /* This is only in the support-all-kernels source code. */
107
108 #define RUN_AT(x) (jiffies + (x))
109
110 MODULE_AUTHOR("Myson or whoever");
111 MODULE_DESCRIPTION("Myson MTD-8xx 100/10M Ethernet PCI Adapter Driver");
112 MODULE_LICENSE("GPL");
113 module_param(max_interrupt_work, int, 0);
114 module_param(debug, int, 0);
115 module_param(rx_copybreak, int, 0);
116 module_param(multicast_filter_limit, int, 0);
117 module_param_array(options, int, NULL, 0);
118 module_param_array(full_duplex, int, NULL, 0);
119 MODULE_PARM_DESC(max_interrupt_work, "fealnx maximum events handled per interrupt");
120 MODULE_PARM_DESC(debug, "fealnx enable debugging (0-1)");
121 MODULE_PARM_DESC(rx_copybreak, "fealnx copy breakpoint for copy-only-tiny-frames");
122 MODULE_PARM_DESC(multicast_filter_limit, "fealnx maximum number of filtered multicast addresses");
123 MODULE_PARM_DESC(options, "fealnx: Bits 0-3: media type, bit 17: full duplex");
124 MODULE_PARM_DESC(full_duplex, "fealnx full duplex setting(s) (1)");
125
126 enum {
127 MIN_REGION_SIZE = 136,
128 };
129
130 /* A chip capabilities table, matching the entries in pci_tbl[] above. */
131 enum chip_capability_flags {
132 HAS_MII_XCVR,
133 HAS_CHIP_XCVR,
134 };
135
136 /* 89/6/13 add, */
137 /* for different PHY */
138 enum phy_type_flags {
139 MysonPHY = 1,
140 AhdocPHY = 2,
141 SeeqPHY = 3,
142 MarvellPHY = 4,
143 Myson981 = 5,
144 LevelOnePHY = 6,
145 OtherPHY = 10,
146 };
147
148 struct chip_info {
149 char *chip_name;
150 int flags;
151 };
152
153 static const struct chip_info skel_netdrv_tbl[] __devinitdata = {
154 { "100/10M Ethernet PCI Adapter", HAS_MII_XCVR },
155 { "100/10M Ethernet PCI Adapter", HAS_CHIP_XCVR },
156 { "1000/100/10M Ethernet PCI Adapter", HAS_MII_XCVR },
157 };
158
159 /* Offsets to the Command and Status Registers. */
160 enum fealnx_offsets {
161 PAR0 = 0x0, /* physical address 0-3 */
162 PAR1 = 0x04, /* physical address 4-5 */
163 MAR0 = 0x08, /* multicast address 0-3 */
164 MAR1 = 0x0C, /* multicast address 4-7 */
165 FAR0 = 0x10, /* flow-control address 0-3 */
166 FAR1 = 0x14, /* flow-control address 4-5 */
167 TCRRCR = 0x18, /* receive & transmit configuration */
168 BCR = 0x1C, /* bus command */
169 TXPDR = 0x20, /* transmit polling demand */
170 RXPDR = 0x24, /* receive polling demand */
171 RXCWP = 0x28, /* receive current word pointer */
172 TXLBA = 0x2C, /* transmit list base address */
173 RXLBA = 0x30, /* receive list base address */
174 ISR = 0x34, /* interrupt status */
175 IMR = 0x38, /* interrupt mask */
176 FTH = 0x3C, /* flow control high/low threshold */
177 MANAGEMENT = 0x40, /* bootrom/eeprom and mii management */
178 TALLY = 0x44, /* tally counters for crc and mpa */
179 TSR = 0x48, /* tally counter for transmit status */
180 BMCRSR = 0x4c, /* basic mode control and status */
181 PHYIDENTIFIER = 0x50, /* phy identifier */
182 ANARANLPAR = 0x54, /* auto-negotiation advertisement and link
183 partner ability */
184 ANEROCR = 0x58, /* auto-negotiation expansion and pci conf. */
185 BPREMRPSR = 0x5c, /* bypass & receive error mask and phy status */
186 };
187
188 /* Bits in the interrupt status/enable registers. */
189 /* The bits in the Intr Status/Enable registers, mostly interrupt sources. */
190 enum intr_status_bits {
191 RFCON = 0x00020000, /* receive flow control xon packet */
192 RFCOFF = 0x00010000, /* receive flow control xoff packet */
193 LSCStatus = 0x00008000, /* link status change */
194 ANCStatus = 0x00004000, /* autonegotiation completed */
195 FBE = 0x00002000, /* fatal bus error */
196 FBEMask = 0x00001800, /* mask bit12-11 */
197 ParityErr = 0x00000000, /* parity error */
198 TargetErr = 0x00001000, /* target abort */
199 MasterErr = 0x00000800, /* master error */
200 TUNF = 0x00000400, /* transmit underflow */
201 ROVF = 0x00000200, /* receive overflow */
202 ETI = 0x00000100, /* transmit early int */
203 ERI = 0x00000080, /* receive early int */
204 CNTOVF = 0x00000040, /* counter overflow */
205 RBU = 0x00000020, /* receive buffer unavailable */
206 TBU = 0x00000010, /* transmit buffer unavilable */
207 TI = 0x00000008, /* transmit interrupt */
208 RI = 0x00000004, /* receive interrupt */
209 RxErr = 0x00000002, /* receive error */
210 };
211
212 /* Bits in the NetworkConfig register, W for writing, R for reading */
213 /* FIXME: some names are invented by me. Marked with (name?) */
214 /* If you have docs and know bit names, please fix 'em */
215 enum rx_mode_bits {
216 CR_W_ENH = 0x02000000, /* enhanced mode (name?) */
217 CR_W_FD = 0x00100000, /* full duplex */
218 CR_W_PS10 = 0x00080000, /* 10 mbit */
219 CR_W_TXEN = 0x00040000, /* tx enable (name?) */
220 CR_W_PS1000 = 0x00010000, /* 1000 mbit */
221 /* CR_W_RXBURSTMASK= 0x00000e00, Im unsure about this */
222 CR_W_RXMODEMASK = 0x000000e0,
223 CR_W_PROM = 0x00000080, /* promiscuous mode */
224 CR_W_AB = 0x00000040, /* accept broadcast */
225 CR_W_AM = 0x00000020, /* accept mutlicast */
226 CR_W_ARP = 0x00000008, /* receive runt pkt */
227 CR_W_ALP = 0x00000004, /* receive long pkt */
228 CR_W_SEP = 0x00000002, /* receive error pkt */
229 CR_W_RXEN = 0x00000001, /* rx enable (unicast?) (name?) */
230
231 CR_R_TXSTOP = 0x04000000, /* tx stopped (name?) */
232 CR_R_FD = 0x00100000, /* full duplex detected */
233 CR_R_PS10 = 0x00080000, /* 10 mbit detected */
234 CR_R_RXSTOP = 0x00008000, /* rx stopped (name?) */
235 };
236
237 /* The Tulip Rx and Tx buffer descriptors. */
238 struct fealnx_desc {
239 s32 status;
240 s32 control;
241 u32 buffer;
242 u32 next_desc;
243 struct fealnx_desc *next_desc_logical;
244 struct sk_buff *skbuff;
245 u32 reserved1;
246 u32 reserved2;
247 };
248
249 /* Bits in network_desc.status */
250 enum rx_desc_status_bits {
251 RXOWN = 0x80000000, /* own bit */
252 FLNGMASK = 0x0fff0000, /* frame length */
253 FLNGShift = 16,
254 MARSTATUS = 0x00004000, /* multicast address received */
255 BARSTATUS = 0x00002000, /* broadcast address received */
256 PHYSTATUS = 0x00001000, /* physical address received */
257 RXFSD = 0x00000800, /* first descriptor */
258 RXLSD = 0x00000400, /* last descriptor */
259 ErrorSummary = 0x80, /* error summary */
260 RUNT = 0x40, /* runt packet received */
261 LONG = 0x20, /* long packet received */
262 FAE = 0x10, /* frame align error */
263 CRC = 0x08, /* crc error */
264 RXER = 0x04, /* receive error */
265 };
266
267 enum rx_desc_control_bits {
268 RXIC = 0x00800000, /* interrupt control */
269 RBSShift = 0,
270 };
271
272 enum tx_desc_status_bits {
273 TXOWN = 0x80000000, /* own bit */
274 JABTO = 0x00004000, /* jabber timeout */
275 CSL = 0x00002000, /* carrier sense lost */
276 LC = 0x00001000, /* late collision */
277 EC = 0x00000800, /* excessive collision */
278 UDF = 0x00000400, /* fifo underflow */
279 DFR = 0x00000200, /* deferred */
280 HF = 0x00000100, /* heartbeat fail */
281 NCRMask = 0x000000ff, /* collision retry count */
282 NCRShift = 0,
283 };
284
285 enum tx_desc_control_bits {
286 TXIC = 0x80000000, /* interrupt control */
287 ETIControl = 0x40000000, /* early transmit interrupt */
288 TXLD = 0x20000000, /* last descriptor */
289 TXFD = 0x10000000, /* first descriptor */
290 CRCEnable = 0x08000000, /* crc control */
291 PADEnable = 0x04000000, /* padding control */
292 RetryTxLC = 0x02000000, /* retry late collision */
293 PKTSMask = 0x3ff800, /* packet size bit21-11 */
294 PKTSShift = 11,
295 TBSMask = 0x000007ff, /* transmit buffer bit 10-0 */
296 TBSShift = 0,
297 };
298
299 /* BootROM/EEPROM/MII Management Register */
300 #define MASK_MIIR_MII_READ 0x00000000
301 #define MASK_MIIR_MII_WRITE 0x00000008
302 #define MASK_MIIR_MII_MDO 0x00000004
303 #define MASK_MIIR_MII_MDI 0x00000002
304 #define MASK_MIIR_MII_MDC 0x00000001
305
306 /* ST+OP+PHYAD+REGAD+TA */
307 #define OP_READ 0x6000 /* ST:01+OP:10+PHYAD+REGAD+TA:Z0 */
308 #define OP_WRITE 0x5002 /* ST:01+OP:01+PHYAD+REGAD+TA:10 */
309
310 /* ------------------------------------------------------------------------- */
311 /* Constants for Myson PHY */
312 /* ------------------------------------------------------------------------- */
313 #define MysonPHYID 0xd0000302
314 /* 89-7-27 add, (begin) */
315 #define MysonPHYID0 0x0302
316 #define StatusRegister 18
317 #define SPEED100 0x0400 // bit10
318 #define FULLMODE 0x0800 // bit11
319 /* 89-7-27 add, (end) */
320
321 /* ------------------------------------------------------------------------- */
322 /* Constants for Seeq 80225 PHY */
323 /* ------------------------------------------------------------------------- */
324 #define SeeqPHYID0 0x0016
325
326 #define MIIRegister18 18
327 #define SPD_DET_100 0x80
328 #define DPLX_DET_FULL 0x40
329
330 /* ------------------------------------------------------------------------- */
331 /* Constants for Ahdoc 101 PHY */
332 /* ------------------------------------------------------------------------- */
333 #define AhdocPHYID0 0x0022
334
335 #define DiagnosticReg 18
336 #define DPLX_FULL 0x0800
337 #define Speed_100 0x0400
338
339 /* 89/6/13 add, */
340 /* -------------------------------------------------------------------------- */
341 /* Constants */
342 /* -------------------------------------------------------------------------- */
343 #define MarvellPHYID0 0x0141
344 #define LevelOnePHYID0 0x0013
345
346 #define MII1000BaseTControlReg 9
347 #define MII1000BaseTStatusReg 10
348 #define SpecificReg 17
349
350 /* for 1000BaseT Control Register */
351 #define PHYAbletoPerform1000FullDuplex 0x0200
352 #define PHYAbletoPerform1000HalfDuplex 0x0100
353 #define PHY1000AbilityMask 0x300
354
355 // for phy specific status register, marvell phy.
356 #define SpeedMask 0x0c000
357 #define Speed_1000M 0x08000
358 #define Speed_100M 0x4000
359 #define Speed_10M 0
360 #define Full_Duplex 0x2000
361
362 // 89/12/29 add, for phy specific status register, levelone phy, (begin)
363 #define LXT1000_100M 0x08000
364 #define LXT1000_1000M 0x0c000
365 #define LXT1000_Full 0x200
366 // 89/12/29 add, for phy specific status register, levelone phy, (end)
367
368 /* for 3-in-1 case, BMCRSR register */
369 #define LinkIsUp2 0x00040000
370
371 /* for PHY */
372 #define LinkIsUp 0x0004
373
374
375 struct netdev_private {
376 /* Descriptor rings first for alignment. */
377 struct fealnx_desc *rx_ring;
378 struct fealnx_desc *tx_ring;
379
380 dma_addr_t rx_ring_dma;
381 dma_addr_t tx_ring_dma;
382
383 spinlock_t lock;
384
385 /* Media monitoring timer. */
386 struct timer_list timer;
387
388 /* Reset timer */
389 struct timer_list reset_timer;
390 int reset_timer_armed;
391 unsigned long crvalue_sv;
392 unsigned long imrvalue_sv;
393
394 /* Frequently used values: keep some adjacent for cache effect. */
395 int flags;
396 struct pci_dev *pci_dev;
397 unsigned long crvalue;
398 unsigned long bcrvalue;
399 unsigned long imrvalue;
400 struct fealnx_desc *cur_rx;
401 struct fealnx_desc *lack_rxbuf;
402 int really_rx_count;
403 struct fealnx_desc *cur_tx;
404 struct fealnx_desc *cur_tx_copy;
405 int really_tx_count;
406 int free_tx_count;
407 unsigned int rx_buf_sz; /* Based on MTU+slack. */
408
409 /* These values are keep track of the transceiver/media in use. */
410 unsigned int linkok;
411 unsigned int line_speed;
412 unsigned int duplexmode;
413 unsigned int default_port:4; /* Last dev->if_port value. */
414 unsigned int PHYType;
415
416 /* MII transceiver section. */
417 int mii_cnt; /* MII device addresses. */
418 unsigned char phys[2]; /* MII device addresses. */
419 struct mii_if_info mii;
420 void __iomem *mem;
421 };
422
423
424 static int mdio_read(struct net_device *dev, int phy_id, int location);
425 static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
426 static int netdev_open(struct net_device *dev);
427 static void getlinktype(struct net_device *dev);
428 static void getlinkstatus(struct net_device *dev);
429 static void netdev_timer(unsigned long data);
430 static void reset_timer(unsigned long data);
431 static void fealnx_tx_timeout(struct net_device *dev);
432 static void init_ring(struct net_device *dev);
433 static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev);
434 static irqreturn_t intr_handler(int irq, void *dev_instance);
435 static int netdev_rx(struct net_device *dev);
436 static void set_rx_mode(struct net_device *dev);
437 static void __set_rx_mode(struct net_device *dev);
438 static struct net_device_stats *get_stats(struct net_device *dev);
439 static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
440 static const struct ethtool_ops netdev_ethtool_ops;
441 static int netdev_close(struct net_device *dev);
442 static void reset_rx_descriptors(struct net_device *dev);
443 static void reset_tx_descriptors(struct net_device *dev);
444
445 static void stop_nic_rx(void __iomem *ioaddr, long crvalue)
446 {
447 int delay = 0x1000;
448 iowrite32(crvalue & ~(CR_W_RXEN), ioaddr + TCRRCR);
449 while (--delay) {
450 if ( (ioread32(ioaddr + TCRRCR) & CR_R_RXSTOP) == CR_R_RXSTOP)
451 break;
452 }
453 }
454
455
456 static void stop_nic_rxtx(void __iomem *ioaddr, long crvalue)
457 {
458 int delay = 0x1000;
459 iowrite32(crvalue & ~(CR_W_RXEN+CR_W_TXEN), ioaddr + TCRRCR);
460 while (--delay) {
461 if ( (ioread32(ioaddr + TCRRCR) & (CR_R_RXSTOP+CR_R_TXSTOP))
462 == (CR_R_RXSTOP+CR_R_TXSTOP) )
463 break;
464 }
465 }
466
467 static const struct net_device_ops netdev_ops = {
468 .ndo_open = netdev_open,
469 .ndo_stop = netdev_close,
470 .ndo_start_xmit = start_tx,
471 .ndo_get_stats = get_stats,
472 .ndo_set_rx_mode = set_rx_mode,
473 .ndo_do_ioctl = mii_ioctl,
474 .ndo_tx_timeout = fealnx_tx_timeout,
475 .ndo_change_mtu = eth_change_mtu,
476 .ndo_set_mac_address = eth_mac_addr,
477 .ndo_validate_addr = eth_validate_addr,
478 };
479
480 static int __devinit fealnx_init_one(struct pci_dev *pdev,
481 const struct pci_device_id *ent)
482 {
483 struct netdev_private *np;
484 int i, option, err, irq;
485 static int card_idx = -1;
486 char boardname[12];
487 void __iomem *ioaddr;
488 unsigned long len;
489 unsigned int chip_id = ent->driver_data;
490 struct net_device *dev;
491 void *ring_space;
492 dma_addr_t ring_dma;
493 #ifdef USE_IO_OPS
494 int bar = 0;
495 #else
496 int bar = 1;
497 #endif
498
499 /* when built into the kernel, we only print version if device is found */
500 #ifndef MODULE
501 static int printed_version;
502 if (!printed_version++)
503 printk(version);
504 #endif
505
506 card_idx++;
507 sprintf(boardname, "fealnx%d", card_idx);
508
509 option = card_idx < MAX_UNITS ? options[card_idx] : 0;
510
511 i = pci_enable_device(pdev);
512 if (i) return i;
513 pci_set_master(pdev);
514
515 len = pci_resource_len(pdev, bar);
516 if (len < MIN_REGION_SIZE) {
517 dev_err(&pdev->dev,
518 "region size %ld too small, aborting\n", len);
519 return -ENODEV;
520 }
521
522 i = pci_request_regions(pdev, boardname);
523 if (i)
524 return i;
525
526 irq = pdev->irq;
527
528 ioaddr = pci_iomap(pdev, bar, len);
529 if (!ioaddr) {
530 err = -ENOMEM;
531 goto err_out_res;
532 }
533
534 dev = alloc_etherdev(sizeof(struct netdev_private));
535 if (!dev) {
536 err = -ENOMEM;
537 goto err_out_unmap;
538 }
539 SET_NETDEV_DEV(dev, &pdev->dev);
540
541 /* read ethernet id */
542 for (i = 0; i < 6; ++i)
543 dev->dev_addr[i] = ioread8(ioaddr + PAR0 + i);
544
545 /* Reset the chip to erase previous misconfiguration. */
546 iowrite32(0x00000001, ioaddr + BCR);
547
548 dev->base_addr = (unsigned long)ioaddr;
549 dev->irq = irq;
550
551 /* Make certain the descriptor lists are aligned. */
552 np = netdev_priv(dev);
553 np->mem = ioaddr;
554 spin_lock_init(&np->lock);
555 np->pci_dev = pdev;
556 np->flags = skel_netdrv_tbl[chip_id].flags;
557 pci_set_drvdata(pdev, dev);
558 np->mii.dev = dev;
559 np->mii.mdio_read = mdio_read;
560 np->mii.mdio_write = mdio_write;
561 np->mii.phy_id_mask = 0x1f;
562 np->mii.reg_num_mask = 0x1f;
563
564 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
565 if (!ring_space) {
566 err = -ENOMEM;
567 goto err_out_free_dev;
568 }
569 np->rx_ring = ring_space;
570 np->rx_ring_dma = ring_dma;
571
572 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
573 if (!ring_space) {
574 err = -ENOMEM;
575 goto err_out_free_rx;
576 }
577 np->tx_ring = ring_space;
578 np->tx_ring_dma = ring_dma;
579
580 /* find the connected MII xcvrs */
581 if (np->flags == HAS_MII_XCVR) {
582 int phy, phy_idx = 0;
583
584 for (phy = 1; phy < 32 && phy_idx < ARRAY_SIZE(np->phys);
585 phy++) {
586 int mii_status = mdio_read(dev, phy, 1);
587
588 if (mii_status != 0xffff && mii_status != 0x0000) {
589 np->phys[phy_idx++] = phy;
590 dev_info(&pdev->dev,
591 "MII PHY found at address %d, status "
592 "0x%4.4x.\n", phy, mii_status);
593 /* get phy type */
594 {
595 unsigned int data;
596
597 data = mdio_read(dev, np->phys[0], 2);
598 if (data == SeeqPHYID0)
599 np->PHYType = SeeqPHY;
600 else if (data == AhdocPHYID0)
601 np->PHYType = AhdocPHY;
602 else if (data == MarvellPHYID0)
603 np->PHYType = MarvellPHY;
604 else if (data == MysonPHYID0)
605 np->PHYType = Myson981;
606 else if (data == LevelOnePHYID0)
607 np->PHYType = LevelOnePHY;
608 else
609 np->PHYType = OtherPHY;
610 }
611 }
612 }
613
614 np->mii_cnt = phy_idx;
615 if (phy_idx == 0)
616 dev_warn(&pdev->dev,
617 "MII PHY not found -- this device may "
618 "not operate correctly.\n");
619 } else {
620 np->phys[0] = 32;
621 /* 89/6/23 add, (begin) */
622 /* get phy type */
623 if (ioread32(ioaddr + PHYIDENTIFIER) == MysonPHYID)
624 np->PHYType = MysonPHY;
625 else
626 np->PHYType = OtherPHY;
627 }
628 np->mii.phy_id = np->phys[0];
629
630 if (dev->mem_start)
631 option = dev->mem_start;
632
633 /* The lower four bits are the media type. */
634 if (option > 0) {
635 if (option & 0x200)
636 np->mii.full_duplex = 1;
637 np->default_port = option & 15;
638 }
639
640 if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0)
641 np->mii.full_duplex = full_duplex[card_idx];
642
643 if (np->mii.full_duplex) {
644 dev_info(&pdev->dev, "Media type forced to Full Duplex.\n");
645 /* 89/6/13 add, (begin) */
646 // if (np->PHYType==MarvellPHY)
647 if ((np->PHYType == MarvellPHY) || (np->PHYType == LevelOnePHY)) {
648 unsigned int data;
649
650 data = mdio_read(dev, np->phys[0], 9);
651 data = (data & 0xfcff) | 0x0200;
652 mdio_write(dev, np->phys[0], 9, data);
653 }
654 /* 89/6/13 add, (end) */
655 if (np->flags == HAS_MII_XCVR)
656 mdio_write(dev, np->phys[0], MII_ADVERTISE, ADVERTISE_FULL);
657 else
658 iowrite32(ADVERTISE_FULL, ioaddr + ANARANLPAR);
659 np->mii.force_media = 1;
660 }
661
662 dev->netdev_ops = &netdev_ops;
663 dev->ethtool_ops = &netdev_ethtool_ops;
664 dev->watchdog_timeo = TX_TIMEOUT;
665
666 err = register_netdev(dev);
667 if (err)
668 goto err_out_free_tx;
669
670 printk(KERN_INFO "%s: %s at %p, %pM, IRQ %d.\n",
671 dev->name, skel_netdrv_tbl[chip_id].chip_name, ioaddr,
672 dev->dev_addr, irq);
673
674 return 0;
675
676 err_out_free_tx:
677 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
678 err_out_free_rx:
679 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
680 err_out_free_dev:
681 free_netdev(dev);
682 err_out_unmap:
683 pci_iounmap(pdev, ioaddr);
684 err_out_res:
685 pci_release_regions(pdev);
686 return err;
687 }
688
689
690 static void __devexit fealnx_remove_one(struct pci_dev *pdev)
691 {
692 struct net_device *dev = pci_get_drvdata(pdev);
693
694 if (dev) {
695 struct netdev_private *np = netdev_priv(dev);
696
697 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring,
698 np->tx_ring_dma);
699 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring,
700 np->rx_ring_dma);
701 unregister_netdev(dev);
702 pci_iounmap(pdev, np->mem);
703 free_netdev(dev);
704 pci_release_regions(pdev);
705 pci_set_drvdata(pdev, NULL);
706 } else
707 printk(KERN_ERR "fealnx: remove for unknown device\n");
708 }
709
710
711 static ulong m80x_send_cmd_to_phy(void __iomem *miiport, int opcode, int phyad, int regad)
712 {
713 ulong miir;
714 int i;
715 unsigned int mask, data;
716
717 /* enable MII output */
718 miir = (ulong) ioread32(miiport);
719 miir &= 0xfffffff0;
720
721 miir |= MASK_MIIR_MII_WRITE + MASK_MIIR_MII_MDO;
722
723 /* send 32 1's preamble */
724 for (i = 0; i < 32; i++) {
725 /* low MDC; MDO is already high (miir) */
726 miir &= ~MASK_MIIR_MII_MDC;
727 iowrite32(miir, miiport);
728
729 /* high MDC */
730 miir |= MASK_MIIR_MII_MDC;
731 iowrite32(miir, miiport);
732 }
733
734 /* calculate ST+OP+PHYAD+REGAD+TA */
735 data = opcode | (phyad << 7) | (regad << 2);
736
737 /* sent out */
738 mask = 0x8000;
739 while (mask) {
740 /* low MDC, prepare MDO */
741 miir &= ~(MASK_MIIR_MII_MDC + MASK_MIIR_MII_MDO);
742 if (mask & data)
743 miir |= MASK_MIIR_MII_MDO;
744
745 iowrite32(miir, miiport);
746 /* high MDC */
747 miir |= MASK_MIIR_MII_MDC;
748 iowrite32(miir, miiport);
749 udelay(30);
750
751 /* next */
752 mask >>= 1;
753 if (mask == 0x2 && opcode == OP_READ)
754 miir &= ~MASK_MIIR_MII_WRITE;
755 }
756 return miir;
757 }
758
759
760 static int mdio_read(struct net_device *dev, int phyad, int regad)
761 {
762 struct netdev_private *np = netdev_priv(dev);
763 void __iomem *miiport = np->mem + MANAGEMENT;
764 ulong miir;
765 unsigned int mask, data;
766
767 miir = m80x_send_cmd_to_phy(miiport, OP_READ, phyad, regad);
768
769 /* read data */
770 mask = 0x8000;
771 data = 0;
772 while (mask) {
773 /* low MDC */
774 miir &= ~MASK_MIIR_MII_MDC;
775 iowrite32(miir, miiport);
776
777 /* read MDI */
778 miir = ioread32(miiport);
779 if (miir & MASK_MIIR_MII_MDI)
780 data |= mask;
781
782 /* high MDC, and wait */
783 miir |= MASK_MIIR_MII_MDC;
784 iowrite32(miir, miiport);
785 udelay(30);
786
787 /* next */
788 mask >>= 1;
789 }
790
791 /* low MDC */
792 miir &= ~MASK_MIIR_MII_MDC;
793 iowrite32(miir, miiport);
794
795 return data & 0xffff;
796 }
797
798
799 static void mdio_write(struct net_device *dev, int phyad, int regad, int data)
800 {
801 struct netdev_private *np = netdev_priv(dev);
802 void __iomem *miiport = np->mem + MANAGEMENT;
803 ulong miir;
804 unsigned int mask;
805
806 miir = m80x_send_cmd_to_phy(miiport, OP_WRITE, phyad, regad);
807
808 /* write data */
809 mask = 0x8000;
810 while (mask) {
811 /* low MDC, prepare MDO */
812 miir &= ~(MASK_MIIR_MII_MDC + MASK_MIIR_MII_MDO);
813 if (mask & data)
814 miir |= MASK_MIIR_MII_MDO;
815 iowrite32(miir, miiport);
816
817 /* high MDC */
818 miir |= MASK_MIIR_MII_MDC;
819 iowrite32(miir, miiport);
820
821 /* next */
822 mask >>= 1;
823 }
824
825 /* low MDC */
826 miir &= ~MASK_MIIR_MII_MDC;
827 iowrite32(miir, miiport);
828 }
829
830
831 static int netdev_open(struct net_device *dev)
832 {
833 struct netdev_private *np = netdev_priv(dev);
834 void __iomem *ioaddr = np->mem;
835 int i;
836
837 iowrite32(0x00000001, ioaddr + BCR); /* Reset */
838
839 if (request_irq(dev->irq, intr_handler, IRQF_SHARED, dev->name, dev))
840 return -EAGAIN;
841
842 for (i = 0; i < 3; i++)
843 iowrite16(((unsigned short*)dev->dev_addr)[i],
844 ioaddr + PAR0 + i*2);
845
846 init_ring(dev);
847
848 iowrite32(np->rx_ring_dma, ioaddr + RXLBA);
849 iowrite32(np->tx_ring_dma, ioaddr + TXLBA);
850
851 /* Initialize other registers. */
852 /* Configure the PCI bus bursts and FIFO thresholds.
853 486: Set 8 longword burst.
854 586: no burst limit.
855 Burst length 5:3
856 0 0 0 1
857 0 0 1 4
858 0 1 0 8
859 0 1 1 16
860 1 0 0 32
861 1 0 1 64
862 1 1 0 128
863 1 1 1 256
864 Wait the specified 50 PCI cycles after a reset by initializing
865 Tx and Rx queues and the address filter list.
866 FIXME (Ueimor): optimistic for alpha + posted writes ? */
867
868 np->bcrvalue = 0x10; /* little-endian, 8 burst length */
869 #ifdef __BIG_ENDIAN
870 np->bcrvalue |= 0x04; /* big-endian */
871 #endif
872
873 #if defined(__i386__) && !defined(MODULE)
874 if (boot_cpu_data.x86 <= 4)
875 np->crvalue = 0xa00;
876 else
877 #endif
878 np->crvalue = 0xe00; /* rx 128 burst length */
879
880
881 // 89/12/29 add,
882 // 90/1/16 modify,
883 // np->imrvalue=FBE|TUNF|CNTOVF|RBU|TI|RI;
884 np->imrvalue = TUNF | CNTOVF | RBU | TI | RI;
885 if (np->pci_dev->device == 0x891) {
886 np->bcrvalue |= 0x200; /* set PROG bit */
887 np->crvalue |= CR_W_ENH; /* set enhanced bit */
888 np->imrvalue |= ETI;
889 }
890 iowrite32(np->bcrvalue, ioaddr + BCR);
891
892 if (dev->if_port == 0)
893 dev->if_port = np->default_port;
894
895 iowrite32(0, ioaddr + RXPDR);
896 // 89/9/1 modify,
897 // np->crvalue = 0x00e40001; /* tx store and forward, tx/rx enable */
898 np->crvalue |= 0x00e40001; /* tx store and forward, tx/rx enable */
899 np->mii.full_duplex = np->mii.force_media;
900 getlinkstatus(dev);
901 if (np->linkok)
902 getlinktype(dev);
903 __set_rx_mode(dev);
904
905 netif_start_queue(dev);
906
907 /* Clear and Enable interrupts by setting the interrupt mask. */
908 iowrite32(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR);
909 iowrite32(np->imrvalue, ioaddr + IMR);
910
911 if (debug)
912 printk(KERN_DEBUG "%s: Done netdev_open().\n", dev->name);
913
914 /* Set the timer to check for link beat. */
915 init_timer(&np->timer);
916 np->timer.expires = RUN_AT(3 * HZ);
917 np->timer.data = (unsigned long) dev;
918 np->timer.function = netdev_timer;
919
920 /* timer handler */
921 add_timer(&np->timer);
922
923 init_timer(&np->reset_timer);
924 np->reset_timer.data = (unsigned long) dev;
925 np->reset_timer.function = reset_timer;
926 np->reset_timer_armed = 0;
927
928 return 0;
929 }
930
931
932 static void getlinkstatus(struct net_device *dev)
933 /* function: Routine will read MII Status Register to get link status. */
934 /* input : dev... pointer to the adapter block. */
935 /* output : none. */
936 {
937 struct netdev_private *np = netdev_priv(dev);
938 unsigned int i, DelayTime = 0x1000;
939
940 np->linkok = 0;
941
942 if (np->PHYType == MysonPHY) {
943 for (i = 0; i < DelayTime; ++i) {
944 if (ioread32(np->mem + BMCRSR) & LinkIsUp2) {
945 np->linkok = 1;
946 return;
947 }
948 udelay(100);
949 }
950 } else {
951 for (i = 0; i < DelayTime; ++i) {
952 if (mdio_read(dev, np->phys[0], MII_BMSR) & BMSR_LSTATUS) {
953 np->linkok = 1;
954 return;
955 }
956 udelay(100);
957 }
958 }
959 }
960
961
962 static void getlinktype(struct net_device *dev)
963 {
964 struct netdev_private *np = netdev_priv(dev);
965
966 if (np->PHYType == MysonPHY) { /* 3-in-1 case */
967 if (ioread32(np->mem + TCRRCR) & CR_R_FD)
968 np->duplexmode = 2; /* full duplex */
969 else
970 np->duplexmode = 1; /* half duplex */
971 if (ioread32(np->mem + TCRRCR) & CR_R_PS10)
972 np->line_speed = 1; /* 10M */
973 else
974 np->line_speed = 2; /* 100M */
975 } else {
976 if (np->PHYType == SeeqPHY) { /* this PHY is SEEQ 80225 */
977 unsigned int data;
978
979 data = mdio_read(dev, np->phys[0], MIIRegister18);
980 if (data & SPD_DET_100)
981 np->line_speed = 2; /* 100M */
982 else
983 np->line_speed = 1; /* 10M */
984 if (data & DPLX_DET_FULL)
985 np->duplexmode = 2; /* full duplex mode */
986 else
987 np->duplexmode = 1; /* half duplex mode */
988 } else if (np->PHYType == AhdocPHY) {
989 unsigned int data;
990
991 data = mdio_read(dev, np->phys[0], DiagnosticReg);
992 if (data & Speed_100)
993 np->line_speed = 2; /* 100M */
994 else
995 np->line_speed = 1; /* 10M */
996 if (data & DPLX_FULL)
997 np->duplexmode = 2; /* full duplex mode */
998 else
999 np->duplexmode = 1; /* half duplex mode */
1000 }
1001 /* 89/6/13 add, (begin) */
1002 else if (np->PHYType == MarvellPHY) {
1003 unsigned int data;
1004
1005 data = mdio_read(dev, np->phys[0], SpecificReg);
1006 if (data & Full_Duplex)
1007 np->duplexmode = 2; /* full duplex mode */
1008 else
1009 np->duplexmode = 1; /* half duplex mode */
1010 data &= SpeedMask;
1011 if (data == Speed_1000M)
1012 np->line_speed = 3; /* 1000M */
1013 else if (data == Speed_100M)
1014 np->line_speed = 2; /* 100M */
1015 else
1016 np->line_speed = 1; /* 10M */
1017 }
1018 /* 89/6/13 add, (end) */
1019 /* 89/7/27 add, (begin) */
1020 else if (np->PHYType == Myson981) {
1021 unsigned int data;
1022
1023 data = mdio_read(dev, np->phys[0], StatusRegister);
1024
1025 if (data & SPEED100)
1026 np->line_speed = 2;
1027 else
1028 np->line_speed = 1;
1029
1030 if (data & FULLMODE)
1031 np->duplexmode = 2;
1032 else
1033 np->duplexmode = 1;
1034 }
1035 /* 89/7/27 add, (end) */
1036 /* 89/12/29 add */
1037 else if (np->PHYType == LevelOnePHY) {
1038 unsigned int data;
1039
1040 data = mdio_read(dev, np->phys[0], SpecificReg);
1041 if (data & LXT1000_Full)
1042 np->duplexmode = 2; /* full duplex mode */
1043 else
1044 np->duplexmode = 1; /* half duplex mode */
1045 data &= SpeedMask;
1046 if (data == LXT1000_1000M)
1047 np->line_speed = 3; /* 1000M */
1048 else if (data == LXT1000_100M)
1049 np->line_speed = 2; /* 100M */
1050 else
1051 np->line_speed = 1; /* 10M */
1052 }
1053 np->crvalue &= (~CR_W_PS10) & (~CR_W_FD) & (~CR_W_PS1000);
1054 if (np->line_speed == 1)
1055 np->crvalue |= CR_W_PS10;
1056 else if (np->line_speed == 3)
1057 np->crvalue |= CR_W_PS1000;
1058 if (np->duplexmode == 2)
1059 np->crvalue |= CR_W_FD;
1060 }
1061 }
1062
1063
1064 /* Take lock before calling this */
1065 static void allocate_rx_buffers(struct net_device *dev)
1066 {
1067 struct netdev_private *np = netdev_priv(dev);
1068
1069 /* allocate skb for rx buffers */
1070 while (np->really_rx_count != RX_RING_SIZE) {
1071 struct sk_buff *skb;
1072
1073 skb = netdev_alloc_skb(dev, np->rx_buf_sz);
1074 if (skb == NULL)
1075 break; /* Better luck next round. */
1076
1077 while (np->lack_rxbuf->skbuff)
1078 np->lack_rxbuf = np->lack_rxbuf->next_desc_logical;
1079
1080 np->lack_rxbuf->skbuff = skb;
1081 np->lack_rxbuf->buffer = pci_map_single(np->pci_dev, skb->data,
1082 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1083 np->lack_rxbuf->status = RXOWN;
1084 ++np->really_rx_count;
1085 }
1086 }
1087
1088
1089 static void netdev_timer(unsigned long data)
1090 {
1091 struct net_device *dev = (struct net_device *) data;
1092 struct netdev_private *np = netdev_priv(dev);
1093 void __iomem *ioaddr = np->mem;
1094 int old_crvalue = np->crvalue;
1095 unsigned int old_linkok = np->linkok;
1096 unsigned long flags;
1097
1098 if (debug)
1099 printk(KERN_DEBUG "%s: Media selection timer tick, status %8.8x "
1100 "config %8.8x.\n", dev->name, ioread32(ioaddr + ISR),
1101 ioread32(ioaddr + TCRRCR));
1102
1103 spin_lock_irqsave(&np->lock, flags);
1104
1105 if (np->flags == HAS_MII_XCVR) {
1106 getlinkstatus(dev);
1107 if ((old_linkok == 0) && (np->linkok == 1)) { /* we need to detect the media type again */
1108 getlinktype(dev);
1109 if (np->crvalue != old_crvalue) {
1110 stop_nic_rxtx(ioaddr, np->crvalue);
1111 iowrite32(np->crvalue, ioaddr + TCRRCR);
1112 }
1113 }
1114 }
1115
1116 allocate_rx_buffers(dev);
1117
1118 spin_unlock_irqrestore(&np->lock, flags);
1119
1120 np->timer.expires = RUN_AT(10 * HZ);
1121 add_timer(&np->timer);
1122 }
1123
1124
1125 /* Take lock before calling */
1126 /* Reset chip and disable rx, tx and interrupts */
1127 static void reset_and_disable_rxtx(struct net_device *dev)
1128 {
1129 struct netdev_private *np = netdev_priv(dev);
1130 void __iomem *ioaddr = np->mem;
1131 int delay=51;
1132
1133 /* Reset the chip's Tx and Rx processes. */
1134 stop_nic_rxtx(ioaddr, 0);
1135
1136 /* Disable interrupts by clearing the interrupt mask. */
1137 iowrite32(0, ioaddr + IMR);
1138
1139 /* Reset the chip to erase previous misconfiguration. */
1140 iowrite32(0x00000001, ioaddr + BCR);
1141
1142 /* Ueimor: wait for 50 PCI cycles (and flush posted writes btw).
1143 We surely wait too long (address+data phase). Who cares? */
1144 while (--delay) {
1145 ioread32(ioaddr + BCR);
1146 rmb();
1147 }
1148 }
1149
1150
1151 /* Take lock before calling */
1152 /* Restore chip after reset */
1153 static void enable_rxtx(struct net_device *dev)
1154 {
1155 struct netdev_private *np = netdev_priv(dev);
1156 void __iomem *ioaddr = np->mem;
1157
1158 reset_rx_descriptors(dev);
1159
1160 iowrite32(np->tx_ring_dma + ((char*)np->cur_tx - (char*)np->tx_ring),
1161 ioaddr + TXLBA);
1162 iowrite32(np->rx_ring_dma + ((char*)np->cur_rx - (char*)np->rx_ring),
1163 ioaddr + RXLBA);
1164
1165 iowrite32(np->bcrvalue, ioaddr + BCR);
1166
1167 iowrite32(0, ioaddr + RXPDR);
1168 __set_rx_mode(dev); /* changes np->crvalue, writes it into TCRRCR */
1169
1170 /* Clear and Enable interrupts by setting the interrupt mask. */
1171 iowrite32(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR);
1172 iowrite32(np->imrvalue, ioaddr + IMR);
1173
1174 iowrite32(0, ioaddr + TXPDR);
1175 }
1176
1177
1178 static void reset_timer(unsigned long data)
1179 {
1180 struct net_device *dev = (struct net_device *) data;
1181 struct netdev_private *np = netdev_priv(dev);
1182 unsigned long flags;
1183
1184 printk(KERN_WARNING "%s: resetting tx and rx machinery\n", dev->name);
1185
1186 spin_lock_irqsave(&np->lock, flags);
1187 np->crvalue = np->crvalue_sv;
1188 np->imrvalue = np->imrvalue_sv;
1189
1190 reset_and_disable_rxtx(dev);
1191 /* works for me without this:
1192 reset_tx_descriptors(dev); */
1193 enable_rxtx(dev);
1194 netif_start_queue(dev); /* FIXME: or netif_wake_queue(dev); ? */
1195
1196 np->reset_timer_armed = 0;
1197
1198 spin_unlock_irqrestore(&np->lock, flags);
1199 }
1200
1201
1202 static void fealnx_tx_timeout(struct net_device *dev)
1203 {
1204 struct netdev_private *np = netdev_priv(dev);
1205 void __iomem *ioaddr = np->mem;
1206 unsigned long flags;
1207 int i;
1208
1209 printk(KERN_WARNING
1210 "%s: Transmit timed out, status %8.8x, resetting...\n",
1211 dev->name, ioread32(ioaddr + ISR));
1212
1213 {
1214 printk(KERN_DEBUG " Rx ring %p: ", np->rx_ring);
1215 for (i = 0; i < RX_RING_SIZE; i++)
1216 printk(KERN_CONT " %8.8x",
1217 (unsigned int) np->rx_ring[i].status);
1218 printk(KERN_CONT "\n");
1219 printk(KERN_DEBUG " Tx ring %p: ", np->tx_ring);
1220 for (i = 0; i < TX_RING_SIZE; i++)
1221 printk(KERN_CONT " %4.4x", np->tx_ring[i].status);
1222 printk(KERN_CONT "\n");
1223 }
1224
1225 spin_lock_irqsave(&np->lock, flags);
1226
1227 reset_and_disable_rxtx(dev);
1228 reset_tx_descriptors(dev);
1229 enable_rxtx(dev);
1230
1231 spin_unlock_irqrestore(&np->lock, flags);
1232
1233 dev->trans_start = jiffies; /* prevent tx timeout */
1234 dev->stats.tx_errors++;
1235 netif_wake_queue(dev); /* or .._start_.. ?? */
1236 }
1237
1238
1239 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1240 static void init_ring(struct net_device *dev)
1241 {
1242 struct netdev_private *np = netdev_priv(dev);
1243 int i;
1244
1245 /* initialize rx variables */
1246 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
1247 np->cur_rx = &np->rx_ring[0];
1248 np->lack_rxbuf = np->rx_ring;
1249 np->really_rx_count = 0;
1250
1251 /* initial rx descriptors. */
1252 for (i = 0; i < RX_RING_SIZE; i++) {
1253 np->rx_ring[i].status = 0;
1254 np->rx_ring[i].control = np->rx_buf_sz << RBSShift;
1255 np->rx_ring[i].next_desc = np->rx_ring_dma +
1256 (i + 1)*sizeof(struct fealnx_desc);
1257 np->rx_ring[i].next_desc_logical = &np->rx_ring[i + 1];
1258 np->rx_ring[i].skbuff = NULL;
1259 }
1260
1261 /* for the last rx descriptor */
1262 np->rx_ring[i - 1].next_desc = np->rx_ring_dma;
1263 np->rx_ring[i - 1].next_desc_logical = np->rx_ring;
1264
1265 /* allocate skb for rx buffers */
1266 for (i = 0; i < RX_RING_SIZE; i++) {
1267 struct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz);
1268
1269 if (skb == NULL) {
1270 np->lack_rxbuf = &np->rx_ring[i];
1271 break;
1272 }
1273
1274 ++np->really_rx_count;
1275 np->rx_ring[i].skbuff = skb;
1276 np->rx_ring[i].buffer = pci_map_single(np->pci_dev, skb->data,
1277 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1278 np->rx_ring[i].status = RXOWN;
1279 np->rx_ring[i].control |= RXIC;
1280 }
1281
1282 /* initialize tx variables */
1283 np->cur_tx = &np->tx_ring[0];
1284 np->cur_tx_copy = &np->tx_ring[0];
1285 np->really_tx_count = 0;
1286 np->free_tx_count = TX_RING_SIZE;
1287
1288 for (i = 0; i < TX_RING_SIZE; i++) {
1289 np->tx_ring[i].status = 0;
1290 /* do we need np->tx_ring[i].control = XXX; ?? */
1291 np->tx_ring[i].next_desc = np->tx_ring_dma +
1292 (i + 1)*sizeof(struct fealnx_desc);
1293 np->tx_ring[i].next_desc_logical = &np->tx_ring[i + 1];
1294 np->tx_ring[i].skbuff = NULL;
1295 }
1296
1297 /* for the last tx descriptor */
1298 np->tx_ring[i - 1].next_desc = np->tx_ring_dma;
1299 np->tx_ring[i - 1].next_desc_logical = &np->tx_ring[0];
1300 }
1301
1302
1303 static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev)
1304 {
1305 struct netdev_private *np = netdev_priv(dev);
1306 unsigned long flags;
1307
1308 spin_lock_irqsave(&np->lock, flags);
1309
1310 np->cur_tx_copy->skbuff = skb;
1311
1312 #define one_buffer
1313 #define BPT 1022
1314 #if defined(one_buffer)
1315 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1316 skb->len, PCI_DMA_TODEVICE);
1317 np->cur_tx_copy->control = TXIC | TXLD | TXFD | CRCEnable | PADEnable;
1318 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1319 np->cur_tx_copy->control |= (skb->len << TBSShift); /* buffer size */
1320 // 89/12/29 add,
1321 if (np->pci_dev->device == 0x891)
1322 np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1323 np->cur_tx_copy->status = TXOWN;
1324 np->cur_tx_copy = np->cur_tx_copy->next_desc_logical;
1325 --np->free_tx_count;
1326 #elif defined(two_buffer)
1327 if (skb->len > BPT) {
1328 struct fealnx_desc *next;
1329
1330 /* for the first descriptor */
1331 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1332 BPT, PCI_DMA_TODEVICE);
1333 np->cur_tx_copy->control = TXIC | TXFD | CRCEnable | PADEnable;
1334 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1335 np->cur_tx_copy->control |= (BPT << TBSShift); /* buffer size */
1336
1337 /* for the last descriptor */
1338 next = np->cur_tx_copy->next_desc_logical;
1339 next->skbuff = skb;
1340 next->control = TXIC | TXLD | CRCEnable | PADEnable;
1341 next->control |= (skb->len << PKTSShift); /* pkt size */
1342 next->control |= ((skb->len - BPT) << TBSShift); /* buf size */
1343 // 89/12/29 add,
1344 if (np->pci_dev->device == 0x891)
1345 np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1346 next->buffer = pci_map_single(ep->pci_dev, skb->data + BPT,
1347 skb->len - BPT, PCI_DMA_TODEVICE);
1348
1349 next->status = TXOWN;
1350 np->cur_tx_copy->status = TXOWN;
1351
1352 np->cur_tx_copy = next->next_desc_logical;
1353 np->free_tx_count -= 2;
1354 } else {
1355 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1356 skb->len, PCI_DMA_TODEVICE);
1357 np->cur_tx_copy->control = TXIC | TXLD | TXFD | CRCEnable | PADEnable;
1358 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1359 np->cur_tx_copy->control |= (skb->len << TBSShift); /* buffer size */
1360 // 89/12/29 add,
1361 if (np->pci_dev->device == 0x891)
1362 np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1363 np->cur_tx_copy->status = TXOWN;
1364 np->cur_tx_copy = np->cur_tx_copy->next_desc_logical;
1365 --np->free_tx_count;
1366 }
1367 #endif
1368
1369 if (np->free_tx_count < 2)
1370 netif_stop_queue(dev);
1371 ++np->really_tx_count;
1372 iowrite32(0, np->mem + TXPDR);
1373
1374 spin_unlock_irqrestore(&np->lock, flags);
1375 return NETDEV_TX_OK;
1376 }
1377
1378
1379 /* Take lock before calling */
1380 /* Chip probably hosed tx ring. Clean up. */
1381 static void reset_tx_descriptors(struct net_device *dev)
1382 {
1383 struct netdev_private *np = netdev_priv(dev);
1384 struct fealnx_desc *cur;
1385 int i;
1386
1387 /* initialize tx variables */
1388 np->cur_tx = &np->tx_ring[0];
1389 np->cur_tx_copy = &np->tx_ring[0];
1390 np->really_tx_count = 0;
1391 np->free_tx_count = TX_RING_SIZE;
1392
1393 for (i = 0; i < TX_RING_SIZE; i++) {
1394 cur = &np->tx_ring[i];
1395 if (cur->skbuff) {
1396 pci_unmap_single(np->pci_dev, cur->buffer,
1397 cur->skbuff->len, PCI_DMA_TODEVICE);
1398 dev_kfree_skb_any(cur->skbuff);
1399 cur->skbuff = NULL;
1400 }
1401 cur->status = 0;
1402 cur->control = 0; /* needed? */
1403 /* probably not needed. We do it for purely paranoid reasons */
1404 cur->next_desc = np->tx_ring_dma +
1405 (i + 1)*sizeof(struct fealnx_desc);
1406 cur->next_desc_logical = &np->tx_ring[i + 1];
1407 }
1408 /* for the last tx descriptor */
1409 np->tx_ring[TX_RING_SIZE - 1].next_desc = np->tx_ring_dma;
1410 np->tx_ring[TX_RING_SIZE - 1].next_desc_logical = &np->tx_ring[0];
1411 }
1412
1413
1414 /* Take lock and stop rx before calling this */
1415 static void reset_rx_descriptors(struct net_device *dev)
1416 {
1417 struct netdev_private *np = netdev_priv(dev);
1418 struct fealnx_desc *cur = np->cur_rx;
1419 int i;
1420
1421 allocate_rx_buffers(dev);
1422
1423 for (i = 0; i < RX_RING_SIZE; i++) {
1424 if (cur->skbuff)
1425 cur->status = RXOWN;
1426 cur = cur->next_desc_logical;
1427 }
1428
1429 iowrite32(np->rx_ring_dma + ((char*)np->cur_rx - (char*)np->rx_ring),
1430 np->mem + RXLBA);
1431 }
1432
1433
1434 /* The interrupt handler does all of the Rx thread work and cleans up
1435 after the Tx thread. */
1436 static irqreturn_t intr_handler(int irq, void *dev_instance)
1437 {
1438 struct net_device *dev = (struct net_device *) dev_instance;
1439 struct netdev_private *np = netdev_priv(dev);
1440 void __iomem *ioaddr = np->mem;
1441 long boguscnt = max_interrupt_work;
1442 unsigned int num_tx = 0;
1443 int handled = 0;
1444
1445 spin_lock(&np->lock);
1446
1447 iowrite32(0, ioaddr + IMR);
1448
1449 do {
1450 u32 intr_status = ioread32(ioaddr + ISR);
1451
1452 /* Acknowledge all of the current interrupt sources ASAP. */
1453 iowrite32(intr_status, ioaddr + ISR);
1454
1455 if (debug)
1456 printk(KERN_DEBUG "%s: Interrupt, status %4.4x.\n", dev->name,
1457 intr_status);
1458
1459 if (!(intr_status & np->imrvalue))
1460 break;
1461
1462 handled = 1;
1463
1464 // 90/1/16 delete,
1465 //
1466 // if (intr_status & FBE)
1467 // { /* fatal error */
1468 // stop_nic_tx(ioaddr, 0);
1469 // stop_nic_rx(ioaddr, 0);
1470 // break;
1471 // };
1472
1473 if (intr_status & TUNF)
1474 iowrite32(0, ioaddr + TXPDR);
1475
1476 if (intr_status & CNTOVF) {
1477 /* missed pkts */
1478 dev->stats.rx_missed_errors +=
1479 ioread32(ioaddr + TALLY) & 0x7fff;
1480
1481 /* crc error */
1482 dev->stats.rx_crc_errors +=
1483 (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16;
1484 }
1485
1486 if (intr_status & (RI | RBU)) {
1487 if (intr_status & RI)
1488 netdev_rx(dev);
1489 else {
1490 stop_nic_rx(ioaddr, np->crvalue);
1491 reset_rx_descriptors(dev);
1492 iowrite32(np->crvalue, ioaddr + TCRRCR);
1493 }
1494 }
1495
1496 while (np->really_tx_count) {
1497 long tx_status = np->cur_tx->status;
1498 long tx_control = np->cur_tx->control;
1499
1500 if (!(tx_control & TXLD)) { /* this pkt is combined by two tx descriptors */
1501 struct fealnx_desc *next;
1502
1503 next = np->cur_tx->next_desc_logical;
1504 tx_status = next->status;
1505 tx_control = next->control;
1506 }
1507
1508 if (tx_status & TXOWN)
1509 break;
1510
1511 if (!(np->crvalue & CR_W_ENH)) {
1512 if (tx_status & (CSL | LC | EC | UDF | HF)) {
1513 dev->stats.tx_errors++;
1514 if (tx_status & EC)
1515 dev->stats.tx_aborted_errors++;
1516 if (tx_status & CSL)
1517 dev->stats.tx_carrier_errors++;
1518 if (tx_status & LC)
1519 dev->stats.tx_window_errors++;
1520 if (tx_status & UDF)
1521 dev->stats.tx_fifo_errors++;
1522 if ((tx_status & HF) && np->mii.full_duplex == 0)
1523 dev->stats.tx_heartbeat_errors++;
1524
1525 } else {
1526 dev->stats.tx_bytes +=
1527 ((tx_control & PKTSMask) >> PKTSShift);
1528
1529 dev->stats.collisions +=
1530 ((tx_status & NCRMask) >> NCRShift);
1531 dev->stats.tx_packets++;
1532 }
1533 } else {
1534 dev->stats.tx_bytes +=
1535 ((tx_control & PKTSMask) >> PKTSShift);
1536 dev->stats.tx_packets++;
1537 }
1538
1539 /* Free the original skb. */
1540 pci_unmap_single(np->pci_dev, np->cur_tx->buffer,
1541 np->cur_tx->skbuff->len, PCI_DMA_TODEVICE);
1542 dev_kfree_skb_irq(np->cur_tx->skbuff);
1543 np->cur_tx->skbuff = NULL;
1544 --np->really_tx_count;
1545 if (np->cur_tx->control & TXLD) {
1546 np->cur_tx = np->cur_tx->next_desc_logical;
1547 ++np->free_tx_count;
1548 } else {
1549 np->cur_tx = np->cur_tx->next_desc_logical;
1550 np->cur_tx = np->cur_tx->next_desc_logical;
1551 np->free_tx_count += 2;
1552 }
1553 num_tx++;
1554 } /* end of for loop */
1555
1556 if (num_tx && np->free_tx_count >= 2)
1557 netif_wake_queue(dev);
1558
1559 /* read transmit status for enhanced mode only */
1560 if (np->crvalue & CR_W_ENH) {
1561 long data;
1562
1563 data = ioread32(ioaddr + TSR);
1564 dev->stats.tx_errors += (data & 0xff000000) >> 24;
1565 dev->stats.tx_aborted_errors +=
1566 (data & 0xff000000) >> 24;
1567 dev->stats.tx_window_errors +=
1568 (data & 0x00ff0000) >> 16;
1569 dev->stats.collisions += (data & 0x0000ffff);
1570 }
1571
1572 if (--boguscnt < 0) {
1573 printk(KERN_WARNING "%s: Too much work at interrupt, "
1574 "status=0x%4.4x.\n", dev->name, intr_status);
1575 if (!np->reset_timer_armed) {
1576 np->reset_timer_armed = 1;
1577 np->reset_timer.expires = RUN_AT(HZ/2);
1578 add_timer(&np->reset_timer);
1579 stop_nic_rxtx(ioaddr, 0);
1580 netif_stop_queue(dev);
1581 /* or netif_tx_disable(dev); ?? */
1582 /* Prevent other paths from enabling tx,rx,intrs */
1583 np->crvalue_sv = np->crvalue;
1584 np->imrvalue_sv = np->imrvalue;
1585 np->crvalue &= ~(CR_W_TXEN | CR_W_RXEN); /* or simply = 0? */
1586 np->imrvalue = 0;
1587 }
1588
1589 break;
1590 }
1591 } while (1);
1592
1593 /* read the tally counters */
1594 /* missed pkts */
1595 dev->stats.rx_missed_errors += ioread32(ioaddr + TALLY) & 0x7fff;
1596
1597 /* crc error */
1598 dev->stats.rx_crc_errors +=
1599 (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16;
1600
1601 if (debug)
1602 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1603 dev->name, ioread32(ioaddr + ISR));
1604
1605 iowrite32(np->imrvalue, ioaddr + IMR);
1606
1607 spin_unlock(&np->lock);
1608
1609 return IRQ_RETVAL(handled);
1610 }
1611
1612
1613 /* This routine is logically part of the interrupt handler, but separated
1614 for clarity and better register allocation. */
1615 static int netdev_rx(struct net_device *dev)
1616 {
1617 struct netdev_private *np = netdev_priv(dev);
1618 void __iomem *ioaddr = np->mem;
1619
1620 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1621 while (!(np->cur_rx->status & RXOWN) && np->cur_rx->skbuff) {
1622 s32 rx_status = np->cur_rx->status;
1623
1624 if (np->really_rx_count == 0)
1625 break;
1626
1627 if (debug)
1628 printk(KERN_DEBUG " netdev_rx() status was %8.8x.\n", rx_status);
1629
1630 if ((!((rx_status & RXFSD) && (rx_status & RXLSD))) ||
1631 (rx_status & ErrorSummary)) {
1632 if (rx_status & ErrorSummary) { /* there was a fatal error */
1633 if (debug)
1634 printk(KERN_DEBUG
1635 "%s: Receive error, Rx status %8.8x.\n",
1636 dev->name, rx_status);
1637
1638 dev->stats.rx_errors++; /* end of a packet. */
1639 if (rx_status & (LONG | RUNT))
1640 dev->stats.rx_length_errors++;
1641 if (rx_status & RXER)
1642 dev->stats.rx_frame_errors++;
1643 if (rx_status & CRC)
1644 dev->stats.rx_crc_errors++;
1645 } else {
1646 int need_to_reset = 0;
1647 int desno = 0;
1648
1649 if (rx_status & RXFSD) { /* this pkt is too long, over one rx buffer */
1650 struct fealnx_desc *cur;
1651
1652 /* check this packet is received completely? */
1653 cur = np->cur_rx;
1654 while (desno <= np->really_rx_count) {
1655 ++desno;
1656 if ((!(cur->status & RXOWN)) &&
1657 (cur->status & RXLSD))
1658 break;
1659 /* goto next rx descriptor */
1660 cur = cur->next_desc_logical;
1661 }
1662 if (desno > np->really_rx_count)
1663 need_to_reset = 1;
1664 } else /* RXLSD did not find, something error */
1665 need_to_reset = 1;
1666
1667 if (need_to_reset == 0) {
1668 int i;
1669
1670 dev->stats.rx_length_errors++;
1671
1672 /* free all rx descriptors related this long pkt */
1673 for (i = 0; i < desno; ++i) {
1674 if (!np->cur_rx->skbuff) {
1675 printk(KERN_DEBUG
1676 "%s: I'm scared\n", dev->name);
1677 break;
1678 }
1679 np->cur_rx->status = RXOWN;
1680 np->cur_rx = np->cur_rx->next_desc_logical;
1681 }
1682 continue;
1683 } else { /* rx error, need to reset this chip */
1684 stop_nic_rx(ioaddr, np->crvalue);
1685 reset_rx_descriptors(dev);
1686 iowrite32(np->crvalue, ioaddr + TCRRCR);
1687 }
1688 break; /* exit the while loop */
1689 }
1690 } else { /* this received pkt is ok */
1691
1692 struct sk_buff *skb;
1693 /* Omit the four octet CRC from the length. */
1694 short pkt_len = ((rx_status & FLNGMASK) >> FLNGShift) - 4;
1695
1696 #ifndef final_version
1697 if (debug)
1698 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d"
1699 " status %x.\n", pkt_len, rx_status);
1700 #endif
1701
1702 /* Check if the packet is long enough to accept without copying
1703 to a minimally-sized skbuff. */
1704 if (pkt_len < rx_copybreak &&
1705 (skb = netdev_alloc_skb(dev, pkt_len + 2)) != NULL) {
1706 skb_reserve(skb, 2); /* 16 byte align the IP header */
1707 pci_dma_sync_single_for_cpu(np->pci_dev,
1708 np->cur_rx->buffer,
1709 np->rx_buf_sz,
1710 PCI_DMA_FROMDEVICE);
1711 /* Call copy + cksum if available. */
1712
1713 #if ! defined(__alpha__)
1714 skb_copy_to_linear_data(skb,
1715 np->cur_rx->skbuff->data, pkt_len);
1716 skb_put(skb, pkt_len);
1717 #else
1718 memcpy(skb_put(skb, pkt_len),
1719 np->cur_rx->skbuff->data, pkt_len);
1720 #endif
1721 pci_dma_sync_single_for_device(np->pci_dev,
1722 np->cur_rx->buffer,
1723 np->rx_buf_sz,
1724 PCI_DMA_FROMDEVICE);
1725 } else {
1726 pci_unmap_single(np->pci_dev,
1727 np->cur_rx->buffer,
1728 np->rx_buf_sz,
1729 PCI_DMA_FROMDEVICE);
1730 skb_put(skb = np->cur_rx->skbuff, pkt_len);
1731 np->cur_rx->skbuff = NULL;
1732 --np->really_rx_count;
1733 }
1734 skb->protocol = eth_type_trans(skb, dev);
1735 netif_rx(skb);
1736 dev->stats.rx_packets++;
1737 dev->stats.rx_bytes += pkt_len;
1738 }
1739
1740 np->cur_rx = np->cur_rx->next_desc_logical;
1741 } /* end of while loop */
1742
1743 /* allocate skb for rx buffers */
1744 allocate_rx_buffers(dev);
1745
1746 return 0;
1747 }
1748
1749
1750 static struct net_device_stats *get_stats(struct net_device *dev)
1751 {
1752 struct netdev_private *np = netdev_priv(dev);
1753 void __iomem *ioaddr = np->mem;
1754
1755 /* The chip only need report frame silently dropped. */
1756 if (netif_running(dev)) {
1757 dev->stats.rx_missed_errors +=
1758 ioread32(ioaddr + TALLY) & 0x7fff;
1759 dev->stats.rx_crc_errors +=
1760 (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16;
1761 }
1762
1763 return &dev->stats;
1764 }
1765
1766
1767 /* for dev->set_multicast_list */
1768 static void set_rx_mode(struct net_device *dev)
1769 {
1770 spinlock_t *lp = &((struct netdev_private *)netdev_priv(dev))->lock;
1771 unsigned long flags;
1772 spin_lock_irqsave(lp, flags);
1773 __set_rx_mode(dev);
1774 spin_unlock_irqrestore(lp, flags);
1775 }
1776
1777
1778 /* Take lock before calling */
1779 static void __set_rx_mode(struct net_device *dev)
1780 {
1781 struct netdev_private *np = netdev_priv(dev);
1782 void __iomem *ioaddr = np->mem;
1783 u32 mc_filter[2]; /* Multicast hash filter */
1784 u32 rx_mode;
1785
1786 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1787 memset(mc_filter, 0xff, sizeof(mc_filter));
1788 rx_mode = CR_W_PROM | CR_W_AB | CR_W_AM;
1789 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
1790 (dev->flags & IFF_ALLMULTI)) {
1791 /* Too many to match, or accept all multicasts. */
1792 memset(mc_filter, 0xff, sizeof(mc_filter));
1793 rx_mode = CR_W_AB | CR_W_AM;
1794 } else {
1795 struct netdev_hw_addr *ha;
1796
1797 memset(mc_filter, 0, sizeof(mc_filter));
1798 netdev_for_each_mc_addr(ha, dev) {
1799 unsigned int bit;
1800 bit = (ether_crc(ETH_ALEN, ha->addr) >> 26) ^ 0x3F;
1801 mc_filter[bit >> 5] |= (1 << bit);
1802 }
1803 rx_mode = CR_W_AB | CR_W_AM;
1804 }
1805
1806 stop_nic_rxtx(ioaddr, np->crvalue);
1807
1808 iowrite32(mc_filter[0], ioaddr + MAR0);
1809 iowrite32(mc_filter[1], ioaddr + MAR1);
1810 np->crvalue &= ~CR_W_RXMODEMASK;
1811 np->crvalue |= rx_mode;
1812 iowrite32(np->crvalue, ioaddr + TCRRCR);
1813 }
1814
1815 static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1816 {
1817 struct netdev_private *np = netdev_priv(dev);
1818
1819 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1820 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1821 strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info));
1822 }
1823
1824 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1825 {
1826 struct netdev_private *np = netdev_priv(dev);
1827 int rc;
1828
1829 spin_lock_irq(&np->lock);
1830 rc = mii_ethtool_gset(&np->mii, cmd);
1831 spin_unlock_irq(&np->lock);
1832
1833 return rc;
1834 }
1835
1836 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1837 {
1838 struct netdev_private *np = netdev_priv(dev);
1839 int rc;
1840
1841 spin_lock_irq(&np->lock);
1842 rc = mii_ethtool_sset(&np->mii, cmd);
1843 spin_unlock_irq(&np->lock);
1844
1845 return rc;
1846 }
1847
1848 static int netdev_nway_reset(struct net_device *dev)
1849 {
1850 struct netdev_private *np = netdev_priv(dev);
1851 return mii_nway_restart(&np->mii);
1852 }
1853
1854 static u32 netdev_get_link(struct net_device *dev)
1855 {
1856 struct netdev_private *np = netdev_priv(dev);
1857 return mii_link_ok(&np->mii);
1858 }
1859
1860 static u32 netdev_get_msglevel(struct net_device *dev)
1861 {
1862 return debug;
1863 }
1864
1865 static void netdev_set_msglevel(struct net_device *dev, u32 value)
1866 {
1867 debug = value;
1868 }
1869
1870 static const struct ethtool_ops netdev_ethtool_ops = {
1871 .get_drvinfo = netdev_get_drvinfo,
1872 .get_settings = netdev_get_settings,
1873 .set_settings = netdev_set_settings,
1874 .nway_reset = netdev_nway_reset,
1875 .get_link = netdev_get_link,
1876 .get_msglevel = netdev_get_msglevel,
1877 .set_msglevel = netdev_set_msglevel,
1878 };
1879
1880 static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1881 {
1882 struct netdev_private *np = netdev_priv(dev);
1883 int rc;
1884
1885 if (!netif_running(dev))
1886 return -EINVAL;
1887
1888 spin_lock_irq(&np->lock);
1889 rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL);
1890 spin_unlock_irq(&np->lock);
1891
1892 return rc;
1893 }
1894
1895
1896 static int netdev_close(struct net_device *dev)
1897 {
1898 struct netdev_private *np = netdev_priv(dev);
1899 void __iomem *ioaddr = np->mem;
1900 int i;
1901
1902 netif_stop_queue(dev);
1903
1904 /* Disable interrupts by clearing the interrupt mask. */
1905 iowrite32(0x0000, ioaddr + IMR);
1906
1907 /* Stop the chip's Tx and Rx processes. */
1908 stop_nic_rxtx(ioaddr, 0);
1909
1910 del_timer_sync(&np->timer);
1911 del_timer_sync(&np->reset_timer);
1912
1913 free_irq(dev->irq, dev);
1914
1915 /* Free all the skbuffs in the Rx queue. */
1916 for (i = 0; i < RX_RING_SIZE; i++) {
1917 struct sk_buff *skb = np->rx_ring[i].skbuff;
1918
1919 np->rx_ring[i].status = 0;
1920 if (skb) {
1921 pci_unmap_single(np->pci_dev, np->rx_ring[i].buffer,
1922 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1923 dev_kfree_skb(skb);
1924 np->rx_ring[i].skbuff = NULL;
1925 }
1926 }
1927
1928 for (i = 0; i < TX_RING_SIZE; i++) {
1929 struct sk_buff *skb = np->tx_ring[i].skbuff;
1930
1931 if (skb) {
1932 pci_unmap_single(np->pci_dev, np->tx_ring[i].buffer,
1933 skb->len, PCI_DMA_TODEVICE);
1934 dev_kfree_skb(skb);
1935 np->tx_ring[i].skbuff = NULL;
1936 }
1937 }
1938
1939 return 0;
1940 }
1941
1942 static DEFINE_PCI_DEVICE_TABLE(fealnx_pci_tbl) = {
1943 {0x1516, 0x0800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1944 {0x1516, 0x0803, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1945 {0x1516, 0x0891, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1946 {} /* terminate list */
1947 };
1948 MODULE_DEVICE_TABLE(pci, fealnx_pci_tbl);
1949
1950
1951 static struct pci_driver fealnx_driver = {
1952 .name = "fealnx",
1953 .id_table = fealnx_pci_tbl,
1954 .probe = fealnx_init_one,
1955 .remove = __devexit_p(fealnx_remove_one),
1956 };
1957
1958 static int __init fealnx_init(void)
1959 {
1960 /* when a module, this is printed whether or not devices are found in probe */
1961 #ifdef MODULE
1962 printk(version);
1963 #endif
1964
1965 return pci_register_driver(&fealnx_driver);
1966 }
1967
1968 static void __exit fealnx_exit(void)
1969 {
1970 pci_unregister_driver(&fealnx_driver);
1971 }
1972
1973 module_init(fealnx_init);
1974 module_exit(fealnx_exit);
Linux with added FPC-III support