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Linux 3.4.102
[linux/fpc-iii.git] / drivers / net / ethernet / freescale / gianfar.c
blobd5de9a474aeabd0ca6f2955ce5f47ae5fb1f13a3
1 /*
2 * drivers/net/ethernet/freescale/gianfar.c
3 *
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
8 *
9 * Author: Andy Fleming
10 * Maintainer: Kumar Gala
11 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
12 *
13 * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc.
14 * Copyright 2007 MontaVista Software, Inc.
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
20 *
21 * Gianfar: AKA Lambda Draconis, "Dragon"
22 * RA 11 31 24.2
23 * Dec +69 19 52
24 * V 3.84
25 * B-V +1.62
26 *
27 * Theory of operation
28 *
29 * The driver is initialized through of_device. Configuration information
30 * is therefore conveyed through an OF-style device tree.
31 *
32 * The Gianfar Ethernet Controller uses a ring of buffer
33 * descriptors. The beginning is indicated by a register
34 * pointing to the physical address of the start of the ring.
35 * The end is determined by a "wrap" bit being set in the
36 * last descriptor of the ring.
37 *
38 * When a packet is received, the RXF bit in the
39 * IEVENT register is set, triggering an interrupt when the
40 * corresponding bit in the IMASK register is also set (if
41 * interrupt coalescing is active, then the interrupt may not
42 * happen immediately, but will wait until either a set number
43 * of frames or amount of time have passed). In NAPI, the
44 * interrupt handler will signal there is work to be done, and
45 * exit. This method will start at the last known empty
46 * descriptor, and process every subsequent descriptor until there
47 * are none left with data (NAPI will stop after a set number of
48 * packets to give time to other tasks, but will eventually
49 * process all the packets). The data arrives inside a
50 * pre-allocated skb, and so after the skb is passed up to the
51 * stack, a new skb must be allocated, and the address field in
52 * the buffer descriptor must be updated to indicate this new
53 * skb.
54 *
55 * When the kernel requests that a packet be transmitted, the
56 * driver starts where it left off last time, and points the
57 * descriptor at the buffer which was passed in. The driver
58 * then informs the DMA engine that there are packets ready to
59 * be transmitted. Once the controller is finished transmitting
60 * the packet, an interrupt may be triggered (under the same
61 * conditions as for reception, but depending on the TXF bit).
62 * The driver then cleans up the buffer.
63 */
64
65 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
66 #define DEBUG
67
68 #include <linux/kernel.h>
69 #include <linux/string.h>
70 #include <linux/errno.h>
71 #include <linux/unistd.h>
72 #include <linux/slab.h>
73 #include <linux/interrupt.h>
74 #include <linux/init.h>
75 #include <linux/delay.h>
76 #include <linux/netdevice.h>
77 #include <linux/etherdevice.h>
78 #include <linux/skbuff.h>
79 #include <linux/if_vlan.h>
80 #include <linux/spinlock.h>
81 #include <linux/mm.h>
82 #include <linux/of_mdio.h>
83 #include <linux/of_platform.h>
84 #include <linux/ip.h>
85 #include <linux/tcp.h>
86 #include <linux/udp.h>
87 #include <linux/in.h>
88 #include <linux/net_tstamp.h>
89
90 #include <asm/io.h>
91 #include <asm/reg.h>
92 #include <asm/irq.h>
93 #include <asm/uaccess.h>
94 #include <linux/module.h>
95 #include <linux/dma-mapping.h>
96 #include <linux/crc32.h>
97 #include <linux/mii.h>
98 #include <linux/phy.h>
99 #include <linux/phy_fixed.h>
100 #include <linux/of.h>
101 #include <linux/of_net.h>
102
103 #include "gianfar.h"
104 #include "fsl_pq_mdio.h"
105
106 #define TX_TIMEOUT (1*HZ)
107
108 const char gfar_driver_version[] = "1.3";
109
110 static int gfar_enet_open(struct net_device *dev);
111 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
112 static void gfar_reset_task(struct work_struct *work);
113 static void gfar_timeout(struct net_device *dev);
114 static int gfar_close(struct net_device *dev);
115 struct sk_buff *gfar_new_skb(struct net_device *dev);
116 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
117 struct sk_buff *skb);
118 static int gfar_set_mac_address(struct net_device *dev);
119 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
120 static irqreturn_t gfar_error(int irq, void *dev_id);
121 static irqreturn_t gfar_transmit(int irq, void *dev_id);
122 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
123 static void adjust_link(struct net_device *dev);
124 static void init_registers(struct net_device *dev);
125 static int init_phy(struct net_device *dev);
126 static int gfar_probe(struct platform_device *ofdev);
127 static int gfar_remove(struct platform_device *ofdev);
128 static void free_skb_resources(struct gfar_private *priv);
129 static void gfar_set_multi(struct net_device *dev);
130 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
131 static void gfar_configure_serdes(struct net_device *dev);
132 static int gfar_poll(struct napi_struct *napi, int budget);
133 #ifdef CONFIG_NET_POLL_CONTROLLER
134 static void gfar_netpoll(struct net_device *dev);
135 #endif
136 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
137 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
138 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
139 int amount_pull);
140 void gfar_halt(struct net_device *dev);
141 static void gfar_halt_nodisable(struct net_device *dev);
142 void gfar_start(struct net_device *dev);
143 static void gfar_clear_exact_match(struct net_device *dev);
144 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
145 const u8 *addr);
146 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
147
148 MODULE_AUTHOR("Freescale Semiconductor, Inc");
149 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
150 MODULE_LICENSE("GPL");
151
152 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
153 dma_addr_t buf)
154 {
155 u32 lstatus;
156
157 bdp->bufPtr = buf;
158
159 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
160 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
161 lstatus |= BD_LFLAG(RXBD_WRAP);
162
163 eieio();
164
165 bdp->lstatus = lstatus;
166 }
167
168 static int gfar_init_bds(struct net_device *ndev)
169 {
170 struct gfar_private *priv = netdev_priv(ndev);
171 struct gfar_priv_tx_q *tx_queue = NULL;
172 struct gfar_priv_rx_q *rx_queue = NULL;
173 struct txbd8 *txbdp;
174 struct rxbd8 *rxbdp;
175 int i, j;
176
177 for (i = 0; i < priv->num_tx_queues; i++) {
178 tx_queue = priv->tx_queue[i];
179 /* Initialize some variables in our dev structure */
180 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
181 tx_queue->dirty_tx = tx_queue->tx_bd_base;
182 tx_queue->cur_tx = tx_queue->tx_bd_base;
183 tx_queue->skb_curtx = 0;
184 tx_queue->skb_dirtytx = 0;
185
186 /* Initialize Transmit Descriptor Ring */
187 txbdp = tx_queue->tx_bd_base;
188 for (j = 0; j < tx_queue->tx_ring_size; j++) {
189 txbdp->lstatus = 0;
190 txbdp->bufPtr = 0;
191 txbdp++;
192 }
193
194 /* Set the last descriptor in the ring to indicate wrap */
195 txbdp--;
196 txbdp->status |= TXBD_WRAP;
197 }
198
199 for (i = 0; i < priv->num_rx_queues; i++) {
200 rx_queue = priv->rx_queue[i];
201 rx_queue->cur_rx = rx_queue->rx_bd_base;
202 rx_queue->skb_currx = 0;
203 rxbdp = rx_queue->rx_bd_base;
204
205 for (j = 0; j < rx_queue->rx_ring_size; j++) {
206 struct sk_buff *skb = rx_queue->rx_skbuff[j];
207
208 if (skb) {
209 gfar_init_rxbdp(rx_queue, rxbdp,
210 rxbdp->bufPtr);
211 } else {
212 skb = gfar_new_skb(ndev);
213 if (!skb) {
214 netdev_err(ndev, "Can't allocate RX buffers\n");
215 goto err_rxalloc_fail;
216 }
217 rx_queue->rx_skbuff[j] = skb;
218
219 gfar_new_rxbdp(rx_queue, rxbdp, skb);
220 }
221
222 rxbdp++;
223 }
224
225 }
226
227 return 0;
228
229 err_rxalloc_fail:
230 free_skb_resources(priv);
231 return -ENOMEM;
232 }
233
234 static int gfar_alloc_skb_resources(struct net_device *ndev)
235 {
236 void *vaddr;
237 dma_addr_t addr;
238 int i, j, k;
239 struct gfar_private *priv = netdev_priv(ndev);
240 struct device *dev = &priv->ofdev->dev;
241 struct gfar_priv_tx_q *tx_queue = NULL;
242 struct gfar_priv_rx_q *rx_queue = NULL;
243
244 priv->total_tx_ring_size = 0;
245 for (i = 0; i < priv->num_tx_queues; i++)
246 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
247
248 priv->total_rx_ring_size = 0;
249 for (i = 0; i < priv->num_rx_queues; i++)
250 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
251
252 /* Allocate memory for the buffer descriptors */
253 vaddr = dma_alloc_coherent(dev,
254 sizeof(struct txbd8) * priv->total_tx_ring_size +
255 sizeof(struct rxbd8) * priv->total_rx_ring_size,
256 &addr, GFP_KERNEL);
257 if (!vaddr) {
258 netif_err(priv, ifup, ndev,
259 "Could not allocate buffer descriptors!\n");
260 return -ENOMEM;
261 }
262
263 for (i = 0; i < priv->num_tx_queues; i++) {
264 tx_queue = priv->tx_queue[i];
265 tx_queue->tx_bd_base = vaddr;
266 tx_queue->tx_bd_dma_base = addr;
267 tx_queue->dev = ndev;
268 /* enet DMA only understands physical addresses */
269 addr += sizeof(struct txbd8) *tx_queue->tx_ring_size;
270 vaddr += sizeof(struct txbd8) *tx_queue->tx_ring_size;
271 }
272
273 /* Start the rx descriptor ring where the tx ring leaves off */
274 for (i = 0; i < priv->num_rx_queues; i++) {
275 rx_queue = priv->rx_queue[i];
276 rx_queue->rx_bd_base = vaddr;
277 rx_queue->rx_bd_dma_base = addr;
278 rx_queue->dev = ndev;
279 addr += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
280 vaddr += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
281 }
282
283 /* Setup the skbuff rings */
284 for (i = 0; i < priv->num_tx_queues; i++) {
285 tx_queue = priv->tx_queue[i];
286 tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) *
287 tx_queue->tx_ring_size, GFP_KERNEL);
288 if (!tx_queue->tx_skbuff) {
289 netif_err(priv, ifup, ndev,
290 "Could not allocate tx_skbuff\n");
291 goto cleanup;
292 }
293
294 for (k = 0; k < tx_queue->tx_ring_size; k++)
295 tx_queue->tx_skbuff[k] = NULL;
296 }
297
298 for (i = 0; i < priv->num_rx_queues; i++) {
299 rx_queue = priv->rx_queue[i];
300 rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) *
301 rx_queue->rx_ring_size, GFP_KERNEL);
302
303 if (!rx_queue->rx_skbuff) {
304 netif_err(priv, ifup, ndev,
305 "Could not allocate rx_skbuff\n");
306 goto cleanup;
307 }
308
309 for (j = 0; j < rx_queue->rx_ring_size; j++)
310 rx_queue->rx_skbuff[j] = NULL;
311 }
312
313 if (gfar_init_bds(ndev))
314 goto cleanup;
315
316 return 0;
317
318 cleanup:
319 free_skb_resources(priv);
320 return -ENOMEM;
321 }
322
323 static void gfar_init_tx_rx_base(struct gfar_private *priv)
324 {
325 struct gfar __iomem *regs = priv->gfargrp[0].regs;
326 u32 __iomem *baddr;
327 int i;
328
329 baddr = &regs->tbase0;
330 for(i = 0; i < priv->num_tx_queues; i++) {
331 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
332 baddr += 2;
333 }
334
335 baddr = &regs->rbase0;
336 for(i = 0; i < priv->num_rx_queues; i++) {
337 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
338 baddr += 2;
339 }
340 }
341
342 static void gfar_init_mac(struct net_device *ndev)
343 {
344 struct gfar_private *priv = netdev_priv(ndev);
345 struct gfar __iomem *regs = priv->gfargrp[0].regs;
346 u32 rctrl = 0;
347 u32 tctrl = 0;
348 u32 attrs = 0;
349
350 /* write the tx/rx base registers */
351 gfar_init_tx_rx_base(priv);
352
353 /* Configure the coalescing support */
354 gfar_configure_coalescing(priv, 0xFF, 0xFF);
355
356 if (priv->rx_filer_enable) {
357 rctrl |= RCTRL_FILREN;
358 /* Program the RIR0 reg with the required distribution */
359 gfar_write(&regs->rir0, DEFAULT_RIR0);
360 }
361
362 if (ndev->features & NETIF_F_RXCSUM)
363 rctrl |= RCTRL_CHECKSUMMING;
364
365 if (priv->extended_hash) {
366 rctrl |= RCTRL_EXTHASH;
367
368 gfar_clear_exact_match(ndev);
369 rctrl |= RCTRL_EMEN;
370 }
371
372 if (priv->padding) {
373 rctrl &= ~RCTRL_PAL_MASK;
374 rctrl |= RCTRL_PADDING(priv->padding);
375 }
376
377 /* Insert receive time stamps into padding alignment bytes */
378 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
379 rctrl &= ~RCTRL_PAL_MASK;
380 rctrl |= RCTRL_PADDING(8);
381 priv->padding = 8;
382 }
383
384 /* Enable HW time stamping if requested from user space */
385 if (priv->hwts_rx_en)
386 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
387
388 if (ndev->features & NETIF_F_HW_VLAN_RX)
389 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
390
391 /* Init rctrl based on our settings */
392 gfar_write(&regs->rctrl, rctrl);
393
394 if (ndev->features & NETIF_F_IP_CSUM)
395 tctrl |= TCTRL_INIT_CSUM;
396
397 if (priv->prio_sched_en)
398 tctrl |= TCTRL_TXSCHED_PRIO;
399 else {
400 tctrl |= TCTRL_TXSCHED_WRRS;
401 gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
402 gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
403 }
404
405 gfar_write(&regs->tctrl, tctrl);
406
407 /* Set the extraction length and index */
408 attrs = ATTRELI_EL(priv->rx_stash_size) |
409 ATTRELI_EI(priv->rx_stash_index);
410
411 gfar_write(&regs->attreli, attrs);
412
413 /* Start with defaults, and add stashing or locking
414 * depending on the approprate variables */
415 attrs = ATTR_INIT_SETTINGS;
416
417 if (priv->bd_stash_en)
418 attrs |= ATTR_BDSTASH;
419
420 if (priv->rx_stash_size != 0)
421 attrs |= ATTR_BUFSTASH;
422
423 gfar_write(&regs->attr, attrs);
424
425 gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
426 gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
427 gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
428 }
429
430 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
431 {
432 struct gfar_private *priv = netdev_priv(dev);
433 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
434 unsigned long tx_packets = 0, tx_bytes = 0;
435 int i = 0;
436
437 for (i = 0; i < priv->num_rx_queues; i++) {
438 rx_packets += priv->rx_queue[i]->stats.rx_packets;
439 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
440 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
441 }
442
443 dev->stats.rx_packets = rx_packets;
444 dev->stats.rx_bytes = rx_bytes;
445 dev->stats.rx_dropped = rx_dropped;
446
447 for (i = 0; i < priv->num_tx_queues; i++) {
448 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
449 tx_packets += priv->tx_queue[i]->stats.tx_packets;
450 }
451
452 dev->stats.tx_bytes = tx_bytes;
453 dev->stats.tx_packets = tx_packets;
454
455 return &dev->stats;
456 }
457
458 static const struct net_device_ops gfar_netdev_ops = {
459 .ndo_open = gfar_enet_open,
460 .ndo_start_xmit = gfar_start_xmit,
461 .ndo_stop = gfar_close,
462 .ndo_change_mtu = gfar_change_mtu,
463 .ndo_set_features = gfar_set_features,
464 .ndo_set_rx_mode = gfar_set_multi,
465 .ndo_tx_timeout = gfar_timeout,
466 .ndo_do_ioctl = gfar_ioctl,
467 .ndo_get_stats = gfar_get_stats,
468 .ndo_set_mac_address = eth_mac_addr,
469 .ndo_validate_addr = eth_validate_addr,
470 #ifdef CONFIG_NET_POLL_CONTROLLER
471 .ndo_poll_controller = gfar_netpoll,
472 #endif
473 };
474
475 void lock_rx_qs(struct gfar_private *priv)
476 {
477 int i = 0x0;
478
479 for (i = 0; i < priv->num_rx_queues; i++)
480 spin_lock(&priv->rx_queue[i]->rxlock);
481 }
482
483 void lock_tx_qs(struct gfar_private *priv)
484 {
485 int i = 0x0;
486
487 for (i = 0; i < priv->num_tx_queues; i++)
488 spin_lock(&priv->tx_queue[i]->txlock);
489 }
490
491 void unlock_rx_qs(struct gfar_private *priv)
492 {
493 int i = 0x0;
494
495 for (i = 0; i < priv->num_rx_queues; i++)
496 spin_unlock(&priv->rx_queue[i]->rxlock);
497 }
498
499 void unlock_tx_qs(struct gfar_private *priv)
500 {
501 int i = 0x0;
502
503 for (i = 0; i < priv->num_tx_queues; i++)
504 spin_unlock(&priv->tx_queue[i]->txlock);
505 }
506
507 static bool gfar_is_vlan_on(struct gfar_private *priv)
508 {
509 return (priv->ndev->features & NETIF_F_HW_VLAN_RX) ||
510 (priv->ndev->features & NETIF_F_HW_VLAN_TX);
511 }
512
513 /* Returns 1 if incoming frames use an FCB */
514 static inline int gfar_uses_fcb(struct gfar_private *priv)
515 {
516 return gfar_is_vlan_on(priv) ||
517 (priv->ndev->features & NETIF_F_RXCSUM) ||
518 (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER);
519 }
520
521 static void free_tx_pointers(struct gfar_private *priv)
522 {
523 int i = 0;
524
525 for (i = 0; i < priv->num_tx_queues; i++)
526 kfree(priv->tx_queue[i]);
527 }
528
529 static void free_rx_pointers(struct gfar_private *priv)
530 {
531 int i = 0;
532
533 for (i = 0; i < priv->num_rx_queues; i++)
534 kfree(priv->rx_queue[i]);
535 }
536
537 static void unmap_group_regs(struct gfar_private *priv)
538 {
539 int i = 0;
540
541 for (i = 0; i < MAXGROUPS; i++)
542 if (priv->gfargrp[i].regs)
543 iounmap(priv->gfargrp[i].regs);
544 }
545
546 static void disable_napi(struct gfar_private *priv)
547 {
548 int i = 0;
549
550 for (i = 0; i < priv->num_grps; i++)
551 napi_disable(&priv->gfargrp[i].napi);
552 }
553
554 static void enable_napi(struct gfar_private *priv)
555 {
556 int i = 0;
557
558 for (i = 0; i < priv->num_grps; i++)
559 napi_enable(&priv->gfargrp[i].napi);
560 }
561
562 static int gfar_parse_group(struct device_node *np,
563 struct gfar_private *priv, const char *model)
564 {
565 u32 *queue_mask;
566
567 priv->gfargrp[priv->num_grps].regs = of_iomap(np, 0);
568 if (!priv->gfargrp[priv->num_grps].regs)
569 return -ENOMEM;
570
571 priv->gfargrp[priv->num_grps].interruptTransmit =
572 irq_of_parse_and_map(np, 0);
573
574 /* If we aren't the FEC we have multiple interrupts */
575 if (model && strcasecmp(model, "FEC")) {
576 priv->gfargrp[priv->num_grps].interruptReceive =
577 irq_of_parse_and_map(np, 1);
578 priv->gfargrp[priv->num_grps].interruptError =
579 irq_of_parse_and_map(np,2);
580 if (priv->gfargrp[priv->num_grps].interruptTransmit == NO_IRQ ||
581 priv->gfargrp[priv->num_grps].interruptReceive == NO_IRQ ||
582 priv->gfargrp[priv->num_grps].interruptError == NO_IRQ)
583 return -EINVAL;
584 }
585
586 priv->gfargrp[priv->num_grps].grp_id = priv->num_grps;
587 priv->gfargrp[priv->num_grps].priv = priv;
588 spin_lock_init(&priv->gfargrp[priv->num_grps].grplock);
589 if(priv->mode == MQ_MG_MODE) {
590 queue_mask = (u32 *)of_get_property(np,
591 "fsl,rx-bit-map", NULL);
592 priv->gfargrp[priv->num_grps].rx_bit_map =
593 queue_mask ? *queue_mask :(DEFAULT_MAPPING >> priv->num_grps);
594 queue_mask = (u32 *)of_get_property(np,
595 "fsl,tx-bit-map", NULL);
596 priv->gfargrp[priv->num_grps].tx_bit_map =
597 queue_mask ? *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
598 } else {
599 priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF;
600 priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF;
601 }
602 priv->num_grps++;
603
604 return 0;
605 }
606
607 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
608 {
609 const char *model;
610 const char *ctype;
611 const void *mac_addr;
612 int err = 0, i;
613 struct net_device *dev = NULL;
614 struct gfar_private *priv = NULL;
615 struct device_node *np = ofdev->dev.of_node;
616 struct device_node *child = NULL;
617 const u32 *stash;
618 const u32 *stash_len;
619 const u32 *stash_idx;
620 unsigned int num_tx_qs, num_rx_qs;
621 u32 *tx_queues, *rx_queues;
622
623 if (!np || !of_device_is_available(np))
624 return -ENODEV;
625
626 /* parse the num of tx and rx queues */
627 tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
628 num_tx_qs = tx_queues ? *tx_queues : 1;
629
630 if (num_tx_qs > MAX_TX_QS) {
631 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
632 num_tx_qs, MAX_TX_QS);
633 pr_err("Cannot do alloc_etherdev, aborting\n");
634 return -EINVAL;
635 }
636
637 rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
638 num_rx_qs = rx_queues ? *rx_queues : 1;
639
640 if (num_rx_qs > MAX_RX_QS) {
641 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
642 num_rx_qs, MAX_RX_QS);
643 pr_err("Cannot do alloc_etherdev, aborting\n");
644 return -EINVAL;
645 }
646
647 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
648 dev = *pdev;
649 if (NULL == dev)
650 return -ENOMEM;
651
652 priv = netdev_priv(dev);
653 priv->node = ofdev->dev.of_node;
654 priv->ndev = dev;
655
656 priv->num_tx_queues = num_tx_qs;
657 netif_set_real_num_rx_queues(dev, num_rx_qs);
658 priv->num_rx_queues = num_rx_qs;
659 priv->num_grps = 0x0;
660
661 /* Init Rx queue filer rule set linked list*/
662 INIT_LIST_HEAD(&priv->rx_list.list);
663 priv->rx_list.count = 0;
664 mutex_init(&priv->rx_queue_access);
665
666 model = of_get_property(np, "model", NULL);
667
668 for (i = 0; i < MAXGROUPS; i++)
669 priv->gfargrp[i].regs = NULL;
670
671 /* Parse and initialize group specific information */
672 if (of_device_is_compatible(np, "fsl,etsec2")) {
673 priv->mode = MQ_MG_MODE;
674 for_each_child_of_node(np, child) {
675 err = gfar_parse_group(child, priv, model);
676 if (err)
677 goto err_grp_init;
678 }
679 } else {
680 priv->mode = SQ_SG_MODE;
681 err = gfar_parse_group(np, priv, model);
682 if(err)
683 goto err_grp_init;
684 }
685
686 for (i = 0; i < priv->num_tx_queues; i++)
687 priv->tx_queue[i] = NULL;
688 for (i = 0; i < priv->num_rx_queues; i++)
689 priv->rx_queue[i] = NULL;
690
691 for (i = 0; i < priv->num_tx_queues; i++) {
692 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
693 GFP_KERNEL);
694 if (!priv->tx_queue[i]) {
695 err = -ENOMEM;
696 goto tx_alloc_failed;
697 }
698 priv->tx_queue[i]->tx_skbuff = NULL;
699 priv->tx_queue[i]->qindex = i;
700 priv->tx_queue[i]->dev = dev;
701 spin_lock_init(&(priv->tx_queue[i]->txlock));
702 }
703
704 for (i = 0; i < priv->num_rx_queues; i++) {
705 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
706 GFP_KERNEL);
707 if (!priv->rx_queue[i]) {
708 err = -ENOMEM;
709 goto rx_alloc_failed;
710 }
711 priv->rx_queue[i]->rx_skbuff = NULL;
712 priv->rx_queue[i]->qindex = i;
713 priv->rx_queue[i]->dev = dev;
714 spin_lock_init(&(priv->rx_queue[i]->rxlock));
715 }
716
717
718 stash = of_get_property(np, "bd-stash", NULL);
719
720 if (stash) {
721 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
722 priv->bd_stash_en = 1;
723 }
724
725 stash_len = of_get_property(np, "rx-stash-len", NULL);
726
727 if (stash_len)
728 priv->rx_stash_size = *stash_len;
729
730 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
731
732 if (stash_idx)
733 priv->rx_stash_index = *stash_idx;
734
735 if (stash_len || stash_idx)
736 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
737
738 mac_addr = of_get_mac_address(np);
739 if (mac_addr)
740 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
741
742 if (model && !strcasecmp(model, "TSEC"))
743 priv->device_flags =
744 FSL_GIANFAR_DEV_HAS_GIGABIT |
745 FSL_GIANFAR_DEV_HAS_COALESCE |
746 FSL_GIANFAR_DEV_HAS_RMON |
747 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
748 if (model && !strcasecmp(model, "eTSEC"))
749 priv->device_flags =
750 FSL_GIANFAR_DEV_HAS_GIGABIT |
751 FSL_GIANFAR_DEV_HAS_COALESCE |
752 FSL_GIANFAR_DEV_HAS_RMON |
753 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
754 FSL_GIANFAR_DEV_HAS_PADDING |
755 FSL_GIANFAR_DEV_HAS_CSUM |
756 FSL_GIANFAR_DEV_HAS_VLAN |
757 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
758 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
759 FSL_GIANFAR_DEV_HAS_TIMER;
760
761 ctype = of_get_property(np, "phy-connection-type", NULL);
762
763 /* We only care about rgmii-id. The rest are autodetected */
764 if (ctype && !strcmp(ctype, "rgmii-id"))
765 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
766 else
767 priv->interface = PHY_INTERFACE_MODE_MII;
768
769 if (of_get_property(np, "fsl,magic-packet", NULL))
770 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
771
772 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
773
774 /* Find the TBI PHY. If it's not there, we don't support SGMII */
775 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
776
777 return 0;
778
779 rx_alloc_failed:
780 free_rx_pointers(priv);
781 tx_alloc_failed:
782 free_tx_pointers(priv);
783 err_grp_init:
784 unmap_group_regs(priv);
785 free_netdev(dev);
786 return err;
787 }
788
789 static int gfar_hwtstamp_ioctl(struct net_device *netdev,
790 struct ifreq *ifr, int cmd)
791 {
792 struct hwtstamp_config config;
793 struct gfar_private *priv = netdev_priv(netdev);
794
795 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
796 return -EFAULT;
797
798 /* reserved for future extensions */
799 if (config.flags)
800 return -EINVAL;
801
802 switch (config.tx_type) {
803 case HWTSTAMP_TX_OFF:
804 priv->hwts_tx_en = 0;
805 break;
806 case HWTSTAMP_TX_ON:
807 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
808 return -ERANGE;
809 priv->hwts_tx_en = 1;
810 break;
811 default:
812 return -ERANGE;
813 }
814
815 switch (config.rx_filter) {
816 case HWTSTAMP_FILTER_NONE:
817 if (priv->hwts_rx_en) {
818 stop_gfar(netdev);
819 priv->hwts_rx_en = 0;
820 startup_gfar(netdev);
821 }
822 break;
823 default:
824 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
825 return -ERANGE;
826 if (!priv->hwts_rx_en) {
827 stop_gfar(netdev);
828 priv->hwts_rx_en = 1;
829 startup_gfar(netdev);
830 }
831 config.rx_filter = HWTSTAMP_FILTER_ALL;
832 break;
833 }
834
835 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
836 -EFAULT : 0;
837 }
838
839 /* Ioctl MII Interface */
840 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
841 {
842 struct gfar_private *priv = netdev_priv(dev);
843
844 if (!netif_running(dev))
845 return -EINVAL;
846
847 if (cmd == SIOCSHWTSTAMP)
848 return gfar_hwtstamp_ioctl(dev, rq, cmd);
849
850 if (!priv->phydev)
851 return -ENODEV;
852
853 return phy_mii_ioctl(priv->phydev, rq, cmd);
854 }
855
856 static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
857 {
858 unsigned int new_bit_map = 0x0;
859 int mask = 0x1 << (max_qs - 1), i;
860 for (i = 0; i < max_qs; i++) {
861 if (bit_map & mask)
862 new_bit_map = new_bit_map + (1 << i);
863 mask = mask >> 0x1;
864 }
865 return new_bit_map;
866 }
867
868 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
869 u32 class)
870 {
871 u32 rqfpr = FPR_FILER_MASK;
872 u32 rqfcr = 0x0;
873
874 rqfar--;
875 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
876 priv->ftp_rqfpr[rqfar] = rqfpr;
877 priv->ftp_rqfcr[rqfar] = rqfcr;
878 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
879
880 rqfar--;
881 rqfcr = RQFCR_CMP_NOMATCH;
882 priv->ftp_rqfpr[rqfar] = rqfpr;
883 priv->ftp_rqfcr[rqfar] = rqfcr;
884 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
885
886 rqfar--;
887 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
888 rqfpr = class;
889 priv->ftp_rqfcr[rqfar] = rqfcr;
890 priv->ftp_rqfpr[rqfar] = rqfpr;
891 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
892
893 rqfar--;
894 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
895 rqfpr = class;
896 priv->ftp_rqfcr[rqfar] = rqfcr;
897 priv->ftp_rqfpr[rqfar] = rqfpr;
898 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
899
900 return rqfar;
901 }
902
903 static void gfar_init_filer_table(struct gfar_private *priv)
904 {
905 int i = 0x0;
906 u32 rqfar = MAX_FILER_IDX;
907 u32 rqfcr = 0x0;
908 u32 rqfpr = FPR_FILER_MASK;
909
910 /* Default rule */
911 rqfcr = RQFCR_CMP_MATCH;
912 priv->ftp_rqfcr[rqfar] = rqfcr;
913 priv->ftp_rqfpr[rqfar] = rqfpr;
914 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
915
916 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
917 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
918 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
919 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
920 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
921 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
922
923 /* cur_filer_idx indicated the first non-masked rule */
924 priv->cur_filer_idx = rqfar;
925
926 /* Rest are masked rules */
927 rqfcr = RQFCR_CMP_NOMATCH;
928 for (i = 0; i < rqfar; i++) {
929 priv->ftp_rqfcr[i] = rqfcr;
930 priv->ftp_rqfpr[i] = rqfpr;
931 gfar_write_filer(priv, i, rqfcr, rqfpr);
932 }
933 }
934
935 static void gfar_detect_errata(struct gfar_private *priv)
936 {
937 struct device *dev = &priv->ofdev->dev;
938 unsigned int pvr = mfspr(SPRN_PVR);
939 unsigned int svr = mfspr(SPRN_SVR);
940 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
941 unsigned int rev = svr & 0xffff;
942
943 /* MPC8313 Rev 2.0 and higher; All MPC837x */
944 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
945 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
946 priv->errata |= GFAR_ERRATA_74;
947
948 /* MPC8313 and MPC837x all rev */
949 if ((pvr == 0x80850010 && mod == 0x80b0) ||
950 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
951 priv->errata |= GFAR_ERRATA_76;
952
953 /* MPC8313 and MPC837x all rev */
954 if ((pvr == 0x80850010 && mod == 0x80b0) ||
955 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
956 priv->errata |= GFAR_ERRATA_A002;
957
958 /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */
959 if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) ||
960 (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020))
961 priv->errata |= GFAR_ERRATA_12;
962
963 if (priv->errata)
964 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
965 priv->errata);
966 }
967
968 /* Set up the ethernet device structure, private data,
969 * and anything else we need before we start */
970 static int gfar_probe(struct platform_device *ofdev)
971 {
972 u32 tempval;
973 struct net_device *dev = NULL;
974 struct gfar_private *priv = NULL;
975 struct gfar __iomem *regs = NULL;
976 int err = 0, i, grp_idx = 0;
977 u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
978 u32 isrg = 0;
979 u32 __iomem *baddr;
980
981 err = gfar_of_init(ofdev, &dev);
982
983 if (err)
984 return err;
985
986 priv = netdev_priv(dev);
987 priv->ndev = dev;
988 priv->ofdev = ofdev;
989 priv->node = ofdev->dev.of_node;
990 SET_NETDEV_DEV(dev, &ofdev->dev);
991
992 spin_lock_init(&priv->bflock);
993 INIT_WORK(&priv->reset_task, gfar_reset_task);
994
995 dev_set_drvdata(&ofdev->dev, priv);
996 regs = priv->gfargrp[0].regs;
997
998 gfar_detect_errata(priv);
999
1000 /* Stop the DMA engine now, in case it was running before */
1001 /* (The firmware could have used it, and left it running). */
1002 gfar_halt(dev);
1003
1004 /* Reset MAC layer */
1005 gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1006
1007 /* We need to delay at least 3 TX clocks */
1008 udelay(2);
1009
1010 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
1011 gfar_write(&regs->maccfg1, tempval);
1012
1013 /* Initialize MACCFG2. */
1014 tempval = MACCFG2_INIT_SETTINGS;
1015 if (gfar_has_errata(priv, GFAR_ERRATA_74))
1016 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1017 gfar_write(&regs->maccfg2, tempval);
1018
1019 /* Initialize ECNTRL */
1020 gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1021
1022 /* Set the dev->base_addr to the gfar reg region */
1023 dev->base_addr = (unsigned long) regs;
1024
1025 SET_NETDEV_DEV(dev, &ofdev->dev);
1026
1027 /* Fill in the dev structure */
1028 dev->watchdog_timeo = TX_TIMEOUT;
1029 dev->mtu = 1500;
1030 dev->netdev_ops = &gfar_netdev_ops;
1031 dev->ethtool_ops = &gfar_ethtool_ops;
1032
1033 /* Register for napi ...We are registering NAPI for each grp */
1034 for (i = 0; i < priv->num_grps; i++)
1035 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, GFAR_DEV_WEIGHT);
1036
1037 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1038 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1039 NETIF_F_RXCSUM;
1040 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1041 NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1042 }
1043
1044 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1045 dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1046 dev->features |= NETIF_F_HW_VLAN_RX;
1047 }
1048
1049 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1050 priv->extended_hash = 1;
1051 priv->hash_width = 9;
1052
1053 priv->hash_regs[0] = &regs->igaddr0;
1054 priv->hash_regs[1] = &regs->igaddr1;
1055 priv->hash_regs[2] = &regs->igaddr2;
1056 priv->hash_regs[3] = &regs->igaddr3;
1057 priv->hash_regs[4] = &regs->igaddr4;
1058 priv->hash_regs[5] = &regs->igaddr5;
1059 priv->hash_regs[6] = &regs->igaddr6;
1060 priv->hash_regs[7] = &regs->igaddr7;
1061 priv->hash_regs[8] = &regs->gaddr0;
1062 priv->hash_regs[9] = &regs->gaddr1;
1063 priv->hash_regs[10] = &regs->gaddr2;
1064 priv->hash_regs[11] = &regs->gaddr3;
1065 priv->hash_regs[12] = &regs->gaddr4;
1066 priv->hash_regs[13] = &regs->gaddr5;
1067 priv->hash_regs[14] = &regs->gaddr6;
1068 priv->hash_regs[15] = &regs->gaddr7;
1069
1070 } else {
1071 priv->extended_hash = 0;
1072 priv->hash_width = 8;
1073
1074 priv->hash_regs[0] = &regs->gaddr0;
1075 priv->hash_regs[1] = &regs->gaddr1;
1076 priv->hash_regs[2] = &regs->gaddr2;
1077 priv->hash_regs[3] = &regs->gaddr3;
1078 priv->hash_regs[4] = &regs->gaddr4;
1079 priv->hash_regs[5] = &regs->gaddr5;
1080 priv->hash_regs[6] = &regs->gaddr6;
1081 priv->hash_regs[7] = &regs->gaddr7;
1082 }
1083
1084 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
1085 priv->padding = DEFAULT_PADDING;
1086 else
1087 priv->padding = 0;
1088
1089 if (dev->features & NETIF_F_IP_CSUM ||
1090 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1091 dev->hard_header_len += GMAC_FCB_LEN;
1092
1093 /* Program the isrg regs only if number of grps > 1 */
1094 if (priv->num_grps > 1) {
1095 baddr = &regs->isrg0;
1096 for (i = 0; i < priv->num_grps; i++) {
1097 isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1098 isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1099 gfar_write(baddr, isrg);
1100 baddr++;
1101 isrg = 0x0;
1102 }
1103 }
1104
1105 /* Need to reverse the bit maps as bit_map's MSB is q0
1106 * but, for_each_set_bit parses from right to left, which
1107 * basically reverses the queue numbers */
1108 for (i = 0; i< priv->num_grps; i++) {
1109 priv->gfargrp[i].tx_bit_map = reverse_bitmap(
1110 priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1111 priv->gfargrp[i].rx_bit_map = reverse_bitmap(
1112 priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1113 }
1114
1115 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1116 * also assign queues to groups */
1117 for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1118 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
1119 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
1120 priv->num_rx_queues) {
1121 priv->gfargrp[grp_idx].num_rx_queues++;
1122 priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1123 rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1124 rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1125 }
1126 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
1127 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
1128 priv->num_tx_queues) {
1129 priv->gfargrp[grp_idx].num_tx_queues++;
1130 priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1131 tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1132 tqueue = tqueue | (TQUEUE_EN0 >> i);
1133 }
1134 priv->gfargrp[grp_idx].rstat = rstat;
1135 priv->gfargrp[grp_idx].tstat = tstat;
1136 rstat = tstat =0;
1137 }
1138
1139 gfar_write(&regs->rqueue, rqueue);
1140 gfar_write(&regs->tqueue, tqueue);
1141
1142 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1143
1144 /* Initializing some of the rx/tx queue level parameters */
1145 for (i = 0; i < priv->num_tx_queues; i++) {
1146 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1147 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1148 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1149 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1150 }
1151
1152 for (i = 0; i < priv->num_rx_queues; i++) {
1153 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1154 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1155 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1156 }
1157
1158 /* always enable rx filer*/
1159 priv->rx_filer_enable = 1;
1160 /* Enable most messages by default */
1161 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1162 /* use pritority h/w tx queue scheduling for single queue devices */
1163 if (priv->num_tx_queues == 1)
1164 priv->prio_sched_en = 1;
1165
1166 /* Carrier starts down, phylib will bring it up */
1167 netif_carrier_off(dev);
1168
1169 err = register_netdev(dev);
1170
1171 if (err) {
1172 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1173 goto register_fail;
1174 }
1175
1176 device_init_wakeup(&dev->dev,
1177 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1178
1179 /* fill out IRQ number and name fields */
1180 for (i = 0; i < priv->num_grps; i++) {
1181 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1182 sprintf(priv->gfargrp[i].int_name_tx, "%s%s%c%s",
1183 dev->name, "_g", '0' + i, "_tx");
1184 sprintf(priv->gfargrp[i].int_name_rx, "%s%s%c%s",
1185 dev->name, "_g", '0' + i, "_rx");
1186 sprintf(priv->gfargrp[i].int_name_er, "%s%s%c%s",
1187 dev->name, "_g", '0' + i, "_er");
1188 } else
1189 strcpy(priv->gfargrp[i].int_name_tx, dev->name);
1190 }
1191
1192 /* Initialize the filer table */
1193 gfar_init_filer_table(priv);
1194
1195 /* Create all the sysfs files */
1196 gfar_init_sysfs(dev);
1197
1198 /* Print out the device info */
1199 netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1200
1201 /* Even more device info helps when determining which kernel */
1202 /* provided which set of benchmarks. */
1203 netdev_info(dev, "Running with NAPI enabled\n");
1204 for (i = 0; i < priv->num_rx_queues; i++)
1205 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1206 i, priv->rx_queue[i]->rx_ring_size);
1207 for(i = 0; i < priv->num_tx_queues; i++)
1208 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1209 i, priv->tx_queue[i]->tx_ring_size);
1210
1211 return 0;
1212
1213 register_fail:
1214 unmap_group_regs(priv);
1215 free_tx_pointers(priv);
1216 free_rx_pointers(priv);
1217 if (priv->phy_node)
1218 of_node_put(priv->phy_node);
1219 if (priv->tbi_node)
1220 of_node_put(priv->tbi_node);
1221 free_netdev(dev);
1222 return err;
1223 }
1224
1225 static int gfar_remove(struct platform_device *ofdev)
1226 {
1227 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1228
1229 if (priv->phy_node)
1230 of_node_put(priv->phy_node);
1231 if (priv->tbi_node)
1232 of_node_put(priv->tbi_node);
1233
1234 dev_set_drvdata(&ofdev->dev, NULL);
1235
1236 unregister_netdev(priv->ndev);
1237 unmap_group_regs(priv);
1238 free_netdev(priv->ndev);
1239
1240 return 0;
1241 }
1242
1243 #ifdef CONFIG_PM
1244
1245 static int gfar_suspend(struct device *dev)
1246 {
1247 struct gfar_private *priv = dev_get_drvdata(dev);
1248 struct net_device *ndev = priv->ndev;
1249 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1250 unsigned long flags;
1251 u32 tempval;
1252
1253 int magic_packet = priv->wol_en &&
1254 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1255
1256 netif_device_detach(ndev);
1257
1258 if (netif_running(ndev)) {
1259
1260 local_irq_save(flags);
1261 lock_tx_qs(priv);
1262 lock_rx_qs(priv);
1263
1264 gfar_halt_nodisable(ndev);
1265
1266 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1267 tempval = gfar_read(&regs->maccfg1);
1268
1269 tempval &= ~MACCFG1_TX_EN;
1270
1271 if (!magic_packet)
1272 tempval &= ~MACCFG1_RX_EN;
1273
1274 gfar_write(&regs->maccfg1, tempval);
1275
1276 unlock_rx_qs(priv);
1277 unlock_tx_qs(priv);
1278 local_irq_restore(flags);
1279
1280 disable_napi(priv);
1281
1282 if (magic_packet) {
1283 /* Enable interrupt on Magic Packet */
1284 gfar_write(&regs->imask, IMASK_MAG);
1285
1286 /* Enable Magic Packet mode */
1287 tempval = gfar_read(&regs->maccfg2);
1288 tempval |= MACCFG2_MPEN;
1289 gfar_write(&regs->maccfg2, tempval);
1290 } else {
1291 phy_stop(priv->phydev);
1292 }
1293 }
1294
1295 return 0;
1296 }
1297
1298 static int gfar_resume(struct device *dev)
1299 {
1300 struct gfar_private *priv = dev_get_drvdata(dev);
1301 struct net_device *ndev = priv->ndev;
1302 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1303 unsigned long flags;
1304 u32 tempval;
1305 int magic_packet = priv->wol_en &&
1306 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1307
1308 if (!netif_running(ndev)) {
1309 netif_device_attach(ndev);
1310 return 0;
1311 }
1312
1313 if (!magic_packet && priv->phydev)
1314 phy_start(priv->phydev);
1315
1316 /* Disable Magic Packet mode, in case something
1317 * else woke us up.
1318 */
1319 local_irq_save(flags);
1320 lock_tx_qs(priv);
1321 lock_rx_qs(priv);
1322
1323 tempval = gfar_read(&regs->maccfg2);
1324 tempval &= ~MACCFG2_MPEN;
1325 gfar_write(&regs->maccfg2, tempval);
1326
1327 gfar_start(ndev);
1328
1329 unlock_rx_qs(priv);
1330 unlock_tx_qs(priv);
1331 local_irq_restore(flags);
1332
1333 netif_device_attach(ndev);
1334
1335 enable_napi(priv);
1336
1337 return 0;
1338 }
1339
1340 static int gfar_restore(struct device *dev)
1341 {
1342 struct gfar_private *priv = dev_get_drvdata(dev);
1343 struct net_device *ndev = priv->ndev;
1344
1345 if (!netif_running(ndev))
1346 return 0;
1347
1348 gfar_init_bds(ndev);
1349 init_registers(ndev);
1350 gfar_set_mac_address(ndev);
1351 gfar_init_mac(ndev);
1352 gfar_start(ndev);
1353
1354 priv->oldlink = 0;
1355 priv->oldspeed = 0;
1356 priv->oldduplex = -1;
1357
1358 if (priv->phydev)
1359 phy_start(priv->phydev);
1360
1361 netif_device_attach(ndev);
1362 enable_napi(priv);
1363
1364 return 0;
1365 }
1366
1367 static struct dev_pm_ops gfar_pm_ops = {
1368 .suspend = gfar_suspend,
1369 .resume = gfar_resume,
1370 .freeze = gfar_suspend,
1371 .thaw = gfar_resume,
1372 .restore = gfar_restore,
1373 };
1374
1375 #define GFAR_PM_OPS (&gfar_pm_ops)
1376
1377 #else
1378
1379 #define GFAR_PM_OPS NULL
1380
1381 #endif
1382
1383 /* Reads the controller's registers to determine what interface
1384 * connects it to the PHY.
1385 */
1386 static phy_interface_t gfar_get_interface(struct net_device *dev)
1387 {
1388 struct gfar_private *priv = netdev_priv(dev);
1389 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1390 u32 ecntrl;
1391
1392 ecntrl = gfar_read(&regs->ecntrl);
1393
1394 if (ecntrl & ECNTRL_SGMII_MODE)
1395 return PHY_INTERFACE_MODE_SGMII;
1396
1397 if (ecntrl & ECNTRL_TBI_MODE) {
1398 if (ecntrl & ECNTRL_REDUCED_MODE)
1399 return PHY_INTERFACE_MODE_RTBI;
1400 else
1401 return PHY_INTERFACE_MODE_TBI;
1402 }
1403
1404 if (ecntrl & ECNTRL_REDUCED_MODE) {
1405 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
1406 return PHY_INTERFACE_MODE_RMII;
1407 else {
1408 phy_interface_t interface = priv->interface;
1409
1410 /*
1411 * This isn't autodetected right now, so it must
1412 * be set by the device tree or platform code.
1413 */
1414 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1415 return PHY_INTERFACE_MODE_RGMII_ID;
1416
1417 return PHY_INTERFACE_MODE_RGMII;
1418 }
1419 }
1420
1421 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1422 return PHY_INTERFACE_MODE_GMII;
1423
1424 return PHY_INTERFACE_MODE_MII;
1425 }
1426
1427
1428 /* Initializes driver's PHY state, and attaches to the PHY.
1429 * Returns 0 on success.
1430 */
1431 static int init_phy(struct net_device *dev)
1432 {
1433 struct gfar_private *priv = netdev_priv(dev);
1434 uint gigabit_support =
1435 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1436 SUPPORTED_1000baseT_Full : 0;
1437 phy_interface_t interface;
1438
1439 priv->oldlink = 0;
1440 priv->oldspeed = 0;
1441 priv->oldduplex = -1;
1442
1443 interface = gfar_get_interface(dev);
1444
1445 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1446 interface);
1447 if (!priv->phydev)
1448 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1449 interface);
1450 if (!priv->phydev) {
1451 dev_err(&dev->dev, "could not attach to PHY\n");
1452 return -ENODEV;
1453 }
1454
1455 if (interface == PHY_INTERFACE_MODE_SGMII)
1456 gfar_configure_serdes(dev);
1457
1458 /* Remove any features not supported by the controller */
1459 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1460 priv->phydev->advertising = priv->phydev->supported;
1461
1462 return 0;
1463 }
1464
1465 /*
1466 * Initialize TBI PHY interface for communicating with the
1467 * SERDES lynx PHY on the chip. We communicate with this PHY
1468 * through the MDIO bus on each controller, treating it as a
1469 * "normal" PHY at the address found in the TBIPA register. We assume
1470 * that the TBIPA register is valid. Either the MDIO bus code will set
1471 * it to a value that doesn't conflict with other PHYs on the bus, or the
1472 * value doesn't matter, as there are no other PHYs on the bus.
1473 */
1474 static void gfar_configure_serdes(struct net_device *dev)
1475 {
1476 struct gfar_private *priv = netdev_priv(dev);
1477 struct phy_device *tbiphy;
1478
1479 if (!priv->tbi_node) {
1480 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1481 "device tree specify a tbi-handle\n");
1482 return;
1483 }
1484
1485 tbiphy = of_phy_find_device(priv->tbi_node);
1486 if (!tbiphy) {
1487 dev_err(&dev->dev, "error: Could not get TBI device\n");
1488 return;
1489 }
1490
1491 /*
1492 * If the link is already up, we must already be ok, and don't need to
1493 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1494 * everything for us? Resetting it takes the link down and requires
1495 * several seconds for it to come back.
1496 */
1497 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1498 return;
1499
1500 /* Single clk mode, mii mode off(for serdes communication) */
1501 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1502
1503 phy_write(tbiphy, MII_ADVERTISE,
1504 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1505 ADVERTISE_1000XPSE_ASYM);
1506
1507 phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |
1508 BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
1509 }
1510
1511 static void init_registers(struct net_device *dev)
1512 {
1513 struct gfar_private *priv = netdev_priv(dev);
1514 struct gfar __iomem *regs = NULL;
1515 int i = 0;
1516
1517 for (i = 0; i < priv->num_grps; i++) {
1518 regs = priv->gfargrp[i].regs;
1519 /* Clear IEVENT */
1520 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1521
1522 /* Initialize IMASK */
1523 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1524 }
1525
1526 regs = priv->gfargrp[0].regs;
1527 /* Init hash registers to zero */
1528 gfar_write(&regs->igaddr0, 0);
1529 gfar_write(&regs->igaddr1, 0);
1530 gfar_write(&regs->igaddr2, 0);
1531 gfar_write(&regs->igaddr3, 0);
1532 gfar_write(&regs->igaddr4, 0);
1533 gfar_write(&regs->igaddr5, 0);
1534 gfar_write(&regs->igaddr6, 0);
1535 gfar_write(&regs->igaddr7, 0);
1536
1537 gfar_write(&regs->gaddr0, 0);
1538 gfar_write(&regs->gaddr1, 0);
1539 gfar_write(&regs->gaddr2, 0);
1540 gfar_write(&regs->gaddr3, 0);
1541 gfar_write(&regs->gaddr4, 0);
1542 gfar_write(&regs->gaddr5, 0);
1543 gfar_write(&regs->gaddr6, 0);
1544 gfar_write(&regs->gaddr7, 0);
1545
1546 /* Zero out the rmon mib registers if it has them */
1547 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1548 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1549
1550 /* Mask off the CAM interrupts */
1551 gfar_write(&regs->rmon.cam1, 0xffffffff);
1552 gfar_write(&regs->rmon.cam2, 0xffffffff);
1553 }
1554
1555 /* Initialize the max receive buffer length */
1556 gfar_write(&regs->mrblr, priv->rx_buffer_size);
1557
1558 /* Initialize the Minimum Frame Length Register */
1559 gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1560 }
1561
1562 static int __gfar_is_rx_idle(struct gfar_private *priv)
1563 {
1564 u32 res;
1565
1566 /*
1567 * Normaly TSEC should not hang on GRS commands, so we should
1568 * actually wait for IEVENT_GRSC flag.
1569 */
1570 if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002)))
1571 return 0;
1572
1573 /*
1574 * Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1575 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1576 * and the Rx can be safely reset.
1577 */
1578 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1579 res &= 0x7f807f80;
1580 if ((res & 0xffff) == (res >> 16))
1581 return 1;
1582
1583 return 0;
1584 }
1585
1586 /* Halt the receive and transmit queues */
1587 static void gfar_halt_nodisable(struct net_device *dev)
1588 {
1589 struct gfar_private *priv = netdev_priv(dev);
1590 struct gfar __iomem *regs = NULL;
1591 u32 tempval;
1592 int i = 0;
1593
1594 for (i = 0; i < priv->num_grps; i++) {
1595 regs = priv->gfargrp[i].regs;
1596 /* Mask all interrupts */
1597 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1598
1599 /* Clear all interrupts */
1600 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1601 }
1602
1603 regs = priv->gfargrp[0].regs;
1604 /* Stop the DMA, and wait for it to stop */
1605 tempval = gfar_read(&regs->dmactrl);
1606 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
1607 != (DMACTRL_GRS | DMACTRL_GTS)) {
1608 int ret;
1609
1610 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1611 gfar_write(&regs->dmactrl, tempval);
1612
1613 do {
1614 ret = spin_event_timeout(((gfar_read(&regs->ievent) &
1615 (IEVENT_GRSC | IEVENT_GTSC)) ==
1616 (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1617 if (!ret && !(gfar_read(&regs->ievent) & IEVENT_GRSC))
1618 ret = __gfar_is_rx_idle(priv);
1619 } while (!ret);
1620 }
1621 }
1622
1623 /* Halt the receive and transmit queues */
1624 void gfar_halt(struct net_device *dev)
1625 {
1626 struct gfar_private *priv = netdev_priv(dev);
1627 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1628 u32 tempval;
1629
1630 gfar_halt_nodisable(dev);
1631
1632 /* Disable Rx and Tx */
1633 tempval = gfar_read(&regs->maccfg1);
1634 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1635 gfar_write(&regs->maccfg1, tempval);
1636 }
1637
1638 static void free_grp_irqs(struct gfar_priv_grp *grp)
1639 {
1640 free_irq(grp->interruptError, grp);
1641 free_irq(grp->interruptTransmit, grp);
1642 free_irq(grp->interruptReceive, grp);
1643 }
1644
1645 void stop_gfar(struct net_device *dev)
1646 {
1647 struct gfar_private *priv = netdev_priv(dev);
1648 unsigned long flags;
1649 int i;
1650
1651 phy_stop(priv->phydev);
1652
1653
1654 /* Lock it down */
1655 local_irq_save(flags);
1656 lock_tx_qs(priv);
1657 lock_rx_qs(priv);
1658
1659 gfar_halt(dev);
1660
1661 unlock_rx_qs(priv);
1662 unlock_tx_qs(priv);
1663 local_irq_restore(flags);
1664
1665 /* Free the IRQs */
1666 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1667 for (i = 0; i < priv->num_grps; i++)
1668 free_grp_irqs(&priv->gfargrp[i]);
1669 } else {
1670 for (i = 0; i < priv->num_grps; i++)
1671 free_irq(priv->gfargrp[i].interruptTransmit,
1672 &priv->gfargrp[i]);
1673 }
1674
1675 free_skb_resources(priv);
1676 }
1677
1678 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1679 {
1680 struct txbd8 *txbdp;
1681 struct gfar_private *priv = netdev_priv(tx_queue->dev);
1682 int i, j;
1683
1684 txbdp = tx_queue->tx_bd_base;
1685
1686 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1687 if (!tx_queue->tx_skbuff[i])
1688 continue;
1689
1690 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
1691 txbdp->length, DMA_TO_DEVICE);
1692 txbdp->lstatus = 0;
1693 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1694 j++) {
1695 txbdp++;
1696 dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
1697 txbdp->length, DMA_TO_DEVICE);
1698 }
1699 txbdp++;
1700 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1701 tx_queue->tx_skbuff[i] = NULL;
1702 }
1703 kfree(tx_queue->tx_skbuff);
1704 }
1705
1706 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1707 {
1708 struct rxbd8 *rxbdp;
1709 struct gfar_private *priv = netdev_priv(rx_queue->dev);
1710 int i;
1711
1712 rxbdp = rx_queue->rx_bd_base;
1713
1714 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1715 if (rx_queue->rx_skbuff[i]) {
1716 dma_unmap_single(&priv->ofdev->dev,
1717 rxbdp->bufPtr, priv->rx_buffer_size,
1718 DMA_FROM_DEVICE);
1719 dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1720 rx_queue->rx_skbuff[i] = NULL;
1721 }
1722 rxbdp->lstatus = 0;
1723 rxbdp->bufPtr = 0;
1724 rxbdp++;
1725 }
1726 kfree(rx_queue->rx_skbuff);
1727 }
1728
1729 /* If there are any tx skbs or rx skbs still around, free them.
1730 * Then free tx_skbuff and rx_skbuff */
1731 static void free_skb_resources(struct gfar_private *priv)
1732 {
1733 struct gfar_priv_tx_q *tx_queue = NULL;
1734 struct gfar_priv_rx_q *rx_queue = NULL;
1735 int i;
1736
1737 /* Go through all the buffer descriptors and free their data buffers */
1738 for (i = 0; i < priv->num_tx_queues; i++) {
1739 struct netdev_queue *txq;
1740 tx_queue = priv->tx_queue[i];
1741 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
1742 if(tx_queue->tx_skbuff)
1743 free_skb_tx_queue(tx_queue);
1744 netdev_tx_reset_queue(txq);
1745 }
1746
1747 for (i = 0; i < priv->num_rx_queues; i++) {
1748 rx_queue = priv->rx_queue[i];
1749 if(rx_queue->rx_skbuff)
1750 free_skb_rx_queue(rx_queue);
1751 }
1752
1753 dma_free_coherent(&priv->ofdev->dev,
1754 sizeof(struct txbd8) * priv->total_tx_ring_size +
1755 sizeof(struct rxbd8) * priv->total_rx_ring_size,
1756 priv->tx_queue[0]->tx_bd_base,
1757 priv->tx_queue[0]->tx_bd_dma_base);
1758 skb_queue_purge(&priv->rx_recycle);
1759 }
1760
1761 void gfar_start(struct net_device *dev)
1762 {
1763 struct gfar_private *priv = netdev_priv(dev);
1764 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1765 u32 tempval;
1766 int i = 0;
1767
1768 /* Enable Rx and Tx in MACCFG1 */
1769 tempval = gfar_read(&regs->maccfg1);
1770 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1771 gfar_write(&regs->maccfg1, tempval);
1772
1773 /* Initialize DMACTRL to have WWR and WOP */
1774 tempval = gfar_read(&regs->dmactrl);
1775 tempval |= DMACTRL_INIT_SETTINGS;
1776 gfar_write(&regs->dmactrl, tempval);
1777
1778 /* Make sure we aren't stopped */
1779 tempval = gfar_read(&regs->dmactrl);
1780 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1781 gfar_write(&regs->dmactrl, tempval);
1782
1783 for (i = 0; i < priv->num_grps; i++) {
1784 regs = priv->gfargrp[i].regs;
1785 /* Clear THLT/RHLT, so that the DMA starts polling now */
1786 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1787 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1788 /* Unmask the interrupts we look for */
1789 gfar_write(&regs->imask, IMASK_DEFAULT);
1790 }
1791
1792 dev->trans_start = jiffies; /* prevent tx timeout */
1793 }
1794
1795 void gfar_configure_coalescing(struct gfar_private *priv,
1796 unsigned long tx_mask, unsigned long rx_mask)
1797 {
1798 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1799 u32 __iomem *baddr;
1800 int i = 0;
1801
1802 /* Backward compatible case ---- even if we enable
1803 * multiple queues, there's only single reg to program
1804 */
1805 gfar_write(&regs->txic, 0);
1806 if(likely(priv->tx_queue[0]->txcoalescing))
1807 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1808
1809 gfar_write(&regs->rxic, 0);
1810 if(unlikely(priv->rx_queue[0]->rxcoalescing))
1811 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
1812
1813 if (priv->mode == MQ_MG_MODE) {
1814 baddr = &regs->txic0;
1815 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
1816 if (likely(priv->tx_queue[i]->txcoalescing)) {
1817 gfar_write(baddr + i, 0);
1818 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1819 }
1820 }
1821
1822 baddr = &regs->rxic0;
1823 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
1824 if (likely(priv->rx_queue[i]->rxcoalescing)) {
1825 gfar_write(baddr + i, 0);
1826 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1827 }
1828 }
1829 }
1830 }
1831
1832 static int register_grp_irqs(struct gfar_priv_grp *grp)
1833 {
1834 struct gfar_private *priv = grp->priv;
1835 struct net_device *dev = priv->ndev;
1836 int err;
1837
1838 /* If the device has multiple interrupts, register for
1839 * them. Otherwise, only register for the one */
1840 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1841 /* Install our interrupt handlers for Error,
1842 * Transmit, and Receive */
1843 if ((err = request_irq(grp->interruptError, gfar_error, 0,
1844 grp->int_name_er,grp)) < 0) {
1845 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1846 grp->interruptError);
1847
1848 goto err_irq_fail;
1849 }
1850
1851 if ((err = request_irq(grp->interruptTransmit, gfar_transmit,
1852 0, grp->int_name_tx, grp)) < 0) {
1853 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1854 grp->interruptTransmit);
1855 goto tx_irq_fail;
1856 }
1857
1858 if ((err = request_irq(grp->interruptReceive, gfar_receive, 0,
1859 grp->int_name_rx, grp)) < 0) {
1860 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1861 grp->interruptReceive);
1862 goto rx_irq_fail;
1863 }
1864 } else {
1865 if ((err = request_irq(grp->interruptTransmit, gfar_interrupt, 0,
1866 grp->int_name_tx, grp)) < 0) {
1867 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1868 grp->interruptTransmit);
1869 goto err_irq_fail;
1870 }
1871 }
1872
1873 return 0;
1874
1875 rx_irq_fail:
1876 free_irq(grp->interruptTransmit, grp);
1877 tx_irq_fail:
1878 free_irq(grp->interruptError, grp);
1879 err_irq_fail:
1880 return err;
1881
1882 }
1883
1884 /* Bring the controller up and running */
1885 int startup_gfar(struct net_device *ndev)
1886 {
1887 struct gfar_private *priv = netdev_priv(ndev);
1888 struct gfar __iomem *regs = NULL;
1889 int err, i, j;
1890
1891 for (i = 0; i < priv->num_grps; i++) {
1892 regs= priv->gfargrp[i].regs;
1893 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1894 }
1895
1896 regs= priv->gfargrp[0].regs;
1897 err = gfar_alloc_skb_resources(ndev);
1898 if (err)
1899 return err;
1900
1901 gfar_init_mac(ndev);
1902
1903 for (i = 0; i < priv->num_grps; i++) {
1904 err = register_grp_irqs(&priv->gfargrp[i]);
1905 if (err) {
1906 for (j = 0; j < i; j++)
1907 free_grp_irqs(&priv->gfargrp[j]);
1908 goto irq_fail;
1909 }
1910 }
1911
1912 /* Start the controller */
1913 gfar_start(ndev);
1914
1915 phy_start(priv->phydev);
1916
1917 gfar_configure_coalescing(priv, 0xFF, 0xFF);
1918
1919 return 0;
1920
1921 irq_fail:
1922 free_skb_resources(priv);
1923 return err;
1924 }
1925
1926 /* Called when something needs to use the ethernet device */
1927 /* Returns 0 for success. */
1928 static int gfar_enet_open(struct net_device *dev)
1929 {
1930 struct gfar_private *priv = netdev_priv(dev);
1931 int err;
1932
1933 enable_napi(priv);
1934
1935 skb_queue_head_init(&priv->rx_recycle);
1936
1937 /* Initialize a bunch of registers */
1938 init_registers(dev);
1939
1940 gfar_set_mac_address(dev);
1941
1942 err = init_phy(dev);
1943
1944 if (err) {
1945 disable_napi(priv);
1946 return err;
1947 }
1948
1949 err = startup_gfar(dev);
1950 if (err) {
1951 disable_napi(priv);
1952 return err;
1953 }
1954
1955 netif_tx_start_all_queues(dev);
1956
1957 device_set_wakeup_enable(&dev->dev, priv->wol_en);
1958
1959 return err;
1960 }
1961
1962 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1963 {
1964 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1965
1966 memset(fcb, 0, GMAC_FCB_LEN);
1967
1968 return fcb;
1969 }
1970
1971 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
1972 int fcb_length)
1973 {
1974 u8 flags = 0;
1975
1976 /* If we're here, it's a IP packet with a TCP or UDP
1977 * payload. We set it to checksum, using a pseudo-header
1978 * we provide
1979 */
1980 flags = TXFCB_DEFAULT;
1981
1982 /* Tell the controller what the protocol is */
1983 /* And provide the already calculated phcs */
1984 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1985 flags |= TXFCB_UDP;
1986 fcb->phcs = udp_hdr(skb)->check;
1987 } else
1988 fcb->phcs = tcp_hdr(skb)->check;
1989
1990 /* l3os is the distance between the start of the
1991 * frame (skb->data) and the start of the IP hdr.
1992 * l4os is the distance between the start of the
1993 * l3 hdr and the l4 hdr */
1994 fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length);
1995 fcb->l4os = skb_network_header_len(skb);
1996
1997 fcb->flags = flags;
1998 }
1999
2000 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2001 {
2002 fcb->flags |= TXFCB_VLN;
2003 fcb->vlctl = vlan_tx_tag_get(skb);
2004 }
2005
2006 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2007 struct txbd8 *base, int ring_size)
2008 {
2009 struct txbd8 *new_bd = bdp + stride;
2010
2011 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2012 }
2013
2014 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2015 int ring_size)
2016 {
2017 return skip_txbd(bdp, 1, base, ring_size);
2018 }
2019
2020 /* This is called by the kernel when a frame is ready for transmission. */
2021 /* It is pointed to by the dev->hard_start_xmit function pointer */
2022 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2023 {
2024 struct gfar_private *priv = netdev_priv(dev);
2025 struct gfar_priv_tx_q *tx_queue = NULL;
2026 struct netdev_queue *txq;
2027 struct gfar __iomem *regs = NULL;
2028 struct txfcb *fcb = NULL;
2029 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2030 u32 lstatus;
2031 int i, rq = 0, do_tstamp = 0;
2032 u32 bufaddr;
2033 unsigned long flags;
2034 unsigned int nr_frags, nr_txbds, length, fcb_length = GMAC_FCB_LEN;
2035
2036 /*
2037 * TOE=1 frames larger than 2500 bytes may see excess delays
2038 * before start of transmission.
2039 */
2040 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) &&
2041 skb->ip_summed == CHECKSUM_PARTIAL &&
2042 skb->len > 2500)) {
2043 int ret;
2044
2045 ret = skb_checksum_help(skb);
2046 if (ret)
2047 return ret;
2048 }
2049
2050 rq = skb->queue_mapping;
2051 tx_queue = priv->tx_queue[rq];
2052 txq = netdev_get_tx_queue(dev, rq);
2053 base = tx_queue->tx_bd_base;
2054 regs = tx_queue->grp->regs;
2055
2056 /* check if time stamp should be generated */
2057 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
2058 priv->hwts_tx_en)) {
2059 do_tstamp = 1;
2060 fcb_length = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2061 }
2062
2063 /* make space for additional header when fcb is needed */
2064 if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
2065 vlan_tx_tag_present(skb) ||
2066 unlikely(do_tstamp)) &&
2067 (skb_headroom(skb) < fcb_length)) {
2068 struct sk_buff *skb_new;
2069
2070 skb_new = skb_realloc_headroom(skb, fcb_length);
2071 if (!skb_new) {
2072 dev->stats.tx_errors++;
2073 kfree_skb(skb);
2074 return NETDEV_TX_OK;
2075 }
2076
2077 if (skb->sk)
2078 skb_set_owner_w(skb_new, skb->sk);
2079 consume_skb(skb);
2080 skb = skb_new;
2081 }
2082
2083 /* total number of fragments in the SKB */
2084 nr_frags = skb_shinfo(skb)->nr_frags;
2085
2086 /* calculate the required number of TxBDs for this skb */
2087 if (unlikely(do_tstamp))
2088 nr_txbds = nr_frags + 2;
2089 else
2090 nr_txbds = nr_frags + 1;
2091
2092 /* check if there is space to queue this packet */
2093 if (nr_txbds > tx_queue->num_txbdfree) {
2094 /* no space, stop the queue */
2095 netif_tx_stop_queue(txq);
2096 dev->stats.tx_fifo_errors++;
2097 return NETDEV_TX_BUSY;
2098 }
2099
2100 /* Update transmit stats */
2101 tx_queue->stats.tx_bytes += skb->len;
2102 tx_queue->stats.tx_packets++;
2103
2104 txbdp = txbdp_start = tx_queue->cur_tx;
2105 lstatus = txbdp->lstatus;
2106
2107 /* Time stamp insertion requires one additional TxBD */
2108 if (unlikely(do_tstamp))
2109 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2110 tx_queue->tx_ring_size);
2111
2112 if (nr_frags == 0) {
2113 if (unlikely(do_tstamp))
2114 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2115 TXBD_INTERRUPT);
2116 else
2117 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2118 } else {
2119 /* Place the fragment addresses and lengths into the TxBDs */
2120 for (i = 0; i < nr_frags; i++) {
2121 /* Point at the next BD, wrapping as needed */
2122 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2123
2124 length = skb_shinfo(skb)->frags[i].size;
2125
2126 lstatus = txbdp->lstatus | length |
2127 BD_LFLAG(TXBD_READY);
2128
2129 /* Handle the last BD specially */
2130 if (i == nr_frags - 1)
2131 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2132
2133 bufaddr = skb_frag_dma_map(&priv->ofdev->dev,
2134 &skb_shinfo(skb)->frags[i],
2135 0,
2136 length,
2137 DMA_TO_DEVICE);
2138
2139 /* set the TxBD length and buffer pointer */
2140 txbdp->bufPtr = bufaddr;
2141 txbdp->lstatus = lstatus;
2142 }
2143
2144 lstatus = txbdp_start->lstatus;
2145 }
2146
2147 /* Add TxPAL between FCB and frame if required */
2148 if (unlikely(do_tstamp)) {
2149 skb_push(skb, GMAC_TXPAL_LEN);
2150 memset(skb->data, 0, GMAC_TXPAL_LEN);
2151 }
2152
2153 /* Set up checksumming */
2154 if (CHECKSUM_PARTIAL == skb->ip_summed) {
2155 fcb = gfar_add_fcb(skb);
2156 /* as specified by errata */
2157 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_12)
2158 && ((unsigned long)fcb % 0x20) > 0x18)) {
2159 __skb_pull(skb, GMAC_FCB_LEN);
2160 skb_checksum_help(skb);
2161 } else {
2162 lstatus |= BD_LFLAG(TXBD_TOE);
2163 gfar_tx_checksum(skb, fcb, fcb_length);
2164 }
2165 }
2166
2167 if (vlan_tx_tag_present(skb)) {
2168 if (unlikely(NULL == fcb)) {
2169 fcb = gfar_add_fcb(skb);
2170 lstatus |= BD_LFLAG(TXBD_TOE);
2171 }
2172
2173 gfar_tx_vlan(skb, fcb);
2174 }
2175
2176 /* Setup tx hardware time stamping if requested */
2177 if (unlikely(do_tstamp)) {
2178 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2179 if (fcb == NULL)
2180 fcb = gfar_add_fcb(skb);
2181 fcb->ptp = 1;
2182 lstatus |= BD_LFLAG(TXBD_TOE);
2183 }
2184
2185 txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
2186 skb_headlen(skb), DMA_TO_DEVICE);
2187
2188 /*
2189 * If time stamping is requested one additional TxBD must be set up. The
2190 * first TxBD points to the FCB and must have a data length of
2191 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2192 * the full frame length.
2193 */
2194 if (unlikely(do_tstamp)) {
2195 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_length;
2196 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2197 (skb_headlen(skb) - fcb_length);
2198 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2199 } else {
2200 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2201 }
2202
2203 netdev_tx_sent_queue(txq, skb->len);
2204
2205 /*
2206 * We can work in parallel with gfar_clean_tx_ring(), except
2207 * when modifying num_txbdfree. Note that we didn't grab the lock
2208 * when we were reading the num_txbdfree and checking for available
2209 * space, that's because outside of this function it can only grow,
2210 * and once we've got needed space, it cannot suddenly disappear.
2211 *
2212 * The lock also protects us from gfar_error(), which can modify
2213 * regs->tstat and thus retrigger the transfers, which is why we
2214 * also must grab the lock before setting ready bit for the first
2215 * to be transmitted BD.
2216 */
2217 spin_lock_irqsave(&tx_queue->txlock, flags);
2218
2219 /*
2220 * The powerpc-specific eieio() is used, as wmb() has too strong
2221 * semantics (it requires synchronization between cacheable and
2222 * uncacheable mappings, which eieio doesn't provide and which we
2223 * don't need), thus requiring a more expensive sync instruction. At
2224 * some point, the set of architecture-independent barrier functions
2225 * should be expanded to include weaker barriers.
2226 */
2227 eieio();
2228
2229 txbdp_start->lstatus = lstatus;
2230
2231 eieio(); /* force lstatus write before tx_skbuff */
2232
2233 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2234
2235 /* Update the current skb pointer to the next entry we will use
2236 * (wrapping if necessary) */
2237 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2238 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2239
2240 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2241
2242 /* reduce TxBD free count */
2243 tx_queue->num_txbdfree -= (nr_txbds);
2244
2245 /* If the next BD still needs to be cleaned up, then the bds
2246 are full. We need to tell the kernel to stop sending us stuff. */
2247 if (!tx_queue->num_txbdfree) {
2248 netif_tx_stop_queue(txq);
2249
2250 dev->stats.tx_fifo_errors++;
2251 }
2252
2253 /* Tell the DMA to go go go */
2254 gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2255
2256 /* Unlock priv */
2257 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2258
2259 return NETDEV_TX_OK;
2260 }
2261
2262 /* Stops the kernel queue, and halts the controller */
2263 static int gfar_close(struct net_device *dev)
2264 {
2265 struct gfar_private *priv = netdev_priv(dev);
2266
2267 disable_napi(priv);
2268
2269 cancel_work_sync(&priv->reset_task);
2270 stop_gfar(dev);
2271
2272 /* Disconnect from the PHY */
2273 phy_disconnect(priv->phydev);
2274 priv->phydev = NULL;
2275
2276 netif_tx_stop_all_queues(dev);
2277
2278 return 0;
2279 }
2280
2281 /* Changes the mac address if the controller is not running. */
2282 static int gfar_set_mac_address(struct net_device *dev)
2283 {
2284 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2285
2286 return 0;
2287 }
2288
2289 /* Check if rx parser should be activated */
2290 void gfar_check_rx_parser_mode(struct gfar_private *priv)
2291 {
2292 struct gfar __iomem *regs;
2293 u32 tempval;
2294
2295 regs = priv->gfargrp[0].regs;
2296
2297 tempval = gfar_read(&regs->rctrl);
2298 /* If parse is no longer required, then disable parser */
2299 if (tempval & RCTRL_REQ_PARSER)
2300 tempval |= RCTRL_PRSDEP_INIT;
2301 else
2302 tempval &= ~RCTRL_PRSDEP_INIT;
2303 gfar_write(&regs->rctrl, tempval);
2304 }
2305
2306 /* Enables and disables VLAN insertion/extraction */
2307 void gfar_vlan_mode(struct net_device *dev, netdev_features_t features)
2308 {
2309 struct gfar_private *priv = netdev_priv(dev);
2310 struct gfar __iomem *regs = NULL;
2311 unsigned long flags;
2312 u32 tempval;
2313
2314 regs = priv->gfargrp[0].regs;
2315 local_irq_save(flags);
2316 lock_rx_qs(priv);
2317
2318 if (features & NETIF_F_HW_VLAN_TX) {
2319 /* Enable VLAN tag insertion */
2320 tempval = gfar_read(&regs->tctrl);
2321 tempval |= TCTRL_VLINS;
2322 gfar_write(&regs->tctrl, tempval);
2323 } else {
2324 /* Disable VLAN tag insertion */
2325 tempval = gfar_read(&regs->tctrl);
2326 tempval &= ~TCTRL_VLINS;
2327 gfar_write(&regs->tctrl, tempval);
2328 }
2329
2330 if (features & NETIF_F_HW_VLAN_RX) {
2331 /* Enable VLAN tag extraction */
2332 tempval = gfar_read(&regs->rctrl);
2333 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
2334 gfar_write(&regs->rctrl, tempval);
2335 } else {
2336 /* Disable VLAN tag extraction */
2337 tempval = gfar_read(&regs->rctrl);
2338 tempval &= ~RCTRL_VLEX;
2339 gfar_write(&regs->rctrl, tempval);
2340
2341 gfar_check_rx_parser_mode(priv);
2342 }
2343
2344 gfar_change_mtu(dev, dev->mtu);
2345
2346 unlock_rx_qs(priv);
2347 local_irq_restore(flags);
2348 }
2349
2350 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2351 {
2352 int tempsize, tempval;
2353 struct gfar_private *priv = netdev_priv(dev);
2354 struct gfar __iomem *regs = priv->gfargrp[0].regs;
2355 int oldsize = priv->rx_buffer_size;
2356 int frame_size = new_mtu + ETH_HLEN;
2357
2358 if (gfar_is_vlan_on(priv))
2359 frame_size += VLAN_HLEN;
2360
2361 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2362 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2363 return -EINVAL;
2364 }
2365
2366 if (gfar_uses_fcb(priv))
2367 frame_size += GMAC_FCB_LEN;
2368
2369 frame_size += priv->padding;
2370
2371 tempsize =
2372 (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2373 INCREMENTAL_BUFFER_SIZE;
2374
2375 /* Only stop and start the controller if it isn't already
2376 * stopped, and we changed something */
2377 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2378 stop_gfar(dev);
2379
2380 priv->rx_buffer_size = tempsize;
2381
2382 dev->mtu = new_mtu;
2383
2384 gfar_write(&regs->mrblr, priv->rx_buffer_size);
2385 gfar_write(&regs->maxfrm, priv->rx_buffer_size);
2386
2387 /* If the mtu is larger than the max size for standard
2388 * ethernet frames (ie, a jumbo frame), then set maccfg2
2389 * to allow huge frames, and to check the length */
2390 tempval = gfar_read(&regs->maccfg2);
2391
2392 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
2393 gfar_has_errata(priv, GFAR_ERRATA_74))
2394 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2395 else
2396 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2397
2398 gfar_write(&regs->maccfg2, tempval);
2399
2400 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2401 startup_gfar(dev);
2402
2403 return 0;
2404 }
2405
2406 /* gfar_reset_task gets scheduled when a packet has not been
2407 * transmitted after a set amount of time.
2408 * For now, assume that clearing out all the structures, and
2409 * starting over will fix the problem.
2410 */
2411 static void gfar_reset_task(struct work_struct *work)
2412 {
2413 struct gfar_private *priv = container_of(work, struct gfar_private,
2414 reset_task);
2415 struct net_device *dev = priv->ndev;
2416
2417 if (dev->flags & IFF_UP) {
2418 netif_tx_stop_all_queues(dev);
2419 stop_gfar(dev);
2420 startup_gfar(dev);
2421 netif_tx_start_all_queues(dev);
2422 }
2423
2424 netif_tx_schedule_all(dev);
2425 }
2426
2427 static void gfar_timeout(struct net_device *dev)
2428 {
2429 struct gfar_private *priv = netdev_priv(dev);
2430
2431 dev->stats.tx_errors++;
2432 schedule_work(&priv->reset_task);
2433 }
2434
2435 static void gfar_align_skb(struct sk_buff *skb)
2436 {
2437 /* We need the data buffer to be aligned properly. We will reserve
2438 * as many bytes as needed to align the data properly
2439 */
2440 skb_reserve(skb, RXBUF_ALIGNMENT -
2441 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2442 }
2443
2444 /* Interrupt Handler for Transmit complete */
2445 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2446 {
2447 struct net_device *dev = tx_queue->dev;
2448 struct netdev_queue *txq;
2449 struct gfar_private *priv = netdev_priv(dev);
2450 struct gfar_priv_rx_q *rx_queue = NULL;
2451 struct txbd8 *bdp, *next = NULL;
2452 struct txbd8 *lbdp = NULL;
2453 struct txbd8 *base = tx_queue->tx_bd_base;
2454 struct sk_buff *skb;
2455 int skb_dirtytx;
2456 int tx_ring_size = tx_queue->tx_ring_size;
2457 int frags = 0, nr_txbds = 0;
2458 int i;
2459 int howmany = 0;
2460 int tqi = tx_queue->qindex;
2461 unsigned int bytes_sent = 0;
2462 u32 lstatus;
2463 size_t buflen;
2464
2465 rx_queue = priv->rx_queue[tqi];
2466 txq = netdev_get_tx_queue(dev, tqi);
2467 bdp = tx_queue->dirty_tx;
2468 skb_dirtytx = tx_queue->skb_dirtytx;
2469
2470 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2471 unsigned long flags;
2472
2473 frags = skb_shinfo(skb)->nr_frags;
2474
2475 /*
2476 * When time stamping, one additional TxBD must be freed.
2477 * Also, we need to dma_unmap_single() the TxPAL.
2478 */
2479 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2480 nr_txbds = frags + 2;
2481 else
2482 nr_txbds = frags + 1;
2483
2484 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2485
2486 lstatus = lbdp->lstatus;
2487
2488 /* Only clean completed frames */
2489 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2490 (lstatus & BD_LENGTH_MASK))
2491 break;
2492
2493 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2494 next = next_txbd(bdp, base, tx_ring_size);
2495 buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2496 } else
2497 buflen = bdp->length;
2498
2499 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2500 buflen, DMA_TO_DEVICE);
2501
2502 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2503 struct skb_shared_hwtstamps shhwtstamps;
2504 u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2505 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2506 shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2507 skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2508 skb_tstamp_tx(skb, &shhwtstamps);
2509 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2510 bdp = next;
2511 }
2512
2513 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2514 bdp = next_txbd(bdp, base, tx_ring_size);
2515
2516 for (i = 0; i < frags; i++) {
2517 dma_unmap_page(&priv->ofdev->dev,
2518 bdp->bufPtr,
2519 bdp->length,
2520 DMA_TO_DEVICE);
2521 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2522 bdp = next_txbd(bdp, base, tx_ring_size);
2523 }
2524
2525 bytes_sent += skb->len;
2526
2527 /*
2528 * If there's room in the queue (limit it to rx_buffer_size)
2529 * we add this skb back into the pool, if it's the right size
2530 */
2531 if (skb_queue_len(&priv->rx_recycle) < rx_queue->rx_ring_size &&
2532 skb_recycle_check(skb, priv->rx_buffer_size +
2533 RXBUF_ALIGNMENT)) {
2534 gfar_align_skb(skb);
2535 skb_queue_head(&priv->rx_recycle, skb);
2536 } else
2537 dev_kfree_skb_any(skb);
2538
2539 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2540
2541 skb_dirtytx = (skb_dirtytx + 1) &
2542 TX_RING_MOD_MASK(tx_ring_size);
2543
2544 howmany++;
2545 spin_lock_irqsave(&tx_queue->txlock, flags);
2546 tx_queue->num_txbdfree += nr_txbds;
2547 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2548 }
2549
2550 /* If we freed a buffer, we can restart transmission, if necessary */
2551 if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree)
2552 netif_wake_subqueue(dev, tqi);
2553
2554 /* Update dirty indicators */
2555 tx_queue->skb_dirtytx = skb_dirtytx;
2556 tx_queue->dirty_tx = bdp;
2557
2558 netdev_tx_completed_queue(txq, howmany, bytes_sent);
2559
2560 return howmany;
2561 }
2562
2563 static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
2564 {
2565 unsigned long flags;
2566
2567 spin_lock_irqsave(&gfargrp->grplock, flags);
2568 if (napi_schedule_prep(&gfargrp->napi)) {
2569 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
2570 __napi_schedule(&gfargrp->napi);
2571 } else {
2572 /*
2573 * Clear IEVENT, so interrupts aren't called again
2574 * because of the packets that have already arrived.
2575 */
2576 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2577 }
2578 spin_unlock_irqrestore(&gfargrp->grplock, flags);
2579
2580 }
2581
2582 /* Interrupt Handler for Transmit complete */
2583 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2584 {
2585 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2586 return IRQ_HANDLED;
2587 }
2588
2589 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
2590 struct sk_buff *skb)
2591 {
2592 struct net_device *dev = rx_queue->dev;
2593 struct gfar_private *priv = netdev_priv(dev);
2594 dma_addr_t buf;
2595
2596 buf = dma_map_single(&priv->ofdev->dev, skb->data,
2597 priv->rx_buffer_size, DMA_FROM_DEVICE);
2598 gfar_init_rxbdp(rx_queue, bdp, buf);
2599 }
2600
2601 static struct sk_buff * gfar_alloc_skb(struct net_device *dev)
2602 {
2603 struct gfar_private *priv = netdev_priv(dev);
2604 struct sk_buff *skb = NULL;
2605
2606 skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
2607 if (!skb)
2608 return NULL;
2609
2610 gfar_align_skb(skb);
2611
2612 return skb;
2613 }
2614
2615 struct sk_buff * gfar_new_skb(struct net_device *dev)
2616 {
2617 struct gfar_private *priv = netdev_priv(dev);
2618 struct sk_buff *skb = NULL;
2619
2620 skb = skb_dequeue(&priv->rx_recycle);
2621 if (!skb)
2622 skb = gfar_alloc_skb(dev);
2623
2624 return skb;
2625 }
2626
2627 static inline void count_errors(unsigned short status, struct net_device *dev)
2628 {
2629 struct gfar_private *priv = netdev_priv(dev);
2630 struct net_device_stats *stats = &dev->stats;
2631 struct gfar_extra_stats *estats = &priv->extra_stats;
2632
2633 /* If the packet was truncated, none of the other errors
2634 * matter */
2635 if (status & RXBD_TRUNCATED) {
2636 stats->rx_length_errors++;
2637
2638 estats->rx_trunc++;
2639
2640 return;
2641 }
2642 /* Count the errors, if there were any */
2643 if (status & (RXBD_LARGE | RXBD_SHORT)) {
2644 stats->rx_length_errors++;
2645
2646 if (status & RXBD_LARGE)
2647 estats->rx_large++;
2648 else
2649 estats->rx_short++;
2650 }
2651 if (status & RXBD_NONOCTET) {
2652 stats->rx_frame_errors++;
2653 estats->rx_nonoctet++;
2654 }
2655 if (status & RXBD_CRCERR) {
2656 estats->rx_crcerr++;
2657 stats->rx_crc_errors++;
2658 }
2659 if (status & RXBD_OVERRUN) {
2660 estats->rx_overrun++;
2661 stats->rx_crc_errors++;
2662 }
2663 }
2664
2665 irqreturn_t gfar_receive(int irq, void *grp_id)
2666 {
2667 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2668 return IRQ_HANDLED;
2669 }
2670
2671 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2672 {
2673 /* If valid headers were found, and valid sums
2674 * were verified, then we tell the kernel that no
2675 * checksumming is necessary. Otherwise, it is */
2676 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
2677 skb->ip_summed = CHECKSUM_UNNECESSARY;
2678 else
2679 skb_checksum_none_assert(skb);
2680 }
2681
2682
2683 /* gfar_process_frame() -- handle one incoming packet if skb
2684 * isn't NULL. */
2685 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2686 int amount_pull)
2687 {
2688 struct gfar_private *priv = netdev_priv(dev);
2689 struct rxfcb *fcb = NULL;
2690
2691 int ret;
2692
2693 /* fcb is at the beginning if exists */
2694 fcb = (struct rxfcb *)skb->data;
2695
2696 /* Remove the FCB from the skb */
2697 /* Remove the padded bytes, if there are any */
2698 if (amount_pull) {
2699 skb_record_rx_queue(skb, fcb->rq);
2700 skb_pull(skb, amount_pull);
2701 }
2702
2703 /* Get receive timestamp from the skb */
2704 if (priv->hwts_rx_en) {
2705 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2706 u64 *ns = (u64 *) skb->data;
2707 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2708 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2709 }
2710
2711 if (priv->padding)
2712 skb_pull(skb, priv->padding);
2713
2714 if (dev->features & NETIF_F_RXCSUM)
2715 gfar_rx_checksum(skb, fcb);
2716
2717 /* Tell the skb what kind of packet this is */
2718 skb->protocol = eth_type_trans(skb, dev);
2719
2720 /*
2721 * There's need to check for NETIF_F_HW_VLAN_RX here.
2722 * Even if vlan rx accel is disabled, on some chips
2723 * RXFCB_VLN is pseudo randomly set.
2724 */
2725 if (dev->features & NETIF_F_HW_VLAN_RX &&
2726 fcb->flags & RXFCB_VLN)
2727 __vlan_hwaccel_put_tag(skb, fcb->vlctl);
2728
2729 /* Send the packet up the stack */
2730 ret = netif_receive_skb(skb);
2731
2732 if (NET_RX_DROP == ret)
2733 priv->extra_stats.kernel_dropped++;
2734
2735 return 0;
2736 }
2737
2738 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2739 * until the budget/quota has been reached. Returns the number
2740 * of frames handled
2741 */
2742 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2743 {
2744 struct net_device *dev = rx_queue->dev;
2745 struct rxbd8 *bdp, *base;
2746 struct sk_buff *skb;
2747 int pkt_len;
2748 int amount_pull;
2749 int howmany = 0;
2750 struct gfar_private *priv = netdev_priv(dev);
2751
2752 /* Get the first full descriptor */
2753 bdp = rx_queue->cur_rx;
2754 base = rx_queue->rx_bd_base;
2755
2756 amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0);
2757
2758 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
2759 struct sk_buff *newskb;
2760 rmb();
2761
2762 /* Add another skb for the future */
2763 newskb = gfar_new_skb(dev);
2764
2765 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2766
2767 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2768 priv->rx_buffer_size, DMA_FROM_DEVICE);
2769
2770 if (unlikely(!(bdp->status & RXBD_ERR) &&
2771 bdp->length > priv->rx_buffer_size))
2772 bdp->status = RXBD_LARGE;
2773
2774 /* We drop the frame if we failed to allocate a new buffer */
2775 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2776 bdp->status & RXBD_ERR)) {
2777 count_errors(bdp->status, dev);
2778
2779 if (unlikely(!newskb))
2780 newskb = skb;
2781 else if (skb)
2782 skb_queue_head(&priv->rx_recycle, skb);
2783 } else {
2784 /* Increment the number of packets */
2785 rx_queue->stats.rx_packets++;
2786 howmany++;
2787
2788 if (likely(skb)) {
2789 pkt_len = bdp->length - ETH_FCS_LEN;
2790 /* Remove the FCS from the packet length */
2791 skb_put(skb, pkt_len);
2792 rx_queue->stats.rx_bytes += pkt_len;
2793 skb_record_rx_queue(skb, rx_queue->qindex);
2794 gfar_process_frame(dev, skb, amount_pull);
2795
2796 } else {
2797 netif_warn(priv, rx_err, dev, "Missing skb!\n");
2798 rx_queue->stats.rx_dropped++;
2799 priv->extra_stats.rx_skbmissing++;
2800 }
2801
2802 }
2803
2804 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2805
2806 /* Setup the new bdp */
2807 gfar_new_rxbdp(rx_queue, bdp, newskb);
2808
2809 /* Update to the next pointer */
2810 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2811
2812 /* update to point at the next skb */
2813 rx_queue->skb_currx =
2814 (rx_queue->skb_currx + 1) &
2815 RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2816 }
2817
2818 /* Update the current rxbd pointer to be the next one */
2819 rx_queue->cur_rx = bdp;
2820
2821 return howmany;
2822 }
2823
2824 static int gfar_poll(struct napi_struct *napi, int budget)
2825 {
2826 struct gfar_priv_grp *gfargrp = container_of(napi,
2827 struct gfar_priv_grp, napi);
2828 struct gfar_private *priv = gfargrp->priv;
2829 struct gfar __iomem *regs = gfargrp->regs;
2830 struct gfar_priv_tx_q *tx_queue = NULL;
2831 struct gfar_priv_rx_q *rx_queue = NULL;
2832 int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
2833 int tx_cleaned = 0, i, left_over_budget = budget;
2834 unsigned long serviced_queues = 0;
2835 int num_queues = 0;
2836
2837 num_queues = gfargrp->num_rx_queues;
2838 budget_per_queue = budget/num_queues;
2839
2840 /* Clear IEVENT, so interrupts aren't called again
2841 * because of the packets that have already arrived */
2842 gfar_write(&regs->ievent, IEVENT_RTX_MASK);
2843
2844 while (num_queues && left_over_budget) {
2845
2846 budget_per_queue = left_over_budget/num_queues;
2847 left_over_budget = 0;
2848
2849 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2850 if (test_bit(i, &serviced_queues))
2851 continue;
2852 rx_queue = priv->rx_queue[i];
2853 tx_queue = priv->tx_queue[rx_queue->qindex];
2854
2855 tx_cleaned += gfar_clean_tx_ring(tx_queue);
2856 rx_cleaned_per_queue = gfar_clean_rx_ring(rx_queue,
2857 budget_per_queue);
2858 rx_cleaned += rx_cleaned_per_queue;
2859 if(rx_cleaned_per_queue < budget_per_queue) {
2860 left_over_budget = left_over_budget +
2861 (budget_per_queue - rx_cleaned_per_queue);
2862 set_bit(i, &serviced_queues);
2863 num_queues--;
2864 }
2865 }
2866 }
2867
2868 if (tx_cleaned)
2869 return budget;
2870
2871 if (rx_cleaned < budget) {
2872 napi_complete(napi);
2873
2874 /* Clear the halt bit in RSTAT */
2875 gfar_write(&regs->rstat, gfargrp->rstat);
2876
2877 gfar_write(&regs->imask, IMASK_DEFAULT);
2878
2879 /* If we are coalescing interrupts, update the timer */
2880 /* Otherwise, clear it */
2881 gfar_configure_coalescing(priv,
2882 gfargrp->rx_bit_map, gfargrp->tx_bit_map);
2883 }
2884
2885 return rx_cleaned;
2886 }
2887
2888 #ifdef CONFIG_NET_POLL_CONTROLLER
2889 /*
2890 * Polling 'interrupt' - used by things like netconsole to send skbs
2891 * without having to re-enable interrupts. It's not called while
2892 * the interrupt routine is executing.
2893 */
2894 static void gfar_netpoll(struct net_device *dev)
2895 {
2896 struct gfar_private *priv = netdev_priv(dev);
2897 int i = 0;
2898
2899 /* If the device has multiple interrupts, run tx/rx */
2900 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2901 for (i = 0; i < priv->num_grps; i++) {
2902 disable_irq(priv->gfargrp[i].interruptTransmit);
2903 disable_irq(priv->gfargrp[i].interruptReceive);
2904 disable_irq(priv->gfargrp[i].interruptError);
2905 gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2906 &priv->gfargrp[i]);
2907 enable_irq(priv->gfargrp[i].interruptError);
2908 enable_irq(priv->gfargrp[i].interruptReceive);
2909 enable_irq(priv->gfargrp[i].interruptTransmit);
2910 }
2911 } else {
2912 for (i = 0; i < priv->num_grps; i++) {
2913 disable_irq(priv->gfargrp[i].interruptTransmit);
2914 gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2915 &priv->gfargrp[i]);
2916 enable_irq(priv->gfargrp[i].interruptTransmit);
2917 }
2918 }
2919 }
2920 #endif
2921
2922 /* The interrupt handler for devices with one interrupt */
2923 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
2924 {
2925 struct gfar_priv_grp *gfargrp = grp_id;
2926
2927 /* Save ievent for future reference */
2928 u32 events = gfar_read(&gfargrp->regs->ievent);
2929
2930 /* Check for reception */
2931 if (events & IEVENT_RX_MASK)
2932 gfar_receive(irq, grp_id);
2933
2934 /* Check for transmit completion */
2935 if (events & IEVENT_TX_MASK)
2936 gfar_transmit(irq, grp_id);
2937
2938 /* Check for errors */
2939 if (events & IEVENT_ERR_MASK)
2940 gfar_error(irq, grp_id);
2941
2942 return IRQ_HANDLED;
2943 }
2944
2945 /* Called every time the controller might need to be made
2946 * aware of new link state. The PHY code conveys this
2947 * information through variables in the phydev structure, and this
2948 * function converts those variables into the appropriate
2949 * register values, and can bring down the device if needed.
2950 */
2951 static void adjust_link(struct net_device *dev)
2952 {
2953 struct gfar_private *priv = netdev_priv(dev);
2954 struct gfar __iomem *regs = priv->gfargrp[0].regs;
2955 unsigned long flags;
2956 struct phy_device *phydev = priv->phydev;
2957 int new_state = 0;
2958
2959 local_irq_save(flags);
2960 lock_tx_qs(priv);
2961
2962 if (phydev->link) {
2963 u32 tempval = gfar_read(&regs->maccfg2);
2964 u32 ecntrl = gfar_read(&regs->ecntrl);
2965
2966 /* Now we make sure that we can be in full duplex mode.
2967 * If not, we operate in half-duplex mode. */
2968 if (phydev->duplex != priv->oldduplex) {
2969 new_state = 1;
2970 if (!(phydev->duplex))
2971 tempval &= ~(MACCFG2_FULL_DUPLEX);
2972 else
2973 tempval |= MACCFG2_FULL_DUPLEX;
2974
2975 priv->oldduplex = phydev->duplex;
2976 }
2977
2978 if (phydev->speed != priv->oldspeed) {
2979 new_state = 1;
2980 switch (phydev->speed) {
2981 case 1000:
2982 tempval =
2983 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2984
2985 ecntrl &= ~(ECNTRL_R100);
2986 break;
2987 case 100:
2988 case 10:
2989 tempval =
2990 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
2991
2992 /* Reduced mode distinguishes
2993 * between 10 and 100 */
2994 if (phydev->speed == SPEED_100)
2995 ecntrl |= ECNTRL_R100;
2996 else
2997 ecntrl &= ~(ECNTRL_R100);
2998 break;
2999 default:
3000 netif_warn(priv, link, dev,
3001 "Ack! Speed (%d) is not 10/100/1000!\n",
3002 phydev->speed);
3003 break;
3004 }
3005
3006 priv->oldspeed = phydev->speed;
3007 }
3008
3009 gfar_write(&regs->maccfg2, tempval);
3010 gfar_write(&regs->ecntrl, ecntrl);
3011
3012 if (!priv->oldlink) {
3013 new_state = 1;
3014 priv->oldlink = 1;
3015 }
3016 } else if (priv->oldlink) {
3017 new_state = 1;
3018 priv->oldlink = 0;
3019 priv->oldspeed = 0;
3020 priv->oldduplex = -1;
3021 }
3022
3023 if (new_state && netif_msg_link(priv))
3024 phy_print_status(phydev);
3025 unlock_tx_qs(priv);
3026 local_irq_restore(flags);
3027 }
3028
3029 /* Update the hash table based on the current list of multicast
3030 * addresses we subscribe to. Also, change the promiscuity of
3031 * the device based on the flags (this function is called
3032 * whenever dev->flags is changed */
3033 static void gfar_set_multi(struct net_device *dev)
3034 {
3035 struct netdev_hw_addr *ha;
3036 struct gfar_private *priv = netdev_priv(dev);
3037 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3038 u32 tempval;
3039
3040 if (dev->flags & IFF_PROMISC) {
3041 /* Set RCTRL to PROM */
3042 tempval = gfar_read(&regs->rctrl);
3043 tempval |= RCTRL_PROM;
3044 gfar_write(&regs->rctrl, tempval);
3045 } else {
3046 /* Set RCTRL to not PROM */
3047 tempval = gfar_read(&regs->rctrl);
3048 tempval &= ~(RCTRL_PROM);
3049 gfar_write(&regs->rctrl, tempval);
3050 }
3051
3052 if (dev->flags & IFF_ALLMULTI) {
3053 /* Set the hash to rx all multicast frames */
3054 gfar_write(&regs->igaddr0, 0xffffffff);
3055 gfar_write(&regs->igaddr1, 0xffffffff);
3056 gfar_write(&regs->igaddr2, 0xffffffff);
3057 gfar_write(&regs->igaddr3, 0xffffffff);
3058 gfar_write(&regs->igaddr4, 0xffffffff);
3059 gfar_write(&regs->igaddr5, 0xffffffff);
3060 gfar_write(&regs->igaddr6, 0xffffffff);
3061 gfar_write(&regs->igaddr7, 0xffffffff);
3062 gfar_write(&regs->gaddr0, 0xffffffff);
3063 gfar_write(&regs->gaddr1, 0xffffffff);
3064 gfar_write(&regs->gaddr2, 0xffffffff);
3065 gfar_write(&regs->gaddr3, 0xffffffff);
3066 gfar_write(&regs->gaddr4, 0xffffffff);
3067 gfar_write(&regs->gaddr5, 0xffffffff);
3068 gfar_write(&regs->gaddr6, 0xffffffff);
3069 gfar_write(&regs->gaddr7, 0xffffffff);
3070 } else {
3071 int em_num;
3072 int idx;
3073
3074 /* zero out the hash */
3075 gfar_write(&regs->igaddr0, 0x0);
3076 gfar_write(&regs->igaddr1, 0x0);
3077 gfar_write(&regs->igaddr2, 0x0);
3078 gfar_write(&regs->igaddr3, 0x0);
3079 gfar_write(&regs->igaddr4, 0x0);
3080 gfar_write(&regs->igaddr5, 0x0);
3081 gfar_write(&regs->igaddr6, 0x0);
3082 gfar_write(&regs->igaddr7, 0x0);
3083 gfar_write(&regs->gaddr0, 0x0);
3084 gfar_write(&regs->gaddr1, 0x0);
3085 gfar_write(&regs->gaddr2, 0x0);
3086 gfar_write(&regs->gaddr3, 0x0);
3087 gfar_write(&regs->gaddr4, 0x0);
3088 gfar_write(&regs->gaddr5, 0x0);
3089 gfar_write(&regs->gaddr6, 0x0);
3090 gfar_write(&regs->gaddr7, 0x0);
3091
3092 /* If we have extended hash tables, we need to
3093 * clear the exact match registers to prepare for
3094 * setting them */
3095 if (priv->extended_hash) {
3096 em_num = GFAR_EM_NUM + 1;
3097 gfar_clear_exact_match(dev);
3098 idx = 1;
3099 } else {
3100 idx = 0;
3101 em_num = 0;
3102 }
3103
3104 if (netdev_mc_empty(dev))
3105 return;
3106
3107 /* Parse the list, and set the appropriate bits */
3108 netdev_for_each_mc_addr(ha, dev) {
3109 if (idx < em_num) {
3110 gfar_set_mac_for_addr(dev, idx, ha->addr);
3111 idx++;
3112 } else
3113 gfar_set_hash_for_addr(dev, ha->addr);
3114 }
3115 }
3116 }
3117
3118
3119 /* Clears each of the exact match registers to zero, so they
3120 * don't interfere with normal reception */
3121 static void gfar_clear_exact_match(struct net_device *dev)
3122 {
3123 int idx;
3124 static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3125
3126 for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
3127 gfar_set_mac_for_addr(dev, idx, zero_arr);
3128 }
3129
3130 /* Set the appropriate hash bit for the given addr */
3131 /* The algorithm works like so:
3132 * 1) Take the Destination Address (ie the multicast address), and
3133 * do a CRC on it (little endian), and reverse the bits of the
3134 * result.
3135 * 2) Use the 8 most significant bits as a hash into a 256-entry
3136 * table. The table is controlled through 8 32-bit registers:
3137 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3138 * gaddr7. This means that the 3 most significant bits in the
3139 * hash index which gaddr register to use, and the 5 other bits
3140 * indicate which bit (assuming an IBM numbering scheme, which
3141 * for PowerPC (tm) is usually the case) in the register holds
3142 * the entry. */
3143 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3144 {
3145 u32 tempval;
3146 struct gfar_private *priv = netdev_priv(dev);
3147 u32 result = ether_crc(ETH_ALEN, addr);
3148 int width = priv->hash_width;
3149 u8 whichbit = (result >> (32 - width)) & 0x1f;
3150 u8 whichreg = result >> (32 - width + 5);
3151 u32 value = (1 << (31-whichbit));
3152
3153 tempval = gfar_read(priv->hash_regs[whichreg]);
3154 tempval |= value;
3155 gfar_write(priv->hash_regs[whichreg], tempval);
3156 }
3157
3158
3159 /* There are multiple MAC Address register pairs on some controllers
3160 * This function sets the numth pair to a given address
3161 */
3162 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3163 const u8 *addr)
3164 {
3165 struct gfar_private *priv = netdev_priv(dev);
3166 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3167 int idx;
3168 char tmpbuf[ETH_ALEN];
3169 u32 tempval;
3170 u32 __iomem *macptr = &regs->macstnaddr1;
3171
3172 macptr += num*2;
3173
3174 /* Now copy it into the mac registers backwards, cuz */
3175 /* little endian is silly */
3176 for (idx = 0; idx < ETH_ALEN; idx++)
3177 tmpbuf[ETH_ALEN - 1 - idx] = addr[idx];
3178
3179 gfar_write(macptr, *((u32 *) (tmpbuf)));
3180
3181 tempval = *((u32 *) (tmpbuf + 4));
3182
3183 gfar_write(macptr+1, tempval);
3184 }
3185
3186 /* GFAR error interrupt handler */
3187 static irqreturn_t gfar_error(int irq, void *grp_id)
3188 {
3189 struct gfar_priv_grp *gfargrp = grp_id;
3190 struct gfar __iomem *regs = gfargrp->regs;
3191 struct gfar_private *priv= gfargrp->priv;
3192 struct net_device *dev = priv->ndev;
3193
3194 /* Save ievent for future reference */
3195 u32 events = gfar_read(&regs->ievent);
3196
3197 /* Clear IEVENT */
3198 gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
3199
3200 /* Magic Packet is not an error. */
3201 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3202 (events & IEVENT_MAG))
3203 events &= ~IEVENT_MAG;
3204
3205 /* Hmm... */
3206 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3207 netdev_dbg(dev, "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3208 events, gfar_read(&regs->imask));
3209
3210 /* Update the error counters */
3211 if (events & IEVENT_TXE) {
3212 dev->stats.tx_errors++;
3213
3214 if (events & IEVENT_LC)
3215 dev->stats.tx_window_errors++;
3216 if (events & IEVENT_CRL)
3217 dev->stats.tx_aborted_errors++;
3218 if (events & IEVENT_XFUN) {
3219 unsigned long flags;
3220
3221 netif_dbg(priv, tx_err, dev,
3222 "TX FIFO underrun, packet dropped\n");
3223 dev->stats.tx_dropped++;
3224 priv->extra_stats.tx_underrun++;
3225
3226 local_irq_save(flags);
3227 lock_tx_qs(priv);
3228
3229 /* Reactivate the Tx Queues */
3230 gfar_write(&regs->tstat, gfargrp->tstat);
3231
3232 unlock_tx_qs(priv);
3233 local_irq_restore(flags);
3234 }
3235 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3236 }
3237 if (events & IEVENT_BSY) {
3238 dev->stats.rx_errors++;
3239 priv->extra_stats.rx_bsy++;
3240
3241 gfar_receive(irq, grp_id);
3242
3243 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3244 gfar_read(&regs->rstat));
3245 }
3246 if (events & IEVENT_BABR) {
3247 dev->stats.rx_errors++;
3248 priv->extra_stats.rx_babr++;
3249
3250 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3251 }
3252 if (events & IEVENT_EBERR) {
3253 priv->extra_stats.eberr++;
3254 netif_dbg(priv, rx_err, dev, "bus error\n");
3255 }
3256 if (events & IEVENT_RXC)
3257 netif_dbg(priv, rx_status, dev, "control frame\n");
3258
3259 if (events & IEVENT_BABT) {
3260 priv->extra_stats.tx_babt++;
3261 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3262 }
3263 return IRQ_HANDLED;
3264 }
3265
3266 static struct of_device_id gfar_match[] =
3267 {
3268 {
3269 .type = "network",
3270 .compatible = "gianfar",
3271 },
3272 {
3273 .compatible = "fsl,etsec2",
3274 },
3275 {},
3276 };
3277 MODULE_DEVICE_TABLE(of, gfar_match);
3278
3279 /* Structure for a device driver */
3280 static struct platform_driver gfar_driver = {
3281 .driver = {
3282 .name = "fsl-gianfar",
3283 .owner = THIS_MODULE,
3284 .pm = GFAR_PM_OPS,
3285 .of_match_table = gfar_match,
3286 },
3287 .probe = gfar_probe,
3288 .remove = gfar_remove,
3289 };
3290
3291 module_platform_driver(gfar_driver);
Linux with added FPC-III support