drivers/net/ethernet/freescale/gianfar_ptp.c

   1 /*
   2  * PTP 1588 clock using the eTSEC
   3  *
   4  * Copyright (C) 2010 OMICRON electronics GmbH
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, write to the Free Software
  18  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20 #include <linux/device.h>
  21 #include <linux/hrtimer.h>
  22 #include <linux/init.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/kernel.h>
  25 #include <linux/module.h>
  26 #include <linux/of.h>
  27 #include <linux/of_platform.h>
  28 #include <linux/timex.h>
  29 #include <linux/io.h>
  30
  31 #include <linux/ptp_clock_kernel.h>
  32
  33 #include "gianfar.h"
  34
  35 /*
  36  * gianfar ptp registers
  37  * Generated by regen.tcl on Thu May 13 01:38:57 PM CEST 2010
  38  */
  39 struct gianfar_ptp_registers {
  40         u32 tmr_ctrl;     /* Timer control register */
  41         u32 tmr_tevent;   /* Timestamp event register */
  42         u32 tmr_temask;   /* Timer event mask register */
  43         u32 tmr_pevent;   /* Timestamp event register */
  44         u32 tmr_pemask;   /* Timer event mask register */
  45         u32 tmr_stat;     /* Timestamp status register */
  46         u32 tmr_cnt_h;    /* Timer counter high register */
  47         u32 tmr_cnt_l;    /* Timer counter low register */
  48         u32 tmr_add;      /* Timer drift compensation addend register */
  49         u32 tmr_acc;      /* Timer accumulator register */
  50         u32 tmr_prsc;     /* Timer prescale */
  51         u8  res1[4];
  52         u32 tmroff_h;     /* Timer offset high */
  53         u32 tmroff_l;     /* Timer offset low */
  54         u8  res2[8];
  55         u32 tmr_alarm1_h; /* Timer alarm 1 high register */
  56         u32 tmr_alarm1_l; /* Timer alarm 1 high register */
  57         u32 tmr_alarm2_h; /* Timer alarm 2 high register */
  58         u32 tmr_alarm2_l; /* Timer alarm 2 high register */
  59         u8  res3[48];
  60         u32 tmr_fiper1;   /* Timer fixed period interval */
  61         u32 tmr_fiper2;   /* Timer fixed period interval */
  62         u32 tmr_fiper3;   /* Timer fixed period interval */
  63         u8  res4[20];
  64         u32 tmr_etts1_h;  /* Timestamp of general purpose external trigger */
  65         u32 tmr_etts1_l;  /* Timestamp of general purpose external trigger */
  66         u32 tmr_etts2_h;  /* Timestamp of general purpose external trigger */
  67         u32 tmr_etts2_l;  /* Timestamp of general purpose external trigger */
  68 };
  69
  70 /* Bit definitions for the TMR_CTRL register */
  71 #define ALM1P                 (1<<31) /* Alarm1 output polarity */
  72 #define ALM2P                 (1<<30) /* Alarm2 output polarity */
  73 #define FS                    (1<<28) /* FIPER start indication */
  74 #define PP1L                  (1<<27) /* Fiper1 pulse loopback mode enabled. */
  75 #define PP2L                  (1<<26) /* Fiper2 pulse loopback mode enabled. */
  76 #define TCLK_PERIOD_SHIFT     (16) /* 1588 timer reference clock period. */
  77 #define TCLK_PERIOD_MASK      (0x3ff)
  78 #define RTPE                  (1<<15) /* Record Tx Timestamp to PAL Enable. */
  79 #define FRD                   (1<<14) /* FIPER Realignment Disable */
  80 #define ESFDP                 (1<<11) /* External Tx/Rx SFD Polarity. */
  81 #define ESFDE                 (1<<10) /* External Tx/Rx SFD Enable. */
  82 #define ETEP2                 (1<<9) /* External trigger 2 edge polarity */
  83 #define ETEP1                 (1<<8) /* External trigger 1 edge polarity */
  84 #define COPH                  (1<<7) /* Generated clock output phase. */
  85 #define CIPH                  (1<<6) /* External oscillator input clock phase */
  86 #define TMSR                  (1<<5) /* Timer soft reset. */
  87 #define BYP                   (1<<3) /* Bypass drift compensated clock */
  88 #define TE                    (1<<2) /* 1588 timer enable. */
  89 #define CKSEL_SHIFT           (0)    /* 1588 Timer reference clock source */
  90 #define CKSEL_MASK            (0x3)
  91
  92 /* Bit definitions for the TMR_TEVENT register */
  93 #define ETS2                  (1<<25) /* External trigger 2 timestamp sampled */
  94 #define ETS1                  (1<<24) /* External trigger 1 timestamp sampled */
  95 #define ALM2                  (1<<17) /* Current time = alarm time register 2 */
  96 #define ALM1                  (1<<16) /* Current time = alarm time register 1 */
  97 #define PP1                   (1<<7)  /* periodic pulse generated on FIPER1 */
  98 #define PP2                   (1<<6)  /* periodic pulse generated on FIPER2 */
  99 #define PP3                   (1<<5)  /* periodic pulse generated on FIPER3 */
 100
 101 /* Bit definitions for the TMR_TEMASK register */
 102 #define ETS2EN                (1<<25) /* External trigger 2 timestamp enable */
 103 #define ETS1EN                (1<<24) /* External trigger 1 timestamp enable */
 104 #define ALM2EN                (1<<17) /* Timer ALM2 event enable */
 105 #define ALM1EN                (1<<16) /* Timer ALM1 event enable */
 106 #define PP1EN                 (1<<7) /* Periodic pulse event 1 enable */
 107 #define PP2EN                 (1<<6) /* Periodic pulse event 2 enable */
 108
 109 /* Bit definitions for the TMR_PEVENT register */
 110 #define TXP2                  (1<<9) /* PTP transmitted timestamp im TXTS2 */
 111 #define TXP1                  (1<<8) /* PTP transmitted timestamp in TXTS1 */
 112 #define RXP                   (1<<0) /* PTP frame has been received */
 113
 114 /* Bit definitions for the TMR_PEMASK register */
 115 #define TXP2EN                (1<<9) /* Transmit PTP packet event 2 enable */
 116 #define TXP1EN                (1<<8) /* Transmit PTP packet event 1 enable */
 117 #define RXPEN                 (1<<0) /* Receive PTP packet event enable */
 118
 119 /* Bit definitions for the TMR_STAT register */
 120 #define STAT_VEC_SHIFT        (0) /* Timer general purpose status vector */
 121 #define STAT_VEC_MASK         (0x3f)
 122
 123 /* Bit definitions for the TMR_PRSC register */
 124 #define PRSC_OCK_SHIFT        (0) /* Output clock division/prescale factor. */
 125 #define PRSC_OCK_MASK         (0xffff)
 126
 127
 128 #define DRIVER          "gianfar_ptp"
 129 #define DEFAULT_CKSEL   1
 130 #define N_EXT_TS        2
 131 #define REG_SIZE        sizeof(struct gianfar_ptp_registers)
 132
 133 struct etsects {
 134         struct gianfar_ptp_registers *regs;
 135         spinlock_t lock; /* protects regs */
 136         struct ptp_clock *clock;
 137         struct ptp_clock_info caps;
 138         struct resource *rsrc;
 139         int irq;
 140         u64 alarm_interval; /* for periodic alarm */
 141         u64 alarm_value;
 142         u32 tclk_period;  /* nanoseconds */
 143         u32 tmr_prsc;
 144         u32 tmr_add;
 145         u32 cksel;
 146         u32 tmr_fiper1;
 147         u32 tmr_fiper2;
 148 };
 149
 150 /*
 151  * Register access functions
 152  */
 153
 154 /* Caller must hold etsects->lock. */
 155 static u64 tmr_cnt_read(struct etsects *etsects)
 156 {
 157         u64 ns;
 158         u32 lo, hi;
 159
 160         lo = gfar_read(&etsects->regs->tmr_cnt_l);
 161         hi = gfar_read(&etsects->regs->tmr_cnt_h);
 162         ns = ((u64) hi) << 32;
 163         ns |= lo;
 164         return ns;
 165 }
 166
 167 /* Caller must hold etsects->lock. */
 168 static void tmr_cnt_write(struct etsects *etsects, u64 ns)
 169 {
 170         u32 hi = ns >> 32;
 171         u32 lo = ns & 0xffffffff;
 172
 173         gfar_write(&etsects->regs->tmr_cnt_l, lo);
 174         gfar_write(&etsects->regs->tmr_cnt_h, hi);
 175 }
 176
 177 /* Caller must hold etsects->lock. */
 178 static void set_alarm(struct etsects *etsects)
 179 {
 180         u64 ns;
 181         u32 lo, hi;
 182
 183         ns = tmr_cnt_read(etsects) + 1500000000ULL;
 184         ns = div_u64(ns, 1000000000UL) * 1000000000ULL;
 185         ns -= etsects->tclk_period;
 186         hi = ns >> 32;
 187         lo = ns & 0xffffffff;
 188         gfar_write(&etsects->regs->tmr_alarm1_l, lo);
 189         gfar_write(&etsects->regs->tmr_alarm1_h, hi);
 190 }
 191
 192 /* Caller must hold etsects->lock. */
 193 static void set_fipers(struct etsects *etsects)
 194 {
 195         set_alarm(etsects);
 196         gfar_write(&etsects->regs->tmr_fiper1, etsects->tmr_fiper1);
 197         gfar_write(&etsects->regs->tmr_fiper2, etsects->tmr_fiper2);
 198 }
 199
 200 /*
 201  * Interrupt service routine
 202  */
 203
 204 static irqreturn_t isr(int irq, void *priv)
 205 {
 206         struct etsects *etsects = priv;
 207         struct ptp_clock_event event;
 208         u64 ns;
 209         u32 ack = 0, lo, hi, mask, val;
 210
 211         val = gfar_read(&etsects->regs->tmr_tevent);
 212
 213         if (val & ETS1) {
 214                 ack |= ETS1;
 215                 hi = gfar_read(&etsects->regs->tmr_etts1_h);
 216                 lo = gfar_read(&etsects->regs->tmr_etts1_l);
 217                 event.type = PTP_CLOCK_EXTTS;
 218                 event.index = 0;
 219                 event.timestamp = ((u64) hi) << 32;
 220                 event.timestamp |= lo;
 221                 ptp_clock_event(etsects->clock, &event);
 222         }
 223
 224         if (val & ETS2) {
 225                 ack |= ETS2;
 226                 hi = gfar_read(&etsects->regs->tmr_etts2_h);
 227                 lo = gfar_read(&etsects->regs->tmr_etts2_l);
 228                 event.type = PTP_CLOCK_EXTTS;
 229                 event.index = 1;
 230                 event.timestamp = ((u64) hi) << 32;
 231                 event.timestamp |= lo;
 232                 ptp_clock_event(etsects->clock, &event);
 233         }
 234
 235         if (val & ALM2) {
 236                 ack |= ALM2;
 237                 if (etsects->alarm_value) {
 238                         event.type = PTP_CLOCK_ALARM;
 239                         event.index = 0;
 240                         event.timestamp = etsects->alarm_value;
 241                         ptp_clock_event(etsects->clock, &event);
 242                 }
 243                 if (etsects->alarm_interval) {
 244                         ns = etsects->alarm_value + etsects->alarm_interval;
 245                         hi = ns >> 32;
 246                         lo = ns & 0xffffffff;
 247                         spin_lock(&etsects->lock);
 248                         gfar_write(&etsects->regs->tmr_alarm2_l, lo);
 249                         gfar_write(&etsects->regs->tmr_alarm2_h, hi);
 250                         spin_unlock(&etsects->lock);
 251                         etsects->alarm_value = ns;
 252                 } else {
 253                         gfar_write(&etsects->regs->tmr_tevent, ALM2);
 254                         spin_lock(&etsects->lock);
 255                         mask = gfar_read(&etsects->regs->tmr_temask);
 256                         mask &= ~ALM2EN;
 257                         gfar_write(&etsects->regs->tmr_temask, mask);
 258                         spin_unlock(&etsects->lock);
 259                         etsects->alarm_value = 0;
 260                         etsects->alarm_interval = 0;
 261                 }
 262         }
 263
 264         if (val & PP1) {
 265                 ack |= PP1;
 266                 event.type = PTP_CLOCK_PPS;
 267                 ptp_clock_event(etsects->clock, &event);
 268         }
 269
 270         if (ack) {
 271                 gfar_write(&etsects->regs->tmr_tevent, ack);
 272                 return IRQ_HANDLED;
 273         } else
 274                 return IRQ_NONE;
 275 }
 276
 277 /*
 278  * PTP clock operations
 279  */
 280
 281 static int ptp_gianfar_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
 282 {
 283         u64 adj;
 284         u32 diff, tmr_add;
 285         int neg_adj = 0;
 286         struct etsects *etsects = container_of(ptp, struct etsects, caps);
 287
 288         if (ppb < 0) {
 289                 neg_adj = 1;
 290                 ppb = -ppb;
 291         }
 292         tmr_add = etsects->tmr_add;
 293         adj = tmr_add;
 294         adj *= ppb;
 295         diff = div_u64(adj, 1000000000ULL);
 296
 297         tmr_add = neg_adj ? tmr_add - diff : tmr_add + diff;
 298
 299         gfar_write(&etsects->regs->tmr_add, tmr_add);
 300
 301         return 0;
 302 }
 303
 304 static int ptp_gianfar_adjtime(struct ptp_clock_info *ptp, s64 delta)
 305 {
 306         s64 now;
 307         unsigned long flags;
 308         struct etsects *etsects = container_of(ptp, struct etsects, caps);
 309
 310         spin_lock_irqsave(&etsects->lock, flags);
 311
 312         now = tmr_cnt_read(etsects);
 313         now += delta;
 314         tmr_cnt_write(etsects, now);
 315
 316         spin_unlock_irqrestore(&etsects->lock, flags);
 317
 318         set_fipers(etsects);
 319
 320         return 0;
 321 }
 322
 323 static int ptp_gianfar_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
 324 {
 325         u64 ns;
 326         u32 remainder;
 327         unsigned long flags;
 328         struct etsects *etsects = container_of(ptp, struct etsects, caps);
 329
 330         spin_lock_irqsave(&etsects->lock, flags);
 331
 332         ns = tmr_cnt_read(etsects);
 333
 334         spin_unlock_irqrestore(&etsects->lock, flags);
 335
 336         ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
 337         ts->tv_nsec = remainder;
 338         return 0;
 339 }
 340
 341 static int ptp_gianfar_settime(struct ptp_clock_info *ptp,
 342                                const struct timespec *ts)
 343 {
 344         u64 ns;
 345         unsigned long flags;
 346         struct etsects *etsects = container_of(ptp, struct etsects, caps);
 347
 348         ns = ts->tv_sec * 1000000000ULL;
 349         ns += ts->tv_nsec;
 350
 351         spin_lock_irqsave(&etsects->lock, flags);
 352
 353         tmr_cnt_write(etsects, ns);
 354         set_fipers(etsects);
 355
 356         spin_unlock_irqrestore(&etsects->lock, flags);
 357
 358         return 0;
 359 }
 360
 361 static int ptp_gianfar_enable(struct ptp_clock_info *ptp,
 362                               struct ptp_clock_request *rq, int on)
 363 {
 364         struct etsects *etsects = container_of(ptp, struct etsects, caps);
 365         unsigned long flags;
 366         u32 bit, mask;
 367
 368         switch (rq->type) {
 369         case PTP_CLK_REQ_EXTTS:
 370                 switch (rq->extts.index) {
 371                 case 0:
 372                         bit = ETS1EN;
 373                         break;
 374                 case 1:
 375                         bit = ETS2EN;
 376                         break;
 377                 default:
 378                         return -EINVAL;
 379                 }
 380                 spin_lock_irqsave(&etsects->lock, flags);
 381                 mask = gfar_read(&etsects->regs->tmr_temask);
 382                 if (on)
 383                         mask |= bit;
 384                 else
 385                         mask &= ~bit;
 386                 gfar_write(&etsects->regs->tmr_temask, mask);
 387                 spin_unlock_irqrestore(&etsects->lock, flags);
 388                 return 0;
 389
 390         case PTP_CLK_REQ_PPS:
 391                 spin_lock_irqsave(&etsects->lock, flags);
 392                 mask = gfar_read(&etsects->regs->tmr_temask);
 393                 if (on)
 394                         mask |= PP1EN;
 395                 else
 396                         mask &= ~PP1EN;
 397                 gfar_write(&etsects->regs->tmr_temask, mask);
 398                 spin_unlock_irqrestore(&etsects->lock, flags);
 399                 return 0;
 400
 401         default:
 402                 break;
 403         }
 404
 405         return -EOPNOTSUPP;
 406 }
 407
 408 static struct ptp_clock_info ptp_gianfar_caps = {
 409         .owner          = THIS_MODULE,
 410         .name           = "gianfar clock",
 411         .max_adj        = 512000,
 412         .n_alarm        = 0,
 413         .n_ext_ts       = N_EXT_TS,
 414         .n_per_out      = 0,
 415         .pps            = 1,
 416         .adjfreq        = ptp_gianfar_adjfreq,
 417         .adjtime        = ptp_gianfar_adjtime,
 418         .gettime        = ptp_gianfar_gettime,
 419         .settime        = ptp_gianfar_settime,
 420         .enable         = ptp_gianfar_enable,
 421 };
 422
 423 /* OF device tree */
 424
 425 static int get_of_u32(struct device_node *node, char *str, u32 *val)
 426 {
 427         int plen;
 428         const u32 *prop = of_get_property(node, str, &plen);
 429
 430         if (!prop || plen != sizeof(*prop))
 431                 return -1;
 432         *val = *prop;
 433         return 0;
 434 }
 435
 436 static int gianfar_ptp_probe(struct platform_device *dev)
 437 {
 438         struct device_node *node = dev->dev.of_node;
 439         struct etsects *etsects;
 440         struct timespec now;
 441         int err = -ENOMEM;
 442         u32 tmr_ctrl;
 443         unsigned long flags;
 444
 445         etsects = kzalloc(sizeof(*etsects), GFP_KERNEL);
 446         if (!etsects)
 447                 goto no_memory;
 448
 449         err = -ENODEV;
 450
 451         etsects->caps = ptp_gianfar_caps;
 452         etsects->cksel = DEFAULT_CKSEL;
 453
 454         if (get_of_u32(node, "fsl,tclk-period", &etsects->tclk_period) ||
 455             get_of_u32(node, "fsl,tmr-prsc", &etsects->tmr_prsc) ||
 456             get_of_u32(node, "fsl,tmr-add", &etsects->tmr_add) ||
 457             get_of_u32(node, "fsl,tmr-fiper1", &etsects->tmr_fiper1) ||
 458             get_of_u32(node, "fsl,tmr-fiper2", &etsects->tmr_fiper2) ||
 459             get_of_u32(node, "fsl,max-adj", &etsects->caps.max_adj)) {
 460                 pr_err("device tree node missing required elements\n");
 461                 goto no_node;
 462         }
 463
 464         etsects->irq = platform_get_irq(dev, 0);
 465
 466         if (etsects->irq == NO_IRQ) {
 467                 pr_err("irq not in device tree\n");
 468                 goto no_node;
 469         }
 470         if (request_irq(etsects->irq, isr, 0, DRIVER, etsects)) {
 471                 pr_err("request_irq failed\n");
 472                 goto no_node;
 473         }
 474
 475         etsects->rsrc = platform_get_resource(dev, IORESOURCE_MEM, 0);
 476         if (!etsects->rsrc) {
 477                 pr_err("no resource\n");
 478                 goto no_resource;
 479         }
 480         if (request_resource(&ioport_resource, etsects->rsrc)) {
 481                 pr_err("resource busy\n");
 482                 goto no_resource;
 483         }
 484
 485         spin_lock_init(&etsects->lock);
 486
 487         etsects->regs = ioremap(etsects->rsrc->start,
 488                                 resource_size(etsects->rsrc));
 489         if (!etsects->regs) {
 490                 pr_err("ioremap ptp registers failed\n");
 491                 goto no_ioremap;
 492         }
 493         getnstimeofday(&now);
 494         ptp_gianfar_settime(&etsects->caps, &now);
 495
 496         tmr_ctrl =
 497           (etsects->tclk_period & TCLK_PERIOD_MASK) << TCLK_PERIOD_SHIFT |
 498           (etsects->cksel & CKSEL_MASK) << CKSEL_SHIFT;
 499
 500         spin_lock_irqsave(&etsects->lock, flags);
 501
 502         gfar_write(&etsects->regs->tmr_ctrl,   tmr_ctrl);
 503         gfar_write(&etsects->regs->tmr_add,    etsects->tmr_add);
 504         gfar_write(&etsects->regs->tmr_prsc,   etsects->tmr_prsc);
 505         gfar_write(&etsects->regs->tmr_fiper1, etsects->tmr_fiper1);
 506         gfar_write(&etsects->regs->tmr_fiper2, etsects->tmr_fiper2);
 507         set_alarm(etsects);
 508         gfar_write(&etsects->regs->tmr_ctrl,   tmr_ctrl|FS|RTPE|TE|FRD);
 509
 510         spin_unlock_irqrestore(&etsects->lock, flags);
 511
 512         etsects->clock = ptp_clock_register(&etsects->caps);
 513         if (IS_ERR(etsects->clock)) {
 514                 err = PTR_ERR(etsects->clock);
 515                 goto no_clock;
 516         }
 517
 518         dev_set_drvdata(&dev->dev, etsects);
 519
 520         return 0;
 521
 522 no_clock:
 523         iounmap(etsects->regs);
 524 no_ioremap:
 525         release_resource(etsects->rsrc);
 526 no_resource:
 527         free_irq(etsects->irq, etsects);
 528 no_node:
 529         kfree(etsects);
 530 no_memory:
 531         return err;
 532 }
 533
 534 static int gianfar_ptp_remove(struct platform_device *dev)
 535 {
 536         struct etsects *etsects = dev_get_drvdata(&dev->dev);
 537
 538         gfar_write(&etsects->regs->tmr_temask, 0);
 539         gfar_write(&etsects->regs->tmr_ctrl,   0);
 540
 541         ptp_clock_unregister(etsects->clock);
 542         iounmap(etsects->regs);
 543         release_resource(etsects->rsrc);
 544         free_irq(etsects->irq, etsects);
 545         kfree(etsects);
 546
 547         return 0;
 548 }
 549
 550 static struct of_device_id match_table[] = {
 551         { .compatible = "fsl,etsec-ptp" },
 552         {},
 553 };
 554
 555 static struct platform_driver gianfar_ptp_driver = {
 556         .driver = {
 557                 .name           = "gianfar_ptp",
 558                 .of_match_table = match_table,
 559                 .owner          = THIS_MODULE,
 560         },
 561         .probe       = gianfar_ptp_probe,
 562         .remove      = gianfar_ptp_remove,
 563 };
 564
 565 module_platform_driver(gianfar_ptp_driver);
 566
 567 MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
 568 MODULE_DESCRIPTION("PTP clock using the eTSEC");
 569 MODULE_LICENSE("GPL");