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Linux 3.4.102
[linux/fpc-iii.git] / drivers / net / ethernet / marvell / sky2.c
blob0dc9a35e73abc1fd4703375f512f55832adde0dd
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
27 #include <linux/crc32.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
35 #include <linux/interrupt.h>
36 #include <linux/ip.h>
37 #include <linux/slab.h>
38 #include <net/ip.h>
39 #include <linux/tcp.h>
40 #include <linux/in.h>
41 #include <linux/delay.h>
42 #include <linux/workqueue.h>
43 #include <linux/if_vlan.h>
44 #include <linux/prefetch.h>
45 #include <linux/debugfs.h>
46 #include <linux/mii.h>
47
48 #include <asm/irq.h>
49
50 #include "sky2.h"
51
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.30"
54
55 /*
56 * The Yukon II chipset takes 64 bit command blocks (called list elements)
57 * that are organized into three (receive, transmit, status) different rings
58 * similar to Tigon3.
59 */
60
61 #define RX_LE_SIZE 1024
62 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
63 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
64 #define RX_DEF_PENDING RX_MAX_PENDING
65
66 /* This is the worst case number of transmit list elements for a single skb:
67 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
68 #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
69 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
70 #define TX_MAX_PENDING 1024
71 #define TX_DEF_PENDING 63
72
73 #define TX_WATCHDOG (5 * HZ)
74 #define NAPI_WEIGHT 64
75 #define PHY_RETRIES 1000
76
77 #define SKY2_EEPROM_MAGIC 0x9955aabb
78
79 #define RING_NEXT(x, s) (((x)+1) & ((s)-1))
80
81 static const u32 default_msg =
82 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
83 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
84 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
85
86 static int debug = -1; /* defaults above */
87 module_param(debug, int, 0);
88 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
89
90 static int copybreak __read_mostly = 128;
91 module_param(copybreak, int, 0);
92 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
93
94 static int disable_msi = 0;
95 module_param(disable_msi, int, 0);
96 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
97
98 static int legacy_pme = 0;
99 module_param(legacy_pme, int, 0);
100 MODULE_PARM_DESC(legacy_pme, "Legacy power management");
101
102 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
143 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
144 { 0 }
145 };
146
147 MODULE_DEVICE_TABLE(pci, sky2_id_table);
148
149 /* Avoid conditionals by using array */
150 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
151 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
152 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
153
154 static void sky2_set_multicast(struct net_device *dev);
155 static irqreturn_t sky2_intr(int irq, void *dev_id);
156
157 /* Access to PHY via serial interconnect */
158 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
159 {
160 int i;
161
162 gma_write16(hw, port, GM_SMI_DATA, val);
163 gma_write16(hw, port, GM_SMI_CTRL,
164 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
165
166 for (i = 0; i < PHY_RETRIES; i++) {
167 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
168 if (ctrl == 0xffff)
169 goto io_error;
170
171 if (!(ctrl & GM_SMI_CT_BUSY))
172 return 0;
173
174 udelay(10);
175 }
176
177 dev_warn(&hw->pdev->dev, "%s: phy write timeout\n", hw->dev[port]->name);
178 return -ETIMEDOUT;
179
180 io_error:
181 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
182 return -EIO;
183 }
184
185 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
186 {
187 int i;
188
189 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
190 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
191
192 for (i = 0; i < PHY_RETRIES; i++) {
193 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
194 if (ctrl == 0xffff)
195 goto io_error;
196
197 if (ctrl & GM_SMI_CT_RD_VAL) {
198 *val = gma_read16(hw, port, GM_SMI_DATA);
199 return 0;
200 }
201
202 udelay(10);
203 }
204
205 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
206 return -ETIMEDOUT;
207 io_error:
208 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
209 return -EIO;
210 }
211
212 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
213 {
214 u16 v;
215 __gm_phy_read(hw, port, reg, &v);
216 return v;
217 }
218
219
220 static void sky2_power_on(struct sky2_hw *hw)
221 {
222 /* switch power to VCC (WA for VAUX problem) */
223 sky2_write8(hw, B0_POWER_CTRL,
224 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
225
226 /* disable Core Clock Division, */
227 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
228
229 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
230 /* enable bits are inverted */
231 sky2_write8(hw, B2_Y2_CLK_GATE,
232 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
233 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
234 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
235 else
236 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
237
238 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
239 u32 reg;
240
241 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
242
243 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
244 /* set all bits to 0 except bits 15..12 and 8 */
245 reg &= P_ASPM_CONTROL_MSK;
246 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
247
248 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
249 /* set all bits to 0 except bits 28 & 27 */
250 reg &= P_CTL_TIM_VMAIN_AV_MSK;
251 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
252
253 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
254
255 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
256
257 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
258 reg = sky2_read32(hw, B2_GP_IO);
259 reg |= GLB_GPIO_STAT_RACE_DIS;
260 sky2_write32(hw, B2_GP_IO, reg);
261
262 sky2_read32(hw, B2_GP_IO);
263 }
264
265 /* Turn on "driver loaded" LED */
266 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
267 }
268
269 static void sky2_power_aux(struct sky2_hw *hw)
270 {
271 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
272 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
273 else
274 /* enable bits are inverted */
275 sky2_write8(hw, B2_Y2_CLK_GATE,
276 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
277 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
278 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
279
280 /* switch power to VAUX if supported and PME from D3cold */
281 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
282 pci_pme_capable(hw->pdev, PCI_D3cold))
283 sky2_write8(hw, B0_POWER_CTRL,
284 (PC_VAUX_ENA | PC_VCC_ENA |
285 PC_VAUX_ON | PC_VCC_OFF));
286
287 /* turn off "driver loaded LED" */
288 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
289 }
290
291 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
292 {
293 u16 reg;
294
295 /* disable all GMAC IRQ's */
296 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
297
298 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
299 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
300 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
301 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
302
303 reg = gma_read16(hw, port, GM_RX_CTRL);
304 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
305 gma_write16(hw, port, GM_RX_CTRL, reg);
306 }
307
308 /* flow control to advertise bits */
309 static const u16 copper_fc_adv[] = {
310 [FC_NONE] = 0,
311 [FC_TX] = PHY_M_AN_ASP,
312 [FC_RX] = PHY_M_AN_PC,
313 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
314 };
315
316 /* flow control to advertise bits when using 1000BaseX */
317 static const u16 fiber_fc_adv[] = {
318 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
319 [FC_TX] = PHY_M_P_ASYM_MD_X,
320 [FC_RX] = PHY_M_P_SYM_MD_X,
321 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
322 };
323
324 /* flow control to GMA disable bits */
325 static const u16 gm_fc_disable[] = {
326 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
327 [FC_TX] = GM_GPCR_FC_RX_DIS,
328 [FC_RX] = GM_GPCR_FC_TX_DIS,
329 [FC_BOTH] = 0,
330 };
331
332
333 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
334 {
335 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
336 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
337
338 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
339 !(hw->flags & SKY2_HW_NEWER_PHY)) {
340 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
341
342 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
343 PHY_M_EC_MAC_S_MSK);
344 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
345
346 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
347 if (hw->chip_id == CHIP_ID_YUKON_EC)
348 /* set downshift counter to 3x and enable downshift */
349 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
350 else
351 /* set master & slave downshift counter to 1x */
352 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
353
354 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
355 }
356
357 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
358 if (sky2_is_copper(hw)) {
359 if (!(hw->flags & SKY2_HW_GIGABIT)) {
360 /* enable automatic crossover */
361 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
362
363 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
364 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
365 u16 spec;
366
367 /* Enable Class A driver for FE+ A0 */
368 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
369 spec |= PHY_M_FESC_SEL_CL_A;
370 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
371 }
372 } else {
373 /* disable energy detect */
374 ctrl &= ~PHY_M_PC_EN_DET_MSK;
375
376 /* enable automatic crossover */
377 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
378
379 /* downshift on PHY 88E1112 and 88E1149 is changed */
380 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
381 (hw->flags & SKY2_HW_NEWER_PHY)) {
382 /* set downshift counter to 3x and enable downshift */
383 ctrl &= ~PHY_M_PC_DSC_MSK;
384 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
385 }
386 }
387 } else {
388 /* workaround for deviation #4.88 (CRC errors) */
389 /* disable Automatic Crossover */
390
391 ctrl &= ~PHY_M_PC_MDIX_MSK;
392 }
393
394 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
395
396 /* special setup for PHY 88E1112 Fiber */
397 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
398 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
399
400 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
401 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
402 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
403 ctrl &= ~PHY_M_MAC_MD_MSK;
404 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
405 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
406
407 if (hw->pmd_type == 'P') {
408 /* select page 1 to access Fiber registers */
409 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
410
411 /* for SFP-module set SIGDET polarity to low */
412 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
413 ctrl |= PHY_M_FIB_SIGD_POL;
414 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
415 }
416
417 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
418 }
419
420 ctrl = PHY_CT_RESET;
421 ct1000 = 0;
422 adv = PHY_AN_CSMA;
423 reg = 0;
424
425 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
426 if (sky2_is_copper(hw)) {
427 if (sky2->advertising & ADVERTISED_1000baseT_Full)
428 ct1000 |= PHY_M_1000C_AFD;
429 if (sky2->advertising & ADVERTISED_1000baseT_Half)
430 ct1000 |= PHY_M_1000C_AHD;
431 if (sky2->advertising & ADVERTISED_100baseT_Full)
432 adv |= PHY_M_AN_100_FD;
433 if (sky2->advertising & ADVERTISED_100baseT_Half)
434 adv |= PHY_M_AN_100_HD;
435 if (sky2->advertising & ADVERTISED_10baseT_Full)
436 adv |= PHY_M_AN_10_FD;
437 if (sky2->advertising & ADVERTISED_10baseT_Half)
438 adv |= PHY_M_AN_10_HD;
439
440 } else { /* special defines for FIBER (88E1040S only) */
441 if (sky2->advertising & ADVERTISED_1000baseT_Full)
442 adv |= PHY_M_AN_1000X_AFD;
443 if (sky2->advertising & ADVERTISED_1000baseT_Half)
444 adv |= PHY_M_AN_1000X_AHD;
445 }
446
447 /* Restart Auto-negotiation */
448 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
449 } else {
450 /* forced speed/duplex settings */
451 ct1000 = PHY_M_1000C_MSE;
452
453 /* Disable auto update for duplex flow control and duplex */
454 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
455
456 switch (sky2->speed) {
457 case SPEED_1000:
458 ctrl |= PHY_CT_SP1000;
459 reg |= GM_GPCR_SPEED_1000;
460 break;
461 case SPEED_100:
462 ctrl |= PHY_CT_SP100;
463 reg |= GM_GPCR_SPEED_100;
464 break;
465 }
466
467 if (sky2->duplex == DUPLEX_FULL) {
468 reg |= GM_GPCR_DUP_FULL;
469 ctrl |= PHY_CT_DUP_MD;
470 } else if (sky2->speed < SPEED_1000)
471 sky2->flow_mode = FC_NONE;
472 }
473
474 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
475 if (sky2_is_copper(hw))
476 adv |= copper_fc_adv[sky2->flow_mode];
477 else
478 adv |= fiber_fc_adv[sky2->flow_mode];
479 } else {
480 reg |= GM_GPCR_AU_FCT_DIS;
481 reg |= gm_fc_disable[sky2->flow_mode];
482
483 /* Forward pause packets to GMAC? */
484 if (sky2->flow_mode & FC_RX)
485 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
486 else
487 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
488 }
489
490 gma_write16(hw, port, GM_GP_CTRL, reg);
491
492 if (hw->flags & SKY2_HW_GIGABIT)
493 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
494
495 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
496 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
497
498 /* Setup Phy LED's */
499 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
500 ledover = 0;
501
502 switch (hw->chip_id) {
503 case CHIP_ID_YUKON_FE:
504 /* on 88E3082 these bits are at 11..9 (shifted left) */
505 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
506
507 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
508
509 /* delete ACT LED control bits */
510 ctrl &= ~PHY_M_FELP_LED1_MSK;
511 /* change ACT LED control to blink mode */
512 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
513 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
514 break;
515
516 case CHIP_ID_YUKON_FE_P:
517 /* Enable Link Partner Next Page */
518 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
519 ctrl |= PHY_M_PC_ENA_LIP_NP;
520
521 /* disable Energy Detect and enable scrambler */
522 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
523 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
524
525 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
526 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
527 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
528 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
529
530 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
531 break;
532
533 case CHIP_ID_YUKON_XL:
534 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
535
536 /* select page 3 to access LED control register */
537 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
538
539 /* set LED Function Control register */
540 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
541 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
542 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
543 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
544 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
545
546 /* set Polarity Control register */
547 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
548 (PHY_M_POLC_LS1_P_MIX(4) |
549 PHY_M_POLC_IS0_P_MIX(4) |
550 PHY_M_POLC_LOS_CTRL(2) |
551 PHY_M_POLC_INIT_CTRL(2) |
552 PHY_M_POLC_STA1_CTRL(2) |
553 PHY_M_POLC_STA0_CTRL(2)));
554
555 /* restore page register */
556 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
557 break;
558
559 case CHIP_ID_YUKON_EC_U:
560 case CHIP_ID_YUKON_EX:
561 case CHIP_ID_YUKON_SUPR:
562 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
563
564 /* select page 3 to access LED control register */
565 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
566
567 /* set LED Function Control register */
568 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
569 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
570 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
571 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
572 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
573
574 /* set Blink Rate in LED Timer Control Register */
575 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
576 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
577 /* restore page register */
578 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
579 break;
580
581 default:
582 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
583 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
584
585 /* turn off the Rx LED (LED_RX) */
586 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
587 }
588
589 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
590 /* apply fixes in PHY AFE */
591 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
592
593 /* increase differential signal amplitude in 10BASE-T */
594 gm_phy_write(hw, port, 0x18, 0xaa99);
595 gm_phy_write(hw, port, 0x17, 0x2011);
596
597 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
598 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
599 gm_phy_write(hw, port, 0x18, 0xa204);
600 gm_phy_write(hw, port, 0x17, 0x2002);
601 }
602
603 /* set page register to 0 */
604 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
605 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
606 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
607 /* apply workaround for integrated resistors calibration */
608 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
609 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
610 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
611 /* apply fixes in PHY AFE */
612 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
613
614 /* apply RDAC termination workaround */
615 gm_phy_write(hw, port, 24, 0x2800);
616 gm_phy_write(hw, port, 23, 0x2001);
617
618 /* set page register back to 0 */
619 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
620 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
621 hw->chip_id < CHIP_ID_YUKON_SUPR) {
622 /* no effect on Yukon-XL */
623 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
624
625 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
626 sky2->speed == SPEED_100) {
627 /* turn on 100 Mbps LED (LED_LINK100) */
628 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
629 }
630
631 if (ledover)
632 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
633
634 } else if (hw->chip_id == CHIP_ID_YUKON_PRM &&
635 (sky2_read8(hw, B2_MAC_CFG) & 0xf) == 0x7) {
636 int i;
637 /* This a phy register setup workaround copied from vendor driver. */
638 static const struct {
639 u16 reg, val;
640 } eee_afe[] = {
641 { 0x156, 0x58ce },
642 { 0x153, 0x99eb },
643 { 0x141, 0x8064 },
644 /* { 0x155, 0x130b },*/
645 { 0x000, 0x0000 },
646 { 0x151, 0x8433 },
647 { 0x14b, 0x8c44 },
648 { 0x14c, 0x0f90 },
649 { 0x14f, 0x39aa },
650 /* { 0x154, 0x2f39 },*/
651 { 0x14d, 0xba33 },
652 { 0x144, 0x0048 },
653 { 0x152, 0x2010 },
654 /* { 0x158, 0x1223 },*/
655 { 0x140, 0x4444 },
656 { 0x154, 0x2f3b },
657 { 0x158, 0xb203 },
658 { 0x157, 0x2029 },
659 };
660
661 /* Start Workaround for OptimaEEE Rev.Z0 */
662 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fb);
663
664 gm_phy_write(hw, port, 1, 0x4099);
665 gm_phy_write(hw, port, 3, 0x1120);
666 gm_phy_write(hw, port, 11, 0x113c);
667 gm_phy_write(hw, port, 14, 0x8100);
668 gm_phy_write(hw, port, 15, 0x112a);
669 gm_phy_write(hw, port, 17, 0x1008);
670
671 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fc);
672 gm_phy_write(hw, port, 1, 0x20b0);
673
674 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
675
676 for (i = 0; i < ARRAY_SIZE(eee_afe); i++) {
677 /* apply AFE settings */
678 gm_phy_write(hw, port, 17, eee_afe[i].val);
679 gm_phy_write(hw, port, 16, eee_afe[i].reg | 1u<<13);
680 }
681
682 /* End Workaround for OptimaEEE */
683 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
684
685 /* Enable 10Base-Te (EEE) */
686 if (hw->chip_id >= CHIP_ID_YUKON_PRM) {
687 reg = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
688 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL,
689 reg | PHY_M_10B_TE_ENABLE);
690 }
691 }
692
693 /* Enable phy interrupt on auto-negotiation complete (or link up) */
694 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
695 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
696 else
697 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
698 }
699
700 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
701 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
702
703 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
704 {
705 u32 reg1;
706
707 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
708 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
709 reg1 &= ~phy_power[port];
710
711 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
712 reg1 |= coma_mode[port];
713
714 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
715 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
716 sky2_pci_read32(hw, PCI_DEV_REG1);
717
718 if (hw->chip_id == CHIP_ID_YUKON_FE)
719 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
720 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
721 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
722 }
723
724 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
725 {
726 u32 reg1;
727 u16 ctrl;
728
729 /* release GPHY Control reset */
730 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
731
732 /* release GMAC reset */
733 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
734
735 if (hw->flags & SKY2_HW_NEWER_PHY) {
736 /* select page 2 to access MAC control register */
737 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
738
739 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
740 /* allow GMII Power Down */
741 ctrl &= ~PHY_M_MAC_GMIF_PUP;
742 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
743
744 /* set page register back to 0 */
745 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
746 }
747
748 /* setup General Purpose Control Register */
749 gma_write16(hw, port, GM_GP_CTRL,
750 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
751 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
752 GM_GPCR_AU_SPD_DIS);
753
754 if (hw->chip_id != CHIP_ID_YUKON_EC) {
755 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
756 /* select page 2 to access MAC control register */
757 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
758
759 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
760 /* enable Power Down */
761 ctrl |= PHY_M_PC_POW_D_ENA;
762 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
763
764 /* set page register back to 0 */
765 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
766 }
767
768 /* set IEEE compatible Power Down Mode (dev. #4.99) */
769 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
770 }
771
772 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
773 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
774 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
775 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
776 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
777 }
778
779 /* configure IPG according to used link speed */
780 static void sky2_set_ipg(struct sky2_port *sky2)
781 {
782 u16 reg;
783
784 reg = gma_read16(sky2->hw, sky2->port, GM_SERIAL_MODE);
785 reg &= ~GM_SMOD_IPG_MSK;
786 if (sky2->speed > SPEED_100)
787 reg |= IPG_DATA_VAL(IPG_DATA_DEF_1000);
788 else
789 reg |= IPG_DATA_VAL(IPG_DATA_DEF_10_100);
790 gma_write16(sky2->hw, sky2->port, GM_SERIAL_MODE, reg);
791 }
792
793 /* Enable Rx/Tx */
794 static void sky2_enable_rx_tx(struct sky2_port *sky2)
795 {
796 struct sky2_hw *hw = sky2->hw;
797 unsigned port = sky2->port;
798 u16 reg;
799
800 reg = gma_read16(hw, port, GM_GP_CTRL);
801 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
802 gma_write16(hw, port, GM_GP_CTRL, reg);
803 }
804
805 /* Force a renegotiation */
806 static void sky2_phy_reinit(struct sky2_port *sky2)
807 {
808 spin_lock_bh(&sky2->phy_lock);
809 sky2_phy_init(sky2->hw, sky2->port);
810 sky2_enable_rx_tx(sky2);
811 spin_unlock_bh(&sky2->phy_lock);
812 }
813
814 /* Put device in state to listen for Wake On Lan */
815 static void sky2_wol_init(struct sky2_port *sky2)
816 {
817 struct sky2_hw *hw = sky2->hw;
818 unsigned port = sky2->port;
819 enum flow_control save_mode;
820 u16 ctrl;
821
822 /* Bring hardware out of reset */
823 sky2_write16(hw, B0_CTST, CS_RST_CLR);
824 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
825
826 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
827 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
828
829 /* Force to 10/100
830 * sky2_reset will re-enable on resume
831 */
832 save_mode = sky2->flow_mode;
833 ctrl = sky2->advertising;
834
835 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
836 sky2->flow_mode = FC_NONE;
837
838 spin_lock_bh(&sky2->phy_lock);
839 sky2_phy_power_up(hw, port);
840 sky2_phy_init(hw, port);
841 spin_unlock_bh(&sky2->phy_lock);
842
843 sky2->flow_mode = save_mode;
844 sky2->advertising = ctrl;
845
846 /* Set GMAC to no flow control and auto update for speed/duplex */
847 gma_write16(hw, port, GM_GP_CTRL,
848 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
849 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
850
851 /* Set WOL address */
852 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
853 sky2->netdev->dev_addr, ETH_ALEN);
854
855 /* Turn on appropriate WOL control bits */
856 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
857 ctrl = 0;
858 if (sky2->wol & WAKE_PHY)
859 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
860 else
861 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
862
863 if (sky2->wol & WAKE_MAGIC)
864 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
865 else
866 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
867
868 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
869 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
870
871 /* Disable PiG firmware */
872 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF);
873
874 /* Needed by some broken BIOSes, use PCI rather than PCI-e for WOL */
875 if (legacy_pme) {
876 u32 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
877 reg1 |= PCI_Y2_PME_LEGACY;
878 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
879 }
880
881 /* block receiver */
882 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
883 sky2_read32(hw, B0_CTST);
884 }
885
886 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
887 {
888 struct net_device *dev = hw->dev[port];
889
890 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
891 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
892 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
893 /* Yukon-Extreme B0 and further Extreme devices */
894 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
895 } else if (dev->mtu > ETH_DATA_LEN) {
896 /* set Tx GMAC FIFO Almost Empty Threshold */
897 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
898 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
899
900 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
901 } else
902 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
903 }
904
905 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
906 {
907 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
908 u16 reg;
909 u32 rx_reg;
910 int i;
911 const u8 *addr = hw->dev[port]->dev_addr;
912
913 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
914 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
915
916 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
917
918 if (hw->chip_id == CHIP_ID_YUKON_XL &&
919 hw->chip_rev == CHIP_REV_YU_XL_A0 &&
920 port == 1) {
921 /* WA DEV_472 -- looks like crossed wires on port 2 */
922 /* clear GMAC 1 Control reset */
923 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
924 do {
925 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
926 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
927 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
928 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
929 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
930 }
931
932 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
933
934 /* Enable Transmit FIFO Underrun */
935 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
936
937 spin_lock_bh(&sky2->phy_lock);
938 sky2_phy_power_up(hw, port);
939 sky2_phy_init(hw, port);
940 spin_unlock_bh(&sky2->phy_lock);
941
942 /* MIB clear */
943 reg = gma_read16(hw, port, GM_PHY_ADDR);
944 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
945
946 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
947 gma_read16(hw, port, i);
948 gma_write16(hw, port, GM_PHY_ADDR, reg);
949
950 /* transmit control */
951 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
952
953 /* receive control reg: unicast + multicast + no FCS */
954 gma_write16(hw, port, GM_RX_CTRL,
955 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
956
957 /* transmit flow control */
958 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
959
960 /* transmit parameter */
961 gma_write16(hw, port, GM_TX_PARAM,
962 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
963 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
964 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
965 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
966
967 /* serial mode register */
968 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
969 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF_1000);
970
971 if (hw->dev[port]->mtu > ETH_DATA_LEN)
972 reg |= GM_SMOD_JUMBO_ENA;
973
974 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
975 hw->chip_rev == CHIP_REV_YU_EC_U_B1)
976 reg |= GM_NEW_FLOW_CTRL;
977
978 gma_write16(hw, port, GM_SERIAL_MODE, reg);
979
980 /* virtual address for data */
981 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
982
983 /* physical address: used for pause frames */
984 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
985
986 /* ignore counter overflows */
987 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
988 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
989 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
990
991 /* Configure Rx MAC FIFO */
992 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
993 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
994 if (hw->chip_id == CHIP_ID_YUKON_EX ||
995 hw->chip_id == CHIP_ID_YUKON_FE_P)
996 rx_reg |= GMF_RX_OVER_ON;
997
998 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
999
1000 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1001 /* Hardware errata - clear flush mask */
1002 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
1003 } else {
1004 /* Flush Rx MAC FIFO on any flow control or error */
1005 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
1006 }
1007
1008 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
1009 reg = RX_GMF_FL_THR_DEF + 1;
1010 /* Another magic mystery workaround from sk98lin */
1011 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1012 hw->chip_rev == CHIP_REV_YU_FE2_A0)
1013 reg = 0x178;
1014 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
1015
1016 /* Configure Tx MAC FIFO */
1017 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1018 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
1019
1020 /* On chips without ram buffer, pause is controlled by MAC level */
1021 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
1022 /* Pause threshold is scaled by 8 in bytes */
1023 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1024 hw->chip_rev == CHIP_REV_YU_FE2_A0)
1025 reg = 1568 / 8;
1026 else
1027 reg = 1024 / 8;
1028 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
1029 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
1030
1031 sky2_set_tx_stfwd(hw, port);
1032 }
1033
1034 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1035 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
1036 /* disable dynamic watermark */
1037 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
1038 reg &= ~TX_DYN_WM_ENA;
1039 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
1040 }
1041 }
1042
1043 /* Assign Ram Buffer allocation to queue */
1044 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
1045 {
1046 u32 end;
1047
1048 /* convert from K bytes to qwords used for hw register */
1049 start *= 1024/8;
1050 space *= 1024/8;
1051 end = start + space - 1;
1052
1053 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
1054 sky2_write32(hw, RB_ADDR(q, RB_START), start);
1055 sky2_write32(hw, RB_ADDR(q, RB_END), end);
1056 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
1057 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
1058
1059 if (q == Q_R1 || q == Q_R2) {
1060 u32 tp = space - space/4;
1061
1062 /* On receive queue's set the thresholds
1063 * give receiver priority when > 3/4 full
1064 * send pause when down to 2K
1065 */
1066 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
1067 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
1068
1069 tp = space - 8192/8;
1070 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
1071 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
1072 } else {
1073 /* Enable store & forward on Tx queue's because
1074 * Tx FIFO is only 1K on Yukon
1075 */
1076 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
1077 }
1078
1079 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
1080 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
1081 }
1082
1083 /* Setup Bus Memory Interface */
1084 static void sky2_qset(struct sky2_hw *hw, u16 q)
1085 {
1086 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1087 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1088 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
1089 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
1090 }
1091
1092 /* Setup prefetch unit registers. This is the interface between
1093 * hardware and driver list elements
1094 */
1095 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
1096 dma_addr_t addr, u32 last)
1097 {
1098 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1099 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
1100 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1101 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
1102 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1103 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
1104
1105 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
1106 }
1107
1108 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
1109 {
1110 struct sky2_tx_le *le = sky2->tx_le + *slot;
1111
1112 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
1113 le->ctrl = 0;
1114 return le;
1115 }
1116
1117 static void tx_init(struct sky2_port *sky2)
1118 {
1119 struct sky2_tx_le *le;
1120
1121 sky2->tx_prod = sky2->tx_cons = 0;
1122 sky2->tx_tcpsum = 0;
1123 sky2->tx_last_mss = 0;
1124 netdev_reset_queue(sky2->netdev);
1125
1126 le = get_tx_le(sky2, &sky2->tx_prod);
1127 le->addr = 0;
1128 le->opcode = OP_ADDR64 | HW_OWNER;
1129 sky2->tx_last_upper = 0;
1130 }
1131
1132 /* Update chip's next pointer */
1133 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1134 {
1135 /* Make sure write' to descriptors are complete before we tell hardware */
1136 wmb();
1137 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1138
1139 /* Synchronize I/O on since next processor may write to tail */
1140 mmiowb();
1141 }
1142
1143
1144 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1145 {
1146 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1147 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1148 le->ctrl = 0;
1149 return le;
1150 }
1151
1152 static unsigned sky2_get_rx_threshold(struct sky2_port *sky2)
1153 {
1154 unsigned size;
1155
1156 /* Space needed for frame data + headers rounded up */
1157 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1158
1159 /* Stopping point for hardware truncation */
1160 return (size - 8) / sizeof(u32);
1161 }
1162
1163 static unsigned sky2_get_rx_data_size(struct sky2_port *sky2)
1164 {
1165 struct rx_ring_info *re;
1166 unsigned size;
1167
1168 /* Space needed for frame data + headers rounded up */
1169 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1170
1171 sky2->rx_nfrags = size >> PAGE_SHIFT;
1172 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1173
1174 /* Compute residue after pages */
1175 size -= sky2->rx_nfrags << PAGE_SHIFT;
1176
1177 /* Optimize to handle small packets and headers */
1178 if (size < copybreak)
1179 size = copybreak;
1180 if (size < ETH_HLEN)
1181 size = ETH_HLEN;
1182
1183 return size;
1184 }
1185
1186 /* Build description to hardware for one receive segment */
1187 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1188 dma_addr_t map, unsigned len)
1189 {
1190 struct sky2_rx_le *le;
1191
1192 if (sizeof(dma_addr_t) > sizeof(u32)) {
1193 le = sky2_next_rx(sky2);
1194 le->addr = cpu_to_le32(upper_32_bits(map));
1195 le->opcode = OP_ADDR64 | HW_OWNER;
1196 }
1197
1198 le = sky2_next_rx(sky2);
1199 le->addr = cpu_to_le32(lower_32_bits(map));
1200 le->length = cpu_to_le16(len);
1201 le->opcode = op | HW_OWNER;
1202 }
1203
1204 /* Build description to hardware for one possibly fragmented skb */
1205 static void sky2_rx_submit(struct sky2_port *sky2,
1206 const struct rx_ring_info *re)
1207 {
1208 int i;
1209
1210 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1211
1212 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1213 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1214 }
1215
1216
1217 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1218 unsigned size)
1219 {
1220 struct sk_buff *skb = re->skb;
1221 int i;
1222
1223 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1224 if (pci_dma_mapping_error(pdev, re->data_addr))
1225 goto mapping_error;
1226
1227 dma_unmap_len_set(re, data_size, size);
1228
1229 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1230 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1231
1232 re->frag_addr[i] = skb_frag_dma_map(&pdev->dev, frag, 0,
1233 skb_frag_size(frag),
1234 DMA_FROM_DEVICE);
1235
1236 if (dma_mapping_error(&pdev->dev, re->frag_addr[i]))
1237 goto map_page_error;
1238 }
1239 return 0;
1240
1241 map_page_error:
1242 while (--i >= 0) {
1243 pci_unmap_page(pdev, re->frag_addr[i],
1244 skb_frag_size(&skb_shinfo(skb)->frags[i]),
1245 PCI_DMA_FROMDEVICE);
1246 }
1247
1248 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
1249 PCI_DMA_FROMDEVICE);
1250
1251 mapping_error:
1252 if (net_ratelimit())
1253 dev_warn(&pdev->dev, "%s: rx mapping error\n",
1254 skb->dev->name);
1255 return -EIO;
1256 }
1257
1258 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1259 {
1260 struct sk_buff *skb = re->skb;
1261 int i;
1262
1263 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
1264 PCI_DMA_FROMDEVICE);
1265
1266 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1267 pci_unmap_page(pdev, re->frag_addr[i],
1268 skb_frag_size(&skb_shinfo(skb)->frags[i]),
1269 PCI_DMA_FROMDEVICE);
1270 }
1271
1272 /* Tell chip where to start receive checksum.
1273 * Actually has two checksums, but set both same to avoid possible byte
1274 * order problems.
1275 */
1276 static void rx_set_checksum(struct sky2_port *sky2)
1277 {
1278 struct sky2_rx_le *le = sky2_next_rx(sky2);
1279
1280 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1281 le->ctrl = 0;
1282 le->opcode = OP_TCPSTART | HW_OWNER;
1283
1284 sky2_write32(sky2->hw,
1285 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1286 (sky2->netdev->features & NETIF_F_RXCSUM)
1287 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1288 }
1289
1290 /*
1291 * Fixed initial key as seed to RSS.
1292 */
1293 static const uint32_t rss_init_key[10] = {
1294 0x7c3351da, 0x51c5cf4e, 0x44adbdd1, 0xe8d38d18, 0x48897c43,
1295 0xb1d60e7e, 0x6a3dd760, 0x01a2e453, 0x16f46f13, 0x1a0e7b30
1296 };
1297
1298 /* Enable/disable receive hash calculation (RSS) */
1299 static void rx_set_rss(struct net_device *dev, netdev_features_t features)
1300 {
1301 struct sky2_port *sky2 = netdev_priv(dev);
1302 struct sky2_hw *hw = sky2->hw;
1303 int i, nkeys = 4;
1304
1305 /* Supports IPv6 and other modes */
1306 if (hw->flags & SKY2_HW_NEW_LE) {
1307 nkeys = 10;
1308 sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL);
1309 }
1310
1311 /* Program RSS initial values */
1312 if (features & NETIF_F_RXHASH) {
1313 for (i = 0; i < nkeys; i++)
1314 sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4),
1315 rss_init_key[i]);
1316
1317 /* Need to turn on (undocumented) flag to make hashing work */
1318 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T),
1319 RX_STFW_ENA);
1320
1321 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1322 BMU_ENA_RX_RSS_HASH);
1323 } else
1324 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1325 BMU_DIS_RX_RSS_HASH);
1326 }
1327
1328 /*
1329 * The RX Stop command will not work for Yukon-2 if the BMU does not
1330 * reach the end of packet and since we can't make sure that we have
1331 * incoming data, we must reset the BMU while it is not doing a DMA
1332 * transfer. Since it is possible that the RX path is still active,
1333 * the RX RAM buffer will be stopped first, so any possible incoming
1334 * data will not trigger a DMA. After the RAM buffer is stopped, the
1335 * BMU is polled until any DMA in progress is ended and only then it
1336 * will be reset.
1337 */
1338 static void sky2_rx_stop(struct sky2_port *sky2)
1339 {
1340 struct sky2_hw *hw = sky2->hw;
1341 unsigned rxq = rxqaddr[sky2->port];
1342 int i;
1343
1344 /* disable the RAM Buffer receive queue */
1345 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1346
1347 for (i = 0; i < 0xffff; i++)
1348 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1349 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1350 goto stopped;
1351
1352 netdev_warn(sky2->netdev, "receiver stop failed\n");
1353 stopped:
1354 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1355
1356 /* reset the Rx prefetch unit */
1357 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1358 mmiowb();
1359 }
1360
1361 /* Clean out receive buffer area, assumes receiver hardware stopped */
1362 static void sky2_rx_clean(struct sky2_port *sky2)
1363 {
1364 unsigned i;
1365
1366 memset(sky2->rx_le, 0, RX_LE_BYTES);
1367 for (i = 0; i < sky2->rx_pending; i++) {
1368 struct rx_ring_info *re = sky2->rx_ring + i;
1369
1370 if (re->skb) {
1371 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1372 kfree_skb(re->skb);
1373 re->skb = NULL;
1374 }
1375 }
1376 }
1377
1378 /* Basic MII support */
1379 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1380 {
1381 struct mii_ioctl_data *data = if_mii(ifr);
1382 struct sky2_port *sky2 = netdev_priv(dev);
1383 struct sky2_hw *hw = sky2->hw;
1384 int err = -EOPNOTSUPP;
1385
1386 if (!netif_running(dev))
1387 return -ENODEV; /* Phy still in reset */
1388
1389 switch (cmd) {
1390 case SIOCGMIIPHY:
1391 data->phy_id = PHY_ADDR_MARV;
1392
1393 /* fallthru */
1394 case SIOCGMIIREG: {
1395 u16 val = 0;
1396
1397 spin_lock_bh(&sky2->phy_lock);
1398 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1399 spin_unlock_bh(&sky2->phy_lock);
1400
1401 data->val_out = val;
1402 break;
1403 }
1404
1405 case SIOCSMIIREG:
1406 spin_lock_bh(&sky2->phy_lock);
1407 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1408 data->val_in);
1409 spin_unlock_bh(&sky2->phy_lock);
1410 break;
1411 }
1412 return err;
1413 }
1414
1415 #define SKY2_VLAN_OFFLOADS (NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO)
1416
1417 static void sky2_vlan_mode(struct net_device *dev, netdev_features_t features)
1418 {
1419 struct sky2_port *sky2 = netdev_priv(dev);
1420 struct sky2_hw *hw = sky2->hw;
1421 u16 port = sky2->port;
1422
1423 if (features & NETIF_F_HW_VLAN_RX)
1424 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1425 RX_VLAN_STRIP_ON);
1426 else
1427 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1428 RX_VLAN_STRIP_OFF);
1429
1430 if (features & NETIF_F_HW_VLAN_TX) {
1431 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1432 TX_VLAN_TAG_ON);
1433
1434 dev->vlan_features |= SKY2_VLAN_OFFLOADS;
1435 } else {
1436 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1437 TX_VLAN_TAG_OFF);
1438
1439 /* Can't do transmit offload of vlan without hw vlan */
1440 dev->vlan_features &= ~SKY2_VLAN_OFFLOADS;
1441 }
1442 }
1443
1444 /* Amount of required worst case padding in rx buffer */
1445 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1446 {
1447 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1448 }
1449
1450 /*
1451 * Allocate an skb for receiving. If the MTU is large enough
1452 * make the skb non-linear with a fragment list of pages.
1453 */
1454 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2, gfp_t gfp)
1455 {
1456 struct sk_buff *skb;
1457 int i;
1458
1459 skb = __netdev_alloc_skb(sky2->netdev,
1460 sky2->rx_data_size + sky2_rx_pad(sky2->hw),
1461 gfp);
1462 if (!skb)
1463 goto nomem;
1464
1465 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1466 unsigned char *start;
1467 /*
1468 * Workaround for a bug in FIFO that cause hang
1469 * if the FIFO if the receive buffer is not 64 byte aligned.
1470 * The buffer returned from netdev_alloc_skb is
1471 * aligned except if slab debugging is enabled.
1472 */
1473 start = PTR_ALIGN(skb->data, 8);
1474 skb_reserve(skb, start - skb->data);
1475 } else
1476 skb_reserve(skb, NET_IP_ALIGN);
1477
1478 for (i = 0; i < sky2->rx_nfrags; i++) {
1479 struct page *page = alloc_page(gfp);
1480
1481 if (!page)
1482 goto free_partial;
1483 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1484 }
1485
1486 return skb;
1487 free_partial:
1488 kfree_skb(skb);
1489 nomem:
1490 return NULL;
1491 }
1492
1493 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1494 {
1495 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1496 }
1497
1498 static int sky2_alloc_rx_skbs(struct sky2_port *sky2)
1499 {
1500 struct sky2_hw *hw = sky2->hw;
1501 unsigned i;
1502
1503 sky2->rx_data_size = sky2_get_rx_data_size(sky2);
1504
1505 /* Fill Rx ring */
1506 for (i = 0; i < sky2->rx_pending; i++) {
1507 struct rx_ring_info *re = sky2->rx_ring + i;
1508
1509 re->skb = sky2_rx_alloc(sky2, GFP_KERNEL);
1510 if (!re->skb)
1511 return -ENOMEM;
1512
1513 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1514 dev_kfree_skb(re->skb);
1515 re->skb = NULL;
1516 return -ENOMEM;
1517 }
1518 }
1519 return 0;
1520 }
1521
1522 /*
1523 * Setup receiver buffer pool.
1524 * Normal case this ends up creating one list element for skb
1525 * in the receive ring. Worst case if using large MTU and each
1526 * allocation falls on a different 64 bit region, that results
1527 * in 6 list elements per ring entry.
1528 * One element is used for checksum enable/disable, and one
1529 * extra to avoid wrap.
1530 */
1531 static void sky2_rx_start(struct sky2_port *sky2)
1532 {
1533 struct sky2_hw *hw = sky2->hw;
1534 struct rx_ring_info *re;
1535 unsigned rxq = rxqaddr[sky2->port];
1536 unsigned i, thresh;
1537
1538 sky2->rx_put = sky2->rx_next = 0;
1539 sky2_qset(hw, rxq);
1540
1541 /* On PCI express lowering the watermark gives better performance */
1542 if (pci_is_pcie(hw->pdev))
1543 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1544
1545 /* These chips have no ram buffer?
1546 * MAC Rx RAM Read is controlled by hardware */
1547 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1548 hw->chip_rev > CHIP_REV_YU_EC_U_A0)
1549 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1550
1551 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1552
1553 if (!(hw->flags & SKY2_HW_NEW_LE))
1554 rx_set_checksum(sky2);
1555
1556 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
1557 rx_set_rss(sky2->netdev, sky2->netdev->features);
1558
1559 /* submit Rx ring */
1560 for (i = 0; i < sky2->rx_pending; i++) {
1561 re = sky2->rx_ring + i;
1562 sky2_rx_submit(sky2, re);
1563 }
1564
1565 /*
1566 * The receiver hangs if it receives frames larger than the
1567 * packet buffer. As a workaround, truncate oversize frames, but
1568 * the register is limited to 9 bits, so if you do frames > 2052
1569 * you better get the MTU right!
1570 */
1571 thresh = sky2_get_rx_threshold(sky2);
1572 if (thresh > 0x1ff)
1573 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1574 else {
1575 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1576 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1577 }
1578
1579 /* Tell chip about available buffers */
1580 sky2_rx_update(sky2, rxq);
1581
1582 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1583 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1584 /*
1585 * Disable flushing of non ASF packets;
1586 * must be done after initializing the BMUs;
1587 * drivers without ASF support should do this too, otherwise
1588 * it may happen that they cannot run on ASF devices;
1589 * remember that the MAC FIFO isn't reset during initialization.
1590 */
1591 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1592 }
1593
1594 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1595 /* Enable RX Home Address & Routing Header checksum fix */
1596 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1597 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1598
1599 /* Enable TX Home Address & Routing Header checksum fix */
1600 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1601 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1602 }
1603 }
1604
1605 static int sky2_alloc_buffers(struct sky2_port *sky2)
1606 {
1607 struct sky2_hw *hw = sky2->hw;
1608
1609 /* must be power of 2 */
1610 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1611 sky2->tx_ring_size *
1612 sizeof(struct sky2_tx_le),
1613 &sky2->tx_le_map);
1614 if (!sky2->tx_le)
1615 goto nomem;
1616
1617 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1618 GFP_KERNEL);
1619 if (!sky2->tx_ring)
1620 goto nomem;
1621
1622 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1623 &sky2->rx_le_map);
1624 if (!sky2->rx_le)
1625 goto nomem;
1626 memset(sky2->rx_le, 0, RX_LE_BYTES);
1627
1628 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1629 GFP_KERNEL);
1630 if (!sky2->rx_ring)
1631 goto nomem;
1632
1633 return sky2_alloc_rx_skbs(sky2);
1634 nomem:
1635 return -ENOMEM;
1636 }
1637
1638 static void sky2_free_buffers(struct sky2_port *sky2)
1639 {
1640 struct sky2_hw *hw = sky2->hw;
1641
1642 sky2_rx_clean(sky2);
1643
1644 if (sky2->rx_le) {
1645 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1646 sky2->rx_le, sky2->rx_le_map);
1647 sky2->rx_le = NULL;
1648 }
1649 if (sky2->tx_le) {
1650 pci_free_consistent(hw->pdev,
1651 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1652 sky2->tx_le, sky2->tx_le_map);
1653 sky2->tx_le = NULL;
1654 }
1655 kfree(sky2->tx_ring);
1656 kfree(sky2->rx_ring);
1657
1658 sky2->tx_ring = NULL;
1659 sky2->rx_ring = NULL;
1660 }
1661
1662 static void sky2_hw_up(struct sky2_port *sky2)
1663 {
1664 struct sky2_hw *hw = sky2->hw;
1665 unsigned port = sky2->port;
1666 u32 ramsize;
1667 int cap;
1668 struct net_device *otherdev = hw->dev[sky2->port^1];
1669
1670 tx_init(sky2);
1671
1672 /*
1673 * On dual port PCI-X card, there is an problem where status
1674 * can be received out of order due to split transactions
1675 */
1676 if (otherdev && netif_running(otherdev) &&
1677 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1678 u16 cmd;
1679
1680 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1681 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1682 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1683 }
1684
1685 sky2_mac_init(hw, port);
1686
1687 /* Register is number of 4K blocks on internal RAM buffer. */
1688 ramsize = sky2_read8(hw, B2_E_0) * 4;
1689 if (ramsize > 0) {
1690 u32 rxspace;
1691
1692 netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize);
1693 if (ramsize < 16)
1694 rxspace = ramsize / 2;
1695 else
1696 rxspace = 8 + (2*(ramsize - 16))/3;
1697
1698 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1699 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1700
1701 /* Make sure SyncQ is disabled */
1702 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1703 RB_RST_SET);
1704 }
1705
1706 sky2_qset(hw, txqaddr[port]);
1707
1708 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1709 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1710 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1711
1712 /* Set almost empty threshold */
1713 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1714 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1715 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1716
1717 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1718 sky2->tx_ring_size - 1);
1719
1720 sky2_vlan_mode(sky2->netdev, sky2->netdev->features);
1721 netdev_update_features(sky2->netdev);
1722
1723 sky2_rx_start(sky2);
1724 }
1725
1726 /* Setup device IRQ and enable napi to process */
1727 static int sky2_setup_irq(struct sky2_hw *hw, const char *name)
1728 {
1729 struct pci_dev *pdev = hw->pdev;
1730 int err;
1731
1732 err = request_irq(pdev->irq, sky2_intr,
1733 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
1734 name, hw);
1735 if (err)
1736 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
1737 else {
1738 hw->flags |= SKY2_HW_IRQ_SETUP;
1739
1740 napi_enable(&hw->napi);
1741 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
1742 sky2_read32(hw, B0_IMSK);
1743 }
1744
1745 return err;
1746 }
1747
1748
1749 /* Bring up network interface. */
1750 static int sky2_open(struct net_device *dev)
1751 {
1752 struct sky2_port *sky2 = netdev_priv(dev);
1753 struct sky2_hw *hw = sky2->hw;
1754 unsigned port = sky2->port;
1755 u32 imask;
1756 int err;
1757
1758 netif_carrier_off(dev);
1759
1760 err = sky2_alloc_buffers(sky2);
1761 if (err)
1762 goto err_out;
1763
1764 /* With single port, IRQ is setup when device is brought up */
1765 if (hw->ports == 1 && (err = sky2_setup_irq(hw, dev->name)))
1766 goto err_out;
1767
1768 sky2_hw_up(sky2);
1769
1770 /* Enable interrupts from phy/mac for port */
1771 imask = sky2_read32(hw, B0_IMSK);
1772
1773 if (hw->chip_id == CHIP_ID_YUKON_OPT ||
1774 hw->chip_id == CHIP_ID_YUKON_PRM ||
1775 hw->chip_id == CHIP_ID_YUKON_OP_2)
1776 imask |= Y2_IS_PHY_QLNK; /* enable PHY Quick Link */
1777
1778 imask |= portirq_msk[port];
1779 sky2_write32(hw, B0_IMSK, imask);
1780 sky2_read32(hw, B0_IMSK);
1781
1782 netif_info(sky2, ifup, dev, "enabling interface\n");
1783
1784 return 0;
1785
1786 err_out:
1787 sky2_free_buffers(sky2);
1788 return err;
1789 }
1790
1791 /* Modular subtraction in ring */
1792 static inline int tx_inuse(const struct sky2_port *sky2)
1793 {
1794 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
1795 }
1796
1797 /* Number of list elements available for next tx */
1798 static inline int tx_avail(const struct sky2_port *sky2)
1799 {
1800 return sky2->tx_pending - tx_inuse(sky2);
1801 }
1802
1803 /* Estimate of number of transmit list elements required */
1804 static unsigned tx_le_req(const struct sk_buff *skb)
1805 {
1806 unsigned count;
1807
1808 count = (skb_shinfo(skb)->nr_frags + 1)
1809 * (sizeof(dma_addr_t) / sizeof(u32));
1810
1811 if (skb_is_gso(skb))
1812 ++count;
1813 else if (sizeof(dma_addr_t) == sizeof(u32))
1814 ++count; /* possible vlan */
1815
1816 if (skb->ip_summed == CHECKSUM_PARTIAL)
1817 ++count;
1818
1819 return count;
1820 }
1821
1822 static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
1823 {
1824 if (re->flags & TX_MAP_SINGLE)
1825 pci_unmap_single(pdev, dma_unmap_addr(re, mapaddr),
1826 dma_unmap_len(re, maplen),
1827 PCI_DMA_TODEVICE);
1828 else if (re->flags & TX_MAP_PAGE)
1829 pci_unmap_page(pdev, dma_unmap_addr(re, mapaddr),
1830 dma_unmap_len(re, maplen),
1831 PCI_DMA_TODEVICE);
1832 re->flags = 0;
1833 }
1834
1835 /*
1836 * Put one packet in ring for transmit.
1837 * A single packet can generate multiple list elements, and
1838 * the number of ring elements will probably be less than the number
1839 * of list elements used.
1840 */
1841 static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1842 struct net_device *dev)
1843 {
1844 struct sky2_port *sky2 = netdev_priv(dev);
1845 struct sky2_hw *hw = sky2->hw;
1846 struct sky2_tx_le *le = NULL;
1847 struct tx_ring_info *re;
1848 unsigned i, len;
1849 dma_addr_t mapping;
1850 u32 upper;
1851 u16 slot;
1852 u16 mss;
1853 u8 ctrl;
1854
1855 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1856 return NETDEV_TX_BUSY;
1857
1858 len = skb_headlen(skb);
1859 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1860
1861 if (pci_dma_mapping_error(hw->pdev, mapping))
1862 goto mapping_error;
1863
1864 slot = sky2->tx_prod;
1865 netif_printk(sky2, tx_queued, KERN_DEBUG, dev,
1866 "tx queued, slot %u, len %d\n", slot, skb->len);
1867
1868 /* Send high bits if needed */
1869 upper = upper_32_bits(mapping);
1870 if (upper != sky2->tx_last_upper) {
1871 le = get_tx_le(sky2, &slot);
1872 le->addr = cpu_to_le32(upper);
1873 sky2->tx_last_upper = upper;
1874 le->opcode = OP_ADDR64 | HW_OWNER;
1875 }
1876
1877 /* Check for TCP Segmentation Offload */
1878 mss = skb_shinfo(skb)->gso_size;
1879 if (mss != 0) {
1880
1881 if (!(hw->flags & SKY2_HW_NEW_LE))
1882 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1883
1884 if (mss != sky2->tx_last_mss) {
1885 le = get_tx_le(sky2, &slot);
1886 le->addr = cpu_to_le32(mss);
1887
1888 if (hw->flags & SKY2_HW_NEW_LE)
1889 le->opcode = OP_MSS | HW_OWNER;
1890 else
1891 le->opcode = OP_LRGLEN | HW_OWNER;
1892 sky2->tx_last_mss = mss;
1893 }
1894 }
1895
1896 ctrl = 0;
1897
1898 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1899 if (vlan_tx_tag_present(skb)) {
1900 if (!le) {
1901 le = get_tx_le(sky2, &slot);
1902 le->addr = 0;
1903 le->opcode = OP_VLAN|HW_OWNER;
1904 } else
1905 le->opcode |= OP_VLAN;
1906 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1907 ctrl |= INS_VLAN;
1908 }
1909
1910 /* Handle TCP checksum offload */
1911 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1912 /* On Yukon EX (some versions) encoding change. */
1913 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1914 ctrl |= CALSUM; /* auto checksum */
1915 else {
1916 const unsigned offset = skb_transport_offset(skb);
1917 u32 tcpsum;
1918
1919 tcpsum = offset << 16; /* sum start */
1920 tcpsum |= offset + skb->csum_offset; /* sum write */
1921
1922 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1923 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1924 ctrl |= UDPTCP;
1925
1926 if (tcpsum != sky2->tx_tcpsum) {
1927 sky2->tx_tcpsum = tcpsum;
1928
1929 le = get_tx_le(sky2, &slot);
1930 le->addr = cpu_to_le32(tcpsum);
1931 le->length = 0; /* initial checksum value */
1932 le->ctrl = 1; /* one packet */
1933 le->opcode = OP_TCPLISW | HW_OWNER;
1934 }
1935 }
1936 }
1937
1938 re = sky2->tx_ring + slot;
1939 re->flags = TX_MAP_SINGLE;
1940 dma_unmap_addr_set(re, mapaddr, mapping);
1941 dma_unmap_len_set(re, maplen, len);
1942
1943 le = get_tx_le(sky2, &slot);
1944 le->addr = cpu_to_le32(lower_32_bits(mapping));
1945 le->length = cpu_to_le16(len);
1946 le->ctrl = ctrl;
1947 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1948
1949
1950 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1951 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1952
1953 mapping = skb_frag_dma_map(&hw->pdev->dev, frag, 0,
1954 skb_frag_size(frag), DMA_TO_DEVICE);
1955
1956 if (dma_mapping_error(&hw->pdev->dev, mapping))
1957 goto mapping_unwind;
1958
1959 upper = upper_32_bits(mapping);
1960 if (upper != sky2->tx_last_upper) {
1961 le = get_tx_le(sky2, &slot);
1962 le->addr = cpu_to_le32(upper);
1963 sky2->tx_last_upper = upper;
1964 le->opcode = OP_ADDR64 | HW_OWNER;
1965 }
1966
1967 re = sky2->tx_ring + slot;
1968 re->flags = TX_MAP_PAGE;
1969 dma_unmap_addr_set(re, mapaddr, mapping);
1970 dma_unmap_len_set(re, maplen, skb_frag_size(frag));
1971
1972 le = get_tx_le(sky2, &slot);
1973 le->addr = cpu_to_le32(lower_32_bits(mapping));
1974 le->length = cpu_to_le16(skb_frag_size(frag));
1975 le->ctrl = ctrl;
1976 le->opcode = OP_BUFFER | HW_OWNER;
1977 }
1978
1979 re->skb = skb;
1980 le->ctrl |= EOP;
1981
1982 sky2->tx_prod = slot;
1983
1984 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1985 netif_stop_queue(dev);
1986
1987 netdev_sent_queue(dev, skb->len);
1988 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1989
1990 return NETDEV_TX_OK;
1991
1992 mapping_unwind:
1993 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
1994 re = sky2->tx_ring + i;
1995
1996 sky2_tx_unmap(hw->pdev, re);
1997 }
1998
1999 mapping_error:
2000 if (net_ratelimit())
2001 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
2002 dev_kfree_skb(skb);
2003 return NETDEV_TX_OK;
2004 }
2005
2006 /*
2007 * Free ring elements from starting at tx_cons until "done"
2008 *
2009 * NB:
2010 * 1. The hardware will tell us about partial completion of multi-part
2011 * buffers so make sure not to free skb to early.
2012 * 2. This may run in parallel start_xmit because the it only
2013 * looks at the tail of the queue of FIFO (tx_cons), not
2014 * the head (tx_prod)
2015 */
2016 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
2017 {
2018 struct net_device *dev = sky2->netdev;
2019 u16 idx;
2020 unsigned int bytes_compl = 0, pkts_compl = 0;
2021
2022 BUG_ON(done >= sky2->tx_ring_size);
2023
2024 for (idx = sky2->tx_cons; idx != done;
2025 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
2026 struct tx_ring_info *re = sky2->tx_ring + idx;
2027 struct sk_buff *skb = re->skb;
2028
2029 sky2_tx_unmap(sky2->hw->pdev, re);
2030
2031 if (skb) {
2032 netif_printk(sky2, tx_done, KERN_DEBUG, dev,
2033 "tx done %u\n", idx);
2034
2035 pkts_compl++;
2036 bytes_compl += skb->len;
2037
2038 re->skb = NULL;
2039 dev_kfree_skb_any(skb);
2040
2041 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
2042 }
2043 }
2044
2045 sky2->tx_cons = idx;
2046 smp_mb();
2047
2048 netdev_completed_queue(dev, pkts_compl, bytes_compl);
2049
2050 u64_stats_update_begin(&sky2->tx_stats.syncp);
2051 sky2->tx_stats.packets += pkts_compl;
2052 sky2->tx_stats.bytes += bytes_compl;
2053 u64_stats_update_end(&sky2->tx_stats.syncp);
2054 }
2055
2056 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
2057 {
2058 /* Disable Force Sync bit and Enable Alloc bit */
2059 sky2_write8(hw, SK_REG(port, TXA_CTRL),
2060 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2061
2062 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2063 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2064 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2065
2066 /* Reset the PCI FIFO of the async Tx queue */
2067 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
2068 BMU_RST_SET | BMU_FIFO_RST);
2069
2070 /* Reset the Tx prefetch units */
2071 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
2072 PREF_UNIT_RST_SET);
2073
2074 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2075 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2076
2077 sky2_read32(hw, B0_CTST);
2078 }
2079
2080 static void sky2_hw_down(struct sky2_port *sky2)
2081 {
2082 struct sky2_hw *hw = sky2->hw;
2083 unsigned port = sky2->port;
2084 u16 ctrl;
2085
2086 /* Force flow control off */
2087 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2088
2089 /* Stop transmitter */
2090 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
2091 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
2092
2093 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2094 RB_RST_SET | RB_DIS_OP_MD);
2095
2096 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2097 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
2098 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2099
2100 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2101
2102 /* Workaround shared GMAC reset */
2103 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
2104 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
2105 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2106
2107 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2108
2109 /* Force any delayed status interrupt and NAPI */
2110 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
2111 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
2112 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
2113 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
2114
2115 sky2_rx_stop(sky2);
2116
2117 spin_lock_bh(&sky2->phy_lock);
2118 sky2_phy_power_down(hw, port);
2119 spin_unlock_bh(&sky2->phy_lock);
2120
2121 sky2_tx_reset(hw, port);
2122
2123 /* Free any pending frames stuck in HW queue */
2124 sky2_tx_complete(sky2, sky2->tx_prod);
2125 }
2126
2127 /* Network shutdown */
2128 static int sky2_close(struct net_device *dev)
2129 {
2130 struct sky2_port *sky2 = netdev_priv(dev);
2131 struct sky2_hw *hw = sky2->hw;
2132
2133 /* Never really got started! */
2134 if (!sky2->tx_le)
2135 return 0;
2136
2137 netif_info(sky2, ifdown, dev, "disabling interface\n");
2138
2139 if (hw->ports == 1) {
2140 sky2_write32(hw, B0_IMSK, 0);
2141 sky2_read32(hw, B0_IMSK);
2142
2143 napi_disable(&hw->napi);
2144 free_irq(hw->pdev->irq, hw);
2145 hw->flags &= ~SKY2_HW_IRQ_SETUP;
2146 } else {
2147 u32 imask;
2148
2149 /* Disable port IRQ */
2150 imask = sky2_read32(hw, B0_IMSK);
2151 imask &= ~portirq_msk[sky2->port];
2152 sky2_write32(hw, B0_IMSK, imask);
2153 sky2_read32(hw, B0_IMSK);
2154
2155 synchronize_irq(hw->pdev->irq);
2156 napi_synchronize(&hw->napi);
2157 }
2158
2159 sky2_hw_down(sky2);
2160
2161 sky2_free_buffers(sky2);
2162
2163 return 0;
2164 }
2165
2166 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
2167 {
2168 if (hw->flags & SKY2_HW_FIBRE_PHY)
2169 return SPEED_1000;
2170
2171 if (!(hw->flags & SKY2_HW_GIGABIT)) {
2172 if (aux & PHY_M_PS_SPEED_100)
2173 return SPEED_100;
2174 else
2175 return SPEED_10;
2176 }
2177
2178 switch (aux & PHY_M_PS_SPEED_MSK) {
2179 case PHY_M_PS_SPEED_1000:
2180 return SPEED_1000;
2181 case PHY_M_PS_SPEED_100:
2182 return SPEED_100;
2183 default:
2184 return SPEED_10;
2185 }
2186 }
2187
2188 static void sky2_link_up(struct sky2_port *sky2)
2189 {
2190 struct sky2_hw *hw = sky2->hw;
2191 unsigned port = sky2->port;
2192 static const char *fc_name[] = {
2193 [FC_NONE] = "none",
2194 [FC_TX] = "tx",
2195 [FC_RX] = "rx",
2196 [FC_BOTH] = "both",
2197 };
2198
2199 sky2_set_ipg(sky2);
2200
2201 sky2_enable_rx_tx(sky2);
2202
2203 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
2204
2205 netif_carrier_on(sky2->netdev);
2206
2207 mod_timer(&hw->watchdog_timer, jiffies + 1);
2208
2209 /* Turn on link LED */
2210 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
2211 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
2212
2213 netif_info(sky2, link, sky2->netdev,
2214 "Link is up at %d Mbps, %s duplex, flow control %s\n",
2215 sky2->speed,
2216 sky2->duplex == DUPLEX_FULL ? "full" : "half",
2217 fc_name[sky2->flow_status]);
2218 }
2219
2220 static void sky2_link_down(struct sky2_port *sky2)
2221 {
2222 struct sky2_hw *hw = sky2->hw;
2223 unsigned port = sky2->port;
2224 u16 reg;
2225
2226 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2227
2228 reg = gma_read16(hw, port, GM_GP_CTRL);
2229 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2230 gma_write16(hw, port, GM_GP_CTRL, reg);
2231
2232 netif_carrier_off(sky2->netdev);
2233
2234 /* Turn off link LED */
2235 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2236
2237 netif_info(sky2, link, sky2->netdev, "Link is down\n");
2238
2239 sky2_phy_init(hw, port);
2240 }
2241
2242 static enum flow_control sky2_flow(int rx, int tx)
2243 {
2244 if (rx)
2245 return tx ? FC_BOTH : FC_RX;
2246 else
2247 return tx ? FC_TX : FC_NONE;
2248 }
2249
2250 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2251 {
2252 struct sky2_hw *hw = sky2->hw;
2253 unsigned port = sky2->port;
2254 u16 advert, lpa;
2255
2256 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2257 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
2258 if (lpa & PHY_M_AN_RF) {
2259 netdev_err(sky2->netdev, "remote fault\n");
2260 return -1;
2261 }
2262
2263 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2264 netdev_err(sky2->netdev, "speed/duplex mismatch\n");
2265 return -1;
2266 }
2267
2268 sky2->speed = sky2_phy_speed(hw, aux);
2269 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2270
2271 /* Since the pause result bits seem to in different positions on
2272 * different chips. look at registers.
2273 */
2274 if (hw->flags & SKY2_HW_FIBRE_PHY) {
2275 /* Shift for bits in fiber PHY */
2276 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2277 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2278
2279 if (advert & ADVERTISE_1000XPAUSE)
2280 advert |= ADVERTISE_PAUSE_CAP;
2281 if (advert & ADVERTISE_1000XPSE_ASYM)
2282 advert |= ADVERTISE_PAUSE_ASYM;
2283 if (lpa & LPA_1000XPAUSE)
2284 lpa |= LPA_PAUSE_CAP;
2285 if (lpa & LPA_1000XPAUSE_ASYM)
2286 lpa |= LPA_PAUSE_ASYM;
2287 }
2288
2289 sky2->flow_status = FC_NONE;
2290 if (advert & ADVERTISE_PAUSE_CAP) {
2291 if (lpa & LPA_PAUSE_CAP)
2292 sky2->flow_status = FC_BOTH;
2293 else if (advert & ADVERTISE_PAUSE_ASYM)
2294 sky2->flow_status = FC_RX;
2295 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2296 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2297 sky2->flow_status = FC_TX;
2298 }
2299
2300 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2301 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2302 sky2->flow_status = FC_NONE;
2303
2304 if (sky2->flow_status & FC_TX)
2305 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2306 else
2307 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2308
2309 return 0;
2310 }
2311
2312 /* Interrupt from PHY */
2313 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2314 {
2315 struct net_device *dev = hw->dev[port];
2316 struct sky2_port *sky2 = netdev_priv(dev);
2317 u16 istatus, phystat;
2318
2319 if (!netif_running(dev))
2320 return;
2321
2322 spin_lock(&sky2->phy_lock);
2323 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2324 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2325
2326 netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n",
2327 istatus, phystat);
2328
2329 if (istatus & PHY_M_IS_AN_COMPL) {
2330 if (sky2_autoneg_done(sky2, phystat) == 0 &&
2331 !netif_carrier_ok(dev))
2332 sky2_link_up(sky2);
2333 goto out;
2334 }
2335
2336 if (istatus & PHY_M_IS_LSP_CHANGE)
2337 sky2->speed = sky2_phy_speed(hw, phystat);
2338
2339 if (istatus & PHY_M_IS_DUP_CHANGE)
2340 sky2->duplex =
2341 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2342
2343 if (istatus & PHY_M_IS_LST_CHANGE) {
2344 if (phystat & PHY_M_PS_LINK_UP)
2345 sky2_link_up(sky2);
2346 else
2347 sky2_link_down(sky2);
2348 }
2349 out:
2350 spin_unlock(&sky2->phy_lock);
2351 }
2352
2353 /* Special quick link interrupt (Yukon-2 Optima only) */
2354 static void sky2_qlink_intr(struct sky2_hw *hw)
2355 {
2356 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2357 u32 imask;
2358 u16 phy;
2359
2360 /* disable irq */
2361 imask = sky2_read32(hw, B0_IMSK);
2362 imask &= ~Y2_IS_PHY_QLNK;
2363 sky2_write32(hw, B0_IMSK, imask);
2364
2365 /* reset PHY Link Detect */
2366 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
2367 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2368 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
2369 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2370
2371 sky2_link_up(sky2);
2372 }
2373
2374 /* Transmit timeout is only called if we are running, carrier is up
2375 * and tx queue is full (stopped).
2376 */
2377 static void sky2_tx_timeout(struct net_device *dev)
2378 {
2379 struct sky2_port *sky2 = netdev_priv(dev);
2380 struct sky2_hw *hw = sky2->hw;
2381
2382 netif_err(sky2, timer, dev, "tx timeout\n");
2383
2384 netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n",
2385 sky2->tx_cons, sky2->tx_prod,
2386 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2387 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2388
2389 /* can't restart safely under softirq */
2390 schedule_work(&hw->restart_work);
2391 }
2392
2393 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2394 {
2395 struct sky2_port *sky2 = netdev_priv(dev);
2396 struct sky2_hw *hw = sky2->hw;
2397 unsigned port = sky2->port;
2398 int err;
2399 u16 ctl, mode;
2400 u32 imask;
2401
2402 /* MTU size outside the spec */
2403 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2404 return -EINVAL;
2405
2406 /* MTU > 1500 on yukon FE and FE+ not allowed */
2407 if (new_mtu > ETH_DATA_LEN &&
2408 (hw->chip_id == CHIP_ID_YUKON_FE ||
2409 hw->chip_id == CHIP_ID_YUKON_FE_P))
2410 return -EINVAL;
2411
2412 if (!netif_running(dev)) {
2413 dev->mtu = new_mtu;
2414 netdev_update_features(dev);
2415 return 0;
2416 }
2417
2418 imask = sky2_read32(hw, B0_IMSK);
2419 sky2_write32(hw, B0_IMSK, 0);
2420
2421 dev->trans_start = jiffies; /* prevent tx timeout */
2422 napi_disable(&hw->napi);
2423 netif_tx_disable(dev);
2424
2425 synchronize_irq(hw->pdev->irq);
2426
2427 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2428 sky2_set_tx_stfwd(hw, port);
2429
2430 ctl = gma_read16(hw, port, GM_GP_CTRL);
2431 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2432 sky2_rx_stop(sky2);
2433 sky2_rx_clean(sky2);
2434
2435 dev->mtu = new_mtu;
2436 netdev_update_features(dev);
2437
2438 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | GM_SMOD_VLAN_ENA;
2439 if (sky2->speed > SPEED_100)
2440 mode |= IPG_DATA_VAL(IPG_DATA_DEF_1000);
2441 else
2442 mode |= IPG_DATA_VAL(IPG_DATA_DEF_10_100);
2443
2444 if (dev->mtu > ETH_DATA_LEN)
2445 mode |= GM_SMOD_JUMBO_ENA;
2446
2447 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2448
2449 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2450
2451 err = sky2_alloc_rx_skbs(sky2);
2452 if (!err)
2453 sky2_rx_start(sky2);
2454 else
2455 sky2_rx_clean(sky2);
2456 sky2_write32(hw, B0_IMSK, imask);
2457
2458 sky2_read32(hw, B0_Y2_SP_LISR);
2459 napi_enable(&hw->napi);
2460
2461 if (err)
2462 dev_close(dev);
2463 else {
2464 gma_write16(hw, port, GM_GP_CTRL, ctl);
2465
2466 netif_wake_queue(dev);
2467 }
2468
2469 return err;
2470 }
2471
2472 static inline bool needs_copy(const struct rx_ring_info *re,
2473 unsigned length)
2474 {
2475 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2476 /* Some architectures need the IP header to be aligned */
2477 if (!IS_ALIGNED(re->data_addr + ETH_HLEN, sizeof(u32)))
2478 return true;
2479 #endif
2480 return length < copybreak;
2481 }
2482
2483 /* For small just reuse existing skb for next receive */
2484 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2485 const struct rx_ring_info *re,
2486 unsigned length)
2487 {
2488 struct sk_buff *skb;
2489
2490 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
2491 if (likely(skb)) {
2492 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2493 length, PCI_DMA_FROMDEVICE);
2494 skb_copy_from_linear_data(re->skb, skb->data, length);
2495 skb->ip_summed = re->skb->ip_summed;
2496 skb->csum = re->skb->csum;
2497 skb->rxhash = re->skb->rxhash;
2498 skb->vlan_tci = re->skb->vlan_tci;
2499
2500 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2501 length, PCI_DMA_FROMDEVICE);
2502 re->skb->vlan_tci = 0;
2503 re->skb->rxhash = 0;
2504 re->skb->ip_summed = CHECKSUM_NONE;
2505 skb_put(skb, length);
2506 }
2507 return skb;
2508 }
2509
2510 /* Adjust length of skb with fragments to match received data */
2511 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2512 unsigned int length)
2513 {
2514 int i, num_frags;
2515 unsigned int size;
2516
2517 /* put header into skb */
2518 size = min(length, hdr_space);
2519 skb->tail += size;
2520 skb->len += size;
2521 length -= size;
2522
2523 num_frags = skb_shinfo(skb)->nr_frags;
2524 for (i = 0; i < num_frags; i++) {
2525 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2526
2527 if (length == 0) {
2528 /* don't need this page */
2529 __skb_frag_unref(frag);
2530 --skb_shinfo(skb)->nr_frags;
2531 } else {
2532 size = min(length, (unsigned) PAGE_SIZE);
2533
2534 skb_frag_size_set(frag, size);
2535 skb->data_len += size;
2536 skb->truesize += PAGE_SIZE;
2537 skb->len += size;
2538 length -= size;
2539 }
2540 }
2541 }
2542
2543 /* Normal packet - take skb from ring element and put in a new one */
2544 static struct sk_buff *receive_new(struct sky2_port *sky2,
2545 struct rx_ring_info *re,
2546 unsigned int length)
2547 {
2548 struct sk_buff *skb;
2549 struct rx_ring_info nre;
2550 unsigned hdr_space = sky2->rx_data_size;
2551
2552 nre.skb = sky2_rx_alloc(sky2, GFP_ATOMIC);
2553 if (unlikely(!nre.skb))
2554 goto nobuf;
2555
2556 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space))
2557 goto nomap;
2558
2559 skb = re->skb;
2560 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2561 prefetch(skb->data);
2562 *re = nre;
2563
2564 if (skb_shinfo(skb)->nr_frags)
2565 skb_put_frags(skb, hdr_space, length);
2566 else
2567 skb_put(skb, length);
2568 return skb;
2569
2570 nomap:
2571 dev_kfree_skb(nre.skb);
2572 nobuf:
2573 return NULL;
2574 }
2575
2576 /*
2577 * Receive one packet.
2578 * For larger packets, get new buffer.
2579 */
2580 static struct sk_buff *sky2_receive(struct net_device *dev,
2581 u16 length, u32 status)
2582 {
2583 struct sky2_port *sky2 = netdev_priv(dev);
2584 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2585 struct sk_buff *skb = NULL;
2586 u16 count = (status & GMR_FS_LEN) >> 16;
2587
2588 netif_printk(sky2, rx_status, KERN_DEBUG, dev,
2589 "rx slot %u status 0x%x len %d\n",
2590 sky2->rx_next, status, length);
2591
2592 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2593 prefetch(sky2->rx_ring + sky2->rx_next);
2594
2595 if (vlan_tx_tag_present(re->skb))
2596 count -= VLAN_HLEN; /* Account for vlan tag */
2597
2598 /* This chip has hardware problems that generates bogus status.
2599 * So do only marginal checking and expect higher level protocols
2600 * to handle crap frames.
2601 */
2602 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2603 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2604 length != count)
2605 goto okay;
2606
2607 if (status & GMR_FS_ANY_ERR)
2608 goto error;
2609
2610 if (!(status & GMR_FS_RX_OK))
2611 goto resubmit;
2612
2613 /* if length reported by DMA does not match PHY, packet was truncated */
2614 if (length != count)
2615 goto error;
2616
2617 okay:
2618 if (needs_copy(re, length))
2619 skb = receive_copy(sky2, re, length);
2620 else
2621 skb = receive_new(sky2, re, length);
2622
2623 dev->stats.rx_dropped += (skb == NULL);
2624
2625 resubmit:
2626 sky2_rx_submit(sky2, re);
2627
2628 return skb;
2629
2630 error:
2631 ++dev->stats.rx_errors;
2632
2633 if (net_ratelimit())
2634 netif_info(sky2, rx_err, dev,
2635 "rx error, status 0x%x length %d\n", status, length);
2636
2637 goto resubmit;
2638 }
2639
2640 /* Transmit complete */
2641 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2642 {
2643 struct sky2_port *sky2 = netdev_priv(dev);
2644
2645 if (netif_running(dev)) {
2646 sky2_tx_complete(sky2, last);
2647
2648 /* Wake unless it's detached, and called e.g. from sky2_close() */
2649 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
2650 netif_wake_queue(dev);
2651 }
2652 }
2653
2654 static inline void sky2_skb_rx(const struct sky2_port *sky2,
2655 struct sk_buff *skb)
2656 {
2657 if (skb->ip_summed == CHECKSUM_NONE)
2658 netif_receive_skb(skb);
2659 else
2660 napi_gro_receive(&sky2->hw->napi, skb);
2661 }
2662
2663 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2664 unsigned packets, unsigned bytes)
2665 {
2666 struct net_device *dev = hw->dev[port];
2667 struct sky2_port *sky2 = netdev_priv(dev);
2668
2669 if (packets == 0)
2670 return;
2671
2672 u64_stats_update_begin(&sky2->rx_stats.syncp);
2673 sky2->rx_stats.packets += packets;
2674 sky2->rx_stats.bytes += bytes;
2675 u64_stats_update_end(&sky2->rx_stats.syncp);
2676
2677 dev->last_rx = jiffies;
2678 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2679 }
2680
2681 static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
2682 {
2683 /* If this happens then driver assuming wrong format for chip type */
2684 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE);
2685
2686 /* Both checksum counters are programmed to start at
2687 * the same offset, so unless there is a problem they
2688 * should match. This failure is an early indication that
2689 * hardware receive checksumming won't work.
2690 */
2691 if (likely((u16)(status >> 16) == (u16)status)) {
2692 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb;
2693 skb->ip_summed = CHECKSUM_COMPLETE;
2694 skb->csum = le16_to_cpu(status);
2695 } else {
2696 dev_notice(&sky2->hw->pdev->dev,
2697 "%s: receive checksum problem (status = %#x)\n",
2698 sky2->netdev->name, status);
2699
2700 /* Disable checksum offload
2701 * It will be reenabled on next ndo_set_features, but if it's
2702 * really broken, will get disabled again
2703 */
2704 sky2->netdev->features &= ~NETIF_F_RXCSUM;
2705 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2706 BMU_DIS_RX_CHKSUM);
2707 }
2708 }
2709
2710 static void sky2_rx_tag(struct sky2_port *sky2, u16 length)
2711 {
2712 struct sk_buff *skb;
2713
2714 skb = sky2->rx_ring[sky2->rx_next].skb;
2715 __vlan_hwaccel_put_tag(skb, be16_to_cpu(length));
2716 }
2717
2718 static void sky2_rx_hash(struct sky2_port *sky2, u32 status)
2719 {
2720 struct sk_buff *skb;
2721
2722 skb = sky2->rx_ring[sky2->rx_next].skb;
2723 skb->rxhash = le32_to_cpu(status);
2724 }
2725
2726 /* Process status response ring */
2727 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2728 {
2729 int work_done = 0;
2730 unsigned int total_bytes[2] = { 0 };
2731 unsigned int total_packets[2] = { 0 };
2732
2733 rmb();
2734 do {
2735 struct sky2_port *sky2;
2736 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2737 unsigned port;
2738 struct net_device *dev;
2739 struct sk_buff *skb;
2740 u32 status;
2741 u16 length;
2742 u8 opcode = le->opcode;
2743
2744 if (!(opcode & HW_OWNER))
2745 break;
2746
2747 hw->st_idx = RING_NEXT(hw->st_idx, hw->st_size);
2748
2749 port = le->css & CSS_LINK_BIT;
2750 dev = hw->dev[port];
2751 sky2 = netdev_priv(dev);
2752 length = le16_to_cpu(le->length);
2753 status = le32_to_cpu(le->status);
2754
2755 le->opcode = 0;
2756 switch (opcode & ~HW_OWNER) {
2757 case OP_RXSTAT:
2758 total_packets[port]++;
2759 total_bytes[port] += length;
2760
2761 skb = sky2_receive(dev, length, status);
2762 if (!skb)
2763 break;
2764
2765 /* This chip reports checksum status differently */
2766 if (hw->flags & SKY2_HW_NEW_LE) {
2767 if ((dev->features & NETIF_F_RXCSUM) &&
2768 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2769 (le->css & CSS_TCPUDPCSOK))
2770 skb->ip_summed = CHECKSUM_UNNECESSARY;
2771 else
2772 skb->ip_summed = CHECKSUM_NONE;
2773 }
2774
2775 skb->protocol = eth_type_trans(skb, dev);
2776 sky2_skb_rx(sky2, skb);
2777
2778 /* Stop after net poll weight */
2779 if (++work_done >= to_do)
2780 goto exit_loop;
2781 break;
2782
2783 case OP_RXVLAN:
2784 sky2_rx_tag(sky2, length);
2785 break;
2786
2787 case OP_RXCHKSVLAN:
2788 sky2_rx_tag(sky2, length);
2789 /* fall through */
2790 case OP_RXCHKS:
2791 if (likely(dev->features & NETIF_F_RXCSUM))
2792 sky2_rx_checksum(sky2, status);
2793 break;
2794
2795 case OP_RSS_HASH:
2796 sky2_rx_hash(sky2, status);
2797 break;
2798
2799 case OP_TXINDEXLE:
2800 /* TX index reports status for both ports */
2801 sky2_tx_done(hw->dev[0], status & 0xfff);
2802 if (hw->dev[1])
2803 sky2_tx_done(hw->dev[1],
2804 ((status >> 24) & 0xff)
2805 | (u16)(length & 0xf) << 8);
2806 break;
2807
2808 default:
2809 if (net_ratelimit())
2810 pr_warning("unknown status opcode 0x%x\n", opcode);
2811 }
2812 } while (hw->st_idx != idx);
2813
2814 /* Fully processed status ring so clear irq */
2815 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2816
2817 exit_loop:
2818 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2819 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
2820
2821 return work_done;
2822 }
2823
2824 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2825 {
2826 struct net_device *dev = hw->dev[port];
2827
2828 if (net_ratelimit())
2829 netdev_info(dev, "hw error interrupt status 0x%x\n", status);
2830
2831 if (status & Y2_IS_PAR_RD1) {
2832 if (net_ratelimit())
2833 netdev_err(dev, "ram data read parity error\n");
2834 /* Clear IRQ */
2835 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2836 }
2837
2838 if (status & Y2_IS_PAR_WR1) {
2839 if (net_ratelimit())
2840 netdev_err(dev, "ram data write parity error\n");
2841
2842 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2843 }
2844
2845 if (status & Y2_IS_PAR_MAC1) {
2846 if (net_ratelimit())
2847 netdev_err(dev, "MAC parity error\n");
2848 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2849 }
2850
2851 if (status & Y2_IS_PAR_RX1) {
2852 if (net_ratelimit())
2853 netdev_err(dev, "RX parity error\n");
2854 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2855 }
2856
2857 if (status & Y2_IS_TCP_TXA1) {
2858 if (net_ratelimit())
2859 netdev_err(dev, "TCP segmentation error\n");
2860 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2861 }
2862 }
2863
2864 static void sky2_hw_intr(struct sky2_hw *hw)
2865 {
2866 struct pci_dev *pdev = hw->pdev;
2867 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2868 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2869
2870 status &= hwmsk;
2871
2872 if (status & Y2_IS_TIST_OV)
2873 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2874
2875 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2876 u16 pci_err;
2877
2878 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2879 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2880 if (net_ratelimit())
2881 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2882 pci_err);
2883
2884 sky2_pci_write16(hw, PCI_STATUS,
2885 pci_err | PCI_STATUS_ERROR_BITS);
2886 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2887 }
2888
2889 if (status & Y2_IS_PCI_EXP) {
2890 /* PCI-Express uncorrectable Error occurred */
2891 u32 err;
2892
2893 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2894 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2895 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2896 0xfffffffful);
2897 if (net_ratelimit())
2898 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2899
2900 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2901 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2902 }
2903
2904 if (status & Y2_HWE_L1_MASK)
2905 sky2_hw_error(hw, 0, status);
2906 status >>= 8;
2907 if (status & Y2_HWE_L1_MASK)
2908 sky2_hw_error(hw, 1, status);
2909 }
2910
2911 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2912 {
2913 struct net_device *dev = hw->dev[port];
2914 struct sky2_port *sky2 = netdev_priv(dev);
2915 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2916
2917 netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status);
2918
2919 if (status & GM_IS_RX_CO_OV)
2920 gma_read16(hw, port, GM_RX_IRQ_SRC);
2921
2922 if (status & GM_IS_TX_CO_OV)
2923 gma_read16(hw, port, GM_TX_IRQ_SRC);
2924
2925 if (status & GM_IS_RX_FF_OR) {
2926 ++dev->stats.rx_fifo_errors;
2927 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2928 }
2929
2930 if (status & GM_IS_TX_FF_UR) {
2931 ++dev->stats.tx_fifo_errors;
2932 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2933 }
2934 }
2935
2936 /* This should never happen it is a bug. */
2937 static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
2938 {
2939 struct net_device *dev = hw->dev[port];
2940 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2941
2942 dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n",
2943 dev->name, (unsigned) q, (unsigned) idx,
2944 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2945
2946 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2947 }
2948
2949 static int sky2_rx_hung(struct net_device *dev)
2950 {
2951 struct sky2_port *sky2 = netdev_priv(dev);
2952 struct sky2_hw *hw = sky2->hw;
2953 unsigned port = sky2->port;
2954 unsigned rxq = rxqaddr[port];
2955 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2956 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2957 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2958 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2959
2960 /* If idle and MAC or PCI is stuck */
2961 if (sky2->check.last == dev->last_rx &&
2962 ((mac_rp == sky2->check.mac_rp &&
2963 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2964 /* Check if the PCI RX hang */
2965 (fifo_rp == sky2->check.fifo_rp &&
2966 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2967 netdev_printk(KERN_DEBUG, dev,
2968 "hung mac %d:%d fifo %d (%d:%d)\n",
2969 mac_lev, mac_rp, fifo_lev,
2970 fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2971 return 1;
2972 } else {
2973 sky2->check.last = dev->last_rx;
2974 sky2->check.mac_rp = mac_rp;
2975 sky2->check.mac_lev = mac_lev;
2976 sky2->check.fifo_rp = fifo_rp;
2977 sky2->check.fifo_lev = fifo_lev;
2978 return 0;
2979 }
2980 }
2981
2982 static void sky2_watchdog(unsigned long arg)
2983 {
2984 struct sky2_hw *hw = (struct sky2_hw *) arg;
2985
2986 /* Check for lost IRQ once a second */
2987 if (sky2_read32(hw, B0_ISRC)) {
2988 napi_schedule(&hw->napi);
2989 } else {
2990 int i, active = 0;
2991
2992 for (i = 0; i < hw->ports; i++) {
2993 struct net_device *dev = hw->dev[i];
2994 if (!netif_running(dev))
2995 continue;
2996 ++active;
2997
2998 /* For chips with Rx FIFO, check if stuck */
2999 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
3000 sky2_rx_hung(dev)) {
3001 netdev_info(dev, "receiver hang detected\n");
3002 schedule_work(&hw->restart_work);
3003 return;
3004 }
3005 }
3006
3007 if (active == 0)
3008 return;
3009 }
3010
3011 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
3012 }
3013
3014 /* Hardware/software error handling */
3015 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
3016 {
3017 if (net_ratelimit())
3018 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
3019
3020 if (status & Y2_IS_HW_ERR)
3021 sky2_hw_intr(hw);
3022
3023 if (status & Y2_IS_IRQ_MAC1)
3024 sky2_mac_intr(hw, 0);
3025
3026 if (status & Y2_IS_IRQ_MAC2)
3027 sky2_mac_intr(hw, 1);
3028
3029 if (status & Y2_IS_CHK_RX1)
3030 sky2_le_error(hw, 0, Q_R1);
3031
3032 if (status & Y2_IS_CHK_RX2)
3033 sky2_le_error(hw, 1, Q_R2);
3034
3035 if (status & Y2_IS_CHK_TXA1)
3036 sky2_le_error(hw, 0, Q_XA1);
3037
3038 if (status & Y2_IS_CHK_TXA2)
3039 sky2_le_error(hw, 1, Q_XA2);
3040 }
3041
3042 static int sky2_poll(struct napi_struct *napi, int work_limit)
3043 {
3044 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
3045 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
3046 int work_done = 0;
3047 u16 idx;
3048
3049 if (unlikely(status & Y2_IS_ERROR))
3050 sky2_err_intr(hw, status);
3051
3052 if (status & Y2_IS_IRQ_PHY1)
3053 sky2_phy_intr(hw, 0);
3054
3055 if (status & Y2_IS_IRQ_PHY2)
3056 sky2_phy_intr(hw, 1);
3057
3058 if (status & Y2_IS_PHY_QLNK)
3059 sky2_qlink_intr(hw);
3060
3061 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
3062 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
3063
3064 if (work_done >= work_limit)
3065 goto done;
3066 }
3067
3068 napi_complete(napi);
3069 sky2_read32(hw, B0_Y2_SP_LISR);
3070 done:
3071
3072 return work_done;
3073 }
3074
3075 static irqreturn_t sky2_intr(int irq, void *dev_id)
3076 {
3077 struct sky2_hw *hw = dev_id;
3078 u32 status;
3079
3080 /* Reading this mask interrupts as side effect */
3081 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3082 if (status == 0 || status == ~0) {
3083 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3084 return IRQ_NONE;
3085 }
3086
3087 prefetch(&hw->st_le[hw->st_idx]);
3088
3089 napi_schedule(&hw->napi);
3090
3091 return IRQ_HANDLED;
3092 }
3093
3094 #ifdef CONFIG_NET_POLL_CONTROLLER
3095 static void sky2_netpoll(struct net_device *dev)
3096 {
3097 struct sky2_port *sky2 = netdev_priv(dev);
3098
3099 napi_schedule(&sky2->hw->napi);
3100 }
3101 #endif
3102
3103 /* Chip internal frequency for clock calculations */
3104 static u32 sky2_mhz(const struct sky2_hw *hw)
3105 {
3106 switch (hw->chip_id) {
3107 case CHIP_ID_YUKON_EC:
3108 case CHIP_ID_YUKON_EC_U:
3109 case CHIP_ID_YUKON_EX:
3110 case CHIP_ID_YUKON_SUPR:
3111 case CHIP_ID_YUKON_UL_2:
3112 case CHIP_ID_YUKON_OPT:
3113 case CHIP_ID_YUKON_PRM:
3114 case CHIP_ID_YUKON_OP_2:
3115 return 125;
3116
3117 case CHIP_ID_YUKON_FE:
3118 return 100;
3119
3120 case CHIP_ID_YUKON_FE_P:
3121 return 50;
3122
3123 case CHIP_ID_YUKON_XL:
3124 return 156;
3125
3126 default:
3127 BUG();
3128 }
3129 }
3130
3131 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
3132 {
3133 return sky2_mhz(hw) * us;
3134 }
3135
3136 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
3137 {
3138 return clk / sky2_mhz(hw);
3139 }
3140
3141
3142 static int __devinit sky2_init(struct sky2_hw *hw)
3143 {
3144 u8 t8;
3145
3146 /* Enable all clocks and check for bad PCI access */
3147 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
3148
3149 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3150
3151 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
3152 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
3153
3154 switch (hw->chip_id) {
3155 case CHIP_ID_YUKON_XL:
3156 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
3157 if (hw->chip_rev < CHIP_REV_YU_XL_A2)
3158 hw->flags |= SKY2_HW_RSS_BROKEN;
3159 break;
3160
3161 case CHIP_ID_YUKON_EC_U:
3162 hw->flags = SKY2_HW_GIGABIT
3163 | SKY2_HW_NEWER_PHY
3164 | SKY2_HW_ADV_POWER_CTL;
3165 break;
3166
3167 case CHIP_ID_YUKON_EX:
3168 hw->flags = SKY2_HW_GIGABIT
3169 | SKY2_HW_NEWER_PHY
3170 | SKY2_HW_NEW_LE
3171 | SKY2_HW_ADV_POWER_CTL
3172 | SKY2_HW_RSS_CHKSUM;
3173
3174 /* New transmit checksum */
3175 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
3176 hw->flags |= SKY2_HW_AUTO_TX_SUM;
3177 break;
3178
3179 case CHIP_ID_YUKON_EC:
3180 /* This rev is really old, and requires untested workarounds */
3181 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
3182 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
3183 return -EOPNOTSUPP;
3184 }
3185 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RSS_BROKEN;
3186 break;
3187
3188 case CHIP_ID_YUKON_FE:
3189 hw->flags = SKY2_HW_RSS_BROKEN;
3190 break;
3191
3192 case CHIP_ID_YUKON_FE_P:
3193 hw->flags = SKY2_HW_NEWER_PHY
3194 | SKY2_HW_NEW_LE
3195 | SKY2_HW_AUTO_TX_SUM
3196 | SKY2_HW_ADV_POWER_CTL;
3197
3198 /* The workaround for status conflicts VLAN tag detection. */
3199 if (hw->chip_rev == CHIP_REV_YU_FE2_A0)
3200 hw->flags |= SKY2_HW_VLAN_BROKEN | SKY2_HW_RSS_CHKSUM;
3201 break;
3202
3203 case CHIP_ID_YUKON_SUPR:
3204 hw->flags = SKY2_HW_GIGABIT
3205 | SKY2_HW_NEWER_PHY
3206 | SKY2_HW_NEW_LE
3207 | SKY2_HW_AUTO_TX_SUM
3208 | SKY2_HW_ADV_POWER_CTL;
3209
3210 if (hw->chip_rev == CHIP_REV_YU_SU_A0)
3211 hw->flags |= SKY2_HW_RSS_CHKSUM;
3212 break;
3213
3214 case CHIP_ID_YUKON_UL_2:
3215 hw->flags = SKY2_HW_GIGABIT
3216 | SKY2_HW_ADV_POWER_CTL;
3217 break;
3218
3219 case CHIP_ID_YUKON_OPT:
3220 case CHIP_ID_YUKON_PRM:
3221 case CHIP_ID_YUKON_OP_2:
3222 hw->flags = SKY2_HW_GIGABIT
3223 | SKY2_HW_NEW_LE
3224 | SKY2_HW_ADV_POWER_CTL;
3225 break;
3226
3227 default:
3228 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3229 hw->chip_id);
3230 return -EOPNOTSUPP;
3231 }
3232
3233 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
3234 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
3235 hw->flags |= SKY2_HW_FIBRE_PHY;
3236
3237 hw->ports = 1;
3238 t8 = sky2_read8(hw, B2_Y2_HW_RES);
3239 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
3240 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3241 ++hw->ports;
3242 }
3243
3244 if (sky2_read8(hw, B2_E_0))
3245 hw->flags |= SKY2_HW_RAM_BUFFER;
3246
3247 return 0;
3248 }
3249
3250 static void sky2_reset(struct sky2_hw *hw)
3251 {
3252 struct pci_dev *pdev = hw->pdev;
3253 u16 status;
3254 int i;
3255 u32 hwe_mask = Y2_HWE_ALL_MASK;
3256
3257 /* disable ASF */
3258 if (hw->chip_id == CHIP_ID_YUKON_EX
3259 || hw->chip_id == CHIP_ID_YUKON_SUPR) {
3260 sky2_write32(hw, CPU_WDOG, 0);
3261 status = sky2_read16(hw, HCU_CCSR);
3262 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3263 HCU_CCSR_UC_STATE_MSK);
3264 /*
3265 * CPU clock divider shouldn't be used because
3266 * - ASF firmware may malfunction
3267 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3268 */
3269 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
3270 sky2_write16(hw, HCU_CCSR, status);
3271 sky2_write32(hw, CPU_WDOG, 0);
3272 } else
3273 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3274 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
3275
3276 /* do a SW reset */
3277 sky2_write8(hw, B0_CTST, CS_RST_SET);
3278 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3279
3280 /* allow writes to PCI config */
3281 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3282
3283 /* clear PCI errors, if any */
3284 status = sky2_pci_read16(hw, PCI_STATUS);
3285 status |= PCI_STATUS_ERROR_BITS;
3286 sky2_pci_write16(hw, PCI_STATUS, status);
3287
3288 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3289
3290 if (pci_is_pcie(pdev)) {
3291 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3292 0xfffffffful);
3293
3294 /* If error bit is stuck on ignore it */
3295 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3296 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
3297 else
3298 hwe_mask |= Y2_IS_PCI_EXP;
3299 }
3300
3301 sky2_power_on(hw);
3302 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3303
3304 for (i = 0; i < hw->ports; i++) {
3305 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3306 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3307
3308 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3309 hw->chip_id == CHIP_ID_YUKON_SUPR)
3310 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3311 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3312 | GMC_BYP_RETR_ON);
3313
3314 }
3315
3316 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3317 /* enable MACSec clock gating */
3318 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
3319 }
3320
3321 if (hw->chip_id == CHIP_ID_YUKON_OPT ||
3322 hw->chip_id == CHIP_ID_YUKON_PRM ||
3323 hw->chip_id == CHIP_ID_YUKON_OP_2) {
3324 u16 reg;
3325
3326 if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
3327 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3328 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3329
3330 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3331 reg = 10;
3332
3333 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3334 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3335 } else {
3336 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3337 reg = 3;
3338 }
3339
3340 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3341 reg |= PSM_CONFIG_REG4_RST_PHY_LINK_DETECT;
3342
3343 /* reset PHY Link Detect */
3344 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3345 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3346
3347 /* check if PSMv2 was running before */
3348 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3349 if (reg & PCI_EXP_LNKCTL_ASPMC)
3350 /* restore the PCIe Link Control register */
3351 sky2_pci_write16(hw, pdev->pcie_cap + PCI_EXP_LNKCTL,
3352 reg);
3353
3354 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3355
3356 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3357 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3358 }
3359
3360 /* Clear I2C IRQ noise */
3361 sky2_write32(hw, B2_I2C_IRQ, 1);
3362
3363 /* turn off hardware timer (unused) */
3364 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3365 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3366
3367 /* Turn off descriptor polling */
3368 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
3369
3370 /* Turn off receive timestamp */
3371 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
3372 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3373
3374 /* enable the Tx Arbiters */
3375 for (i = 0; i < hw->ports; i++)
3376 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3377
3378 /* Initialize ram interface */
3379 for (i = 0; i < hw->ports; i++) {
3380 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
3381
3382 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3383 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3384 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3385 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3386 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3387 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3388 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3389 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3390 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3391 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3392 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3393 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3394 }
3395
3396 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
3397
3398 for (i = 0; i < hw->ports; i++)
3399 sky2_gmac_reset(hw, i);
3400
3401 memset(hw->st_le, 0, hw->st_size * sizeof(struct sky2_status_le));
3402 hw->st_idx = 0;
3403
3404 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3405 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3406
3407 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3408 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3409
3410 /* Set the list last index */
3411 sky2_write16(hw, STAT_LAST_IDX, hw->st_size - 1);
3412
3413 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3414 sky2_write8(hw, STAT_FIFO_WM, 16);
3415
3416 /* set Status-FIFO ISR watermark */
3417 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3418 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3419 else
3420 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
3421
3422 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3423 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3424 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3425
3426 /* enable status unit */
3427 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3428
3429 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3430 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3431 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3432 }
3433
3434 /* Take device down (offline).
3435 * Equivalent to doing dev_stop() but this does not
3436 * inform upper layers of the transition.
3437 */
3438 static void sky2_detach(struct net_device *dev)
3439 {
3440 if (netif_running(dev)) {
3441 netif_tx_lock(dev);
3442 netif_device_detach(dev); /* stop txq */
3443 netif_tx_unlock(dev);
3444 sky2_close(dev);
3445 }
3446 }
3447
3448 /* Bring device back after doing sky2_detach */
3449 static int sky2_reattach(struct net_device *dev)
3450 {
3451 int err = 0;
3452
3453 if (netif_running(dev)) {
3454 err = sky2_open(dev);
3455 if (err) {
3456 netdev_info(dev, "could not restart %d\n", err);
3457 dev_close(dev);
3458 } else {
3459 netif_device_attach(dev);
3460 sky2_set_multicast(dev);
3461 }
3462 }
3463
3464 return err;
3465 }
3466
3467 static void sky2_all_down(struct sky2_hw *hw)
3468 {
3469 int i;
3470
3471 if (hw->flags & SKY2_HW_IRQ_SETUP) {
3472 sky2_read32(hw, B0_IMSK);
3473 sky2_write32(hw, B0_IMSK, 0);
3474
3475 synchronize_irq(hw->pdev->irq);
3476 napi_disable(&hw->napi);
3477 }
3478
3479 for (i = 0; i < hw->ports; i++) {
3480 struct net_device *dev = hw->dev[i];
3481 struct sky2_port *sky2 = netdev_priv(dev);
3482
3483 if (!netif_running(dev))
3484 continue;
3485
3486 netif_carrier_off(dev);
3487 netif_tx_disable(dev);
3488 sky2_hw_down(sky2);
3489 }
3490 }
3491
3492 static void sky2_all_up(struct sky2_hw *hw)
3493 {
3494 u32 imask = Y2_IS_BASE;
3495 int i;
3496
3497 for (i = 0; i < hw->ports; i++) {
3498 struct net_device *dev = hw->dev[i];
3499 struct sky2_port *sky2 = netdev_priv(dev);
3500
3501 if (!netif_running(dev))
3502 continue;
3503
3504 sky2_hw_up(sky2);
3505 sky2_set_multicast(dev);
3506 imask |= portirq_msk[i];
3507 netif_wake_queue(dev);
3508 }
3509
3510 if (hw->flags & SKY2_HW_IRQ_SETUP) {
3511 sky2_write32(hw, B0_IMSK, imask);
3512 sky2_read32(hw, B0_IMSK);
3513 sky2_read32(hw, B0_Y2_SP_LISR);
3514 napi_enable(&hw->napi);
3515 }
3516 }
3517
3518 static void sky2_restart(struct work_struct *work)
3519 {
3520 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3521
3522 rtnl_lock();
3523
3524 sky2_all_down(hw);
3525 sky2_reset(hw);
3526 sky2_all_up(hw);
3527
3528 rtnl_unlock();
3529 }
3530
3531 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3532 {
3533 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3534 }
3535
3536 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3537 {
3538 const struct sky2_port *sky2 = netdev_priv(dev);
3539
3540 wol->supported = sky2_wol_supported(sky2->hw);
3541 wol->wolopts = sky2->wol;
3542 }
3543
3544 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3545 {
3546 struct sky2_port *sky2 = netdev_priv(dev);
3547 struct sky2_hw *hw = sky2->hw;
3548 bool enable_wakeup = false;
3549 int i;
3550
3551 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3552 !device_can_wakeup(&hw->pdev->dev))
3553 return -EOPNOTSUPP;
3554
3555 sky2->wol = wol->wolopts;
3556
3557 for (i = 0; i < hw->ports; i++) {
3558 struct net_device *dev = hw->dev[i];
3559 struct sky2_port *sky2 = netdev_priv(dev);
3560
3561 if (sky2->wol)
3562 enable_wakeup = true;
3563 }
3564 device_set_wakeup_enable(&hw->pdev->dev, enable_wakeup);
3565
3566 return 0;
3567 }
3568
3569 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3570 {
3571 if (sky2_is_copper(hw)) {
3572 u32 modes = SUPPORTED_10baseT_Half
3573 | SUPPORTED_10baseT_Full
3574 | SUPPORTED_100baseT_Half
3575 | SUPPORTED_100baseT_Full;
3576
3577 if (hw->flags & SKY2_HW_GIGABIT)
3578 modes |= SUPPORTED_1000baseT_Half
3579 | SUPPORTED_1000baseT_Full;
3580 return modes;
3581 } else
3582 return SUPPORTED_1000baseT_Half
3583 | SUPPORTED_1000baseT_Full;
3584 }
3585
3586 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3587 {
3588 struct sky2_port *sky2 = netdev_priv(dev);
3589 struct sky2_hw *hw = sky2->hw;
3590
3591 ecmd->transceiver = XCVR_INTERNAL;
3592 ecmd->supported = sky2_supported_modes(hw);
3593 ecmd->phy_address = PHY_ADDR_MARV;
3594 if (sky2_is_copper(hw)) {
3595 ecmd->port = PORT_TP;
3596 ethtool_cmd_speed_set(ecmd, sky2->speed);
3597 ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_TP;
3598 } else {
3599 ethtool_cmd_speed_set(ecmd, SPEED_1000);
3600 ecmd->port = PORT_FIBRE;
3601 ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_FIBRE;
3602 }
3603
3604 ecmd->advertising = sky2->advertising;
3605 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3606 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3607 ecmd->duplex = sky2->duplex;
3608 return 0;
3609 }
3610
3611 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3612 {
3613 struct sky2_port *sky2 = netdev_priv(dev);
3614 const struct sky2_hw *hw = sky2->hw;
3615 u32 supported = sky2_supported_modes(hw);
3616
3617 if (ecmd->autoneg == AUTONEG_ENABLE) {
3618 if (ecmd->advertising & ~supported)
3619 return -EINVAL;
3620
3621 if (sky2_is_copper(hw))
3622 sky2->advertising = ecmd->advertising |
3623 ADVERTISED_TP |
3624 ADVERTISED_Autoneg;
3625 else
3626 sky2->advertising = ecmd->advertising |
3627 ADVERTISED_FIBRE |
3628 ADVERTISED_Autoneg;
3629
3630 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
3631 sky2->duplex = -1;
3632 sky2->speed = -1;
3633 } else {
3634 u32 setting;
3635 u32 speed = ethtool_cmd_speed(ecmd);
3636
3637 switch (speed) {
3638 case SPEED_1000:
3639 if (ecmd->duplex == DUPLEX_FULL)
3640 setting = SUPPORTED_1000baseT_Full;
3641 else if (ecmd->duplex == DUPLEX_HALF)
3642 setting = SUPPORTED_1000baseT_Half;
3643 else
3644 return -EINVAL;
3645 break;
3646 case SPEED_100:
3647 if (ecmd->duplex == DUPLEX_FULL)
3648 setting = SUPPORTED_100baseT_Full;
3649 else if (ecmd->duplex == DUPLEX_HALF)
3650 setting = SUPPORTED_100baseT_Half;
3651 else
3652 return -EINVAL;
3653 break;
3654
3655 case SPEED_10:
3656 if (ecmd->duplex == DUPLEX_FULL)
3657 setting = SUPPORTED_10baseT_Full;
3658 else if (ecmd->duplex == DUPLEX_HALF)
3659 setting = SUPPORTED_10baseT_Half;
3660 else
3661 return -EINVAL;
3662 break;
3663 default:
3664 return -EINVAL;
3665 }
3666
3667 if ((setting & supported) == 0)
3668 return -EINVAL;
3669
3670 sky2->speed = speed;
3671 sky2->duplex = ecmd->duplex;
3672 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
3673 }
3674
3675 if (netif_running(dev)) {
3676 sky2_phy_reinit(sky2);
3677 sky2_set_multicast(dev);
3678 }
3679
3680 return 0;
3681 }
3682
3683 static void sky2_get_drvinfo(struct net_device *dev,
3684 struct ethtool_drvinfo *info)
3685 {
3686 struct sky2_port *sky2 = netdev_priv(dev);
3687
3688 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
3689 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
3690 strlcpy(info->bus_info, pci_name(sky2->hw->pdev),
3691 sizeof(info->bus_info));
3692 }
3693
3694 static const struct sky2_stat {
3695 char name[ETH_GSTRING_LEN];
3696 u16 offset;
3697 } sky2_stats[] = {
3698 { "tx_bytes", GM_TXO_OK_HI },
3699 { "rx_bytes", GM_RXO_OK_HI },
3700 { "tx_broadcast", GM_TXF_BC_OK },
3701 { "rx_broadcast", GM_RXF_BC_OK },
3702 { "tx_multicast", GM_TXF_MC_OK },
3703 { "rx_multicast", GM_RXF_MC_OK },
3704 { "tx_unicast", GM_TXF_UC_OK },
3705 { "rx_unicast", GM_RXF_UC_OK },
3706 { "tx_mac_pause", GM_TXF_MPAUSE },
3707 { "rx_mac_pause", GM_RXF_MPAUSE },
3708 { "collisions", GM_TXF_COL },
3709 { "late_collision",GM_TXF_LAT_COL },
3710 { "aborted", GM_TXF_ABO_COL },
3711 { "single_collisions", GM_TXF_SNG_COL },
3712 { "multi_collisions", GM_TXF_MUL_COL },
3713
3714 { "rx_short", GM_RXF_SHT },
3715 { "rx_runt", GM_RXE_FRAG },
3716 { "rx_64_byte_packets", GM_RXF_64B },
3717 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3718 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3719 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3720 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3721 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3722 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3723 { "rx_too_long", GM_RXF_LNG_ERR },
3724 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3725 { "rx_jabber", GM_RXF_JAB_PKT },
3726 { "rx_fcs_error", GM_RXF_FCS_ERR },
3727
3728 { "tx_64_byte_packets", GM_TXF_64B },
3729 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3730 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3731 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3732 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3733 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3734 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3735 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3736 };
3737
3738 static u32 sky2_get_msglevel(struct net_device *netdev)
3739 {
3740 struct sky2_port *sky2 = netdev_priv(netdev);
3741 return sky2->msg_enable;
3742 }
3743
3744 static int sky2_nway_reset(struct net_device *dev)
3745 {
3746 struct sky2_port *sky2 = netdev_priv(dev);
3747
3748 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
3749 return -EINVAL;
3750
3751 sky2_phy_reinit(sky2);
3752 sky2_set_multicast(dev);
3753
3754 return 0;
3755 }
3756
3757 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3758 {
3759 struct sky2_hw *hw = sky2->hw;
3760 unsigned port = sky2->port;
3761 int i;
3762
3763 data[0] = get_stats64(hw, port, GM_TXO_OK_LO);
3764 data[1] = get_stats64(hw, port, GM_RXO_OK_LO);
3765
3766 for (i = 2; i < count; i++)
3767 data[i] = get_stats32(hw, port, sky2_stats[i].offset);
3768 }
3769
3770 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3771 {
3772 struct sky2_port *sky2 = netdev_priv(netdev);
3773 sky2->msg_enable = value;
3774 }
3775
3776 static int sky2_get_sset_count(struct net_device *dev, int sset)
3777 {
3778 switch (sset) {
3779 case ETH_SS_STATS:
3780 return ARRAY_SIZE(sky2_stats);
3781 default:
3782 return -EOPNOTSUPP;
3783 }
3784 }
3785
3786 static void sky2_get_ethtool_stats(struct net_device *dev,
3787 struct ethtool_stats *stats, u64 * data)
3788 {
3789 struct sky2_port *sky2 = netdev_priv(dev);
3790
3791 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3792 }
3793
3794 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3795 {
3796 int i;
3797
3798 switch (stringset) {
3799 case ETH_SS_STATS:
3800 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3801 memcpy(data + i * ETH_GSTRING_LEN,
3802 sky2_stats[i].name, ETH_GSTRING_LEN);
3803 break;
3804 }
3805 }
3806
3807 static int sky2_set_mac_address(struct net_device *dev, void *p)
3808 {
3809 struct sky2_port *sky2 = netdev_priv(dev);
3810 struct sky2_hw *hw = sky2->hw;
3811 unsigned port = sky2->port;
3812 const struct sockaddr *addr = p;
3813
3814 if (!is_valid_ether_addr(addr->sa_data))
3815 return -EADDRNOTAVAIL;
3816
3817 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3818 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3819 dev->dev_addr, ETH_ALEN);
3820 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3821 dev->dev_addr, ETH_ALEN);
3822
3823 /* virtual address for data */
3824 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3825
3826 /* physical address: used for pause frames */
3827 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3828
3829 return 0;
3830 }
3831
3832 static inline void sky2_add_filter(u8 filter[8], const u8 *addr)
3833 {
3834 u32 bit;
3835
3836 bit = ether_crc(ETH_ALEN, addr) & 63;
3837 filter[bit >> 3] |= 1 << (bit & 7);
3838 }
3839
3840 static void sky2_set_multicast(struct net_device *dev)
3841 {
3842 struct sky2_port *sky2 = netdev_priv(dev);
3843 struct sky2_hw *hw = sky2->hw;
3844 unsigned port = sky2->port;
3845 struct netdev_hw_addr *ha;
3846 u16 reg;
3847 u8 filter[8];
3848 int rx_pause;
3849 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3850
3851 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3852 memset(filter, 0, sizeof(filter));
3853
3854 reg = gma_read16(hw, port, GM_RX_CTRL);
3855 reg |= GM_RXCR_UCF_ENA;
3856
3857 if (dev->flags & IFF_PROMISC) /* promiscuous */
3858 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3859 else if (dev->flags & IFF_ALLMULTI)
3860 memset(filter, 0xff, sizeof(filter));
3861 else if (netdev_mc_empty(dev) && !rx_pause)
3862 reg &= ~GM_RXCR_MCF_ENA;
3863 else {
3864 reg |= GM_RXCR_MCF_ENA;
3865
3866 if (rx_pause)
3867 sky2_add_filter(filter, pause_mc_addr);
3868
3869 netdev_for_each_mc_addr(ha, dev)
3870 sky2_add_filter(filter, ha->addr);
3871 }
3872
3873 gma_write16(hw, port, GM_MC_ADDR_H1,
3874 (u16) filter[0] | ((u16) filter[1] << 8));
3875 gma_write16(hw, port, GM_MC_ADDR_H2,
3876 (u16) filter[2] | ((u16) filter[3] << 8));
3877 gma_write16(hw, port, GM_MC_ADDR_H3,
3878 (u16) filter[4] | ((u16) filter[5] << 8));
3879 gma_write16(hw, port, GM_MC_ADDR_H4,
3880 (u16) filter[6] | ((u16) filter[7] << 8));
3881
3882 gma_write16(hw, port, GM_RX_CTRL, reg);
3883 }
3884
3885 static struct rtnl_link_stats64 *sky2_get_stats(struct net_device *dev,
3886 struct rtnl_link_stats64 *stats)
3887 {
3888 struct sky2_port *sky2 = netdev_priv(dev);
3889 struct sky2_hw *hw = sky2->hw;
3890 unsigned port = sky2->port;
3891 unsigned int start;
3892 u64 _bytes, _packets;
3893
3894 do {
3895 start = u64_stats_fetch_begin_bh(&sky2->rx_stats.syncp);
3896 _bytes = sky2->rx_stats.bytes;
3897 _packets = sky2->rx_stats.packets;
3898 } while (u64_stats_fetch_retry_bh(&sky2->rx_stats.syncp, start));
3899
3900 stats->rx_packets = _packets;
3901 stats->rx_bytes = _bytes;
3902
3903 do {
3904 start = u64_stats_fetch_begin_bh(&sky2->tx_stats.syncp);
3905 _bytes = sky2->tx_stats.bytes;
3906 _packets = sky2->tx_stats.packets;
3907 } while (u64_stats_fetch_retry_bh(&sky2->tx_stats.syncp, start));
3908
3909 stats->tx_packets = _packets;
3910 stats->tx_bytes = _bytes;
3911
3912 stats->multicast = get_stats32(hw, port, GM_RXF_MC_OK)
3913 + get_stats32(hw, port, GM_RXF_BC_OK);
3914
3915 stats->collisions = get_stats32(hw, port, GM_TXF_COL);
3916
3917 stats->rx_length_errors = get_stats32(hw, port, GM_RXF_LNG_ERR);
3918 stats->rx_crc_errors = get_stats32(hw, port, GM_RXF_FCS_ERR);
3919 stats->rx_frame_errors = get_stats32(hw, port, GM_RXF_SHT)
3920 + get_stats32(hw, port, GM_RXE_FRAG);
3921 stats->rx_over_errors = get_stats32(hw, port, GM_RXE_FIFO_OV);
3922
3923 stats->rx_dropped = dev->stats.rx_dropped;
3924 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
3925 stats->tx_fifo_errors = dev->stats.tx_fifo_errors;
3926
3927 return stats;
3928 }
3929
3930 /* Can have one global because blinking is controlled by
3931 * ethtool and that is always under RTNL mutex
3932 */
3933 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3934 {
3935 struct sky2_hw *hw = sky2->hw;
3936 unsigned port = sky2->port;
3937
3938 spin_lock_bh(&sky2->phy_lock);
3939 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3940 hw->chip_id == CHIP_ID_YUKON_EX ||
3941 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3942 u16 pg;
3943 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3944 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3945
3946 switch (mode) {
3947 case MO_LED_OFF:
3948 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3949 PHY_M_LEDC_LOS_CTRL(8) |
3950 PHY_M_LEDC_INIT_CTRL(8) |
3951 PHY_M_LEDC_STA1_CTRL(8) |
3952 PHY_M_LEDC_STA0_CTRL(8));
3953 break;
3954 case MO_LED_ON:
3955 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3956 PHY_M_LEDC_LOS_CTRL(9) |
3957 PHY_M_LEDC_INIT_CTRL(9) |
3958 PHY_M_LEDC_STA1_CTRL(9) |
3959 PHY_M_LEDC_STA0_CTRL(9));
3960 break;
3961 case MO_LED_BLINK:
3962 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3963 PHY_M_LEDC_LOS_CTRL(0xa) |
3964 PHY_M_LEDC_INIT_CTRL(0xa) |
3965 PHY_M_LEDC_STA1_CTRL(0xa) |
3966 PHY_M_LEDC_STA0_CTRL(0xa));
3967 break;
3968 case MO_LED_NORM:
3969 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3970 PHY_M_LEDC_LOS_CTRL(1) |
3971 PHY_M_LEDC_INIT_CTRL(8) |
3972 PHY_M_LEDC_STA1_CTRL(7) |
3973 PHY_M_LEDC_STA0_CTRL(7));
3974 }
3975
3976 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3977 } else
3978 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3979 PHY_M_LED_MO_DUP(mode) |
3980 PHY_M_LED_MO_10(mode) |
3981 PHY_M_LED_MO_100(mode) |
3982 PHY_M_LED_MO_1000(mode) |
3983 PHY_M_LED_MO_RX(mode) |
3984 PHY_M_LED_MO_TX(mode));
3985
3986 spin_unlock_bh(&sky2->phy_lock);
3987 }
3988
3989 /* blink LED's for finding board */
3990 static int sky2_set_phys_id(struct net_device *dev,
3991 enum ethtool_phys_id_state state)
3992 {
3993 struct sky2_port *sky2 = netdev_priv(dev);
3994
3995 switch (state) {
3996 case ETHTOOL_ID_ACTIVE:
3997 return 1; /* cycle on/off once per second */
3998 case ETHTOOL_ID_INACTIVE:
3999 sky2_led(sky2, MO_LED_NORM);
4000 break;
4001 case ETHTOOL_ID_ON:
4002 sky2_led(sky2, MO_LED_ON);
4003 break;
4004 case ETHTOOL_ID_OFF:
4005 sky2_led(sky2, MO_LED_OFF);
4006 break;
4007 }
4008
4009 return 0;
4010 }
4011
4012 static void sky2_get_pauseparam(struct net_device *dev,
4013 struct ethtool_pauseparam *ecmd)
4014 {
4015 struct sky2_port *sky2 = netdev_priv(dev);
4016
4017 switch (sky2->flow_mode) {
4018 case FC_NONE:
4019 ecmd->tx_pause = ecmd->rx_pause = 0;
4020 break;
4021 case FC_TX:
4022 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
4023 break;
4024 case FC_RX:
4025 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
4026 break;
4027 case FC_BOTH:
4028 ecmd->tx_pause = ecmd->rx_pause = 1;
4029 }
4030
4031 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
4032 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
4033 }
4034
4035 static int sky2_set_pauseparam(struct net_device *dev,
4036 struct ethtool_pauseparam *ecmd)
4037 {
4038 struct sky2_port *sky2 = netdev_priv(dev);
4039
4040 if (ecmd->autoneg == AUTONEG_ENABLE)
4041 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
4042 else
4043 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
4044
4045 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
4046
4047 if (netif_running(dev))
4048 sky2_phy_reinit(sky2);
4049
4050 return 0;
4051 }
4052
4053 static int sky2_get_coalesce(struct net_device *dev,
4054 struct ethtool_coalesce *ecmd)
4055 {
4056 struct sky2_port *sky2 = netdev_priv(dev);
4057 struct sky2_hw *hw = sky2->hw;
4058
4059 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
4060 ecmd->tx_coalesce_usecs = 0;
4061 else {
4062 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
4063 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
4064 }
4065 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
4066
4067 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
4068 ecmd->rx_coalesce_usecs = 0;
4069 else {
4070 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
4071 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
4072 }
4073 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
4074
4075 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
4076 ecmd->rx_coalesce_usecs_irq = 0;
4077 else {
4078 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
4079 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
4080 }
4081
4082 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
4083
4084 return 0;
4085 }
4086
4087 /* Note: this affect both ports */
4088 static int sky2_set_coalesce(struct net_device *dev,
4089 struct ethtool_coalesce *ecmd)
4090 {
4091 struct sky2_port *sky2 = netdev_priv(dev);
4092 struct sky2_hw *hw = sky2->hw;
4093 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
4094
4095 if (ecmd->tx_coalesce_usecs > tmax ||
4096 ecmd->rx_coalesce_usecs > tmax ||
4097 ecmd->rx_coalesce_usecs_irq > tmax)
4098 return -EINVAL;
4099
4100 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
4101 return -EINVAL;
4102 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
4103 return -EINVAL;
4104 if (ecmd->rx_max_coalesced_frames_irq > RX_MAX_PENDING)
4105 return -EINVAL;
4106
4107 if (ecmd->tx_coalesce_usecs == 0)
4108 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
4109 else {
4110 sky2_write32(hw, STAT_TX_TIMER_INI,
4111 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
4112 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
4113 }
4114 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
4115
4116 if (ecmd->rx_coalesce_usecs == 0)
4117 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
4118 else {
4119 sky2_write32(hw, STAT_LEV_TIMER_INI,
4120 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
4121 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
4122 }
4123 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
4124
4125 if (ecmd->rx_coalesce_usecs_irq == 0)
4126 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
4127 else {
4128 sky2_write32(hw, STAT_ISR_TIMER_INI,
4129 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
4130 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
4131 }
4132 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
4133 return 0;
4134 }
4135
4136 /*
4137 * Hardware is limited to min of 128 and max of 2048 for ring size
4138 * and rounded up to next power of two
4139 * to avoid division in modulus calclation
4140 */
4141 static unsigned long roundup_ring_size(unsigned long pending)
4142 {
4143 return max(128ul, roundup_pow_of_two(pending+1));
4144 }
4145
4146 static void sky2_get_ringparam(struct net_device *dev,
4147 struct ethtool_ringparam *ering)
4148 {
4149 struct sky2_port *sky2 = netdev_priv(dev);
4150
4151 ering->rx_max_pending = RX_MAX_PENDING;
4152 ering->tx_max_pending = TX_MAX_PENDING;
4153
4154 ering->rx_pending = sky2->rx_pending;
4155 ering->tx_pending = sky2->tx_pending;
4156 }
4157
4158 static int sky2_set_ringparam(struct net_device *dev,
4159 struct ethtool_ringparam *ering)
4160 {
4161 struct sky2_port *sky2 = netdev_priv(dev);
4162
4163 if (ering->rx_pending > RX_MAX_PENDING ||
4164 ering->rx_pending < 8 ||
4165 ering->tx_pending < TX_MIN_PENDING ||
4166 ering->tx_pending > TX_MAX_PENDING)
4167 return -EINVAL;
4168
4169 sky2_detach(dev);
4170
4171 sky2->rx_pending = ering->rx_pending;
4172 sky2->tx_pending = ering->tx_pending;
4173 sky2->tx_ring_size = roundup_ring_size(sky2->tx_pending);
4174
4175 return sky2_reattach(dev);
4176 }
4177
4178 static int sky2_get_regs_len(struct net_device *dev)
4179 {
4180 return 0x4000;
4181 }
4182
4183 static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
4184 {
4185 /* This complicated switch statement is to make sure and
4186 * only access regions that are unreserved.
4187 * Some blocks are only valid on dual port cards.
4188 */
4189 switch (b) {
4190 /* second port */
4191 case 5: /* Tx Arbiter 2 */
4192 case 9: /* RX2 */
4193 case 14 ... 15: /* TX2 */
4194 case 17: case 19: /* Ram Buffer 2 */
4195 case 22 ... 23: /* Tx Ram Buffer 2 */
4196 case 25: /* Rx MAC Fifo 1 */
4197 case 27: /* Tx MAC Fifo 2 */
4198 case 31: /* GPHY 2 */
4199 case 40 ... 47: /* Pattern Ram 2 */
4200 case 52: case 54: /* TCP Segmentation 2 */
4201 case 112 ... 116: /* GMAC 2 */
4202 return hw->ports > 1;
4203
4204 case 0: /* Control */
4205 case 2: /* Mac address */
4206 case 4: /* Tx Arbiter 1 */
4207 case 7: /* PCI express reg */
4208 case 8: /* RX1 */
4209 case 12 ... 13: /* TX1 */
4210 case 16: case 18:/* Rx Ram Buffer 1 */
4211 case 20 ... 21: /* Tx Ram Buffer 1 */
4212 case 24: /* Rx MAC Fifo 1 */
4213 case 26: /* Tx MAC Fifo 1 */
4214 case 28 ... 29: /* Descriptor and status unit */
4215 case 30: /* GPHY 1*/
4216 case 32 ... 39: /* Pattern Ram 1 */
4217 case 48: case 50: /* TCP Segmentation 1 */
4218 case 56 ... 60: /* PCI space */
4219 case 80 ... 84: /* GMAC 1 */
4220 return 1;
4221
4222 default:
4223 return 0;
4224 }
4225 }
4226
4227 /*
4228 * Returns copy of control register region
4229 * Note: ethtool_get_regs always provides full size (16k) buffer
4230 */
4231 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4232 void *p)
4233 {
4234 const struct sky2_port *sky2 = netdev_priv(dev);
4235 const void __iomem *io = sky2->hw->regs;
4236 unsigned int b;
4237
4238 regs->version = 1;
4239
4240 for (b = 0; b < 128; b++) {
4241 /* skip poisonous diagnostic ram region in block 3 */
4242 if (b == 3)
4243 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
4244 else if (sky2_reg_access_ok(sky2->hw, b))
4245 memcpy_fromio(p, io, 128);
4246 else
4247 memset(p, 0, 128);
4248
4249 p += 128;
4250 io += 128;
4251 }
4252 }
4253
4254 static int sky2_get_eeprom_len(struct net_device *dev)
4255 {
4256 struct sky2_port *sky2 = netdev_priv(dev);
4257 struct sky2_hw *hw = sky2->hw;
4258 u16 reg2;
4259
4260 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4261 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4262 }
4263
4264 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
4265 {
4266 unsigned long start = jiffies;
4267
4268 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
4269 /* Can take up to 10.6 ms for write */
4270 if (time_after(jiffies, start + HZ/4)) {
4271 dev_err(&hw->pdev->dev, "VPD cycle timed out\n");
4272 return -ETIMEDOUT;
4273 }
4274 mdelay(1);
4275 }
4276
4277 return 0;
4278 }
4279
4280 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
4281 u16 offset, size_t length)
4282 {
4283 int rc = 0;
4284
4285 while (length > 0) {
4286 u32 val;
4287
4288 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
4289 rc = sky2_vpd_wait(hw, cap, 0);
4290 if (rc)
4291 break;
4292
4293 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
4294
4295 memcpy(data, &val, min(sizeof(val), length));
4296 offset += sizeof(u32);
4297 data += sizeof(u32);
4298 length -= sizeof(u32);
4299 }
4300
4301 return rc;
4302 }
4303
4304 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4305 u16 offset, unsigned int length)
4306 {
4307 unsigned int i;
4308 int rc = 0;
4309
4310 for (i = 0; i < length; i += sizeof(u32)) {
4311 u32 val = *(u32 *)(data + i);
4312
4313 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4314 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4315
4316 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4317 if (rc)
4318 break;
4319 }
4320 return rc;
4321 }
4322
4323 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4324 u8 *data)
4325 {
4326 struct sky2_port *sky2 = netdev_priv(dev);
4327 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4328
4329 if (!cap)
4330 return -EINVAL;
4331
4332 eeprom->magic = SKY2_EEPROM_MAGIC;
4333
4334 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4335 }
4336
4337 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4338 u8 *data)
4339 {
4340 struct sky2_port *sky2 = netdev_priv(dev);
4341 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4342
4343 if (!cap)
4344 return -EINVAL;
4345
4346 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4347 return -EINVAL;
4348
4349 /* Partial writes not supported */
4350 if ((eeprom->offset & 3) || (eeprom->len & 3))
4351 return -EINVAL;
4352
4353 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4354 }
4355
4356 static netdev_features_t sky2_fix_features(struct net_device *dev,
4357 netdev_features_t features)
4358 {
4359 const struct sky2_port *sky2 = netdev_priv(dev);
4360 const struct sky2_hw *hw = sky2->hw;
4361
4362 /* In order to do Jumbo packets on these chips, need to turn off the
4363 * transmit store/forward. Therefore checksum offload won't work.
4364 */
4365 if (dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U) {
4366 netdev_info(dev, "checksum offload not possible with jumbo frames\n");
4367 features &= ~(NETIF_F_TSO|NETIF_F_SG|NETIF_F_ALL_CSUM);
4368 }
4369
4370 /* Some hardware requires receive checksum for RSS to work. */
4371 if ( (features & NETIF_F_RXHASH) &&
4372 !(features & NETIF_F_RXCSUM) &&
4373 (sky2->hw->flags & SKY2_HW_RSS_CHKSUM)) {
4374 netdev_info(dev, "receive hashing forces receive checksum\n");
4375 features |= NETIF_F_RXCSUM;
4376 }
4377
4378 return features;
4379 }
4380
4381 static int sky2_set_features(struct net_device *dev, netdev_features_t features)
4382 {
4383 struct sky2_port *sky2 = netdev_priv(dev);
4384 netdev_features_t changed = dev->features ^ features;
4385
4386 if ((changed & NETIF_F_RXCSUM) &&
4387 !(sky2->hw->flags & SKY2_HW_NEW_LE)) {
4388 sky2_write32(sky2->hw,
4389 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
4390 (features & NETIF_F_RXCSUM)
4391 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
4392 }
4393
4394 if (changed & NETIF_F_RXHASH)
4395 rx_set_rss(dev, features);
4396
4397 if (changed & (NETIF_F_HW_VLAN_TX|NETIF_F_HW_VLAN_RX))
4398 sky2_vlan_mode(dev, features);
4399
4400 return 0;
4401 }
4402
4403 static const struct ethtool_ops sky2_ethtool_ops = {
4404 .get_settings = sky2_get_settings,
4405 .set_settings = sky2_set_settings,
4406 .get_drvinfo = sky2_get_drvinfo,
4407 .get_wol = sky2_get_wol,
4408 .set_wol = sky2_set_wol,
4409 .get_msglevel = sky2_get_msglevel,
4410 .set_msglevel = sky2_set_msglevel,
4411 .nway_reset = sky2_nway_reset,
4412 .get_regs_len = sky2_get_regs_len,
4413 .get_regs = sky2_get_regs,
4414 .get_link = ethtool_op_get_link,
4415 .get_eeprom_len = sky2_get_eeprom_len,
4416 .get_eeprom = sky2_get_eeprom,
4417 .set_eeprom = sky2_set_eeprom,
4418 .get_strings = sky2_get_strings,
4419 .get_coalesce = sky2_get_coalesce,
4420 .set_coalesce = sky2_set_coalesce,
4421 .get_ringparam = sky2_get_ringparam,
4422 .set_ringparam = sky2_set_ringparam,
4423 .get_pauseparam = sky2_get_pauseparam,
4424 .set_pauseparam = sky2_set_pauseparam,
4425 .set_phys_id = sky2_set_phys_id,
4426 .get_sset_count = sky2_get_sset_count,
4427 .get_ethtool_stats = sky2_get_ethtool_stats,
4428 };
4429
4430 #ifdef CONFIG_SKY2_DEBUG
4431
4432 static struct dentry *sky2_debug;
4433
4434
4435 /*
4436 * Read and parse the first part of Vital Product Data
4437 */
4438 #define VPD_SIZE 128
4439 #define VPD_MAGIC 0x82
4440
4441 static const struct vpd_tag {
4442 char tag[2];
4443 char *label;
4444 } vpd_tags[] = {
4445 { "PN", "Part Number" },
4446 { "EC", "Engineering Level" },
4447 { "MN", "Manufacturer" },
4448 { "SN", "Serial Number" },
4449 { "YA", "Asset Tag" },
4450 { "VL", "First Error Log Message" },
4451 { "VF", "Second Error Log Message" },
4452 { "VB", "Boot Agent ROM Configuration" },
4453 { "VE", "EFI UNDI Configuration" },
4454 };
4455
4456 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4457 {
4458 size_t vpd_size;
4459 loff_t offs;
4460 u8 len;
4461 unsigned char *buf;
4462 u16 reg2;
4463
4464 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4465 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4466
4467 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4468 buf = kmalloc(vpd_size, GFP_KERNEL);
4469 if (!buf) {
4470 seq_puts(seq, "no memory!\n");
4471 return;
4472 }
4473
4474 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4475 seq_puts(seq, "VPD read failed\n");
4476 goto out;
4477 }
4478
4479 if (buf[0] != VPD_MAGIC) {
4480 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4481 goto out;
4482 }
4483 len = buf[1];
4484 if (len == 0 || len > vpd_size - 4) {
4485 seq_printf(seq, "Invalid id length: %d\n", len);
4486 goto out;
4487 }
4488
4489 seq_printf(seq, "%.*s\n", len, buf + 3);
4490 offs = len + 3;
4491
4492 while (offs < vpd_size - 4) {
4493 int i;
4494
4495 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4496 break;
4497 len = buf[offs + 2];
4498 if (offs + len + 3 >= vpd_size)
4499 break;
4500
4501 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4502 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4503 seq_printf(seq, " %s: %.*s\n",
4504 vpd_tags[i].label, len, buf + offs + 3);
4505 break;
4506 }
4507 }
4508 offs += len + 3;
4509 }
4510 out:
4511 kfree(buf);
4512 }
4513
4514 static int sky2_debug_show(struct seq_file *seq, void *v)
4515 {
4516 struct net_device *dev = seq->private;
4517 const struct sky2_port *sky2 = netdev_priv(dev);
4518 struct sky2_hw *hw = sky2->hw;
4519 unsigned port = sky2->port;
4520 unsigned idx, last;
4521 int sop;
4522
4523 sky2_show_vpd(seq, hw);
4524
4525 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
4526 sky2_read32(hw, B0_ISRC),
4527 sky2_read32(hw, B0_IMSK),
4528 sky2_read32(hw, B0_Y2_SP_ICR));
4529
4530 if (!netif_running(dev)) {
4531 seq_printf(seq, "network not running\n");
4532 return 0;
4533 }
4534
4535 napi_disable(&hw->napi);
4536 last = sky2_read16(hw, STAT_PUT_IDX);
4537
4538 seq_printf(seq, "Status ring %u\n", hw->st_size);
4539 if (hw->st_idx == last)
4540 seq_puts(seq, "Status ring (empty)\n");
4541 else {
4542 seq_puts(seq, "Status ring\n");
4543 for (idx = hw->st_idx; idx != last && idx < hw->st_size;
4544 idx = RING_NEXT(idx, hw->st_size)) {
4545 const struct sky2_status_le *le = hw->st_le + idx;
4546 seq_printf(seq, "[%d] %#x %d %#x\n",
4547 idx, le->opcode, le->length, le->status);
4548 }
4549 seq_puts(seq, "\n");
4550 }
4551
4552 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4553 sky2->tx_cons, sky2->tx_prod,
4554 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4555 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4556
4557 /* Dump contents of tx ring */
4558 sop = 1;
4559 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4560 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
4561 const struct sky2_tx_le *le = sky2->tx_le + idx;
4562 u32 a = le32_to_cpu(le->addr);
4563
4564 if (sop)
4565 seq_printf(seq, "%u:", idx);
4566 sop = 0;
4567
4568 switch (le->opcode & ~HW_OWNER) {
4569 case OP_ADDR64:
4570 seq_printf(seq, " %#x:", a);
4571 break;
4572 case OP_LRGLEN:
4573 seq_printf(seq, " mtu=%d", a);
4574 break;
4575 case OP_VLAN:
4576 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4577 break;
4578 case OP_TCPLISW:
4579 seq_printf(seq, " csum=%#x", a);
4580 break;
4581 case OP_LARGESEND:
4582 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4583 break;
4584 case OP_PACKET:
4585 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4586 break;
4587 case OP_BUFFER:
4588 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4589 break;
4590 default:
4591 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4592 a, le16_to_cpu(le->length));
4593 }
4594
4595 if (le->ctrl & EOP) {
4596 seq_putc(seq, '\n');
4597 sop = 1;
4598 }
4599 }
4600
4601 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4602 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4603 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4604 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4605
4606 sky2_read32(hw, B0_Y2_SP_LISR);
4607 napi_enable(&hw->napi);
4608 return 0;
4609 }
4610
4611 static int sky2_debug_open(struct inode *inode, struct file *file)
4612 {
4613 return single_open(file, sky2_debug_show, inode->i_private);
4614 }
4615
4616 static const struct file_operations sky2_debug_fops = {
4617 .owner = THIS_MODULE,
4618 .open = sky2_debug_open,
4619 .read = seq_read,
4620 .llseek = seq_lseek,
4621 .release = single_release,
4622 };
4623
4624 /*
4625 * Use network device events to create/remove/rename
4626 * debugfs file entries
4627 */
4628 static int sky2_device_event(struct notifier_block *unused,
4629 unsigned long event, void *ptr)
4630 {
4631 struct net_device *dev = ptr;
4632 struct sky2_port *sky2 = netdev_priv(dev);
4633
4634 if (dev->netdev_ops->ndo_open != sky2_open || !sky2_debug)
4635 return NOTIFY_DONE;
4636
4637 switch (event) {
4638 case NETDEV_CHANGENAME:
4639 if (sky2->debugfs) {
4640 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4641 sky2_debug, dev->name);
4642 }
4643 break;
4644
4645 case NETDEV_GOING_DOWN:
4646 if (sky2->debugfs) {
4647 netdev_printk(KERN_DEBUG, dev, "remove debugfs\n");
4648 debugfs_remove(sky2->debugfs);
4649 sky2->debugfs = NULL;
4650 }
4651 break;
4652
4653 case NETDEV_UP:
4654 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4655 sky2_debug, dev,
4656 &sky2_debug_fops);
4657 if (IS_ERR(sky2->debugfs))
4658 sky2->debugfs = NULL;
4659 }
4660
4661 return NOTIFY_DONE;
4662 }
4663
4664 static struct notifier_block sky2_notifier = {
4665 .notifier_call = sky2_device_event,
4666 };
4667
4668
4669 static __init void sky2_debug_init(void)
4670 {
4671 struct dentry *ent;
4672
4673 ent = debugfs_create_dir("sky2", NULL);
4674 if (!ent || IS_ERR(ent))
4675 return;
4676
4677 sky2_debug = ent;
4678 register_netdevice_notifier(&sky2_notifier);
4679 }
4680
4681 static __exit void sky2_debug_cleanup(void)
4682 {
4683 if (sky2_debug) {
4684 unregister_netdevice_notifier(&sky2_notifier);
4685 debugfs_remove(sky2_debug);
4686 sky2_debug = NULL;
4687 }
4688 }
4689
4690 #else
4691 #define sky2_debug_init()
4692 #define sky2_debug_cleanup()
4693 #endif
4694
4695 /* Two copies of network device operations to handle special case of
4696 not allowing netpoll on second port */
4697 static const struct net_device_ops sky2_netdev_ops[2] = {
4698 {
4699 .ndo_open = sky2_open,
4700 .ndo_stop = sky2_close,
4701 .ndo_start_xmit = sky2_xmit_frame,
4702 .ndo_do_ioctl = sky2_ioctl,
4703 .ndo_validate_addr = eth_validate_addr,
4704 .ndo_set_mac_address = sky2_set_mac_address,
4705 .ndo_set_rx_mode = sky2_set_multicast,
4706 .ndo_change_mtu = sky2_change_mtu,
4707 .ndo_fix_features = sky2_fix_features,
4708 .ndo_set_features = sky2_set_features,
4709 .ndo_tx_timeout = sky2_tx_timeout,
4710 .ndo_get_stats64 = sky2_get_stats,
4711 #ifdef CONFIG_NET_POLL_CONTROLLER
4712 .ndo_poll_controller = sky2_netpoll,
4713 #endif
4714 },
4715 {
4716 .ndo_open = sky2_open,
4717 .ndo_stop = sky2_close,
4718 .ndo_start_xmit = sky2_xmit_frame,
4719 .ndo_do_ioctl = sky2_ioctl,
4720 .ndo_validate_addr = eth_validate_addr,
4721 .ndo_set_mac_address = sky2_set_mac_address,
4722 .ndo_set_rx_mode = sky2_set_multicast,
4723 .ndo_change_mtu = sky2_change_mtu,
4724 .ndo_fix_features = sky2_fix_features,
4725 .ndo_set_features = sky2_set_features,
4726 .ndo_tx_timeout = sky2_tx_timeout,
4727 .ndo_get_stats64 = sky2_get_stats,
4728 },
4729 };
4730
4731 /* Initialize network device */
4732 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
4733 unsigned port,
4734 int highmem, int wol)
4735 {
4736 struct sky2_port *sky2;
4737 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4738
4739 if (!dev)
4740 return NULL;
4741
4742 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4743 dev->irq = hw->pdev->irq;
4744 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4745 dev->watchdog_timeo = TX_WATCHDOG;
4746 dev->netdev_ops = &sky2_netdev_ops[port];
4747
4748 sky2 = netdev_priv(dev);
4749 sky2->netdev = dev;
4750 sky2->hw = hw;
4751 sky2->msg_enable = netif_msg_init(debug, default_msg);
4752
4753 /* Auto speed and flow control */
4754 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4755 if (hw->chip_id != CHIP_ID_YUKON_XL)
4756 dev->hw_features |= NETIF_F_RXCSUM;
4757
4758 sky2->flow_mode = FC_BOTH;
4759
4760 sky2->duplex = -1;
4761 sky2->speed = -1;
4762 sky2->advertising = sky2_supported_modes(hw);
4763 sky2->wol = wol;
4764
4765 spin_lock_init(&sky2->phy_lock);
4766
4767 sky2->tx_pending = TX_DEF_PENDING;
4768 sky2->tx_ring_size = roundup_ring_size(TX_DEF_PENDING);
4769 sky2->rx_pending = RX_DEF_PENDING;
4770
4771 hw->dev[port] = dev;
4772
4773 sky2->port = port;
4774
4775 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO;
4776
4777 if (highmem)
4778 dev->features |= NETIF_F_HIGHDMA;
4779
4780 /* Enable receive hashing unless hardware is known broken */
4781 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
4782 dev->hw_features |= NETIF_F_RXHASH;
4783
4784 if (!(hw->flags & SKY2_HW_VLAN_BROKEN)) {
4785 dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4786 dev->vlan_features |= SKY2_VLAN_OFFLOADS;
4787 }
4788
4789 dev->features |= dev->hw_features;
4790
4791 /* read the mac address */
4792 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4793 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4794
4795 return dev;
4796 }
4797
4798 static void __devinit sky2_show_addr(struct net_device *dev)
4799 {
4800 const struct sky2_port *sky2 = netdev_priv(dev);
4801
4802 netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr);
4803 }
4804
4805 /* Handle software interrupt used during MSI test */
4806 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4807 {
4808 struct sky2_hw *hw = dev_id;
4809 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4810
4811 if (status == 0)
4812 return IRQ_NONE;
4813
4814 if (status & Y2_IS_IRQ_SW) {
4815 hw->flags |= SKY2_HW_USE_MSI;
4816 wake_up(&hw->msi_wait);
4817 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4818 }
4819 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4820
4821 return IRQ_HANDLED;
4822 }
4823
4824 /* Test interrupt path by forcing a a software IRQ */
4825 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4826 {
4827 struct pci_dev *pdev = hw->pdev;
4828 int err;
4829
4830 init_waitqueue_head(&hw->msi_wait);
4831
4832 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4833
4834 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4835 if (err) {
4836 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4837 return err;
4838 }
4839
4840 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4841 sky2_read8(hw, B0_CTST);
4842
4843 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4844
4845 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4846 /* MSI test failed, go back to INTx mode */
4847 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4848 "switching to INTx mode.\n");
4849
4850 err = -EOPNOTSUPP;
4851 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4852 }
4853
4854 sky2_write32(hw, B0_IMSK, 0);
4855 sky2_read32(hw, B0_IMSK);
4856
4857 free_irq(pdev->irq, hw);
4858
4859 return err;
4860 }
4861
4862 /* This driver supports yukon2 chipset only */
4863 static const char *sky2_name(u8 chipid, char *buf, int sz)
4864 {
4865 const char *name[] = {
4866 "XL", /* 0xb3 */
4867 "EC Ultra", /* 0xb4 */
4868 "Extreme", /* 0xb5 */
4869 "EC", /* 0xb6 */
4870 "FE", /* 0xb7 */
4871 "FE+", /* 0xb8 */
4872 "Supreme", /* 0xb9 */
4873 "UL 2", /* 0xba */
4874 "Unknown", /* 0xbb */
4875 "Optima", /* 0xbc */
4876 "Optima Prime", /* 0xbd */
4877 "Optima 2", /* 0xbe */
4878 };
4879
4880 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OP_2)
4881 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4882 else
4883 snprintf(buf, sz, "(chip %#x)", chipid);
4884 return buf;
4885 }
4886
4887 static int __devinit sky2_probe(struct pci_dev *pdev,
4888 const struct pci_device_id *ent)
4889 {
4890 struct net_device *dev, *dev1;
4891 struct sky2_hw *hw;
4892 int err, using_dac = 0, wol_default;
4893 u32 reg;
4894 char buf1[16];
4895
4896 err = pci_enable_device(pdev);
4897 if (err) {
4898 dev_err(&pdev->dev, "cannot enable PCI device\n");
4899 goto err_out;
4900 }
4901
4902 /* Get configuration information
4903 * Note: only regular PCI config access once to test for HW issues
4904 * other PCI access through shared memory for speed and to
4905 * avoid MMCONFIG problems.
4906 */
4907 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4908 if (err) {
4909 dev_err(&pdev->dev, "PCI read config failed\n");
4910 goto err_out;
4911 }
4912
4913 if (~reg == 0) {
4914 dev_err(&pdev->dev, "PCI configuration read error\n");
4915 goto err_out;
4916 }
4917
4918 err = pci_request_regions(pdev, DRV_NAME);
4919 if (err) {
4920 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4921 goto err_out_disable;
4922 }
4923
4924 pci_set_master(pdev);
4925
4926 if (sizeof(dma_addr_t) > sizeof(u32) &&
4927 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
4928 using_dac = 1;
4929 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4930 if (err < 0) {
4931 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4932 "for consistent allocations\n");
4933 goto err_out_free_regions;
4934 }
4935 } else {
4936 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4937 if (err) {
4938 dev_err(&pdev->dev, "no usable DMA configuration\n");
4939 goto err_out_free_regions;
4940 }
4941 }
4942
4943
4944 #ifdef __BIG_ENDIAN
4945 /* The sk98lin vendor driver uses hardware byte swapping but
4946 * this driver uses software swapping.
4947 */
4948 reg &= ~PCI_REV_DESC;
4949 err = pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
4950 if (err) {
4951 dev_err(&pdev->dev, "PCI write config failed\n");
4952 goto err_out_free_regions;
4953 }
4954 #endif
4955
4956 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
4957
4958 err = -ENOMEM;
4959
4960 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4961 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
4962 if (!hw) {
4963 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4964 goto err_out_free_regions;
4965 }
4966
4967 hw->pdev = pdev;
4968 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
4969
4970 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4971 if (!hw->regs) {
4972 dev_err(&pdev->dev, "cannot map device registers\n");
4973 goto err_out_free_hw;
4974 }
4975
4976 err = sky2_init(hw);
4977 if (err)
4978 goto err_out_iounmap;
4979
4980 /* ring for status responses */
4981 hw->st_size = hw->ports * roundup_pow_of_two(3*RX_MAX_PENDING + TX_MAX_PENDING);
4982 hw->st_le = pci_alloc_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4983 &hw->st_dma);
4984 if (!hw->st_le)
4985 goto err_out_reset;
4986
4987 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4988 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
4989
4990 sky2_reset(hw);
4991
4992 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4993 if (!dev) {
4994 err = -ENOMEM;
4995 goto err_out_free_pci;
4996 }
4997
4998 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4999 err = sky2_test_msi(hw);
5000 if (err == -EOPNOTSUPP)
5001 pci_disable_msi(pdev);
5002 else if (err)
5003 goto err_out_free_netdev;
5004 }
5005
5006 err = register_netdev(dev);
5007 if (err) {
5008 dev_err(&pdev->dev, "cannot register net device\n");
5009 goto err_out_free_netdev;
5010 }
5011
5012 netif_carrier_off(dev);
5013
5014 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
5015
5016 sky2_show_addr(dev);
5017
5018 if (hw->ports > 1) {
5019 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
5020 if (!dev1) {
5021 err = -ENOMEM;
5022 goto err_out_unregister;
5023 }
5024
5025 err = register_netdev(dev1);
5026 if (err) {
5027 dev_err(&pdev->dev, "cannot register second net device\n");
5028 goto err_out_free_dev1;
5029 }
5030
5031 err = sky2_setup_irq(hw, hw->irq_name);
5032 if (err)
5033 goto err_out_unregister_dev1;
5034
5035 sky2_show_addr(dev1);
5036 }
5037
5038 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
5039 INIT_WORK(&hw->restart_work, sky2_restart);
5040
5041 pci_set_drvdata(pdev, hw);
5042 pdev->d3_delay = 150;
5043
5044 return 0;
5045
5046 err_out_unregister_dev1:
5047 unregister_netdev(dev1);
5048 err_out_free_dev1:
5049 free_netdev(dev1);
5050 err_out_unregister:
5051 if (hw->flags & SKY2_HW_USE_MSI)
5052 pci_disable_msi(pdev);
5053 unregister_netdev(dev);
5054 err_out_free_netdev:
5055 free_netdev(dev);
5056 err_out_free_pci:
5057 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
5058 hw->st_le, hw->st_dma);
5059 err_out_reset:
5060 sky2_write8(hw, B0_CTST, CS_RST_SET);
5061 err_out_iounmap:
5062 iounmap(hw->regs);
5063 err_out_free_hw:
5064 kfree(hw);
5065 err_out_free_regions:
5066 pci_release_regions(pdev);
5067 err_out_disable:
5068 pci_disable_device(pdev);
5069 err_out:
5070 pci_set_drvdata(pdev, NULL);
5071 return err;
5072 }
5073
5074 static void __devexit sky2_remove(struct pci_dev *pdev)
5075 {
5076 struct sky2_hw *hw = pci_get_drvdata(pdev);
5077 int i;
5078
5079 if (!hw)
5080 return;
5081
5082 del_timer_sync(&hw->watchdog_timer);
5083 cancel_work_sync(&hw->restart_work);
5084
5085 for (i = hw->ports-1; i >= 0; --i)
5086 unregister_netdev(hw->dev[i]);
5087
5088 sky2_write32(hw, B0_IMSK, 0);
5089 sky2_read32(hw, B0_IMSK);
5090
5091 sky2_power_aux(hw);
5092
5093 sky2_write8(hw, B0_CTST, CS_RST_SET);
5094 sky2_read8(hw, B0_CTST);
5095
5096 if (hw->ports > 1) {
5097 napi_disable(&hw->napi);
5098 free_irq(pdev->irq, hw);
5099 }
5100
5101 if (hw->flags & SKY2_HW_USE_MSI)
5102 pci_disable_msi(pdev);
5103 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
5104 hw->st_le, hw->st_dma);
5105 pci_release_regions(pdev);
5106 pci_disable_device(pdev);
5107
5108 for (i = hw->ports-1; i >= 0; --i)
5109 free_netdev(hw->dev[i]);
5110
5111 iounmap(hw->regs);
5112 kfree(hw);
5113
5114 pci_set_drvdata(pdev, NULL);
5115 }
5116
5117 static int sky2_suspend(struct device *dev)
5118 {
5119 struct pci_dev *pdev = to_pci_dev(dev);
5120 struct sky2_hw *hw = pci_get_drvdata(pdev);
5121 int i;
5122
5123 if (!hw)
5124 return 0;
5125
5126 del_timer_sync(&hw->watchdog_timer);
5127 cancel_work_sync(&hw->restart_work);
5128
5129 rtnl_lock();
5130
5131 sky2_all_down(hw);
5132 for (i = 0; i < hw->ports; i++) {
5133 struct net_device *dev = hw->dev[i];
5134 struct sky2_port *sky2 = netdev_priv(dev);
5135
5136 if (sky2->wol)
5137 sky2_wol_init(sky2);
5138 }
5139
5140 sky2_power_aux(hw);
5141 rtnl_unlock();
5142
5143 return 0;
5144 }
5145
5146 #ifdef CONFIG_PM_SLEEP
5147 static int sky2_resume(struct device *dev)
5148 {
5149 struct pci_dev *pdev = to_pci_dev(dev);
5150 struct sky2_hw *hw = pci_get_drvdata(pdev);
5151 int err;
5152
5153 if (!hw)
5154 return 0;
5155
5156 /* Re-enable all clocks */
5157 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
5158 if (err) {
5159 dev_err(&pdev->dev, "PCI write config failed\n");
5160 goto out;
5161 }
5162
5163 rtnl_lock();
5164 sky2_reset(hw);
5165 sky2_all_up(hw);
5166 rtnl_unlock();
5167
5168 return 0;
5169 out:
5170
5171 dev_err(&pdev->dev, "resume failed (%d)\n", err);
5172 pci_disable_device(pdev);
5173 return err;
5174 }
5175
5176 static SIMPLE_DEV_PM_OPS(sky2_pm_ops, sky2_suspend, sky2_resume);
5177 #define SKY2_PM_OPS (&sky2_pm_ops)
5178
5179 #else
5180
5181 #define SKY2_PM_OPS NULL
5182 #endif
5183
5184 static void sky2_shutdown(struct pci_dev *pdev)
5185 {
5186 sky2_suspend(&pdev->dev);
5187 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));
5188 pci_set_power_state(pdev, PCI_D3hot);
5189 }
5190
5191 static struct pci_driver sky2_driver = {
5192 .name = DRV_NAME,
5193 .id_table = sky2_id_table,
5194 .probe = sky2_probe,
5195 .remove = __devexit_p(sky2_remove),
5196 .shutdown = sky2_shutdown,
5197 .driver.pm = SKY2_PM_OPS,
5198 };
5199
5200 static int __init sky2_init_module(void)
5201 {
5202 pr_info("driver version " DRV_VERSION "\n");
5203
5204 sky2_debug_init();
5205 return pci_register_driver(&sky2_driver);
5206 }
5207
5208 static void __exit sky2_cleanup_module(void)
5209 {
5210 pci_unregister_driver(&sky2_driver);
5211 sky2_debug_cleanup();
5212 }
5213
5214 module_init(sky2_init_module);
5215 module_exit(sky2_cleanup_module);
5216
5217 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
5218 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
5219 MODULE_LICENSE("GPL");
5220 MODULE_VERSION(DRV_VERSION);
Linux with added FPC-III support