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Linux 3.4.102
[linux/fpc-iii.git] / drivers / net / ethernet / mellanox / mlx4 / main.c
blob6e49bb47f8b2cd8353674c8bfcf74d68aca0d165
1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36 #include <linux/module.h>
37 #include <linux/init.h>
38 #include <linux/errno.h>
39 #include <linux/pci.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/slab.h>
42 #include <linux/io-mapping.h>
43 #include <linux/delay.h>
44
45 #include <linux/mlx4/device.h>
46 #include <linux/mlx4/doorbell.h>
47
48 #include "mlx4.h"
49 #include "fw.h"
50 #include "icm.h"
51
52 MODULE_AUTHOR("Roland Dreier");
53 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
54 MODULE_LICENSE("Dual BSD/GPL");
55 MODULE_VERSION(DRV_VERSION);
56
57 struct workqueue_struct *mlx4_wq;
58
59 #ifdef CONFIG_MLX4_DEBUG
60
61 int mlx4_debug_level = 0;
62 module_param_named(debug_level, mlx4_debug_level, int, 0644);
63 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
64
65 #endif /* CONFIG_MLX4_DEBUG */
66
67 #ifdef CONFIG_PCI_MSI
68
69 static int msi_x = 1;
70 module_param(msi_x, int, 0444);
71 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
72
73 #else /* CONFIG_PCI_MSI */
74
75 #define msi_x (0)
76
77 #endif /* CONFIG_PCI_MSI */
78
79 static int num_vfs;
80 module_param(num_vfs, int, 0444);
81 MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0");
82
83 static int probe_vf;
84 module_param(probe_vf, int, 0644);
85 MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)");
86
87 int mlx4_log_num_mgm_entry_size = 10;
88 module_param_named(log_num_mgm_entry_size,
89 mlx4_log_num_mgm_entry_size, int, 0444);
90 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
91 " of qp per mcg, for example:"
92 " 10 gives 248.range: 9<="
93 " log_num_mgm_entry_size <= 12");
94
95 #define HCA_GLOBAL_CAP_MASK 0
96 #define PF_CONTEXT_BEHAVIOUR_MASK 0
97
98 static char mlx4_version[] __devinitdata =
99 DRV_NAME ": Mellanox ConnectX core driver v"
100 DRV_VERSION " (" DRV_RELDATE ")\n";
101
102 static struct mlx4_profile default_profile = {
103 .num_qp = 1 << 18,
104 .num_srq = 1 << 16,
105 .rdmarc_per_qp = 1 << 4,
106 .num_cq = 1 << 16,
107 .num_mcg = 1 << 13,
108 .num_mpt = 1 << 19,
109 .num_mtt = 1 << 20, /* It is really num mtt segements */
110 };
111
112 static int log_num_mac = 7;
113 module_param_named(log_num_mac, log_num_mac, int, 0444);
114 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
115
116 static int log_num_vlan;
117 module_param_named(log_num_vlan, log_num_vlan, int, 0444);
118 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
119 /* Log2 max number of VLANs per ETH port (0-7) */
120 #define MLX4_LOG_NUM_VLANS 7
121
122 static bool use_prio;
123 module_param_named(use_prio, use_prio, bool, 0444);
124 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports "
125 "(0/1, default 0)");
126
127 int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
128 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
129 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
130
131 static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
132 static int arr_argc = 2;
133 module_param_array(port_type_array, int, &arr_argc, 0444);
134 MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
135 "1 for IB, 2 for Ethernet");
136
137 struct mlx4_port_config {
138 struct list_head list;
139 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
140 struct pci_dev *pdev;
141 };
142
143 static inline int mlx4_master_get_num_eqs(struct mlx4_dev *dev)
144 {
145 return dev->caps.reserved_eqs +
146 MLX4_MFUNC_EQ_NUM * (dev->num_slaves + 1);
147 }
148
149 int mlx4_check_port_params(struct mlx4_dev *dev,
150 enum mlx4_port_type *port_type)
151 {
152 int i;
153
154 for (i = 0; i < dev->caps.num_ports - 1; i++) {
155 if (port_type[i] != port_type[i + 1]) {
156 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
157 mlx4_err(dev, "Only same port types supported "
158 "on this HCA, aborting.\n");
159 return -EINVAL;
160 }
161 if (port_type[i] == MLX4_PORT_TYPE_ETH &&
162 port_type[i + 1] == MLX4_PORT_TYPE_IB)
163 return -EINVAL;
164 }
165 }
166
167 for (i = 0; i < dev->caps.num_ports; i++) {
168 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
169 mlx4_err(dev, "Requested port type for port %d is not "
170 "supported on this HCA\n", i + 1);
171 return -EINVAL;
172 }
173 }
174 return 0;
175 }
176
177 static void mlx4_set_port_mask(struct mlx4_dev *dev)
178 {
179 int i;
180
181 for (i = 1; i <= dev->caps.num_ports; ++i)
182 dev->caps.port_mask[i] = dev->caps.port_type[i];
183 }
184
185 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
186 {
187 int err;
188 int i;
189
190 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
191 if (err) {
192 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
193 return err;
194 }
195
196 if (dev_cap->min_page_sz > PAGE_SIZE) {
197 mlx4_err(dev, "HCA minimum page size of %d bigger than "
198 "kernel PAGE_SIZE of %ld, aborting.\n",
199 dev_cap->min_page_sz, PAGE_SIZE);
200 return -ENODEV;
201 }
202 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
203 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
204 "aborting.\n",
205 dev_cap->num_ports, MLX4_MAX_PORTS);
206 return -ENODEV;
207 }
208
209 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
210 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
211 "PCI resource 2 size of 0x%llx, aborting.\n",
212 dev_cap->uar_size,
213 (unsigned long long) pci_resource_len(dev->pdev, 2));
214 return -ENODEV;
215 }
216
217 dev->caps.num_ports = dev_cap->num_ports;
218 for (i = 1; i <= dev->caps.num_ports; ++i) {
219 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
220 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i];
221 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
222 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
223 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
224 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i];
225 dev->caps.def_mac[i] = dev_cap->def_mac[i];
226 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
227 dev->caps.suggested_type[i] = dev_cap->suggested_type[i];
228 dev->caps.default_sense[i] = dev_cap->default_sense[i];
229 dev->caps.trans_type[i] = dev_cap->trans_type[i];
230 dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i];
231 dev->caps.wavelength[i] = dev_cap->wavelength[i];
232 dev->caps.trans_code[i] = dev_cap->trans_code[i];
233 }
234
235 dev->caps.uar_page_size = PAGE_SIZE;
236 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
237 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
238 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
239 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
240 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
241 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
242 dev->caps.max_wqes = dev_cap->max_qp_sz;
243 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
244 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
245 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
246 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
247 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
248 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
249 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
250 /*
251 * Subtract 1 from the limit because we need to allocate a
252 * spare CQE so the HCA HW can tell the difference between an
253 * empty CQ and a full CQ.
254 */
255 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
256 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
257 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
258 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
259 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
260
261 /* The first 128 UARs are used for EQ doorbells */
262 dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars);
263 dev->caps.reserved_pds = dev_cap->reserved_pds;
264 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
265 dev_cap->reserved_xrcds : 0;
266 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
267 dev_cap->max_xrcds : 0;
268 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
269
270 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
271 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
272 dev->caps.flags = dev_cap->flags;
273 dev->caps.bmme_flags = dev_cap->bmme_flags;
274 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
275 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
276 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
277
278 /* Sense port always allowed on supported devices for ConnectX1 and 2 */
279 if (dev->pdev->device != 0x1003)
280 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
281
282 dev->caps.log_num_macs = log_num_mac;
283 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
284 dev->caps.log_num_prios = use_prio ? 3 : 0;
285
286 for (i = 1; i <= dev->caps.num_ports; ++i) {
287 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
288 if (dev->caps.supported_type[i]) {
289 /* if only ETH is supported - assign ETH */
290 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
291 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
292 /* if only IB is supported,
293 * assign IB only if SRIOV is off*/
294 else if (dev->caps.supported_type[i] ==
295 MLX4_PORT_TYPE_IB) {
296 if (dev->flags & MLX4_FLAG_SRIOV)
297 dev->caps.port_type[i] =
298 MLX4_PORT_TYPE_NONE;
299 else
300 dev->caps.port_type[i] =
301 MLX4_PORT_TYPE_IB;
302 /* if IB and ETH are supported,
303 * first of all check if SRIOV is on */
304 } else if (dev->flags & MLX4_FLAG_SRIOV)
305 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
306 else {
307 /* In non-SRIOV mode, we set the port type
308 * according to user selection of port type,
309 * if usere selected none, take the FW hint */
310 if (port_type_array[i-1] == MLX4_PORT_TYPE_NONE)
311 dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
312 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
313 else
314 dev->caps.port_type[i] = port_type_array[i-1];
315 }
316 }
317 /*
318 * Link sensing is allowed on the port if 3 conditions are true:
319 * 1. Both protocols are supported on the port.
320 * 2. Different types are supported on the port
321 * 3. FW declared that it supports link sensing
322 */
323 mlx4_priv(dev)->sense.sense_allowed[i] =
324 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
325 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
326 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
327
328 /*
329 * If "default_sense" bit is set, we move the port to "AUTO" mode
330 * and perform sense_port FW command to try and set the correct
331 * port type from beginning
332 */
333 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
334 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
335 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
336 mlx4_SENSE_PORT(dev, i, &sensed_port);
337 if (sensed_port != MLX4_PORT_TYPE_NONE)
338 dev->caps.port_type[i] = sensed_port;
339 } else {
340 dev->caps.possible_type[i] = dev->caps.port_type[i];
341 }
342
343 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
344 dev->caps.log_num_macs = dev_cap->log_max_macs[i];
345 mlx4_warn(dev, "Requested number of MACs is too much "
346 "for port %d, reducing to %d.\n",
347 i, 1 << dev->caps.log_num_macs);
348 }
349 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
350 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
351 mlx4_warn(dev, "Requested number of VLANs is too much "
352 "for port %d, reducing to %d.\n",
353 i, 1 << dev->caps.log_num_vlans);
354 }
355 }
356
357 dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters);
358
359 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
360 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
361 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
362 (1 << dev->caps.log_num_macs) *
363 (1 << dev->caps.log_num_vlans) *
364 (1 << dev->caps.log_num_prios) *
365 dev->caps.num_ports;
366 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
367
368 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
369 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
370 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
371 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
372
373 return 0;
374 }
375 /*The function checks if there are live vf, return the num of them*/
376 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
377 {
378 struct mlx4_priv *priv = mlx4_priv(dev);
379 struct mlx4_slave_state *s_state;
380 int i;
381 int ret = 0;
382
383 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
384 s_state = &priv->mfunc.master.slave_state[i];
385 if (s_state->active && s_state->last_cmd !=
386 MLX4_COMM_CMD_RESET) {
387 mlx4_warn(dev, "%s: slave: %d is still active\n",
388 __func__, i);
389 ret++;
390 }
391 }
392 return ret;
393 }
394
395 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
396 {
397 struct mlx4_priv *priv = mlx4_priv(dev);
398 struct mlx4_slave_state *s_slave;
399
400 if (!mlx4_is_master(dev))
401 return 0;
402
403 s_slave = &priv->mfunc.master.slave_state[slave];
404 return !!s_slave->active;
405 }
406 EXPORT_SYMBOL(mlx4_is_slave_active);
407
408 static int mlx4_slave_cap(struct mlx4_dev *dev)
409 {
410 int err;
411 u32 page_size;
412 struct mlx4_dev_cap dev_cap;
413 struct mlx4_func_cap func_cap;
414 struct mlx4_init_hca_param hca_param;
415 int i;
416
417 memset(&hca_param, 0, sizeof(hca_param));
418 err = mlx4_QUERY_HCA(dev, &hca_param);
419 if (err) {
420 mlx4_err(dev, "QUERY_HCA command failed, aborting.\n");
421 return err;
422 }
423
424 /*fail if the hca has an unknown capability */
425 if ((hca_param.global_caps | HCA_GLOBAL_CAP_MASK) !=
426 HCA_GLOBAL_CAP_MASK) {
427 mlx4_err(dev, "Unknown hca global capabilities\n");
428 return -ENOSYS;
429 }
430
431 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
432
433 memset(&dev_cap, 0, sizeof(dev_cap));
434 err = mlx4_dev_cap(dev, &dev_cap);
435 if (err) {
436 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
437 return err;
438 }
439
440 page_size = ~dev->caps.page_size_cap + 1;
441 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
442 if (page_size > PAGE_SIZE) {
443 mlx4_err(dev, "HCA minimum page size of %d bigger than "
444 "kernel PAGE_SIZE of %ld, aborting.\n",
445 page_size, PAGE_SIZE);
446 return -ENODEV;
447 }
448
449 /* slave gets uar page size from QUERY_HCA fw command */
450 dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
451
452 /* TODO: relax this assumption */
453 if (dev->caps.uar_page_size != PAGE_SIZE) {
454 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
455 dev->caps.uar_page_size, PAGE_SIZE);
456 return -ENODEV;
457 }
458
459 memset(&func_cap, 0, sizeof(func_cap));
460 err = mlx4_QUERY_FUNC_CAP(dev, &func_cap);
461 if (err) {
462 mlx4_err(dev, "QUERY_FUNC_CAP command failed, aborting.\n");
463 return err;
464 }
465
466 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
467 PF_CONTEXT_BEHAVIOUR_MASK) {
468 mlx4_err(dev, "Unknown pf context behaviour\n");
469 return -ENOSYS;
470 }
471
472 dev->caps.num_ports = func_cap.num_ports;
473 dev->caps.num_qps = func_cap.qp_quota;
474 dev->caps.num_srqs = func_cap.srq_quota;
475 dev->caps.num_cqs = func_cap.cq_quota;
476 dev->caps.num_eqs = func_cap.max_eq;
477 dev->caps.reserved_eqs = func_cap.reserved_eq;
478 dev->caps.num_mpts = func_cap.mpt_quota;
479 dev->caps.num_mtts = func_cap.mtt_quota;
480 dev->caps.num_pds = MLX4_NUM_PDS;
481 dev->caps.num_mgms = 0;
482 dev->caps.num_amgms = 0;
483
484 for (i = 1; i <= dev->caps.num_ports; ++i)
485 dev->caps.port_mask[i] = dev->caps.port_type[i];
486
487 if (dev->caps.num_ports > MLX4_MAX_PORTS) {
488 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
489 "aborting.\n", dev->caps.num_ports, MLX4_MAX_PORTS);
490 return -ENODEV;
491 }
492
493 if (dev->caps.uar_page_size * (dev->caps.num_uars -
494 dev->caps.reserved_uars) >
495 pci_resource_len(dev->pdev, 2)) {
496 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than "
497 "PCI resource 2 size of 0x%llx, aborting.\n",
498 dev->caps.uar_page_size * dev->caps.num_uars,
499 (unsigned long long) pci_resource_len(dev->pdev, 2));
500 return -ENODEV;
501 }
502
503 #if 0
504 mlx4_warn(dev, "sqp_demux:%d\n", dev->caps.sqp_demux);
505 mlx4_warn(dev, "num_uars:%d reserved_uars:%d uar region:0x%x bar2:0x%llx\n",
506 dev->caps.num_uars, dev->caps.reserved_uars,
507 dev->caps.uar_page_size * dev->caps.num_uars,
508 pci_resource_len(dev->pdev, 2));
509 mlx4_warn(dev, "num_eqs:%d reserved_eqs:%d\n", dev->caps.num_eqs,
510 dev->caps.reserved_eqs);
511 mlx4_warn(dev, "num_pds:%d reserved_pds:%d slave_pd_shift:%d pd_base:%d\n",
512 dev->caps.num_pds, dev->caps.reserved_pds,
513 dev->caps.slave_pd_shift, dev->caps.pd_base);
514 #endif
515 return 0;
516 }
517
518 /*
519 * Change the port configuration of the device.
520 * Every user of this function must hold the port mutex.
521 */
522 int mlx4_change_port_types(struct mlx4_dev *dev,
523 enum mlx4_port_type *port_types)
524 {
525 int err = 0;
526 int change = 0;
527 int port;
528
529 for (port = 0; port < dev->caps.num_ports; port++) {
530 /* Change the port type only if the new type is different
531 * from the current, and not set to Auto */
532 if (port_types[port] != dev->caps.port_type[port + 1])
533 change = 1;
534 }
535 if (change) {
536 mlx4_unregister_device(dev);
537 for (port = 1; port <= dev->caps.num_ports; port++) {
538 mlx4_CLOSE_PORT(dev, port);
539 dev->caps.port_type[port] = port_types[port - 1];
540 err = mlx4_SET_PORT(dev, port);
541 if (err) {
542 mlx4_err(dev, "Failed to set port %d, "
543 "aborting\n", port);
544 goto out;
545 }
546 }
547 mlx4_set_port_mask(dev);
548 err = mlx4_register_device(dev);
549 }
550
551 out:
552 return err;
553 }
554
555 static ssize_t show_port_type(struct device *dev,
556 struct device_attribute *attr,
557 char *buf)
558 {
559 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
560 port_attr);
561 struct mlx4_dev *mdev = info->dev;
562 char type[8];
563
564 sprintf(type, "%s",
565 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
566 "ib" : "eth");
567 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
568 sprintf(buf, "auto (%s)\n", type);
569 else
570 sprintf(buf, "%s\n", type);
571
572 return strlen(buf);
573 }
574
575 static ssize_t set_port_type(struct device *dev,
576 struct device_attribute *attr,
577 const char *buf, size_t count)
578 {
579 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
580 port_attr);
581 struct mlx4_dev *mdev = info->dev;
582 struct mlx4_priv *priv = mlx4_priv(mdev);
583 enum mlx4_port_type types[MLX4_MAX_PORTS];
584 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
585 int i;
586 int err = 0;
587
588 if (!strcmp(buf, "ib\n"))
589 info->tmp_type = MLX4_PORT_TYPE_IB;
590 else if (!strcmp(buf, "eth\n"))
591 info->tmp_type = MLX4_PORT_TYPE_ETH;
592 else if (!strcmp(buf, "auto\n"))
593 info->tmp_type = MLX4_PORT_TYPE_AUTO;
594 else {
595 mlx4_err(mdev, "%s is not supported port type\n", buf);
596 return -EINVAL;
597 }
598
599 mlx4_stop_sense(mdev);
600 mutex_lock(&priv->port_mutex);
601 /* Possible type is always the one that was delivered */
602 mdev->caps.possible_type[info->port] = info->tmp_type;
603
604 for (i = 0; i < mdev->caps.num_ports; i++) {
605 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
606 mdev->caps.possible_type[i+1];
607 if (types[i] == MLX4_PORT_TYPE_AUTO)
608 types[i] = mdev->caps.port_type[i+1];
609 }
610
611 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
612 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
613 for (i = 1; i <= mdev->caps.num_ports; i++) {
614 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
615 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
616 err = -EINVAL;
617 }
618 }
619 }
620 if (err) {
621 mlx4_err(mdev, "Auto sensing is not supported on this HCA. "
622 "Set only 'eth' or 'ib' for both ports "
623 "(should be the same)\n");
624 goto out;
625 }
626
627 mlx4_do_sense_ports(mdev, new_types, types);
628
629 err = mlx4_check_port_params(mdev, new_types);
630 if (err)
631 goto out;
632
633 /* We are about to apply the changes after the configuration
634 * was verified, no need to remember the temporary types
635 * any more */
636 for (i = 0; i < mdev->caps.num_ports; i++)
637 priv->port[i + 1].tmp_type = 0;
638
639 err = mlx4_change_port_types(mdev, new_types);
640
641 out:
642 mlx4_start_sense(mdev);
643 mutex_unlock(&priv->port_mutex);
644 return err ? err : count;
645 }
646
647 enum ibta_mtu {
648 IB_MTU_256 = 1,
649 IB_MTU_512 = 2,
650 IB_MTU_1024 = 3,
651 IB_MTU_2048 = 4,
652 IB_MTU_4096 = 5
653 };
654
655 static inline int int_to_ibta_mtu(int mtu)
656 {
657 switch (mtu) {
658 case 256: return IB_MTU_256;
659 case 512: return IB_MTU_512;
660 case 1024: return IB_MTU_1024;
661 case 2048: return IB_MTU_2048;
662 case 4096: return IB_MTU_4096;
663 default: return -1;
664 }
665 }
666
667 static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
668 {
669 switch (mtu) {
670 case IB_MTU_256: return 256;
671 case IB_MTU_512: return 512;
672 case IB_MTU_1024: return 1024;
673 case IB_MTU_2048: return 2048;
674 case IB_MTU_4096: return 4096;
675 default: return -1;
676 }
677 }
678
679 static ssize_t show_port_ib_mtu(struct device *dev,
680 struct device_attribute *attr,
681 char *buf)
682 {
683 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
684 port_mtu_attr);
685 struct mlx4_dev *mdev = info->dev;
686
687 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
688 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
689
690 sprintf(buf, "%d\n",
691 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
692 return strlen(buf);
693 }
694
695 static ssize_t set_port_ib_mtu(struct device *dev,
696 struct device_attribute *attr,
697 const char *buf, size_t count)
698 {
699 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
700 port_mtu_attr);
701 struct mlx4_dev *mdev = info->dev;
702 struct mlx4_priv *priv = mlx4_priv(mdev);
703 int err, port, mtu, ibta_mtu = -1;
704
705 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
706 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
707 return -EINVAL;
708 }
709
710 err = sscanf(buf, "%d", &mtu);
711 if (err > 0)
712 ibta_mtu = int_to_ibta_mtu(mtu);
713
714 if (err <= 0 || ibta_mtu < 0) {
715 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
716 return -EINVAL;
717 }
718
719 mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
720
721 mlx4_stop_sense(mdev);
722 mutex_lock(&priv->port_mutex);
723 mlx4_unregister_device(mdev);
724 for (port = 1; port <= mdev->caps.num_ports; port++) {
725 mlx4_CLOSE_PORT(mdev, port);
726 err = mlx4_SET_PORT(mdev, port);
727 if (err) {
728 mlx4_err(mdev, "Failed to set port %d, "
729 "aborting\n", port);
730 goto err_set_port;
731 }
732 }
733 err = mlx4_register_device(mdev);
734 err_set_port:
735 mutex_unlock(&priv->port_mutex);
736 mlx4_start_sense(mdev);
737 return err ? err : count;
738 }
739
740 static int mlx4_load_fw(struct mlx4_dev *dev)
741 {
742 struct mlx4_priv *priv = mlx4_priv(dev);
743 int err;
744
745 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
746 GFP_HIGHUSER | __GFP_NOWARN, 0);
747 if (!priv->fw.fw_icm) {
748 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
749 return -ENOMEM;
750 }
751
752 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
753 if (err) {
754 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
755 goto err_free;
756 }
757
758 err = mlx4_RUN_FW(dev);
759 if (err) {
760 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
761 goto err_unmap_fa;
762 }
763
764 return 0;
765
766 err_unmap_fa:
767 mlx4_UNMAP_FA(dev);
768
769 err_free:
770 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
771 return err;
772 }
773
774 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
775 int cmpt_entry_sz)
776 {
777 struct mlx4_priv *priv = mlx4_priv(dev);
778 int err;
779 int num_eqs;
780
781 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
782 cmpt_base +
783 ((u64) (MLX4_CMPT_TYPE_QP *
784 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
785 cmpt_entry_sz, dev->caps.num_qps,
786 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
787 0, 0);
788 if (err)
789 goto err;
790
791 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
792 cmpt_base +
793 ((u64) (MLX4_CMPT_TYPE_SRQ *
794 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
795 cmpt_entry_sz, dev->caps.num_srqs,
796 dev->caps.reserved_srqs, 0, 0);
797 if (err)
798 goto err_qp;
799
800 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
801 cmpt_base +
802 ((u64) (MLX4_CMPT_TYPE_CQ *
803 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
804 cmpt_entry_sz, dev->caps.num_cqs,
805 dev->caps.reserved_cqs, 0, 0);
806 if (err)
807 goto err_srq;
808
809 num_eqs = (mlx4_is_master(dev)) ?
810 roundup_pow_of_two(mlx4_master_get_num_eqs(dev)) :
811 dev->caps.num_eqs;
812 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
813 cmpt_base +
814 ((u64) (MLX4_CMPT_TYPE_EQ *
815 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
816 cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
817 if (err)
818 goto err_cq;
819
820 return 0;
821
822 err_cq:
823 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
824
825 err_srq:
826 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
827
828 err_qp:
829 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
830
831 err:
832 return err;
833 }
834
835 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
836 struct mlx4_init_hca_param *init_hca, u64 icm_size)
837 {
838 struct mlx4_priv *priv = mlx4_priv(dev);
839 u64 aux_pages;
840 int num_eqs;
841 int err;
842
843 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
844 if (err) {
845 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
846 return err;
847 }
848
849 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
850 (unsigned long long) icm_size >> 10,
851 (unsigned long long) aux_pages << 2);
852
853 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
854 GFP_HIGHUSER | __GFP_NOWARN, 0);
855 if (!priv->fw.aux_icm) {
856 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
857 return -ENOMEM;
858 }
859
860 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
861 if (err) {
862 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
863 goto err_free_aux;
864 }
865
866 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
867 if (err) {
868 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
869 goto err_unmap_aux;
870 }
871
872
873 num_eqs = (mlx4_is_master(dev)) ?
874 roundup_pow_of_two(mlx4_master_get_num_eqs(dev)) :
875 dev->caps.num_eqs;
876 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
877 init_hca->eqc_base, dev_cap->eqc_entry_sz,
878 num_eqs, num_eqs, 0, 0);
879 if (err) {
880 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
881 goto err_unmap_cmpt;
882 }
883
884 /*
885 * Reserved MTT entries must be aligned up to a cacheline
886 * boundary, since the FW will write to them, while the driver
887 * writes to all other MTT entries. (The variable
888 * dev->caps.mtt_entry_sz below is really the MTT segment
889 * size, not the raw entry size)
890 */
891 dev->caps.reserved_mtts =
892 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
893 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
894
895 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
896 init_hca->mtt_base,
897 dev->caps.mtt_entry_sz,
898 dev->caps.num_mtts,
899 dev->caps.reserved_mtts, 1, 0);
900 if (err) {
901 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
902 goto err_unmap_eq;
903 }
904
905 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
906 init_hca->dmpt_base,
907 dev_cap->dmpt_entry_sz,
908 dev->caps.num_mpts,
909 dev->caps.reserved_mrws, 1, 1);
910 if (err) {
911 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
912 goto err_unmap_mtt;
913 }
914
915 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
916 init_hca->qpc_base,
917 dev_cap->qpc_entry_sz,
918 dev->caps.num_qps,
919 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
920 0, 0);
921 if (err) {
922 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
923 goto err_unmap_dmpt;
924 }
925
926 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
927 init_hca->auxc_base,
928 dev_cap->aux_entry_sz,
929 dev->caps.num_qps,
930 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
931 0, 0);
932 if (err) {
933 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
934 goto err_unmap_qp;
935 }
936
937 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
938 init_hca->altc_base,
939 dev_cap->altc_entry_sz,
940 dev->caps.num_qps,
941 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
942 0, 0);
943 if (err) {
944 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
945 goto err_unmap_auxc;
946 }
947
948 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
949 init_hca->rdmarc_base,
950 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
951 dev->caps.num_qps,
952 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
953 0, 0);
954 if (err) {
955 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
956 goto err_unmap_altc;
957 }
958
959 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
960 init_hca->cqc_base,
961 dev_cap->cqc_entry_sz,
962 dev->caps.num_cqs,
963 dev->caps.reserved_cqs, 0, 0);
964 if (err) {
965 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
966 goto err_unmap_rdmarc;
967 }
968
969 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
970 init_hca->srqc_base,
971 dev_cap->srq_entry_sz,
972 dev->caps.num_srqs,
973 dev->caps.reserved_srqs, 0, 0);
974 if (err) {
975 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
976 goto err_unmap_cq;
977 }
978
979 /*
980 * It's not strictly required, but for simplicity just map the
981 * whole multicast group table now. The table isn't very big
982 * and it's a lot easier than trying to track ref counts.
983 */
984 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
985 init_hca->mc_base,
986 mlx4_get_mgm_entry_size(dev),
987 dev->caps.num_mgms + dev->caps.num_amgms,
988 dev->caps.num_mgms + dev->caps.num_amgms,
989 0, 0);
990 if (err) {
991 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
992 goto err_unmap_srq;
993 }
994
995 return 0;
996
997 err_unmap_srq:
998 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
999
1000 err_unmap_cq:
1001 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1002
1003 err_unmap_rdmarc:
1004 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1005
1006 err_unmap_altc:
1007 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1008
1009 err_unmap_auxc:
1010 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1011
1012 err_unmap_qp:
1013 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1014
1015 err_unmap_dmpt:
1016 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1017
1018 err_unmap_mtt:
1019 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1020
1021 err_unmap_eq:
1022 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1023
1024 err_unmap_cmpt:
1025 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1026 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1027 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1028 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1029
1030 err_unmap_aux:
1031 mlx4_UNMAP_ICM_AUX(dev);
1032
1033 err_free_aux:
1034 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1035
1036 return err;
1037 }
1038
1039 static void mlx4_free_icms(struct mlx4_dev *dev)
1040 {
1041 struct mlx4_priv *priv = mlx4_priv(dev);
1042
1043 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1044 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1045 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1046 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1047 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1048 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1049 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1050 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1051 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1052 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1053 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1054 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1055 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1056 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1057
1058 mlx4_UNMAP_ICM_AUX(dev);
1059 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1060 }
1061
1062 static void mlx4_slave_exit(struct mlx4_dev *dev)
1063 {
1064 struct mlx4_priv *priv = mlx4_priv(dev);
1065
1066 down(&priv->cmd.slave_sem);
1067 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME))
1068 mlx4_warn(dev, "Failed to close slave function.\n");
1069 up(&priv->cmd.slave_sem);
1070 }
1071
1072 static int map_bf_area(struct mlx4_dev *dev)
1073 {
1074 struct mlx4_priv *priv = mlx4_priv(dev);
1075 resource_size_t bf_start;
1076 resource_size_t bf_len;
1077 int err = 0;
1078
1079 if (!dev->caps.bf_reg_size)
1080 return -ENXIO;
1081
1082 bf_start = pci_resource_start(dev->pdev, 2) +
1083 (dev->caps.num_uars << PAGE_SHIFT);
1084 bf_len = pci_resource_len(dev->pdev, 2) -
1085 (dev->caps.num_uars << PAGE_SHIFT);
1086 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1087 if (!priv->bf_mapping)
1088 err = -ENOMEM;
1089
1090 return err;
1091 }
1092
1093 static void unmap_bf_area(struct mlx4_dev *dev)
1094 {
1095 if (mlx4_priv(dev)->bf_mapping)
1096 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1097 }
1098
1099 static void mlx4_close_hca(struct mlx4_dev *dev)
1100 {
1101 unmap_bf_area(dev);
1102 if (mlx4_is_slave(dev))
1103 mlx4_slave_exit(dev);
1104 else {
1105 mlx4_CLOSE_HCA(dev, 0);
1106 mlx4_free_icms(dev);
1107 mlx4_UNMAP_FA(dev);
1108 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1109 }
1110 }
1111
1112 static int mlx4_init_slave(struct mlx4_dev *dev)
1113 {
1114 struct mlx4_priv *priv = mlx4_priv(dev);
1115 u64 dma = (u64) priv->mfunc.vhcr_dma;
1116 int num_of_reset_retries = NUM_OF_RESET_RETRIES;
1117 int ret_from_reset = 0;
1118 u32 slave_read;
1119 u32 cmd_channel_ver;
1120
1121 down(&priv->cmd.slave_sem);
1122 priv->cmd.max_cmds = 1;
1123 mlx4_warn(dev, "Sending reset\n");
1124 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1125 MLX4_COMM_TIME);
1126 /* if we are in the middle of flr the slave will try
1127 * NUM_OF_RESET_RETRIES times before leaving.*/
1128 if (ret_from_reset) {
1129 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1130 msleep(SLEEP_TIME_IN_RESET);
1131 while (ret_from_reset && num_of_reset_retries) {
1132 mlx4_warn(dev, "slave is currently in the"
1133 "middle of FLR. retrying..."
1134 "(try num:%d)\n",
1135 (NUM_OF_RESET_RETRIES -
1136 num_of_reset_retries + 1));
1137 ret_from_reset =
1138 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET,
1139 0, MLX4_COMM_TIME);
1140 num_of_reset_retries = num_of_reset_retries - 1;
1141 }
1142 } else
1143 goto err;
1144 }
1145
1146 /* check the driver version - the slave I/F revision
1147 * must match the master's */
1148 slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1149 cmd_channel_ver = mlx4_comm_get_version();
1150
1151 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1152 MLX4_COMM_GET_IF_REV(slave_read)) {
1153 mlx4_err(dev, "slave driver version is not supported"
1154 " by the master\n");
1155 goto err;
1156 }
1157
1158 mlx4_warn(dev, "Sending vhcr0\n");
1159 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1160 MLX4_COMM_TIME))
1161 goto err;
1162 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1163 MLX4_COMM_TIME))
1164 goto err;
1165 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1166 MLX4_COMM_TIME))
1167 goto err;
1168 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME))
1169 goto err;
1170 up(&priv->cmd.slave_sem);
1171 return 0;
1172
1173 err:
1174 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0);
1175 up(&priv->cmd.slave_sem);
1176 return -EIO;
1177 }
1178
1179 static int mlx4_init_hca(struct mlx4_dev *dev)
1180 {
1181 struct mlx4_priv *priv = mlx4_priv(dev);
1182 struct mlx4_adapter adapter;
1183 struct mlx4_dev_cap dev_cap;
1184 struct mlx4_mod_stat_cfg mlx4_cfg;
1185 struct mlx4_profile profile;
1186 struct mlx4_init_hca_param init_hca;
1187 u64 icm_size;
1188 int err;
1189
1190 if (!mlx4_is_slave(dev)) {
1191 err = mlx4_QUERY_FW(dev);
1192 if (err) {
1193 if (err == -EACCES)
1194 mlx4_info(dev, "non-primary physical function, skipping.\n");
1195 else
1196 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
1197 goto unmap_bf;
1198 }
1199
1200 err = mlx4_load_fw(dev);
1201 if (err) {
1202 mlx4_err(dev, "Failed to start FW, aborting.\n");
1203 goto unmap_bf;
1204 }
1205
1206 mlx4_cfg.log_pg_sz_m = 1;
1207 mlx4_cfg.log_pg_sz = 0;
1208 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
1209 if (err)
1210 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
1211
1212 err = mlx4_dev_cap(dev, &dev_cap);
1213 if (err) {
1214 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
1215 goto err_stop_fw;
1216 }
1217
1218 profile = default_profile;
1219
1220 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
1221 &init_hca);
1222 if ((long long) icm_size < 0) {
1223 err = icm_size;
1224 goto err_stop_fw;
1225 }
1226
1227 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
1228
1229 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
1230 init_hca.uar_page_sz = PAGE_SHIFT - 12;
1231
1232 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
1233 if (err)
1234 goto err_stop_fw;
1235
1236 err = mlx4_INIT_HCA(dev, &init_hca);
1237 if (err) {
1238 mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
1239 goto err_free_icm;
1240 }
1241 } else {
1242 err = mlx4_init_slave(dev);
1243 if (err) {
1244 mlx4_err(dev, "Failed to initialize slave\n");
1245 goto unmap_bf;
1246 }
1247
1248 err = mlx4_slave_cap(dev);
1249 if (err) {
1250 mlx4_err(dev, "Failed to obtain slave caps\n");
1251 goto err_close;
1252 }
1253 }
1254
1255 if (map_bf_area(dev))
1256 mlx4_dbg(dev, "Failed to map blue flame area\n");
1257
1258 /*Only the master set the ports, all the rest got it from it.*/
1259 if (!mlx4_is_slave(dev))
1260 mlx4_set_port_mask(dev);
1261
1262 err = mlx4_QUERY_ADAPTER(dev, &adapter);
1263 if (err) {
1264 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
1265 goto err_close;
1266 }
1267
1268 priv->eq_table.inta_pin = adapter.inta_pin;
1269 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
1270
1271 return 0;
1272
1273 err_close:
1274 mlx4_close_hca(dev);
1275
1276 err_free_icm:
1277 if (!mlx4_is_slave(dev))
1278 mlx4_free_icms(dev);
1279
1280 err_stop_fw:
1281 if (!mlx4_is_slave(dev)) {
1282 mlx4_UNMAP_FA(dev);
1283 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1284 }
1285 unmap_bf:
1286 unmap_bf_area(dev);
1287 return err;
1288 }
1289
1290 static int mlx4_init_counters_table(struct mlx4_dev *dev)
1291 {
1292 struct mlx4_priv *priv = mlx4_priv(dev);
1293 int nent;
1294
1295 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1296 return -ENOENT;
1297
1298 nent = dev->caps.max_counters;
1299 return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0);
1300 }
1301
1302 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
1303 {
1304 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
1305 }
1306
1307 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
1308 {
1309 struct mlx4_priv *priv = mlx4_priv(dev);
1310
1311 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1312 return -ENOENT;
1313
1314 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
1315 if (*idx == -1)
1316 return -ENOMEM;
1317
1318 return 0;
1319 }
1320 EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
1321
1322 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
1323 {
1324 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx);
1325 return;
1326 }
1327 EXPORT_SYMBOL_GPL(mlx4_counter_free);
1328
1329 static int mlx4_setup_hca(struct mlx4_dev *dev)
1330 {
1331 struct mlx4_priv *priv = mlx4_priv(dev);
1332 int err;
1333 int port;
1334 __be32 ib_port_default_caps;
1335
1336 err = mlx4_init_uar_table(dev);
1337 if (err) {
1338 mlx4_err(dev, "Failed to initialize "
1339 "user access region table, aborting.\n");
1340 return err;
1341 }
1342
1343 err = mlx4_uar_alloc(dev, &priv->driver_uar);
1344 if (err) {
1345 mlx4_err(dev, "Failed to allocate driver access region, "
1346 "aborting.\n");
1347 goto err_uar_table_free;
1348 }
1349
1350 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
1351 if (!priv->kar) {
1352 mlx4_err(dev, "Couldn't map kernel access region, "
1353 "aborting.\n");
1354 err = -ENOMEM;
1355 goto err_uar_free;
1356 }
1357
1358 err = mlx4_init_pd_table(dev);
1359 if (err) {
1360 mlx4_err(dev, "Failed to initialize "
1361 "protection domain table, aborting.\n");
1362 goto err_kar_unmap;
1363 }
1364
1365 err = mlx4_init_xrcd_table(dev);
1366 if (err) {
1367 mlx4_err(dev, "Failed to initialize "
1368 "reliable connection domain table, aborting.\n");
1369 goto err_pd_table_free;
1370 }
1371
1372 err = mlx4_init_mr_table(dev);
1373 if (err) {
1374 mlx4_err(dev, "Failed to initialize "
1375 "memory region table, aborting.\n");
1376 goto err_xrcd_table_free;
1377 }
1378
1379 err = mlx4_init_eq_table(dev);
1380 if (err) {
1381 mlx4_err(dev, "Failed to initialize "
1382 "event queue table, aborting.\n");
1383 goto err_mr_table_free;
1384 }
1385
1386 err = mlx4_cmd_use_events(dev);
1387 if (err) {
1388 mlx4_err(dev, "Failed to switch to event-driven "
1389 "firmware commands, aborting.\n");
1390 goto err_eq_table_free;
1391 }
1392
1393 err = mlx4_NOP(dev);
1394 if (err) {
1395 if (dev->flags & MLX4_FLAG_MSI_X) {
1396 mlx4_warn(dev, "NOP command failed to generate MSI-X "
1397 "interrupt IRQ %d).\n",
1398 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
1399 mlx4_warn(dev, "Trying again without MSI-X.\n");
1400 } else {
1401 mlx4_err(dev, "NOP command failed to generate interrupt "
1402 "(IRQ %d), aborting.\n",
1403 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
1404 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
1405 }
1406
1407 goto err_cmd_poll;
1408 }
1409
1410 mlx4_dbg(dev, "NOP command IRQ test passed\n");
1411
1412 err = mlx4_init_cq_table(dev);
1413 if (err) {
1414 mlx4_err(dev, "Failed to initialize "
1415 "completion queue table, aborting.\n");
1416 goto err_cmd_poll;
1417 }
1418
1419 err = mlx4_init_srq_table(dev);
1420 if (err) {
1421 mlx4_err(dev, "Failed to initialize "
1422 "shared receive queue table, aborting.\n");
1423 goto err_cq_table_free;
1424 }
1425
1426 err = mlx4_init_qp_table(dev);
1427 if (err) {
1428 mlx4_err(dev, "Failed to initialize "
1429 "queue pair table, aborting.\n");
1430 goto err_srq_table_free;
1431 }
1432
1433 if (!mlx4_is_slave(dev)) {
1434 err = mlx4_init_mcg_table(dev);
1435 if (err) {
1436 mlx4_err(dev, "Failed to initialize "
1437 "multicast group table, aborting.\n");
1438 goto err_qp_table_free;
1439 }
1440 }
1441
1442 err = mlx4_init_counters_table(dev);
1443 if (err && err != -ENOENT) {
1444 mlx4_err(dev, "Failed to initialize counters table, aborting.\n");
1445 goto err_mcg_table_free;
1446 }
1447
1448 if (!mlx4_is_slave(dev)) {
1449 for (port = 1; port <= dev->caps.num_ports; port++) {
1450 ib_port_default_caps = 0;
1451 err = mlx4_get_port_ib_caps(dev, port,
1452 &ib_port_default_caps);
1453 if (err)
1454 mlx4_warn(dev, "failed to get port %d default "
1455 "ib capabilities (%d). Continuing "
1456 "with caps = 0\n", port, err);
1457 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
1458
1459 if (mlx4_is_mfunc(dev))
1460 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
1461 else
1462 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
1463
1464 err = mlx4_SET_PORT(dev, port);
1465 if (err) {
1466 mlx4_err(dev, "Failed to set port %d, aborting\n",
1467 port);
1468 goto err_counters_table_free;
1469 }
1470 }
1471 }
1472
1473 return 0;
1474
1475 err_counters_table_free:
1476 mlx4_cleanup_counters_table(dev);
1477
1478 err_mcg_table_free:
1479 mlx4_cleanup_mcg_table(dev);
1480
1481 err_qp_table_free:
1482 mlx4_cleanup_qp_table(dev);
1483
1484 err_srq_table_free:
1485 mlx4_cleanup_srq_table(dev);
1486
1487 err_cq_table_free:
1488 mlx4_cleanup_cq_table(dev);
1489
1490 err_cmd_poll:
1491 mlx4_cmd_use_polling(dev);
1492
1493 err_eq_table_free:
1494 mlx4_cleanup_eq_table(dev);
1495
1496 err_mr_table_free:
1497 mlx4_cleanup_mr_table(dev);
1498
1499 err_xrcd_table_free:
1500 mlx4_cleanup_xrcd_table(dev);
1501
1502 err_pd_table_free:
1503 mlx4_cleanup_pd_table(dev);
1504
1505 err_kar_unmap:
1506 iounmap(priv->kar);
1507
1508 err_uar_free:
1509 mlx4_uar_free(dev, &priv->driver_uar);
1510
1511 err_uar_table_free:
1512 mlx4_cleanup_uar_table(dev);
1513 return err;
1514 }
1515
1516 static void mlx4_enable_msi_x(struct mlx4_dev *dev)
1517 {
1518 struct mlx4_priv *priv = mlx4_priv(dev);
1519 struct msix_entry *entries;
1520 int nreq = min_t(int, dev->caps.num_ports *
1521 min_t(int, num_online_cpus() + 1, MAX_MSIX_P_PORT)
1522 + MSIX_LEGACY_SZ, MAX_MSIX);
1523 int err;
1524 int i;
1525
1526 if (msi_x) {
1527 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
1528 nreq);
1529
1530 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
1531 if (!entries)
1532 goto no_msi;
1533
1534 for (i = 0; i < nreq; ++i)
1535 entries[i].entry = i;
1536
1537 retry:
1538 err = pci_enable_msix(dev->pdev, entries, nreq);
1539 if (err) {
1540 /* Try again if at least 2 vectors are available */
1541 if (err > 1) {
1542 mlx4_info(dev, "Requested %d vectors, "
1543 "but only %d MSI-X vectors available, "
1544 "trying again\n", nreq, err);
1545 nreq = err;
1546 goto retry;
1547 }
1548 kfree(entries);
1549 goto no_msi;
1550 }
1551
1552 if (nreq <
1553 MSIX_LEGACY_SZ + dev->caps.num_ports * MIN_MSIX_P_PORT) {
1554 /*Working in legacy mode , all EQ's shared*/
1555 dev->caps.comp_pool = 0;
1556 dev->caps.num_comp_vectors = nreq - 1;
1557 } else {
1558 dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ;
1559 dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
1560 }
1561 for (i = 0; i < nreq; ++i)
1562 priv->eq_table.eq[i].irq = entries[i].vector;
1563
1564 dev->flags |= MLX4_FLAG_MSI_X;
1565
1566 kfree(entries);
1567 return;
1568 }
1569
1570 no_msi:
1571 dev->caps.num_comp_vectors = 1;
1572 dev->caps.comp_pool = 0;
1573
1574 for (i = 0; i < 2; ++i)
1575 priv->eq_table.eq[i].irq = dev->pdev->irq;
1576 }
1577
1578 static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
1579 {
1580 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
1581 int err = 0;
1582
1583 info->dev = dev;
1584 info->port = port;
1585 if (!mlx4_is_slave(dev)) {
1586 INIT_RADIX_TREE(&info->mac_tree, GFP_KERNEL);
1587 mlx4_init_mac_table(dev, &info->mac_table);
1588 mlx4_init_vlan_table(dev, &info->vlan_table);
1589 info->base_qpn =
1590 dev->caps.reserved_qps_base[MLX4_QP_REGION_ETH_ADDR] +
1591 (port - 1) * (1 << log_num_mac);
1592 }
1593
1594 sprintf(info->dev_name, "mlx4_port%d", port);
1595 info->port_attr.attr.name = info->dev_name;
1596 if (mlx4_is_mfunc(dev))
1597 info->port_attr.attr.mode = S_IRUGO;
1598 else {
1599 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
1600 info->port_attr.store = set_port_type;
1601 }
1602 info->port_attr.show = show_port_type;
1603 sysfs_attr_init(&info->port_attr.attr);
1604
1605 err = device_create_file(&dev->pdev->dev, &info->port_attr);
1606 if (err) {
1607 mlx4_err(dev, "Failed to create file for port %d\n", port);
1608 info->port = -1;
1609 }
1610
1611 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
1612 info->port_mtu_attr.attr.name = info->dev_mtu_name;
1613 if (mlx4_is_mfunc(dev))
1614 info->port_mtu_attr.attr.mode = S_IRUGO;
1615 else {
1616 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
1617 info->port_mtu_attr.store = set_port_ib_mtu;
1618 }
1619 info->port_mtu_attr.show = show_port_ib_mtu;
1620 sysfs_attr_init(&info->port_mtu_attr.attr);
1621
1622 err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr);
1623 if (err) {
1624 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
1625 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
1626 info->port = -1;
1627 }
1628
1629 return err;
1630 }
1631
1632 static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
1633 {
1634 if (info->port < 0)
1635 return;
1636
1637 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
1638 device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr);
1639 }
1640
1641 static int mlx4_init_steering(struct mlx4_dev *dev)
1642 {
1643 struct mlx4_priv *priv = mlx4_priv(dev);
1644 int num_entries = dev->caps.num_ports;
1645 int i, j;
1646
1647 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
1648 if (!priv->steer)
1649 return -ENOMEM;
1650
1651 for (i = 0; i < num_entries; i++)
1652 for (j = 0; j < MLX4_NUM_STEERS; j++) {
1653 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
1654 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
1655 }
1656 return 0;
1657 }
1658
1659 static void mlx4_clear_steering(struct mlx4_dev *dev)
1660 {
1661 struct mlx4_priv *priv = mlx4_priv(dev);
1662 struct mlx4_steer_index *entry, *tmp_entry;
1663 struct mlx4_promisc_qp *pqp, *tmp_pqp;
1664 int num_entries = dev->caps.num_ports;
1665 int i, j;
1666
1667 for (i = 0; i < num_entries; i++) {
1668 for (j = 0; j < MLX4_NUM_STEERS; j++) {
1669 list_for_each_entry_safe(pqp, tmp_pqp,
1670 &priv->steer[i].promisc_qps[j],
1671 list) {
1672 list_del(&pqp->list);
1673 kfree(pqp);
1674 }
1675 list_for_each_entry_safe(entry, tmp_entry,
1676 &priv->steer[i].steer_entries[j],
1677 list) {
1678 list_del(&entry->list);
1679 list_for_each_entry_safe(pqp, tmp_pqp,
1680 &entry->duplicates,
1681 list) {
1682 list_del(&pqp->list);
1683 kfree(pqp);
1684 }
1685 kfree(entry);
1686 }
1687 }
1688 }
1689 kfree(priv->steer);
1690 }
1691
1692 static int extended_func_num(struct pci_dev *pdev)
1693 {
1694 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
1695 }
1696
1697 #define MLX4_OWNER_BASE 0x8069c
1698 #define MLX4_OWNER_SIZE 4
1699
1700 static int mlx4_get_ownership(struct mlx4_dev *dev)
1701 {
1702 void __iomem *owner;
1703 u32 ret;
1704
1705 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
1706 MLX4_OWNER_SIZE);
1707 if (!owner) {
1708 mlx4_err(dev, "Failed to obtain ownership bit\n");
1709 return -ENOMEM;
1710 }
1711
1712 ret = readl(owner);
1713 iounmap(owner);
1714 return (int) !!ret;
1715 }
1716
1717 static void mlx4_free_ownership(struct mlx4_dev *dev)
1718 {
1719 void __iomem *owner;
1720
1721 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
1722 MLX4_OWNER_SIZE);
1723 if (!owner) {
1724 mlx4_err(dev, "Failed to obtain ownership bit\n");
1725 return;
1726 }
1727 writel(0, owner);
1728 msleep(1000);
1729 iounmap(owner);
1730 }
1731
1732 static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data)
1733 {
1734 struct mlx4_priv *priv;
1735 struct mlx4_dev *dev;
1736 int err;
1737 int port;
1738
1739 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
1740
1741 err = pci_enable_device(pdev);
1742 if (err) {
1743 dev_err(&pdev->dev, "Cannot enable PCI device, "
1744 "aborting.\n");
1745 return err;
1746 }
1747 if (num_vfs > MLX4_MAX_NUM_VF) {
1748 printk(KERN_ERR "There are more VF's (%d) than allowed(%d)\n",
1749 num_vfs, MLX4_MAX_NUM_VF);
1750 return -EINVAL;
1751 }
1752 /*
1753 * Check for BARs.
1754 */
1755 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
1756 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1757 dev_err(&pdev->dev, "Missing DCS, aborting."
1758 "(driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
1759 pci_dev_data, pci_resource_flags(pdev, 0));
1760 err = -ENODEV;
1761 goto err_disable_pdev;
1762 }
1763 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
1764 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
1765 err = -ENODEV;
1766 goto err_disable_pdev;
1767 }
1768
1769 err = pci_request_regions(pdev, DRV_NAME);
1770 if (err) {
1771 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
1772 goto err_disable_pdev;
1773 }
1774
1775 pci_set_master(pdev);
1776
1777 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1778 if (err) {
1779 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
1780 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1781 if (err) {
1782 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
1783 goto err_release_regions;
1784 }
1785 }
1786 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1787 if (err) {
1788 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
1789 "consistent PCI DMA mask.\n");
1790 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1791 if (err) {
1792 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
1793 "aborting.\n");
1794 goto err_release_regions;
1795 }
1796 }
1797
1798 /* Allow large DMA segments, up to the firmware limit of 1 GB */
1799 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
1800
1801 dev = pci_get_drvdata(pdev);
1802 priv = mlx4_priv(dev);
1803 dev->pdev = pdev;
1804 INIT_LIST_HEAD(&priv->ctx_list);
1805 spin_lock_init(&priv->ctx_lock);
1806
1807 mutex_init(&priv->port_mutex);
1808
1809 INIT_LIST_HEAD(&priv->pgdir_list);
1810 mutex_init(&priv->pgdir_mutex);
1811
1812 INIT_LIST_HEAD(&priv->bf_list);
1813 mutex_init(&priv->bf_mutex);
1814
1815 dev->rev_id = pdev->revision;
1816 /* Detect if this device is a virtual function */
1817 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
1818 /* When acting as pf, we normally skip vfs unless explicitly
1819 * requested to probe them. */
1820 if (num_vfs && extended_func_num(pdev) > probe_vf) {
1821 mlx4_warn(dev, "Skipping virtual function:%d\n",
1822 extended_func_num(pdev));
1823 err = -ENODEV;
1824 goto err_free_dev;
1825 }
1826 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
1827 dev->flags |= MLX4_FLAG_SLAVE;
1828 } else {
1829 /* We reset the device and enable SRIOV only for physical
1830 * devices. Try to claim ownership on the device;
1831 * if already taken, skip -- do not allow multiple PFs */
1832 err = mlx4_get_ownership(dev);
1833 if (err) {
1834 if (err < 0)
1835 goto err_free_dev;
1836 else {
1837 mlx4_warn(dev, "Multiple PFs not yet supported."
1838 " Skipping PF.\n");
1839 err = -EINVAL;
1840 goto err_free_dev;
1841 }
1842 }
1843
1844 if (num_vfs) {
1845 mlx4_warn(dev, "Enabling sriov with:%d vfs\n", num_vfs);
1846 err = pci_enable_sriov(pdev, num_vfs);
1847 if (err) {
1848 mlx4_err(dev, "Failed to enable sriov,"
1849 "continuing without sriov enabled"
1850 " (err = %d).\n", err);
1851 num_vfs = 0;
1852 err = 0;
1853 } else {
1854 mlx4_warn(dev, "Running in master mode\n");
1855 dev->flags |= MLX4_FLAG_SRIOV |
1856 MLX4_FLAG_MASTER;
1857 dev->num_vfs = num_vfs;
1858 }
1859 }
1860
1861 /*
1862 * Now reset the HCA before we touch the PCI capabilities or
1863 * attempt a firmware command, since a boot ROM may have left
1864 * the HCA in an undefined state.
1865 */
1866 err = mlx4_reset(dev);
1867 if (err) {
1868 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
1869 goto err_rel_own;
1870 }
1871 }
1872
1873 slave_start:
1874 if (mlx4_cmd_init(dev)) {
1875 mlx4_err(dev, "Failed to init command interface, aborting.\n");
1876 goto err_sriov;
1877 }
1878
1879 /* In slave functions, the communication channel must be initialized
1880 * before posting commands. Also, init num_slaves before calling
1881 * mlx4_init_hca */
1882 if (mlx4_is_mfunc(dev)) {
1883 if (mlx4_is_master(dev))
1884 dev->num_slaves = MLX4_MAX_NUM_SLAVES;
1885 else {
1886 dev->num_slaves = 0;
1887 if (mlx4_multi_func_init(dev)) {
1888 mlx4_err(dev, "Failed to init slave mfunc"
1889 " interface, aborting.\n");
1890 goto err_cmd;
1891 }
1892 }
1893 }
1894
1895 err = mlx4_init_hca(dev);
1896 if (err) {
1897 if (err == -EACCES) {
1898 /* Not primary Physical function
1899 * Running in slave mode */
1900 mlx4_cmd_cleanup(dev);
1901 dev->flags |= MLX4_FLAG_SLAVE;
1902 dev->flags &= ~MLX4_FLAG_MASTER;
1903 goto slave_start;
1904 } else
1905 goto err_mfunc;
1906 }
1907
1908 /* In master functions, the communication channel must be initialized
1909 * after obtaining its address from fw */
1910 if (mlx4_is_master(dev)) {
1911 if (mlx4_multi_func_init(dev)) {
1912 mlx4_err(dev, "Failed to init master mfunc"
1913 "interface, aborting.\n");
1914 goto err_close;
1915 }
1916 }
1917
1918 err = mlx4_alloc_eq_table(dev);
1919 if (err)
1920 goto err_master_mfunc;
1921
1922 priv->msix_ctl.pool_bm = 0;
1923 mutex_init(&priv->msix_ctl.pool_lock);
1924
1925 mlx4_enable_msi_x(dev);
1926 if ((mlx4_is_mfunc(dev)) &&
1927 !(dev->flags & MLX4_FLAG_MSI_X)) {
1928 mlx4_err(dev, "INTx is not supported in multi-function mode."
1929 " aborting.\n");
1930 goto err_free_eq;
1931 }
1932
1933 if (!mlx4_is_slave(dev)) {
1934 err = mlx4_init_steering(dev);
1935 if (err)
1936 goto err_free_eq;
1937 }
1938
1939 err = mlx4_setup_hca(dev);
1940 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
1941 !mlx4_is_mfunc(dev)) {
1942 dev->flags &= ~MLX4_FLAG_MSI_X;
1943 pci_disable_msix(pdev);
1944 err = mlx4_setup_hca(dev);
1945 }
1946
1947 if (err)
1948 goto err_steer;
1949
1950 for (port = 1; port <= dev->caps.num_ports; port++) {
1951 err = mlx4_init_port_info(dev, port);
1952 if (err)
1953 goto err_port;
1954 }
1955
1956 err = mlx4_register_device(dev);
1957 if (err)
1958 goto err_port;
1959
1960 mlx4_sense_init(dev);
1961 mlx4_start_sense(dev);
1962
1963 priv->removed = 0;
1964
1965 return 0;
1966
1967 err_port:
1968 for (--port; port >= 1; --port)
1969 mlx4_cleanup_port_info(&priv->port[port]);
1970
1971 mlx4_cleanup_counters_table(dev);
1972 mlx4_cleanup_mcg_table(dev);
1973 mlx4_cleanup_qp_table(dev);
1974 mlx4_cleanup_srq_table(dev);
1975 mlx4_cleanup_cq_table(dev);
1976 mlx4_cmd_use_polling(dev);
1977 mlx4_cleanup_eq_table(dev);
1978 mlx4_cleanup_mr_table(dev);
1979 mlx4_cleanup_xrcd_table(dev);
1980 mlx4_cleanup_pd_table(dev);
1981 mlx4_cleanup_uar_table(dev);
1982
1983 err_steer:
1984 if (!mlx4_is_slave(dev))
1985 mlx4_clear_steering(dev);
1986
1987 err_free_eq:
1988 mlx4_free_eq_table(dev);
1989
1990 err_master_mfunc:
1991 if (mlx4_is_master(dev))
1992 mlx4_multi_func_cleanup(dev);
1993
1994 err_close:
1995 if (dev->flags & MLX4_FLAG_MSI_X)
1996 pci_disable_msix(pdev);
1997
1998 mlx4_close_hca(dev);
1999
2000 err_mfunc:
2001 if (mlx4_is_slave(dev))
2002 mlx4_multi_func_cleanup(dev);
2003
2004 err_cmd:
2005 mlx4_cmd_cleanup(dev);
2006
2007 err_sriov:
2008 if (num_vfs && (dev->flags & MLX4_FLAG_SRIOV))
2009 pci_disable_sriov(pdev);
2010
2011 err_rel_own:
2012 if (!mlx4_is_slave(dev))
2013 mlx4_free_ownership(dev);
2014
2015 err_free_dev:
2016 kfree(priv);
2017
2018 err_release_regions:
2019 pci_release_regions(pdev);
2020
2021 err_disable_pdev:
2022 pci_disable_device(pdev);
2023 pci_set_drvdata(pdev, NULL);
2024 return err;
2025 }
2026
2027 static int __devinit mlx4_init_one(struct pci_dev *pdev,
2028 const struct pci_device_id *id)
2029 {
2030 struct mlx4_priv *priv;
2031 struct mlx4_dev *dev;
2032
2033 printk_once(KERN_INFO "%s", mlx4_version);
2034
2035 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
2036 if (!priv)
2037 return -ENOMEM;
2038
2039 dev = &priv->dev;
2040 pci_set_drvdata(pdev, dev);
2041 priv->pci_dev_data = id->driver_data;
2042
2043 return __mlx4_init_one(pdev, id->driver_data);
2044 }
2045
2046 static void __mlx4_remove_one(struct pci_dev *pdev)
2047 {
2048 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2049 struct mlx4_priv *priv = mlx4_priv(dev);
2050 int pci_dev_data;
2051 int p;
2052
2053 if (priv->removed)
2054 return;
2055
2056 pci_dev_data = priv->pci_dev_data;
2057
2058 /* in SRIOV it is not allowed to unload the pf's
2059 * driver while there are alive vf's */
2060 if (mlx4_is_master(dev)) {
2061 if (mlx4_how_many_lives_vf(dev))
2062 printk(KERN_ERR "Removing PF when there are assigned VF's !!!\n");
2063 }
2064 mlx4_stop_sense(dev);
2065 mlx4_unregister_device(dev);
2066
2067 for (p = 1; p <= dev->caps.num_ports; p++) {
2068 mlx4_cleanup_port_info(&priv->port[p]);
2069 mlx4_CLOSE_PORT(dev, p);
2070 }
2071
2072 mlx4_cleanup_counters_table(dev);
2073 mlx4_cleanup_mcg_table(dev);
2074 mlx4_cleanup_qp_table(dev);
2075 mlx4_cleanup_srq_table(dev);
2076 mlx4_cleanup_cq_table(dev);
2077 mlx4_cmd_use_polling(dev);
2078 mlx4_cleanup_eq_table(dev);
2079 mlx4_cleanup_mr_table(dev);
2080 mlx4_cleanup_xrcd_table(dev);
2081 mlx4_cleanup_pd_table(dev);
2082
2083 if (mlx4_is_master(dev))
2084 mlx4_free_resource_tracker(dev);
2085
2086 iounmap(priv->kar);
2087 mlx4_uar_free(dev, &priv->driver_uar);
2088 mlx4_cleanup_uar_table(dev);
2089 if (!mlx4_is_slave(dev))
2090 mlx4_clear_steering(dev);
2091 mlx4_free_eq_table(dev);
2092 if (mlx4_is_master(dev))
2093 mlx4_multi_func_cleanup(dev);
2094 mlx4_close_hca(dev);
2095 if (mlx4_is_slave(dev))
2096 mlx4_multi_func_cleanup(dev);
2097 mlx4_cmd_cleanup(dev);
2098
2099 if (dev->flags & MLX4_FLAG_MSI_X)
2100 pci_disable_msix(pdev);
2101 if (num_vfs && (dev->flags & MLX4_FLAG_SRIOV)) {
2102 mlx4_warn(dev, "Disabling sriov\n");
2103 pci_disable_sriov(pdev);
2104 }
2105
2106 if (!mlx4_is_slave(dev))
2107 mlx4_free_ownership(dev);
2108
2109 pci_release_regions(pdev);
2110 pci_disable_device(pdev);
2111 memset(priv, 0, sizeof(*priv));
2112 priv->pci_dev_data = pci_dev_data;
2113 priv->removed = 1;
2114 }
2115
2116 static void mlx4_remove_one(struct pci_dev *pdev)
2117 {
2118 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2119 struct mlx4_priv *priv = mlx4_priv(dev);
2120
2121 __mlx4_remove_one(pdev);
2122 kfree(priv);
2123 pci_set_drvdata(pdev, NULL);
2124 }
2125
2126 int mlx4_restart_one(struct pci_dev *pdev)
2127 {
2128 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2129 struct mlx4_priv *priv = mlx4_priv(dev);
2130 int pci_dev_data;
2131
2132 pci_dev_data = priv->pci_dev_data;
2133 __mlx4_remove_one(pdev);
2134 return __mlx4_init_one(pdev, pci_dev_data);
2135 }
2136
2137 static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = {
2138 /* MT25408 "Hermon" SDR */
2139 { PCI_VDEVICE(MELLANOX, 0x6340), 0 },
2140 /* MT25408 "Hermon" DDR */
2141 { PCI_VDEVICE(MELLANOX, 0x634a), 0 },
2142 /* MT25408 "Hermon" QDR */
2143 { PCI_VDEVICE(MELLANOX, 0x6354), 0 },
2144 /* MT25408 "Hermon" DDR PCIe gen2 */
2145 { PCI_VDEVICE(MELLANOX, 0x6732), 0 },
2146 /* MT25408 "Hermon" QDR PCIe gen2 */
2147 { PCI_VDEVICE(MELLANOX, 0x673c), 0 },
2148 /* MT25408 "Hermon" EN 10GigE */
2149 { PCI_VDEVICE(MELLANOX, 0x6368), 0 },
2150 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
2151 { PCI_VDEVICE(MELLANOX, 0x6750), 0 },
2152 /* MT25458 ConnectX EN 10GBASE-T 10GigE */
2153 { PCI_VDEVICE(MELLANOX, 0x6372), 0 },
2154 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
2155 { PCI_VDEVICE(MELLANOX, 0x675a), 0 },
2156 /* MT26468 ConnectX EN 10GigE PCIe gen2*/
2157 { PCI_VDEVICE(MELLANOX, 0x6764), 0 },
2158 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
2159 { PCI_VDEVICE(MELLANOX, 0x6746), 0 },
2160 /* MT26478 ConnectX2 40GigE PCIe gen2 */
2161 { PCI_VDEVICE(MELLANOX, 0x676e), 0 },
2162 /* MT25400 Family [ConnectX-2 Virtual Function] */
2163 { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF },
2164 /* MT27500 Family [ConnectX-3] */
2165 { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
2166 /* MT27500 Family [ConnectX-3 Virtual Function] */
2167 { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF },
2168 { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
2169 { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
2170 { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
2171 { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
2172 { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
2173 { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
2174 { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
2175 { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
2176 { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
2177 { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
2178 { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
2179 { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
2180 { 0, }
2181 };
2182
2183 MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
2184
2185 static struct pci_driver mlx4_driver = {
2186 .name = DRV_NAME,
2187 .id_table = mlx4_pci_table,
2188 .probe = mlx4_init_one,
2189 .remove = __devexit_p(mlx4_remove_one)
2190 };
2191
2192 static int __init mlx4_verify_params(void)
2193 {
2194 if ((log_num_mac < 0) || (log_num_mac > 7)) {
2195 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac);
2196 return -1;
2197 }
2198
2199 if (log_num_vlan != 0)
2200 pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
2201 MLX4_LOG_NUM_VLANS);
2202
2203 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
2204 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg);
2205 return -1;
2206 }
2207
2208 /* Check if module param for ports type has legal combination */
2209 if (port_type_array[0] == false && port_type_array[1] == true) {
2210 printk(KERN_WARNING "Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
2211 port_type_array[0] = true;
2212 }
2213
2214 return 0;
2215 }
2216
2217 static int __init mlx4_init(void)
2218 {
2219 int ret;
2220
2221 if (mlx4_verify_params())
2222 return -EINVAL;
2223
2224 mlx4_catas_init();
2225
2226 mlx4_wq = create_singlethread_workqueue("mlx4");
2227 if (!mlx4_wq)
2228 return -ENOMEM;
2229
2230 ret = pci_register_driver(&mlx4_driver);
2231 return ret < 0 ? ret : 0;
2232 }
2233
2234 static void __exit mlx4_cleanup(void)
2235 {
2236 pci_unregister_driver(&mlx4_driver);
2237 destroy_workqueue(mlx4_wq);
2238 }
2239
2240 module_init(mlx4_init);
2241 module_exit(mlx4_cleanup);
Linux with added FPC-III support