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Linux 3.4.102
[linux/fpc-iii.git] / drivers / net / ethernet / packetengines / yellowfin.c
blob7757b80ef924b8000c2b7e13066c0961566a38ee
1 /* yellowfin.c: A Packet Engines G-NIC ethernet driver for linux. */
2 /*
3 Written 1997-2001 by Donald Becker.
4
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
11
12 This driver is for the Packet Engines G-NIC PCI Gigabit Ethernet adapter.
13 It also supports the Symbios Logic version of the same chip core.
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
20 Support and updates available at
21 http://www.scyld.com/network/yellowfin.html
22 [link no longer provides useful info -jgarzik]
23
24 */
25
26 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27
28 #define DRV_NAME "yellowfin"
29 #define DRV_VERSION "2.1"
30 #define DRV_RELDATE "Sep 11, 2006"
31
32 /* The user-configurable values.
33 These may be modified when a driver module is loaded.*/
34
35 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
36 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
37 static int max_interrupt_work = 20;
38 static int mtu;
39 #ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
40 /* System-wide count of bogus-rx frames. */
41 static int bogus_rx;
42 static int dma_ctrl = 0x004A0263; /* Constrained by errata */
43 static int fifo_cfg = 0x0020; /* Bypass external Tx FIFO. */
44 #elif defined(YF_NEW) /* A future perfect board :->. */
45 static int dma_ctrl = 0x00CAC277; /* Override when loading module! */
46 static int fifo_cfg = 0x0028;
47 #else
48 static const int dma_ctrl = 0x004A0263; /* Constrained by errata */
49 static const int fifo_cfg = 0x0020; /* Bypass external Tx FIFO. */
50 #endif
51
52 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
53 Setting to > 1514 effectively disables this feature. */
54 static int rx_copybreak;
55
56 /* Used to pass the media type, etc.
57 No media types are currently defined. These exist for driver
58 interoperability.
59 */
60 #define MAX_UNITS 8 /* More are supported, limit only on options */
61 static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
62 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
63
64 /* Do ugly workaround for GX server chipset errata. */
65 static int gx_fix;
66
67 /* Operational parameters that are set at compile time. */
68
69 /* Keep the ring sizes a power of two for efficiency.
70 Making the Tx ring too long decreases the effectiveness of channel
71 bonding and packet priority.
72 There are no ill effects from too-large receive rings. */
73 #define TX_RING_SIZE 16
74 #define TX_QUEUE_SIZE 12 /* Must be > 4 && <= TX_RING_SIZE */
75 #define RX_RING_SIZE 64
76 #define STATUS_TOTAL_SIZE TX_RING_SIZE*sizeof(struct tx_status_words)
77 #define TX_TOTAL_SIZE 2*TX_RING_SIZE*sizeof(struct yellowfin_desc)
78 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct yellowfin_desc)
79
80 /* Operational parameters that usually are not changed. */
81 /* Time in jiffies before concluding the transmitter is hung. */
82 #define TX_TIMEOUT (2*HZ)
83 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
84
85 #define yellowfin_debug debug
86
87 #include <linux/module.h>
88 #include <linux/kernel.h>
89 #include <linux/string.h>
90 #include <linux/timer.h>
91 #include <linux/errno.h>
92 #include <linux/ioport.h>
93 #include <linux/interrupt.h>
94 #include <linux/pci.h>
95 #include <linux/init.h>
96 #include <linux/mii.h>
97 #include <linux/netdevice.h>
98 #include <linux/etherdevice.h>
99 #include <linux/skbuff.h>
100 #include <linux/ethtool.h>
101 #include <linux/crc32.h>
102 #include <linux/bitops.h>
103 #include <asm/uaccess.h>
104 #include <asm/processor.h> /* Processor type for cache alignment. */
105 #include <asm/unaligned.h>
106 #include <asm/io.h>
107
108 /* These identify the driver base version and may not be removed. */
109 static const char version[] __devinitconst =
110 KERN_INFO DRV_NAME ".c:v1.05 1/09/2001 Written by Donald Becker <becker@scyld.com>\n"
111 " (unofficial 2.4.x port, " DRV_VERSION ", " DRV_RELDATE ")\n";
112
113 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
114 MODULE_DESCRIPTION("Packet Engines Yellowfin G-NIC Gigabit Ethernet driver");
115 MODULE_LICENSE("GPL");
116
117 module_param(max_interrupt_work, int, 0);
118 module_param(mtu, int, 0);
119 module_param(debug, int, 0);
120 module_param(rx_copybreak, int, 0);
121 module_param_array(options, int, NULL, 0);
122 module_param_array(full_duplex, int, NULL, 0);
123 module_param(gx_fix, int, 0);
124 MODULE_PARM_DESC(max_interrupt_work, "G-NIC maximum events handled per interrupt");
125 MODULE_PARM_DESC(mtu, "G-NIC MTU (all boards)");
126 MODULE_PARM_DESC(debug, "G-NIC debug level (0-7)");
127 MODULE_PARM_DESC(rx_copybreak, "G-NIC copy breakpoint for copy-only-tiny-frames");
128 MODULE_PARM_DESC(options, "G-NIC: Bits 0-3: media type, bit 17: full duplex");
129 MODULE_PARM_DESC(full_duplex, "G-NIC full duplex setting(s) (1)");
130 MODULE_PARM_DESC(gx_fix, "G-NIC: enable GX server chipset bug workaround (0-1)");
131
132 /*
133 Theory of Operation
134
135 I. Board Compatibility
136
137 This device driver is designed for the Packet Engines "Yellowfin" Gigabit
138 Ethernet adapter. The G-NIC 64-bit PCI card is supported, as well as the
139 Symbios 53C885E dual function chip.
140
141 II. Board-specific settings
142
143 PCI bus devices are configured by the system at boot time, so no jumpers
144 need to be set on the board. The system BIOS preferably should assign the
145 PCI INTA signal to an otherwise unused system IRQ line.
146 Note: Kernel versions earlier than 1.3.73 do not support shared PCI
147 interrupt lines.
148
149 III. Driver operation
150
151 IIIa. Ring buffers
152
153 The Yellowfin uses the Descriptor Based DMA Architecture specified by Apple.
154 This is a descriptor list scheme similar to that used by the EEPro100 and
155 Tulip. This driver uses two statically allocated fixed-size descriptor lists
156 formed into rings by a branch from the final descriptor to the beginning of
157 the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
158
159 The driver allocates full frame size skbuffs for the Rx ring buffers at
160 open() time and passes the skb->data field to the Yellowfin as receive data
161 buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
162 a fresh skbuff is allocated and the frame is copied to the new skbuff.
163 When the incoming frame is larger, the skbuff is passed directly up the
164 protocol stack and replaced by a newly allocated skbuff.
165
166 The RX_COPYBREAK value is chosen to trade-off the memory wasted by
167 using a full-sized skbuff for small frames vs. the copying costs of larger
168 frames. For small frames the copying cost is negligible (esp. considering
169 that we are pre-loading the cache with immediately useful header
170 information). For large frames the copying cost is non-trivial, and the
171 larger copy might flush the cache of useful data.
172
173 IIIC. Synchronization
174
175 The driver runs as two independent, single-threaded flows of control. One
176 is the send-packet routine, which enforces single-threaded use by the
177 dev->tbusy flag. The other thread is the interrupt handler, which is single
178 threaded by the hardware and other software.
179
180 The send packet thread has partial control over the Tx ring and 'dev->tbusy'
181 flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next
182 queue slot is empty, it clears the tbusy flag when finished otherwise it sets
183 the 'yp->tx_full' flag.
184
185 The interrupt handler has exclusive control over the Rx ring and records stats
186 from the Tx ring. After reaping the stats, it marks the Tx queue entry as
187 empty by incrementing the dirty_tx mark. Iff the 'yp->tx_full' flag is set, it
188 clears both the tx_full and tbusy flags.
189
190 IV. Notes
191
192 Thanks to Kim Stearns of Packet Engines for providing a pair of G-NIC boards.
193 Thanks to Bruce Faust of Digitalscape for providing both their SYM53C885 board
194 and an AlphaStation to verifty the Alpha port!
195
196 IVb. References
197
198 Yellowfin Engineering Design Specification, 4/23/97 Preliminary/Confidential
199 Symbios SYM53C885 PCI-SCSI/Fast Ethernet Multifunction Controller Preliminary
200 Data Manual v3.0
201 http://cesdis.gsfc.nasa.gov/linux/misc/NWay.html
202 http://cesdis.gsfc.nasa.gov/linux/misc/100mbps.html
203
204 IVc. Errata
205
206 See Packet Engines confidential appendix (prototype chips only).
207 */
208
209
210
211 enum capability_flags {
212 HasMII=1, FullTxStatus=2, IsGigabit=4, HasMulticastBug=8, FullRxStatus=16,
213 HasMACAddrBug=32, /* Only on early revs. */
214 DontUseEeprom=64, /* Don't read the MAC from the EEPROm. */
215 };
216
217 /* The PCI I/O space extent. */
218 enum {
219 YELLOWFIN_SIZE = 0x100,
220 };
221
222 struct pci_id_info {
223 const char *name;
224 struct match_info {
225 int pci, pci_mask, subsystem, subsystem_mask;
226 int revision, revision_mask; /* Only 8 bits. */
227 } id;
228 int drv_flags; /* Driver use, intended as capability flags. */
229 };
230
231 static const struct pci_id_info pci_id_tbl[] = {
232 {"Yellowfin G-NIC Gigabit Ethernet", { 0x07021000, 0xffffffff},
233 FullTxStatus | IsGigabit | HasMulticastBug | HasMACAddrBug | DontUseEeprom},
234 {"Symbios SYM83C885", { 0x07011000, 0xffffffff},
235 HasMII | DontUseEeprom },
236 { }
237 };
238
239 static DEFINE_PCI_DEVICE_TABLE(yellowfin_pci_tbl) = {
240 { 0x1000, 0x0702, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
241 { 0x1000, 0x0701, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
242 { }
243 };
244 MODULE_DEVICE_TABLE (pci, yellowfin_pci_tbl);
245
246
247 /* Offsets to the Yellowfin registers. Various sizes and alignments. */
248 enum yellowfin_offsets {
249 TxCtrl=0x00, TxStatus=0x04, TxPtr=0x0C,
250 TxIntrSel=0x10, TxBranchSel=0x14, TxWaitSel=0x18,
251 RxCtrl=0x40, RxStatus=0x44, RxPtr=0x4C,
252 RxIntrSel=0x50, RxBranchSel=0x54, RxWaitSel=0x58,
253 EventStatus=0x80, IntrEnb=0x82, IntrClear=0x84, IntrStatus=0x86,
254 ChipRev=0x8C, DMACtrl=0x90, TxThreshold=0x94,
255 Cnfg=0xA0, FrameGap0=0xA2, FrameGap1=0xA4,
256 MII_Cmd=0xA6, MII_Addr=0xA8, MII_Wr_Data=0xAA, MII_Rd_Data=0xAC,
257 MII_Status=0xAE,
258 RxDepth=0xB8, FlowCtrl=0xBC,
259 AddrMode=0xD0, StnAddr=0xD2, HashTbl=0xD8, FIFOcfg=0xF8,
260 EEStatus=0xF0, EECtrl=0xF1, EEAddr=0xF2, EERead=0xF3, EEWrite=0xF4,
261 EEFeature=0xF5,
262 };
263
264 /* The Yellowfin Rx and Tx buffer descriptors.
265 Elements are written as 32 bit for endian portability. */
266 struct yellowfin_desc {
267 __le32 dbdma_cmd;
268 __le32 addr;
269 __le32 branch_addr;
270 __le32 result_status;
271 };
272
273 struct tx_status_words {
274 #ifdef __BIG_ENDIAN
275 u16 tx_errs;
276 u16 tx_cnt;
277 u16 paused;
278 u16 total_tx_cnt;
279 #else /* Little endian chips. */
280 u16 tx_cnt;
281 u16 tx_errs;
282 u16 total_tx_cnt;
283 u16 paused;
284 #endif /* __BIG_ENDIAN */
285 };
286
287 /* Bits in yellowfin_desc.cmd */
288 enum desc_cmd_bits {
289 CMD_TX_PKT=0x10000000, CMD_RX_BUF=0x20000000, CMD_TXSTATUS=0x30000000,
290 CMD_NOP=0x60000000, CMD_STOP=0x70000000,
291 BRANCH_ALWAYS=0x0C0000, INTR_ALWAYS=0x300000, WAIT_ALWAYS=0x030000,
292 BRANCH_IFTRUE=0x040000,
293 };
294
295 /* Bits in yellowfin_desc.status */
296 enum desc_status_bits { RX_EOP=0x0040, };
297
298 /* Bits in the interrupt status/mask registers. */
299 enum intr_status_bits {
300 IntrRxDone=0x01, IntrRxInvalid=0x02, IntrRxPCIFault=0x04,IntrRxPCIErr=0x08,
301 IntrTxDone=0x10, IntrTxInvalid=0x20, IntrTxPCIFault=0x40,IntrTxPCIErr=0x80,
302 IntrEarlyRx=0x100, IntrWakeup=0x200, };
303
304 #define PRIV_ALIGN 31 /* Required alignment mask */
305 #define MII_CNT 4
306 struct yellowfin_private {
307 /* Descriptor rings first for alignment.
308 Tx requires a second descriptor for status. */
309 struct yellowfin_desc *rx_ring;
310 struct yellowfin_desc *tx_ring;
311 struct sk_buff* rx_skbuff[RX_RING_SIZE];
312 struct sk_buff* tx_skbuff[TX_RING_SIZE];
313 dma_addr_t rx_ring_dma;
314 dma_addr_t tx_ring_dma;
315
316 struct tx_status_words *tx_status;
317 dma_addr_t tx_status_dma;
318
319 struct timer_list timer; /* Media selection timer. */
320 /* Frequently used and paired value: keep adjacent for cache effect. */
321 int chip_id, drv_flags;
322 struct pci_dev *pci_dev;
323 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
324 unsigned int rx_buf_sz; /* Based on MTU+slack. */
325 struct tx_status_words *tx_tail_desc;
326 unsigned int cur_tx, dirty_tx;
327 int tx_threshold;
328 unsigned int tx_full:1; /* The Tx queue is full. */
329 unsigned int full_duplex:1; /* Full-duplex operation requested. */
330 unsigned int duplex_lock:1;
331 unsigned int medialock:1; /* Do not sense media. */
332 unsigned int default_port:4; /* Last dev->if_port value. */
333 /* MII transceiver section. */
334 int mii_cnt; /* MII device addresses. */
335 u16 advertising; /* NWay media advertisement */
336 unsigned char phys[MII_CNT]; /* MII device addresses, only first one used */
337 spinlock_t lock;
338 void __iomem *base;
339 };
340
341 static int read_eeprom(void __iomem *ioaddr, int location);
342 static int mdio_read(void __iomem *ioaddr, int phy_id, int location);
343 static void mdio_write(void __iomem *ioaddr, int phy_id, int location, int value);
344 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
345 static int yellowfin_open(struct net_device *dev);
346 static void yellowfin_timer(unsigned long data);
347 static void yellowfin_tx_timeout(struct net_device *dev);
348 static int yellowfin_init_ring(struct net_device *dev);
349 static netdev_tx_t yellowfin_start_xmit(struct sk_buff *skb,
350 struct net_device *dev);
351 static irqreturn_t yellowfin_interrupt(int irq, void *dev_instance);
352 static int yellowfin_rx(struct net_device *dev);
353 static void yellowfin_error(struct net_device *dev, int intr_status);
354 static int yellowfin_close(struct net_device *dev);
355 static void set_rx_mode(struct net_device *dev);
356 static const struct ethtool_ops ethtool_ops;
357
358 static const struct net_device_ops netdev_ops = {
359 .ndo_open = yellowfin_open,
360 .ndo_stop = yellowfin_close,
361 .ndo_start_xmit = yellowfin_start_xmit,
362 .ndo_set_rx_mode = set_rx_mode,
363 .ndo_change_mtu = eth_change_mtu,
364 .ndo_validate_addr = eth_validate_addr,
365 .ndo_set_mac_address = eth_mac_addr,
366 .ndo_do_ioctl = netdev_ioctl,
367 .ndo_tx_timeout = yellowfin_tx_timeout,
368 };
369
370 static int __devinit yellowfin_init_one(struct pci_dev *pdev,
371 const struct pci_device_id *ent)
372 {
373 struct net_device *dev;
374 struct yellowfin_private *np;
375 int irq;
376 int chip_idx = ent->driver_data;
377 static int find_cnt;
378 void __iomem *ioaddr;
379 int i, option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
380 int drv_flags = pci_id_tbl[chip_idx].drv_flags;
381 void *ring_space;
382 dma_addr_t ring_dma;
383 #ifdef USE_IO_OPS
384 int bar = 0;
385 #else
386 int bar = 1;
387 #endif
388
389 /* when built into the kernel, we only print version if device is found */
390 #ifndef MODULE
391 static int printed_version;
392 if (!printed_version++)
393 printk(version);
394 #endif
395
396 i = pci_enable_device(pdev);
397 if (i) return i;
398
399 dev = alloc_etherdev(sizeof(*np));
400 if (!dev)
401 return -ENOMEM;
402
403 SET_NETDEV_DEV(dev, &pdev->dev);
404
405 np = netdev_priv(dev);
406
407 if (pci_request_regions(pdev, DRV_NAME))
408 goto err_out_free_netdev;
409
410 pci_set_master (pdev);
411
412 ioaddr = pci_iomap(pdev, bar, YELLOWFIN_SIZE);
413 if (!ioaddr)
414 goto err_out_free_res;
415
416 irq = pdev->irq;
417
418 if (drv_flags & DontUseEeprom)
419 for (i = 0; i < 6; i++)
420 dev->dev_addr[i] = ioread8(ioaddr + StnAddr + i);
421 else {
422 int ee_offset = (read_eeprom(ioaddr, 6) == 0xff ? 0x100 : 0);
423 for (i = 0; i < 6; i++)
424 dev->dev_addr[i] = read_eeprom(ioaddr, ee_offset + i);
425 }
426
427 /* Reset the chip. */
428 iowrite32(0x80000000, ioaddr + DMACtrl);
429
430 dev->base_addr = (unsigned long)ioaddr;
431 dev->irq = irq;
432
433 pci_set_drvdata(pdev, dev);
434 spin_lock_init(&np->lock);
435
436 np->pci_dev = pdev;
437 np->chip_id = chip_idx;
438 np->drv_flags = drv_flags;
439 np->base = ioaddr;
440
441 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
442 if (!ring_space)
443 goto err_out_cleardev;
444 np->tx_ring = ring_space;
445 np->tx_ring_dma = ring_dma;
446
447 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
448 if (!ring_space)
449 goto err_out_unmap_tx;
450 np->rx_ring = ring_space;
451 np->rx_ring_dma = ring_dma;
452
453 ring_space = pci_alloc_consistent(pdev, STATUS_TOTAL_SIZE, &ring_dma);
454 if (!ring_space)
455 goto err_out_unmap_rx;
456 np->tx_status = ring_space;
457 np->tx_status_dma = ring_dma;
458
459 if (dev->mem_start)
460 option = dev->mem_start;
461
462 /* The lower four bits are the media type. */
463 if (option > 0) {
464 if (option & 0x200)
465 np->full_duplex = 1;
466 np->default_port = option & 15;
467 if (np->default_port)
468 np->medialock = 1;
469 }
470 if (find_cnt < MAX_UNITS && full_duplex[find_cnt] > 0)
471 np->full_duplex = 1;
472
473 if (np->full_duplex)
474 np->duplex_lock = 1;
475
476 /* The Yellowfin-specific entries in the device structure. */
477 dev->netdev_ops = &netdev_ops;
478 SET_ETHTOOL_OPS(dev, &ethtool_ops);
479 dev->watchdog_timeo = TX_TIMEOUT;
480
481 if (mtu)
482 dev->mtu = mtu;
483
484 i = register_netdev(dev);
485 if (i)
486 goto err_out_unmap_status;
487
488 netdev_info(dev, "%s type %8x at %p, %pM, IRQ %d\n",
489 pci_id_tbl[chip_idx].name,
490 ioread32(ioaddr + ChipRev), ioaddr,
491 dev->dev_addr, irq);
492
493 if (np->drv_flags & HasMII) {
494 int phy, phy_idx = 0;
495 for (phy = 0; phy < 32 && phy_idx < MII_CNT; phy++) {
496 int mii_status = mdio_read(ioaddr, phy, 1);
497 if (mii_status != 0xffff && mii_status != 0x0000) {
498 np->phys[phy_idx++] = phy;
499 np->advertising = mdio_read(ioaddr, phy, 4);
500 netdev_info(dev, "MII PHY found at address %d, status 0x%04x advertising %04x\n",
501 phy, mii_status, np->advertising);
502 }
503 }
504 np->mii_cnt = phy_idx;
505 }
506
507 find_cnt++;
508
509 return 0;
510
511 err_out_unmap_status:
512 pci_free_consistent(pdev, STATUS_TOTAL_SIZE, np->tx_status,
513 np->tx_status_dma);
514 err_out_unmap_rx:
515 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
516 err_out_unmap_tx:
517 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
518 err_out_cleardev:
519 pci_set_drvdata(pdev, NULL);
520 pci_iounmap(pdev, ioaddr);
521 err_out_free_res:
522 pci_release_regions(pdev);
523 err_out_free_netdev:
524 free_netdev (dev);
525 return -ENODEV;
526 }
527
528 static int __devinit read_eeprom(void __iomem *ioaddr, int location)
529 {
530 int bogus_cnt = 10000; /* Typical 33Mhz: 1050 ticks */
531
532 iowrite8(location, ioaddr + EEAddr);
533 iowrite8(0x30 | ((location >> 8) & 7), ioaddr + EECtrl);
534 while ((ioread8(ioaddr + EEStatus) & 0x80) && --bogus_cnt > 0)
535 ;
536 return ioread8(ioaddr + EERead);
537 }
538
539 /* MII Managemen Data I/O accesses.
540 These routines assume the MDIO controller is idle, and do not exit until
541 the command is finished. */
542
543 static int mdio_read(void __iomem *ioaddr, int phy_id, int location)
544 {
545 int i;
546
547 iowrite16((phy_id<<8) + location, ioaddr + MII_Addr);
548 iowrite16(1, ioaddr + MII_Cmd);
549 for (i = 10000; i >= 0; i--)
550 if ((ioread16(ioaddr + MII_Status) & 1) == 0)
551 break;
552 return ioread16(ioaddr + MII_Rd_Data);
553 }
554
555 static void mdio_write(void __iomem *ioaddr, int phy_id, int location, int value)
556 {
557 int i;
558
559 iowrite16((phy_id<<8) + location, ioaddr + MII_Addr);
560 iowrite16(value, ioaddr + MII_Wr_Data);
561
562 /* Wait for the command to finish. */
563 for (i = 10000; i >= 0; i--)
564 if ((ioread16(ioaddr + MII_Status) & 1) == 0)
565 break;
566 }
567
568
569 static int yellowfin_open(struct net_device *dev)
570 {
571 struct yellowfin_private *yp = netdev_priv(dev);
572 void __iomem *ioaddr = yp->base;
573 int i, ret;
574
575 /* Reset the chip. */
576 iowrite32(0x80000000, ioaddr + DMACtrl);
577
578 ret = request_irq(dev->irq, yellowfin_interrupt, IRQF_SHARED, dev->name, dev);
579 if (ret)
580 return ret;
581
582 if (yellowfin_debug > 1)
583 netdev_printk(KERN_DEBUG, dev, "%s() irq %d\n",
584 __func__, dev->irq);
585
586 ret = yellowfin_init_ring(dev);
587 if (ret) {
588 free_irq(dev->irq, dev);
589 return ret;
590 }
591
592 iowrite32(yp->rx_ring_dma, ioaddr + RxPtr);
593 iowrite32(yp->tx_ring_dma, ioaddr + TxPtr);
594
595 for (i = 0; i < 6; i++)
596 iowrite8(dev->dev_addr[i], ioaddr + StnAddr + i);
597
598 /* Set up various condition 'select' registers.
599 There are no options here. */
600 iowrite32(0x00800080, ioaddr + TxIntrSel); /* Interrupt on Tx abort */
601 iowrite32(0x00800080, ioaddr + TxBranchSel); /* Branch on Tx abort */
602 iowrite32(0x00400040, ioaddr + TxWaitSel); /* Wait on Tx status */
603 iowrite32(0x00400040, ioaddr + RxIntrSel); /* Interrupt on Rx done */
604 iowrite32(0x00400040, ioaddr + RxBranchSel); /* Branch on Rx error */
605 iowrite32(0x00400040, ioaddr + RxWaitSel); /* Wait on Rx done */
606
607 /* Initialize other registers: with so many this eventually this will
608 converted to an offset/value list. */
609 iowrite32(dma_ctrl, ioaddr + DMACtrl);
610 iowrite16(fifo_cfg, ioaddr + FIFOcfg);
611 /* Enable automatic generation of flow control frames, period 0xffff. */
612 iowrite32(0x0030FFFF, ioaddr + FlowCtrl);
613
614 yp->tx_threshold = 32;
615 iowrite32(yp->tx_threshold, ioaddr + TxThreshold);
616
617 if (dev->if_port == 0)
618 dev->if_port = yp->default_port;
619
620 netif_start_queue(dev);
621
622 /* Setting the Rx mode will start the Rx process. */
623 if (yp->drv_flags & IsGigabit) {
624 /* We are always in full-duplex mode with gigabit! */
625 yp->full_duplex = 1;
626 iowrite16(0x01CF, ioaddr + Cnfg);
627 } else {
628 iowrite16(0x0018, ioaddr + FrameGap0); /* 0060/4060 for non-MII 10baseT */
629 iowrite16(0x1018, ioaddr + FrameGap1);
630 iowrite16(0x101C | (yp->full_duplex ? 2 : 0), ioaddr + Cnfg);
631 }
632 set_rx_mode(dev);
633
634 /* Enable interrupts by setting the interrupt mask. */
635 iowrite16(0x81ff, ioaddr + IntrEnb); /* See enum intr_status_bits */
636 iowrite16(0x0000, ioaddr + EventStatus); /* Clear non-interrupting events */
637 iowrite32(0x80008000, ioaddr + RxCtrl); /* Start Rx and Tx channels. */
638 iowrite32(0x80008000, ioaddr + TxCtrl);
639
640 if (yellowfin_debug > 2) {
641 netdev_printk(KERN_DEBUG, dev, "Done %s()\n", __func__);
642 }
643
644 /* Set the timer to check for link beat. */
645 init_timer(&yp->timer);
646 yp->timer.expires = jiffies + 3*HZ;
647 yp->timer.data = (unsigned long)dev;
648 yp->timer.function = yellowfin_timer; /* timer handler */
649 add_timer(&yp->timer);
650
651 return 0;
652 }
653
654 static void yellowfin_timer(unsigned long data)
655 {
656 struct net_device *dev = (struct net_device *)data;
657 struct yellowfin_private *yp = netdev_priv(dev);
658 void __iomem *ioaddr = yp->base;
659 int next_tick = 60*HZ;
660
661 if (yellowfin_debug > 3) {
662 netdev_printk(KERN_DEBUG, dev, "Yellowfin timer tick, status %08x\n",
663 ioread16(ioaddr + IntrStatus));
664 }
665
666 if (yp->mii_cnt) {
667 int bmsr = mdio_read(ioaddr, yp->phys[0], MII_BMSR);
668 int lpa = mdio_read(ioaddr, yp->phys[0], MII_LPA);
669 int negotiated = lpa & yp->advertising;
670 if (yellowfin_debug > 1)
671 netdev_printk(KERN_DEBUG, dev, "MII #%d status register is %04x, link partner capability %04x\n",
672 yp->phys[0], bmsr, lpa);
673
674 yp->full_duplex = mii_duplex(yp->duplex_lock, negotiated);
675
676 iowrite16(0x101C | (yp->full_duplex ? 2 : 0), ioaddr + Cnfg);
677
678 if (bmsr & BMSR_LSTATUS)
679 next_tick = 60*HZ;
680 else
681 next_tick = 3*HZ;
682 }
683
684 yp->timer.expires = jiffies + next_tick;
685 add_timer(&yp->timer);
686 }
687
688 static void yellowfin_tx_timeout(struct net_device *dev)
689 {
690 struct yellowfin_private *yp = netdev_priv(dev);
691 void __iomem *ioaddr = yp->base;
692
693 netdev_warn(dev, "Yellowfin transmit timed out at %d/%d Tx status %04x, Rx status %04x, resetting...\n",
694 yp->cur_tx, yp->dirty_tx,
695 ioread32(ioaddr + TxStatus),
696 ioread32(ioaddr + RxStatus));
697
698 /* Note: these should be KERN_DEBUG. */
699 if (yellowfin_debug) {
700 int i;
701 pr_warning(" Rx ring %p: ", yp->rx_ring);
702 for (i = 0; i < RX_RING_SIZE; i++)
703 pr_cont(" %08x", yp->rx_ring[i].result_status);
704 pr_cont("\n");
705 pr_warning(" Tx ring %p: ", yp->tx_ring);
706 for (i = 0; i < TX_RING_SIZE; i++)
707 pr_cont(" %04x /%08x",
708 yp->tx_status[i].tx_errs,
709 yp->tx_ring[i].result_status);
710 pr_cont("\n");
711 }
712
713 /* If the hardware is found to hang regularly, we will update the code
714 to reinitialize the chip here. */
715 dev->if_port = 0;
716
717 /* Wake the potentially-idle transmit channel. */
718 iowrite32(0x10001000, yp->base + TxCtrl);
719 if (yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE)
720 netif_wake_queue (dev); /* Typical path */
721
722 dev->trans_start = jiffies; /* prevent tx timeout */
723 dev->stats.tx_errors++;
724 }
725
726 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
727 static int yellowfin_init_ring(struct net_device *dev)
728 {
729 struct yellowfin_private *yp = netdev_priv(dev);
730 int i, j;
731
732 yp->tx_full = 0;
733 yp->cur_rx = yp->cur_tx = 0;
734 yp->dirty_tx = 0;
735
736 yp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
737
738 for (i = 0; i < RX_RING_SIZE; i++) {
739 yp->rx_ring[i].dbdma_cmd =
740 cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | yp->rx_buf_sz);
741 yp->rx_ring[i].branch_addr = cpu_to_le32(yp->rx_ring_dma +
742 ((i+1)%RX_RING_SIZE)*sizeof(struct yellowfin_desc));
743 }
744
745 for (i = 0; i < RX_RING_SIZE; i++) {
746 struct sk_buff *skb = netdev_alloc_skb(dev, yp->rx_buf_sz + 2);
747 yp->rx_skbuff[i] = skb;
748 if (skb == NULL)
749 break;
750 skb_reserve(skb, 2); /* 16 byte align the IP header. */
751 yp->rx_ring[i].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
752 skb->data, yp->rx_buf_sz, PCI_DMA_FROMDEVICE));
753 }
754 if (i != RX_RING_SIZE) {
755 for (j = 0; j < i; j++)
756 dev_kfree_skb(yp->rx_skbuff[j]);
757 return -ENOMEM;
758 }
759 yp->rx_ring[i-1].dbdma_cmd = cpu_to_le32(CMD_STOP);
760 yp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
761
762 #define NO_TXSTATS
763 #ifdef NO_TXSTATS
764 /* In this mode the Tx ring needs only a single descriptor. */
765 for (i = 0; i < TX_RING_SIZE; i++) {
766 yp->tx_skbuff[i] = NULL;
767 yp->tx_ring[i].dbdma_cmd = cpu_to_le32(CMD_STOP);
768 yp->tx_ring[i].branch_addr = cpu_to_le32(yp->tx_ring_dma +
769 ((i+1)%TX_RING_SIZE)*sizeof(struct yellowfin_desc));
770 }
771 /* Wrap ring */
772 yp->tx_ring[--i].dbdma_cmd = cpu_to_le32(CMD_STOP | BRANCH_ALWAYS);
773 #else
774 {
775 /* Tx ring needs a pair of descriptors, the second for the status. */
776 for (i = 0; i < TX_RING_SIZE; i++) {
777 j = 2*i;
778 yp->tx_skbuff[i] = 0;
779 /* Branch on Tx error. */
780 yp->tx_ring[j].dbdma_cmd = cpu_to_le32(CMD_STOP);
781 yp->tx_ring[j].branch_addr = cpu_to_le32(yp->tx_ring_dma +
782 (j+1)*sizeof(struct yellowfin_desc));
783 j++;
784 if (yp->flags & FullTxStatus) {
785 yp->tx_ring[j].dbdma_cmd =
786 cpu_to_le32(CMD_TXSTATUS | sizeof(*yp->tx_status));
787 yp->tx_ring[j].request_cnt = sizeof(*yp->tx_status);
788 yp->tx_ring[j].addr = cpu_to_le32(yp->tx_status_dma +
789 i*sizeof(struct tx_status_words));
790 } else {
791 /* Symbios chips write only tx_errs word. */
792 yp->tx_ring[j].dbdma_cmd =
793 cpu_to_le32(CMD_TXSTATUS | INTR_ALWAYS | 2);
794 yp->tx_ring[j].request_cnt = 2;
795 /* Om pade ummmmm... */
796 yp->tx_ring[j].addr = cpu_to_le32(yp->tx_status_dma +
797 i*sizeof(struct tx_status_words) +
798 &(yp->tx_status[0].tx_errs) -
799 &(yp->tx_status[0]));
800 }
801 yp->tx_ring[j].branch_addr = cpu_to_le32(yp->tx_ring_dma +
802 ((j+1)%(2*TX_RING_SIZE))*sizeof(struct yellowfin_desc));
803 }
804 /* Wrap ring */
805 yp->tx_ring[++j].dbdma_cmd |= cpu_to_le32(BRANCH_ALWAYS | INTR_ALWAYS);
806 }
807 #endif
808 yp->tx_tail_desc = &yp->tx_status[0];
809 return 0;
810 }
811
812 static netdev_tx_t yellowfin_start_xmit(struct sk_buff *skb,
813 struct net_device *dev)
814 {
815 struct yellowfin_private *yp = netdev_priv(dev);
816 unsigned entry;
817 int len = skb->len;
818
819 netif_stop_queue (dev);
820
821 /* Note: Ordering is important here, set the field with the
822 "ownership" bit last, and only then increment cur_tx. */
823
824 /* Calculate the next Tx descriptor entry. */
825 entry = yp->cur_tx % TX_RING_SIZE;
826
827 if (gx_fix) { /* Note: only works for paddable protocols e.g. IP. */
828 int cacheline_end = ((unsigned long)skb->data + skb->len) % 32;
829 /* Fix GX chipset errata. */
830 if (cacheline_end > 24 || cacheline_end == 0) {
831 len = skb->len + 32 - cacheline_end + 1;
832 if (skb_padto(skb, len)) {
833 yp->tx_skbuff[entry] = NULL;
834 netif_wake_queue(dev);
835 return NETDEV_TX_OK;
836 }
837 }
838 }
839 yp->tx_skbuff[entry] = skb;
840
841 #ifdef NO_TXSTATS
842 yp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
843 skb->data, len, PCI_DMA_TODEVICE));
844 yp->tx_ring[entry].result_status = 0;
845 if (entry >= TX_RING_SIZE-1) {
846 /* New stop command. */
847 yp->tx_ring[0].dbdma_cmd = cpu_to_le32(CMD_STOP);
848 yp->tx_ring[TX_RING_SIZE-1].dbdma_cmd =
849 cpu_to_le32(CMD_TX_PKT|BRANCH_ALWAYS | len);
850 } else {
851 yp->tx_ring[entry+1].dbdma_cmd = cpu_to_le32(CMD_STOP);
852 yp->tx_ring[entry].dbdma_cmd =
853 cpu_to_le32(CMD_TX_PKT | BRANCH_IFTRUE | len);
854 }
855 yp->cur_tx++;
856 #else
857 yp->tx_ring[entry<<1].request_cnt = len;
858 yp->tx_ring[entry<<1].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
859 skb->data, len, PCI_DMA_TODEVICE));
860 /* The input_last (status-write) command is constant, but we must
861 rewrite the subsequent 'stop' command. */
862
863 yp->cur_tx++;
864 {
865 unsigned next_entry = yp->cur_tx % TX_RING_SIZE;
866 yp->tx_ring[next_entry<<1].dbdma_cmd = cpu_to_le32(CMD_STOP);
867 }
868 /* Final step -- overwrite the old 'stop' command. */
869
870 yp->tx_ring[entry<<1].dbdma_cmd =
871 cpu_to_le32( ((entry % 6) == 0 ? CMD_TX_PKT|INTR_ALWAYS|BRANCH_IFTRUE :
872 CMD_TX_PKT | BRANCH_IFTRUE) | len);
873 #endif
874
875 /* Non-x86 Todo: explicitly flush cache lines here. */
876
877 /* Wake the potentially-idle transmit channel. */
878 iowrite32(0x10001000, yp->base + TxCtrl);
879
880 if (yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE)
881 netif_start_queue (dev); /* Typical path */
882 else
883 yp->tx_full = 1;
884
885 if (yellowfin_debug > 4) {
886 netdev_printk(KERN_DEBUG, dev, "Yellowfin transmit frame #%d queued in slot %d\n",
887 yp->cur_tx, entry);
888 }
889 return NETDEV_TX_OK;
890 }
891
892 /* The interrupt handler does all of the Rx thread work and cleans up
893 after the Tx thread. */
894 static irqreturn_t yellowfin_interrupt(int irq, void *dev_instance)
895 {
896 struct net_device *dev = dev_instance;
897 struct yellowfin_private *yp;
898 void __iomem *ioaddr;
899 int boguscnt = max_interrupt_work;
900 unsigned int handled = 0;
901
902 yp = netdev_priv(dev);
903 ioaddr = yp->base;
904
905 spin_lock (&yp->lock);
906
907 do {
908 u16 intr_status = ioread16(ioaddr + IntrClear);
909
910 if (yellowfin_debug > 4)
911 netdev_printk(KERN_DEBUG, dev, "Yellowfin interrupt, status %04x\n",
912 intr_status);
913
914 if (intr_status == 0)
915 break;
916 handled = 1;
917
918 if (intr_status & (IntrRxDone | IntrEarlyRx)) {
919 yellowfin_rx(dev);
920 iowrite32(0x10001000, ioaddr + RxCtrl); /* Wake Rx engine. */
921 }
922
923 #ifdef NO_TXSTATS
924 for (; yp->cur_tx - yp->dirty_tx > 0; yp->dirty_tx++) {
925 int entry = yp->dirty_tx % TX_RING_SIZE;
926 struct sk_buff *skb;
927
928 if (yp->tx_ring[entry].result_status == 0)
929 break;
930 skb = yp->tx_skbuff[entry];
931 dev->stats.tx_packets++;
932 dev->stats.tx_bytes += skb->len;
933 /* Free the original skb. */
934 pci_unmap_single(yp->pci_dev, le32_to_cpu(yp->tx_ring[entry].addr),
935 skb->len, PCI_DMA_TODEVICE);
936 dev_kfree_skb_irq(skb);
937 yp->tx_skbuff[entry] = NULL;
938 }
939 if (yp->tx_full &&
940 yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE - 4) {
941 /* The ring is no longer full, clear tbusy. */
942 yp->tx_full = 0;
943 netif_wake_queue(dev);
944 }
945 #else
946 if ((intr_status & IntrTxDone) || (yp->tx_tail_desc->tx_errs)) {
947 unsigned dirty_tx = yp->dirty_tx;
948
949 for (dirty_tx = yp->dirty_tx; yp->cur_tx - dirty_tx > 0;
950 dirty_tx++) {
951 /* Todo: optimize this. */
952 int entry = dirty_tx % TX_RING_SIZE;
953 u16 tx_errs = yp->tx_status[entry].tx_errs;
954 struct sk_buff *skb;
955
956 #ifndef final_version
957 if (yellowfin_debug > 5)
958 netdev_printk(KERN_DEBUG, dev, "Tx queue %d check, Tx status %04x %04x %04x %04x\n",
959 entry,
960 yp->tx_status[entry].tx_cnt,
961 yp->tx_status[entry].tx_errs,
962 yp->tx_status[entry].total_tx_cnt,
963 yp->tx_status[entry].paused);
964 #endif
965 if (tx_errs == 0)
966 break; /* It still hasn't been Txed */
967 skb = yp->tx_skbuff[entry];
968 if (tx_errs & 0xF810) {
969 /* There was an major error, log it. */
970 #ifndef final_version
971 if (yellowfin_debug > 1)
972 netdev_printk(KERN_DEBUG, dev, "Transmit error, Tx status %04x\n",
973 tx_errs);
974 #endif
975 dev->stats.tx_errors++;
976 if (tx_errs & 0xF800) dev->stats.tx_aborted_errors++;
977 if (tx_errs & 0x0800) dev->stats.tx_carrier_errors++;
978 if (tx_errs & 0x2000) dev->stats.tx_window_errors++;
979 if (tx_errs & 0x8000) dev->stats.tx_fifo_errors++;
980 } else {
981 #ifndef final_version
982 if (yellowfin_debug > 4)
983 netdev_printk(KERN_DEBUG, dev, "Normal transmit, Tx status %04x\n",
984 tx_errs);
985 #endif
986 dev->stats.tx_bytes += skb->len;
987 dev->stats.collisions += tx_errs & 15;
988 dev->stats.tx_packets++;
989 }
990 /* Free the original skb. */
991 pci_unmap_single(yp->pci_dev,
992 yp->tx_ring[entry<<1].addr, skb->len,
993 PCI_DMA_TODEVICE);
994 dev_kfree_skb_irq(skb);
995 yp->tx_skbuff[entry] = 0;
996 /* Mark status as empty. */
997 yp->tx_status[entry].tx_errs = 0;
998 }
999
1000 #ifndef final_version
1001 if (yp->cur_tx - dirty_tx > TX_RING_SIZE) {
1002 netdev_err(dev, "Out-of-sync dirty pointer, %d vs. %d, full=%d\n",
1003 dirty_tx, yp->cur_tx, yp->tx_full);
1004 dirty_tx += TX_RING_SIZE;
1005 }
1006 #endif
1007
1008 if (yp->tx_full &&
1009 yp->cur_tx - dirty_tx < TX_QUEUE_SIZE - 2) {
1010 /* The ring is no longer full, clear tbusy. */
1011 yp->tx_full = 0;
1012 netif_wake_queue(dev);
1013 }
1014
1015 yp->dirty_tx = dirty_tx;
1016 yp->tx_tail_desc = &yp->tx_status[dirty_tx % TX_RING_SIZE];
1017 }
1018 #endif
1019
1020 /* Log errors and other uncommon events. */
1021 if (intr_status & 0x2ee) /* Abnormal error summary. */
1022 yellowfin_error(dev, intr_status);
1023
1024 if (--boguscnt < 0) {
1025 netdev_warn(dev, "Too much work at interrupt, status=%#04x\n",
1026 intr_status);
1027 break;
1028 }
1029 } while (1);
1030
1031 if (yellowfin_debug > 3)
1032 netdev_printk(KERN_DEBUG, dev, "exiting interrupt, status=%#04x\n",
1033 ioread16(ioaddr + IntrStatus));
1034
1035 spin_unlock (&yp->lock);
1036 return IRQ_RETVAL(handled);
1037 }
1038
1039 /* This routine is logically part of the interrupt handler, but separated
1040 for clarity and better register allocation. */
1041 static int yellowfin_rx(struct net_device *dev)
1042 {
1043 struct yellowfin_private *yp = netdev_priv(dev);
1044 int entry = yp->cur_rx % RX_RING_SIZE;
1045 int boguscnt = yp->dirty_rx + RX_RING_SIZE - yp->cur_rx;
1046
1047 if (yellowfin_debug > 4) {
1048 printk(KERN_DEBUG " In yellowfin_rx(), entry %d status %08x\n",
1049 entry, yp->rx_ring[entry].result_status);
1050 printk(KERN_DEBUG " #%d desc. %08x %08x %08x\n",
1051 entry, yp->rx_ring[entry].dbdma_cmd, yp->rx_ring[entry].addr,
1052 yp->rx_ring[entry].result_status);
1053 }
1054
1055 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1056 while (1) {
1057 struct yellowfin_desc *desc = &yp->rx_ring[entry];
1058 struct sk_buff *rx_skb = yp->rx_skbuff[entry];
1059 s16 frame_status;
1060 u16 desc_status;
1061 int data_size;
1062 u8 *buf_addr;
1063
1064 if(!desc->result_status)
1065 break;
1066 pci_dma_sync_single_for_cpu(yp->pci_dev, le32_to_cpu(desc->addr),
1067 yp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1068 desc_status = le32_to_cpu(desc->result_status) >> 16;
1069 buf_addr = rx_skb->data;
1070 data_size = (le32_to_cpu(desc->dbdma_cmd) -
1071 le32_to_cpu(desc->result_status)) & 0xffff;
1072 frame_status = get_unaligned_le16(&(buf_addr[data_size - 2]));
1073 if (yellowfin_debug > 4)
1074 printk(KERN_DEBUG " %s() status was %04x\n",
1075 __func__, frame_status);
1076 if (--boguscnt < 0)
1077 break;
1078 if ( ! (desc_status & RX_EOP)) {
1079 if (data_size != 0)
1080 netdev_warn(dev, "Oversized Ethernet frame spanned multiple buffers, status %04x, data_size %d!\n",
1081 desc_status, data_size);
1082 dev->stats.rx_length_errors++;
1083 } else if ((yp->drv_flags & IsGigabit) && (frame_status & 0x0038)) {
1084 /* There was a error. */
1085 if (yellowfin_debug > 3)
1086 printk(KERN_DEBUG " %s() Rx error was %04x\n",
1087 __func__, frame_status);
1088 dev->stats.rx_errors++;
1089 if (frame_status & 0x0060) dev->stats.rx_length_errors++;
1090 if (frame_status & 0x0008) dev->stats.rx_frame_errors++;
1091 if (frame_status & 0x0010) dev->stats.rx_crc_errors++;
1092 if (frame_status < 0) dev->stats.rx_dropped++;
1093 } else if ( !(yp->drv_flags & IsGigabit) &&
1094 ((buf_addr[data_size-1] & 0x85) || buf_addr[data_size-2] & 0xC0)) {
1095 u8 status1 = buf_addr[data_size-2];
1096 u8 status2 = buf_addr[data_size-1];
1097 dev->stats.rx_errors++;
1098 if (status1 & 0xC0) dev->stats.rx_length_errors++;
1099 if (status2 & 0x03) dev->stats.rx_frame_errors++;
1100 if (status2 & 0x04) dev->stats.rx_crc_errors++;
1101 if (status2 & 0x80) dev->stats.rx_dropped++;
1102 #ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
1103 } else if ((yp->flags & HasMACAddrBug) &&
1104 memcmp(le32_to_cpu(yp->rx_ring_dma +
1105 entry*sizeof(struct yellowfin_desc)),
1106 dev->dev_addr, 6) != 0 &&
1107 memcmp(le32_to_cpu(yp->rx_ring_dma +
1108 entry*sizeof(struct yellowfin_desc)),
1109 "\377\377\377\377\377\377", 6) != 0) {
1110 if (bogus_rx++ == 0)
1111 netdev_warn(dev, "Bad frame to %pM\n",
1112 buf_addr);
1113 #endif
1114 } else {
1115 struct sk_buff *skb;
1116 int pkt_len = data_size -
1117 (yp->chip_id ? 7 : 8 + buf_addr[data_size - 8]);
1118 /* To verify: Yellowfin Length should omit the CRC! */
1119
1120 #ifndef final_version
1121 if (yellowfin_debug > 4)
1122 printk(KERN_DEBUG " %s() normal Rx pkt length %d of %d, bogus_cnt %d\n",
1123 __func__, pkt_len, data_size, boguscnt);
1124 #endif
1125 /* Check if the packet is long enough to just pass up the skbuff
1126 without copying to a properly sized skbuff. */
1127 if (pkt_len > rx_copybreak) {
1128 skb_put(skb = rx_skb, pkt_len);
1129 pci_unmap_single(yp->pci_dev,
1130 le32_to_cpu(yp->rx_ring[entry].addr),
1131 yp->rx_buf_sz,
1132 PCI_DMA_FROMDEVICE);
1133 yp->rx_skbuff[entry] = NULL;
1134 } else {
1135 skb = netdev_alloc_skb(dev, pkt_len + 2);
1136 if (skb == NULL)
1137 break;
1138 skb_reserve(skb, 2); /* 16 byte align the IP header */
1139 skb_copy_to_linear_data(skb, rx_skb->data, pkt_len);
1140 skb_put(skb, pkt_len);
1141 pci_dma_sync_single_for_device(yp->pci_dev,
1142 le32_to_cpu(desc->addr),
1143 yp->rx_buf_sz,
1144 PCI_DMA_FROMDEVICE);
1145 }
1146 skb->protocol = eth_type_trans(skb, dev);
1147 netif_rx(skb);
1148 dev->stats.rx_packets++;
1149 dev->stats.rx_bytes += pkt_len;
1150 }
1151 entry = (++yp->cur_rx) % RX_RING_SIZE;
1152 }
1153
1154 /* Refill the Rx ring buffers. */
1155 for (; yp->cur_rx - yp->dirty_rx > 0; yp->dirty_rx++) {
1156 entry = yp->dirty_rx % RX_RING_SIZE;
1157 if (yp->rx_skbuff[entry] == NULL) {
1158 struct sk_buff *skb = netdev_alloc_skb(dev, yp->rx_buf_sz + 2);
1159 if (skb == NULL)
1160 break; /* Better luck next round. */
1161 yp->rx_skbuff[entry] = skb;
1162 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1163 yp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
1164 skb->data, yp->rx_buf_sz, PCI_DMA_FROMDEVICE));
1165 }
1166 yp->rx_ring[entry].dbdma_cmd = cpu_to_le32(CMD_STOP);
1167 yp->rx_ring[entry].result_status = 0; /* Clear complete bit. */
1168 if (entry != 0)
1169 yp->rx_ring[entry - 1].dbdma_cmd =
1170 cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | yp->rx_buf_sz);
1171 else
1172 yp->rx_ring[RX_RING_SIZE - 1].dbdma_cmd =
1173 cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | BRANCH_ALWAYS
1174 | yp->rx_buf_sz);
1175 }
1176
1177 return 0;
1178 }
1179
1180 static void yellowfin_error(struct net_device *dev, int intr_status)
1181 {
1182 netdev_err(dev, "Something Wicked happened! %04x\n", intr_status);
1183 /* Hmmmmm, it's not clear what to do here. */
1184 if (intr_status & (IntrTxPCIErr | IntrTxPCIFault))
1185 dev->stats.tx_errors++;
1186 if (intr_status & (IntrRxPCIErr | IntrRxPCIFault))
1187 dev->stats.rx_errors++;
1188 }
1189
1190 static int yellowfin_close(struct net_device *dev)
1191 {
1192 struct yellowfin_private *yp = netdev_priv(dev);
1193 void __iomem *ioaddr = yp->base;
1194 int i;
1195
1196 netif_stop_queue (dev);
1197
1198 if (yellowfin_debug > 1) {
1199 netdev_printk(KERN_DEBUG, dev, "Shutting down ethercard, status was Tx %04x Rx %04x Int %02x\n",
1200 ioread16(ioaddr + TxStatus),
1201 ioread16(ioaddr + RxStatus),
1202 ioread16(ioaddr + IntrStatus));
1203 netdev_printk(KERN_DEBUG, dev, "Queue pointers were Tx %d / %d, Rx %d / %d\n",
1204 yp->cur_tx, yp->dirty_tx,
1205 yp->cur_rx, yp->dirty_rx);
1206 }
1207
1208 /* Disable interrupts by clearing the interrupt mask. */
1209 iowrite16(0x0000, ioaddr + IntrEnb);
1210
1211 /* Stop the chip's Tx and Rx processes. */
1212 iowrite32(0x80000000, ioaddr + RxCtrl);
1213 iowrite32(0x80000000, ioaddr + TxCtrl);
1214
1215 del_timer(&yp->timer);
1216
1217 #if defined(__i386__)
1218 if (yellowfin_debug > 2) {
1219 printk(KERN_DEBUG " Tx ring at %08llx:\n",
1220 (unsigned long long)yp->tx_ring_dma);
1221 for (i = 0; i < TX_RING_SIZE*2; i++)
1222 printk(KERN_DEBUG " %c #%d desc. %08x %08x %08x %08x\n",
1223 ioread32(ioaddr + TxPtr) == (long)&yp->tx_ring[i] ? '>' : ' ',
1224 i, yp->tx_ring[i].dbdma_cmd, yp->tx_ring[i].addr,
1225 yp->tx_ring[i].branch_addr, yp->tx_ring[i].result_status);
1226 printk(KERN_DEBUG " Tx status %p:\n", yp->tx_status);
1227 for (i = 0; i < TX_RING_SIZE; i++)
1228 printk(KERN_DEBUG " #%d status %04x %04x %04x %04x\n",
1229 i, yp->tx_status[i].tx_cnt, yp->tx_status[i].tx_errs,
1230 yp->tx_status[i].total_tx_cnt, yp->tx_status[i].paused);
1231
1232 printk(KERN_DEBUG " Rx ring %08llx:\n",
1233 (unsigned long long)yp->rx_ring_dma);
1234 for (i = 0; i < RX_RING_SIZE; i++) {
1235 printk(KERN_DEBUG " %c #%d desc. %08x %08x %08x\n",
1236 ioread32(ioaddr + RxPtr) == (long)&yp->rx_ring[i] ? '>' : ' ',
1237 i, yp->rx_ring[i].dbdma_cmd, yp->rx_ring[i].addr,
1238 yp->rx_ring[i].result_status);
1239 if (yellowfin_debug > 6) {
1240 if (get_unaligned((u8*)yp->rx_ring[i].addr) != 0x69) {
1241 int j;
1242
1243 printk(KERN_DEBUG);
1244 for (j = 0; j < 0x50; j++)
1245 pr_cont(" %04x",
1246 get_unaligned(((u16*)yp->rx_ring[i].addr) + j));
1247 pr_cont("\n");
1248 }
1249 }
1250 }
1251 }
1252 #endif /* __i386__ debugging only */
1253
1254 free_irq(dev->irq, dev);
1255
1256 /* Free all the skbuffs in the Rx queue. */
1257 for (i = 0; i < RX_RING_SIZE; i++) {
1258 yp->rx_ring[i].dbdma_cmd = cpu_to_le32(CMD_STOP);
1259 yp->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
1260 if (yp->rx_skbuff[i]) {
1261 dev_kfree_skb(yp->rx_skbuff[i]);
1262 }
1263 yp->rx_skbuff[i] = NULL;
1264 }
1265 for (i = 0; i < TX_RING_SIZE; i++) {
1266 if (yp->tx_skbuff[i])
1267 dev_kfree_skb(yp->tx_skbuff[i]);
1268 yp->tx_skbuff[i] = NULL;
1269 }
1270
1271 #ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
1272 if (yellowfin_debug > 0) {
1273 netdev_printk(KERN_DEBUG, dev, "Received %d frames that we should not have\n",
1274 bogus_rx);
1275 }
1276 #endif
1277
1278 return 0;
1279 }
1280
1281 /* Set or clear the multicast filter for this adaptor. */
1282
1283 static void set_rx_mode(struct net_device *dev)
1284 {
1285 struct yellowfin_private *yp = netdev_priv(dev);
1286 void __iomem *ioaddr = yp->base;
1287 u16 cfg_value = ioread16(ioaddr + Cnfg);
1288
1289 /* Stop the Rx process to change any value. */
1290 iowrite16(cfg_value & ~0x1000, ioaddr + Cnfg);
1291 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1292 iowrite16(0x000F, ioaddr + AddrMode);
1293 } else if ((netdev_mc_count(dev) > 64) ||
1294 (dev->flags & IFF_ALLMULTI)) {
1295 /* Too many to filter well, or accept all multicasts. */
1296 iowrite16(0x000B, ioaddr + AddrMode);
1297 } else if (!netdev_mc_empty(dev)) { /* Must use the multicast hash table. */
1298 struct netdev_hw_addr *ha;
1299 u16 hash_table[4];
1300 int i;
1301
1302 memset(hash_table, 0, sizeof(hash_table));
1303 netdev_for_each_mc_addr(ha, dev) {
1304 unsigned int bit;
1305
1306 /* Due to a bug in the early chip versions, multiple filter
1307 slots must be set for each address. */
1308 if (yp->drv_flags & HasMulticastBug) {
1309 bit = (ether_crc_le(3, ha->addr) >> 3) & 0x3f;
1310 hash_table[bit >> 4] |= (1 << bit);
1311 bit = (ether_crc_le(4, ha->addr) >> 3) & 0x3f;
1312 hash_table[bit >> 4] |= (1 << bit);
1313 bit = (ether_crc_le(5, ha->addr) >> 3) & 0x3f;
1314 hash_table[bit >> 4] |= (1 << bit);
1315 }
1316 bit = (ether_crc_le(6, ha->addr) >> 3) & 0x3f;
1317 hash_table[bit >> 4] |= (1 << bit);
1318 }
1319 /* Copy the hash table to the chip. */
1320 for (i = 0; i < 4; i++)
1321 iowrite16(hash_table[i], ioaddr + HashTbl + i*2);
1322 iowrite16(0x0003, ioaddr + AddrMode);
1323 } else { /* Normal, unicast/broadcast-only mode. */
1324 iowrite16(0x0001, ioaddr + AddrMode);
1325 }
1326 /* Restart the Rx process. */
1327 iowrite16(cfg_value | 0x1000, ioaddr + Cnfg);
1328 }
1329
1330 static void yellowfin_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1331 {
1332 struct yellowfin_private *np = netdev_priv(dev);
1333 strcpy(info->driver, DRV_NAME);
1334 strcpy(info->version, DRV_VERSION);
1335 strcpy(info->bus_info, pci_name(np->pci_dev));
1336 }
1337
1338 static const struct ethtool_ops ethtool_ops = {
1339 .get_drvinfo = yellowfin_get_drvinfo
1340 };
1341
1342 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1343 {
1344 struct yellowfin_private *np = netdev_priv(dev);
1345 void __iomem *ioaddr = np->base;
1346 struct mii_ioctl_data *data = if_mii(rq);
1347
1348 switch(cmd) {
1349 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1350 data->phy_id = np->phys[0] & 0x1f;
1351 /* Fall Through */
1352
1353 case SIOCGMIIREG: /* Read MII PHY register. */
1354 data->val_out = mdio_read(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f);
1355 return 0;
1356
1357 case SIOCSMIIREG: /* Write MII PHY register. */
1358 if (data->phy_id == np->phys[0]) {
1359 u16 value = data->val_in;
1360 switch (data->reg_num) {
1361 case 0:
1362 /* Check for autonegotiation on or reset. */
1363 np->medialock = (value & 0x9000) ? 0 : 1;
1364 if (np->medialock)
1365 np->full_duplex = (value & 0x0100) ? 1 : 0;
1366 break;
1367 case 4: np->advertising = value; break;
1368 }
1369 /* Perhaps check_duplex(dev), depending on chip semantics. */
1370 }
1371 mdio_write(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1372 return 0;
1373 default:
1374 return -EOPNOTSUPP;
1375 }
1376 }
1377
1378
1379 static void __devexit yellowfin_remove_one (struct pci_dev *pdev)
1380 {
1381 struct net_device *dev = pci_get_drvdata(pdev);
1382 struct yellowfin_private *np;
1383
1384 BUG_ON(!dev);
1385 np = netdev_priv(dev);
1386
1387 pci_free_consistent(pdev, STATUS_TOTAL_SIZE, np->tx_status,
1388 np->tx_status_dma);
1389 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
1390 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
1391 unregister_netdev (dev);
1392
1393 pci_iounmap(pdev, np->base);
1394
1395 pci_release_regions (pdev);
1396
1397 free_netdev (dev);
1398 pci_set_drvdata(pdev, NULL);
1399 }
1400
1401
1402 static struct pci_driver yellowfin_driver = {
1403 .name = DRV_NAME,
1404 .id_table = yellowfin_pci_tbl,
1405 .probe = yellowfin_init_one,
1406 .remove = __devexit_p(yellowfin_remove_one),
1407 };
1408
1409
1410 static int __init yellowfin_init (void)
1411 {
1412 /* when a module, this is printed whether or not devices are found in probe */
1413 #ifdef MODULE
1414 printk(version);
1415 #endif
1416 return pci_register_driver(&yellowfin_driver);
1417 }
1418
1419
1420 static void __exit yellowfin_cleanup (void)
1421 {
1422 pci_unregister_driver (&yellowfin_driver);
1423 }
1424
1425
1426 module_init(yellowfin_init);
1427 module_exit(yellowfin_cleanup);
Linux with added FPC-III support