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Linux 3.4.102
[linux/fpc-iii.git] / drivers / net / ethernet / realtek / 8139cp.c
blobeffb3b71ce75e10fa2def51e2a6357dd56db4c0b
1 /* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
2 /*
3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
4
5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
11
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
18
19 See the file COPYING in this distribution for more information.
20
21 Contributors:
22
23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
26
27 TODO:
28 * Test Tx checksumming thoroughly
29
30 Low priority TODO:
31 * Complete reset on PciErr
32 * Consider Rx interrupt mitigation using TimerIntr
33 * Investigate using skb->priority with h/w VLAN priority
34 * Investigate using High Priority Tx Queue with skb->priority
35 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
36 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
37 * Implement Tx software interrupt mitigation via
38 Tx descriptor bit
39 * The real minimum of CP_MIN_MTU is 4 bytes. However,
40 for this to be supported, one must(?) turn on packet padding.
41 * Support external MII transceivers (patch available)
42
43 NOTES:
44 * TX checksumming is considered experimental. It is off by
45 default, use ethtool to turn it on.
46
47 */
48
49 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
50
51 #define DRV_NAME "8139cp"
52 #define DRV_VERSION "1.3"
53 #define DRV_RELDATE "Mar 22, 2004"
54
55
56 #include <linux/module.h>
57 #include <linux/moduleparam.h>
58 #include <linux/kernel.h>
59 #include <linux/compiler.h>
60 #include <linux/netdevice.h>
61 #include <linux/etherdevice.h>
62 #include <linux/init.h>
63 #include <linux/interrupt.h>
64 #include <linux/pci.h>
65 #include <linux/dma-mapping.h>
66 #include <linux/delay.h>
67 #include <linux/ethtool.h>
68 #include <linux/gfp.h>
69 #include <linux/mii.h>
70 #include <linux/if_vlan.h>
71 #include <linux/crc32.h>
72 #include <linux/in.h>
73 #include <linux/ip.h>
74 #include <linux/tcp.h>
75 #include <linux/udp.h>
76 #include <linux/cache.h>
77 #include <asm/io.h>
78 #include <asm/irq.h>
79 #include <asm/uaccess.h>
80
81 /* These identify the driver base version and may not be removed. */
82 static char version[] =
83 DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
84
85 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
86 MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
87 MODULE_VERSION(DRV_VERSION);
88 MODULE_LICENSE("GPL");
89
90 static int debug = -1;
91 module_param(debug, int, 0);
92 MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
93
94 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
95 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
96 static int multicast_filter_limit = 32;
97 module_param(multicast_filter_limit, int, 0);
98 MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
99
100 #define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
101 NETIF_MSG_PROBE | \
102 NETIF_MSG_LINK)
103 #define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
104 #define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
105 #define CP_REGS_SIZE (0xff + 1)
106 #define CP_REGS_VER 1 /* version 1 */
107 #define CP_RX_RING_SIZE 64
108 #define CP_TX_RING_SIZE 64
109 #define CP_RING_BYTES \
110 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
111 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
112 CP_STATS_SIZE)
113 #define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
114 #define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
115 #define TX_BUFFS_AVAIL(CP) \
116 (((CP)->tx_tail <= (CP)->tx_head) ? \
117 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
118 (CP)->tx_tail - (CP)->tx_head - 1)
119
120 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
121 #define CP_INTERNAL_PHY 32
122
123 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
124 #define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
125 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
126 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
127 #define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
128
129 /* Time in jiffies before concluding the transmitter is hung. */
130 #define TX_TIMEOUT (6*HZ)
131
132 /* hardware minimum and maximum for a single frame's data payload */
133 #define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
134 #define CP_MAX_MTU 4096
135
136 enum {
137 /* NIC register offsets */
138 MAC0 = 0x00, /* Ethernet hardware address. */
139 MAR0 = 0x08, /* Multicast filter. */
140 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
141 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
142 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
143 Cmd = 0x37, /* Command register */
144 IntrMask = 0x3C, /* Interrupt mask */
145 IntrStatus = 0x3E, /* Interrupt status */
146 TxConfig = 0x40, /* Tx configuration */
147 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
148 RxConfig = 0x44, /* Rx configuration */
149 RxMissed = 0x4C, /* 24 bits valid, write clears */
150 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
151 Config1 = 0x52, /* Config1 */
152 Config3 = 0x59, /* Config3 */
153 Config4 = 0x5A, /* Config4 */
154 MultiIntr = 0x5C, /* Multiple interrupt select */
155 BasicModeCtrl = 0x62, /* MII BMCR */
156 BasicModeStatus = 0x64, /* MII BMSR */
157 NWayAdvert = 0x66, /* MII ADVERTISE */
158 NWayLPAR = 0x68, /* MII LPA */
159 NWayExpansion = 0x6A, /* MII Expansion */
160 Config5 = 0xD8, /* Config5 */
161 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
162 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
163 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
164 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
165 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
166 TxThresh = 0xEC, /* Early Tx threshold */
167 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
168 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
169
170 /* Tx and Rx status descriptors */
171 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
172 RingEnd = (1 << 30), /* End of descriptor ring */
173 FirstFrag = (1 << 29), /* First segment of a packet */
174 LastFrag = (1 << 28), /* Final segment of a packet */
175 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
176 MSSShift = 16, /* MSS value position */
177 MSSMask = 0xfff, /* MSS value: 11 bits */
178 TxError = (1 << 23), /* Tx error summary */
179 RxError = (1 << 20), /* Rx error summary */
180 IPCS = (1 << 18), /* Calculate IP checksum */
181 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
182 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
183 TxVlanTag = (1 << 17), /* Add VLAN tag */
184 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
185 IPFail = (1 << 15), /* IP checksum failed */
186 UDPFail = (1 << 14), /* UDP/IP checksum failed */
187 TCPFail = (1 << 13), /* TCP/IP checksum failed */
188 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
189 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
190 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
191 RxProtoTCP = 1,
192 RxProtoUDP = 2,
193 RxProtoIP = 3,
194 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
195 TxOWC = (1 << 22), /* Tx Out-of-window collision */
196 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
197 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
198 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
199 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
200 RxErrFrame = (1 << 27), /* Rx frame alignment error */
201 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
202 RxErrCRC = (1 << 18), /* Rx CRC error */
203 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
204 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
205 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
206
207 /* StatsAddr register */
208 DumpStats = (1 << 3), /* Begin stats dump */
209
210 /* RxConfig register */
211 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
212 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
213 AcceptErr = 0x20, /* Accept packets with CRC errors */
214 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
215 AcceptBroadcast = 0x08, /* Accept broadcast packets */
216 AcceptMulticast = 0x04, /* Accept multicast packets */
217 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
218 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
219
220 /* IntrMask / IntrStatus registers */
221 PciErr = (1 << 15), /* System error on the PCI bus */
222 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
223 LenChg = (1 << 13), /* Cable length change */
224 SWInt = (1 << 8), /* Software-requested interrupt */
225 TxEmpty = (1 << 7), /* No Tx descriptors available */
226 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
227 LinkChg = (1 << 5), /* Packet underrun, or link change */
228 RxEmpty = (1 << 4), /* No Rx descriptors available */
229 TxErr = (1 << 3), /* Tx error */
230 TxOK = (1 << 2), /* Tx packet sent */
231 RxErr = (1 << 1), /* Rx error */
232 RxOK = (1 << 0), /* Rx packet received */
233 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
234 but hardware likes to raise it */
235
236 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
237 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
238 RxErr | RxOK | IntrResvd,
239
240 /* C mode command register */
241 CmdReset = (1 << 4), /* Enable to reset; self-clearing */
242 RxOn = (1 << 3), /* Rx mode enable */
243 TxOn = (1 << 2), /* Tx mode enable */
244
245 /* C+ mode command register */
246 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
247 RxChkSum = (1 << 5), /* Rx checksum offload enable */
248 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
249 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
250 CpRxOn = (1 << 1), /* Rx mode enable */
251 CpTxOn = (1 << 0), /* Tx mode enable */
252
253 /* Cfg9436 EEPROM control register */
254 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
255 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
256
257 /* TxConfig register */
258 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
259 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
260
261 /* Early Tx Threshold register */
262 TxThreshMask = 0x3f, /* Mask bits 5-0 */
263 TxThreshMax = 2048, /* Max early Tx threshold */
264
265 /* Config1 register */
266 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
267 LWACT = (1 << 4), /* LWAKE active mode */
268 PMEnable = (1 << 0), /* Enable various PM features of chip */
269
270 /* Config3 register */
271 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
272 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
273 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
274
275 /* Config4 register */
276 LWPTN = (1 << 1), /* LWAKE Pattern */
277 LWPME = (1 << 4), /* LANWAKE vs PMEB */
278
279 /* Config5 register */
280 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
281 MWF = (1 << 5), /* Accept Multicast wakeup frame */
282 UWF = (1 << 4), /* Accept Unicast wakeup frame */
283 LANWake = (1 << 1), /* Enable LANWake signal */
284 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
285
286 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
287 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
288 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
289 };
290
291 static const unsigned int cp_rx_config =
292 (RX_FIFO_THRESH << RxCfgFIFOShift) |
293 (RX_DMA_BURST << RxCfgDMAShift);
294
295 struct cp_desc {
296 __le32 opts1;
297 __le32 opts2;
298 __le64 addr;
299 };
300
301 struct cp_dma_stats {
302 __le64 tx_ok;
303 __le64 rx_ok;
304 __le64 tx_err;
305 __le32 rx_err;
306 __le16 rx_fifo;
307 __le16 frame_align;
308 __le32 tx_ok_1col;
309 __le32 tx_ok_mcol;
310 __le64 rx_ok_phys;
311 __le64 rx_ok_bcast;
312 __le32 rx_ok_mcast;
313 __le16 tx_abort;
314 __le16 tx_underrun;
315 } __packed;
316
317 struct cp_extra_stats {
318 unsigned long rx_frags;
319 };
320
321 struct cp_private {
322 void __iomem *regs;
323 struct net_device *dev;
324 spinlock_t lock;
325 u32 msg_enable;
326
327 struct napi_struct napi;
328
329 struct pci_dev *pdev;
330 u32 rx_config;
331 u16 cpcmd;
332
333 struct cp_extra_stats cp_stats;
334
335 unsigned rx_head ____cacheline_aligned;
336 unsigned rx_tail;
337 struct cp_desc *rx_ring;
338 struct sk_buff *rx_skb[CP_RX_RING_SIZE];
339
340 unsigned tx_head ____cacheline_aligned;
341 unsigned tx_tail;
342 struct cp_desc *tx_ring;
343 struct sk_buff *tx_skb[CP_TX_RING_SIZE];
344
345 unsigned rx_buf_sz;
346 unsigned wol_enabled : 1; /* Is Wake-on-LAN enabled? */
347
348 dma_addr_t ring_dma;
349
350 struct mii_if_info mii_if;
351 };
352
353 #define cpr8(reg) readb(cp->regs + (reg))
354 #define cpr16(reg) readw(cp->regs + (reg))
355 #define cpr32(reg) readl(cp->regs + (reg))
356 #define cpw8(reg,val) writeb((val), cp->regs + (reg))
357 #define cpw16(reg,val) writew((val), cp->regs + (reg))
358 #define cpw32(reg,val) writel((val), cp->regs + (reg))
359 #define cpw8_f(reg,val) do { \
360 writeb((val), cp->regs + (reg)); \
361 readb(cp->regs + (reg)); \
362 } while (0)
363 #define cpw16_f(reg,val) do { \
364 writew((val), cp->regs + (reg)); \
365 readw(cp->regs + (reg)); \
366 } while (0)
367 #define cpw32_f(reg,val) do { \
368 writel((val), cp->regs + (reg)); \
369 readl(cp->regs + (reg)); \
370 } while (0)
371
372
373 static void __cp_set_rx_mode (struct net_device *dev);
374 static void cp_tx (struct cp_private *cp);
375 static void cp_clean_rings (struct cp_private *cp);
376 #ifdef CONFIG_NET_POLL_CONTROLLER
377 static void cp_poll_controller(struct net_device *dev);
378 #endif
379 static int cp_get_eeprom_len(struct net_device *dev);
380 static int cp_get_eeprom(struct net_device *dev,
381 struct ethtool_eeprom *eeprom, u8 *data);
382 static int cp_set_eeprom(struct net_device *dev,
383 struct ethtool_eeprom *eeprom, u8 *data);
384
385 static DEFINE_PCI_DEVICE_TABLE(cp_pci_tbl) = {
386 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139), },
387 { PCI_DEVICE(PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322), },
388 { },
389 };
390 MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
391
392 static struct {
393 const char str[ETH_GSTRING_LEN];
394 } ethtool_stats_keys[] = {
395 { "tx_ok" },
396 { "rx_ok" },
397 { "tx_err" },
398 { "rx_err" },
399 { "rx_fifo" },
400 { "frame_align" },
401 { "tx_ok_1col" },
402 { "tx_ok_mcol" },
403 { "rx_ok_phys" },
404 { "rx_ok_bcast" },
405 { "rx_ok_mcast" },
406 { "tx_abort" },
407 { "tx_underrun" },
408 { "rx_frags" },
409 };
410
411
412 static inline void cp_set_rxbufsize (struct cp_private *cp)
413 {
414 unsigned int mtu = cp->dev->mtu;
415
416 if (mtu > ETH_DATA_LEN)
417 /* MTU + ethernet header + FCS + optional VLAN tag */
418 cp->rx_buf_sz = mtu + ETH_HLEN + 8;
419 else
420 cp->rx_buf_sz = PKT_BUF_SZ;
421 }
422
423 static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
424 struct cp_desc *desc)
425 {
426 u32 opts2 = le32_to_cpu(desc->opts2);
427
428 skb->protocol = eth_type_trans (skb, cp->dev);
429
430 cp->dev->stats.rx_packets++;
431 cp->dev->stats.rx_bytes += skb->len;
432
433 if (opts2 & RxVlanTagged)
434 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
435
436 napi_gro_receive(&cp->napi, skb);
437 }
438
439 static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
440 u32 status, u32 len)
441 {
442 netif_dbg(cp, rx_err, cp->dev, "rx err, slot %d status 0x%x len %d\n",
443 rx_tail, status, len);
444 cp->dev->stats.rx_errors++;
445 if (status & RxErrFrame)
446 cp->dev->stats.rx_frame_errors++;
447 if (status & RxErrCRC)
448 cp->dev->stats.rx_crc_errors++;
449 if ((status & RxErrRunt) || (status & RxErrLong))
450 cp->dev->stats.rx_length_errors++;
451 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
452 cp->dev->stats.rx_length_errors++;
453 if (status & RxErrFIFO)
454 cp->dev->stats.rx_fifo_errors++;
455 }
456
457 static inline unsigned int cp_rx_csum_ok (u32 status)
458 {
459 unsigned int protocol = (status >> 16) & 0x3;
460
461 if (((protocol == RxProtoTCP) && !(status & TCPFail)) ||
462 ((protocol == RxProtoUDP) && !(status & UDPFail)))
463 return 1;
464 else
465 return 0;
466 }
467
468 static int cp_rx_poll(struct napi_struct *napi, int budget)
469 {
470 struct cp_private *cp = container_of(napi, struct cp_private, napi);
471 struct net_device *dev = cp->dev;
472 unsigned int rx_tail = cp->rx_tail;
473 int rx;
474
475 rx_status_loop:
476 rx = 0;
477 cpw16(IntrStatus, cp_rx_intr_mask);
478
479 while (1) {
480 u32 status, len;
481 dma_addr_t mapping, new_mapping;
482 struct sk_buff *skb, *new_skb;
483 struct cp_desc *desc;
484 const unsigned buflen = cp->rx_buf_sz;
485
486 skb = cp->rx_skb[rx_tail];
487 BUG_ON(!skb);
488
489 desc = &cp->rx_ring[rx_tail];
490 status = le32_to_cpu(desc->opts1);
491 if (status & DescOwn)
492 break;
493
494 len = (status & 0x1fff) - 4;
495 mapping = le64_to_cpu(desc->addr);
496
497 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
498 /* we don't support incoming fragmented frames.
499 * instead, we attempt to ensure that the
500 * pre-allocated RX skbs are properly sized such
501 * that RX fragments are never encountered
502 */
503 cp_rx_err_acct(cp, rx_tail, status, len);
504 dev->stats.rx_dropped++;
505 cp->cp_stats.rx_frags++;
506 goto rx_next;
507 }
508
509 if (status & (RxError | RxErrFIFO)) {
510 cp_rx_err_acct(cp, rx_tail, status, len);
511 goto rx_next;
512 }
513
514 netif_dbg(cp, rx_status, dev, "rx slot %d status 0x%x len %d\n",
515 rx_tail, status, len);
516
517 new_skb = netdev_alloc_skb_ip_align(dev, buflen);
518 if (!new_skb) {
519 dev->stats.rx_dropped++;
520 goto rx_next;
521 }
522
523 new_mapping = dma_map_single(&cp->pdev->dev, new_skb->data, buflen,
524 PCI_DMA_FROMDEVICE);
525 if (dma_mapping_error(&cp->pdev->dev, new_mapping)) {
526 dev->stats.rx_dropped++;
527 kfree_skb(new_skb);
528 goto rx_next;
529 }
530
531 dma_unmap_single(&cp->pdev->dev, mapping,
532 buflen, PCI_DMA_FROMDEVICE);
533
534 /* Handle checksum offloading for incoming packets. */
535 if (cp_rx_csum_ok(status))
536 skb->ip_summed = CHECKSUM_UNNECESSARY;
537 else
538 skb_checksum_none_assert(skb);
539
540 skb_put(skb, len);
541
542 cp->rx_skb[rx_tail] = new_skb;
543
544 cp_rx_skb(cp, skb, desc);
545 rx++;
546 mapping = new_mapping;
547
548 rx_next:
549 cp->rx_ring[rx_tail].opts2 = 0;
550 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
551 if (rx_tail == (CP_RX_RING_SIZE - 1))
552 desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
553 cp->rx_buf_sz);
554 else
555 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
556 rx_tail = NEXT_RX(rx_tail);
557
558 if (rx >= budget)
559 break;
560 }
561
562 cp->rx_tail = rx_tail;
563
564 /* if we did not reach work limit, then we're done with
565 * this round of polling
566 */
567 if (rx < budget) {
568 unsigned long flags;
569
570 if (cpr16(IntrStatus) & cp_rx_intr_mask)
571 goto rx_status_loop;
572
573 napi_gro_flush(napi);
574 spin_lock_irqsave(&cp->lock, flags);
575 __napi_complete(napi);
576 cpw16_f(IntrMask, cp_intr_mask);
577 spin_unlock_irqrestore(&cp->lock, flags);
578 }
579
580 return rx;
581 }
582
583 static irqreturn_t cp_interrupt (int irq, void *dev_instance)
584 {
585 struct net_device *dev = dev_instance;
586 struct cp_private *cp;
587 u16 status;
588
589 if (unlikely(dev == NULL))
590 return IRQ_NONE;
591 cp = netdev_priv(dev);
592
593 status = cpr16(IntrStatus);
594 if (!status || (status == 0xFFFF))
595 return IRQ_NONE;
596
597 netif_dbg(cp, intr, dev, "intr, status %04x cmd %02x cpcmd %04x\n",
598 status, cpr8(Cmd), cpr16(CpCmd));
599
600 cpw16(IntrStatus, status & ~cp_rx_intr_mask);
601
602 spin_lock(&cp->lock);
603
604 /* close possible race's with dev_close */
605 if (unlikely(!netif_running(dev))) {
606 cpw16(IntrMask, 0);
607 spin_unlock(&cp->lock);
608 return IRQ_HANDLED;
609 }
610
611 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
612 if (napi_schedule_prep(&cp->napi)) {
613 cpw16_f(IntrMask, cp_norx_intr_mask);
614 __napi_schedule(&cp->napi);
615 }
616
617 if (status & (TxOK | TxErr | TxEmpty | SWInt))
618 cp_tx(cp);
619 if (status & LinkChg)
620 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
621
622 spin_unlock(&cp->lock);
623
624 if (status & PciErr) {
625 u16 pci_status;
626
627 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
628 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
629 netdev_err(dev, "PCI bus error, status=%04x, PCI status=%04x\n",
630 status, pci_status);
631
632 /* TODO: reset hardware */
633 }
634
635 return IRQ_HANDLED;
636 }
637
638 #ifdef CONFIG_NET_POLL_CONTROLLER
639 /*
640 * Polling receive - used by netconsole and other diagnostic tools
641 * to allow network i/o with interrupts disabled.
642 */
643 static void cp_poll_controller(struct net_device *dev)
644 {
645 disable_irq(dev->irq);
646 cp_interrupt(dev->irq, dev);
647 enable_irq(dev->irq);
648 }
649 #endif
650
651 static void cp_tx (struct cp_private *cp)
652 {
653 unsigned tx_head = cp->tx_head;
654 unsigned tx_tail = cp->tx_tail;
655
656 while (tx_tail != tx_head) {
657 struct cp_desc *txd = cp->tx_ring + tx_tail;
658 struct sk_buff *skb;
659 u32 status;
660
661 rmb();
662 status = le32_to_cpu(txd->opts1);
663 if (status & DescOwn)
664 break;
665
666 skb = cp->tx_skb[tx_tail];
667 BUG_ON(!skb);
668
669 dma_unmap_single(&cp->pdev->dev, le64_to_cpu(txd->addr),
670 le32_to_cpu(txd->opts1) & 0xffff,
671 PCI_DMA_TODEVICE);
672
673 if (status & LastFrag) {
674 if (status & (TxError | TxFIFOUnder)) {
675 netif_dbg(cp, tx_err, cp->dev,
676 "tx err, status 0x%x\n", status);
677 cp->dev->stats.tx_errors++;
678 if (status & TxOWC)
679 cp->dev->stats.tx_window_errors++;
680 if (status & TxMaxCol)
681 cp->dev->stats.tx_aborted_errors++;
682 if (status & TxLinkFail)
683 cp->dev->stats.tx_carrier_errors++;
684 if (status & TxFIFOUnder)
685 cp->dev->stats.tx_fifo_errors++;
686 } else {
687 cp->dev->stats.collisions +=
688 ((status >> TxColCntShift) & TxColCntMask);
689 cp->dev->stats.tx_packets++;
690 cp->dev->stats.tx_bytes += skb->len;
691 netif_dbg(cp, tx_done, cp->dev,
692 "tx done, slot %d\n", tx_tail);
693 }
694 dev_kfree_skb_irq(skb);
695 }
696
697 cp->tx_skb[tx_tail] = NULL;
698
699 tx_tail = NEXT_TX(tx_tail);
700 }
701
702 cp->tx_tail = tx_tail;
703
704 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
705 netif_wake_queue(cp->dev);
706 }
707
708 static inline u32 cp_tx_vlan_tag(struct sk_buff *skb)
709 {
710 return vlan_tx_tag_present(skb) ?
711 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
712 }
713
714 static void unwind_tx_frag_mapping(struct cp_private *cp, struct sk_buff *skb,
715 int first, int entry_last)
716 {
717 int frag, index;
718 struct cp_desc *txd;
719 skb_frag_t *this_frag;
720 for (frag = 0; frag+first < entry_last; frag++) {
721 index = first+frag;
722 cp->tx_skb[index] = NULL;
723 txd = &cp->tx_ring[index];
724 this_frag = &skb_shinfo(skb)->frags[frag];
725 dma_unmap_single(&cp->pdev->dev, le64_to_cpu(txd->addr),
726 skb_frag_size(this_frag), PCI_DMA_TODEVICE);
727 }
728 }
729
730 static netdev_tx_t cp_start_xmit (struct sk_buff *skb,
731 struct net_device *dev)
732 {
733 struct cp_private *cp = netdev_priv(dev);
734 unsigned entry;
735 u32 eor, flags;
736 unsigned long intr_flags;
737 __le32 opts2;
738 int mss = 0;
739
740 spin_lock_irqsave(&cp->lock, intr_flags);
741
742 /* This is a hard error, log it. */
743 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
744 netif_stop_queue(dev);
745 spin_unlock_irqrestore(&cp->lock, intr_flags);
746 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
747 return NETDEV_TX_BUSY;
748 }
749
750 entry = cp->tx_head;
751 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
752 mss = skb_shinfo(skb)->gso_size;
753
754 opts2 = cpu_to_le32(cp_tx_vlan_tag(skb));
755
756 if (skb_shinfo(skb)->nr_frags == 0) {
757 struct cp_desc *txd = &cp->tx_ring[entry];
758 u32 len;
759 dma_addr_t mapping;
760
761 len = skb->len;
762 mapping = dma_map_single(&cp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);
763 if (dma_mapping_error(&cp->pdev->dev, mapping))
764 goto out_dma_error;
765
766 txd->opts2 = opts2;
767 txd->addr = cpu_to_le64(mapping);
768 wmb();
769
770 flags = eor | len | DescOwn | FirstFrag | LastFrag;
771
772 if (mss)
773 flags |= LargeSend | ((mss & MSSMask) << MSSShift);
774 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
775 const struct iphdr *ip = ip_hdr(skb);
776 if (ip->protocol == IPPROTO_TCP)
777 flags |= IPCS | TCPCS;
778 else if (ip->protocol == IPPROTO_UDP)
779 flags |= IPCS | UDPCS;
780 else
781 WARN_ON(1); /* we need a WARN() */
782 }
783
784 txd->opts1 = cpu_to_le32(flags);
785 wmb();
786
787 cp->tx_skb[entry] = skb;
788 entry = NEXT_TX(entry);
789 } else {
790 struct cp_desc *txd;
791 u32 first_len, first_eor;
792 dma_addr_t first_mapping;
793 int frag, first_entry = entry;
794 const struct iphdr *ip = ip_hdr(skb);
795
796 /* We must give this initial chunk to the device last.
797 * Otherwise we could race with the device.
798 */
799 first_eor = eor;
800 first_len = skb_headlen(skb);
801 first_mapping = dma_map_single(&cp->pdev->dev, skb->data,
802 first_len, PCI_DMA_TODEVICE);
803 if (dma_mapping_error(&cp->pdev->dev, first_mapping))
804 goto out_dma_error;
805
806 cp->tx_skb[entry] = skb;
807 entry = NEXT_TX(entry);
808
809 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
810 const skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
811 u32 len;
812 u32 ctrl;
813 dma_addr_t mapping;
814
815 len = skb_frag_size(this_frag);
816 mapping = dma_map_single(&cp->pdev->dev,
817 skb_frag_address(this_frag),
818 len, PCI_DMA_TODEVICE);
819 if (dma_mapping_error(&cp->pdev->dev, mapping)) {
820 unwind_tx_frag_mapping(cp, skb, first_entry, entry);
821 goto out_dma_error;
822 }
823
824 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
825
826 ctrl = eor | len | DescOwn;
827
828 if (mss)
829 ctrl |= LargeSend |
830 ((mss & MSSMask) << MSSShift);
831 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
832 if (ip->protocol == IPPROTO_TCP)
833 ctrl |= IPCS | TCPCS;
834 else if (ip->protocol == IPPROTO_UDP)
835 ctrl |= IPCS | UDPCS;
836 else
837 BUG();
838 }
839
840 if (frag == skb_shinfo(skb)->nr_frags - 1)
841 ctrl |= LastFrag;
842
843 txd = &cp->tx_ring[entry];
844 txd->opts2 = opts2;
845 txd->addr = cpu_to_le64(mapping);
846 wmb();
847
848 txd->opts1 = cpu_to_le32(ctrl);
849 wmb();
850
851 cp->tx_skb[entry] = skb;
852 entry = NEXT_TX(entry);
853 }
854
855 txd = &cp->tx_ring[first_entry];
856 txd->opts2 = opts2;
857 txd->addr = cpu_to_le64(first_mapping);
858 wmb();
859
860 if (skb->ip_summed == CHECKSUM_PARTIAL) {
861 if (ip->protocol == IPPROTO_TCP)
862 txd->opts1 = cpu_to_le32(first_eor | first_len |
863 FirstFrag | DescOwn |
864 IPCS | TCPCS);
865 else if (ip->protocol == IPPROTO_UDP)
866 txd->opts1 = cpu_to_le32(first_eor | first_len |
867 FirstFrag | DescOwn |
868 IPCS | UDPCS);
869 else
870 BUG();
871 } else
872 txd->opts1 = cpu_to_le32(first_eor | first_len |
873 FirstFrag | DescOwn);
874 wmb();
875 }
876 cp->tx_head = entry;
877 netif_dbg(cp, tx_queued, cp->dev, "tx queued, slot %d, skblen %d\n",
878 entry, skb->len);
879 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
880 netif_stop_queue(dev);
881
882 out_unlock:
883 spin_unlock_irqrestore(&cp->lock, intr_flags);
884
885 cpw8(TxPoll, NormalTxPoll);
886
887 return NETDEV_TX_OK;
888 out_dma_error:
889 kfree_skb(skb);
890 cp->dev->stats.tx_dropped++;
891 goto out_unlock;
892 }
893
894 /* Set or clear the multicast filter for this adaptor.
895 This routine is not state sensitive and need not be SMP locked. */
896
897 static void __cp_set_rx_mode (struct net_device *dev)
898 {
899 struct cp_private *cp = netdev_priv(dev);
900 u32 mc_filter[2]; /* Multicast hash filter */
901 int rx_mode;
902
903 /* Note: do not reorder, GCC is clever about common statements. */
904 if (dev->flags & IFF_PROMISC) {
905 /* Unconditionally log net taps. */
906 rx_mode =
907 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
908 AcceptAllPhys;
909 mc_filter[1] = mc_filter[0] = 0xffffffff;
910 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
911 (dev->flags & IFF_ALLMULTI)) {
912 /* Too many to filter perfectly -- accept all multicasts. */
913 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
914 mc_filter[1] = mc_filter[0] = 0xffffffff;
915 } else {
916 struct netdev_hw_addr *ha;
917 rx_mode = AcceptBroadcast | AcceptMyPhys;
918 mc_filter[1] = mc_filter[0] = 0;
919 netdev_for_each_mc_addr(ha, dev) {
920 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
921
922 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
923 rx_mode |= AcceptMulticast;
924 }
925 }
926
927 /* We can safely update without stopping the chip. */
928 cp->rx_config = cp_rx_config | rx_mode;
929 cpw32_f(RxConfig, cp->rx_config);
930
931 cpw32_f (MAR0 + 0, mc_filter[0]);
932 cpw32_f (MAR0 + 4, mc_filter[1]);
933 }
934
935 static void cp_set_rx_mode (struct net_device *dev)
936 {
937 unsigned long flags;
938 struct cp_private *cp = netdev_priv(dev);
939
940 spin_lock_irqsave (&cp->lock, flags);
941 __cp_set_rx_mode(dev);
942 spin_unlock_irqrestore (&cp->lock, flags);
943 }
944
945 static void __cp_get_stats(struct cp_private *cp)
946 {
947 /* only lower 24 bits valid; write any value to clear */
948 cp->dev->stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
949 cpw32 (RxMissed, 0);
950 }
951
952 static struct net_device_stats *cp_get_stats(struct net_device *dev)
953 {
954 struct cp_private *cp = netdev_priv(dev);
955 unsigned long flags;
956
957 /* The chip only need report frame silently dropped. */
958 spin_lock_irqsave(&cp->lock, flags);
959 if (netif_running(dev) && netif_device_present(dev))
960 __cp_get_stats(cp);
961 spin_unlock_irqrestore(&cp->lock, flags);
962
963 return &dev->stats;
964 }
965
966 static void cp_stop_hw (struct cp_private *cp)
967 {
968 cpw16(IntrStatus, ~(cpr16(IntrStatus)));
969 cpw16_f(IntrMask, 0);
970 cpw8(Cmd, 0);
971 cpw16_f(CpCmd, 0);
972 cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
973
974 cp->rx_tail = 0;
975 cp->tx_head = cp->tx_tail = 0;
976 }
977
978 static void cp_reset_hw (struct cp_private *cp)
979 {
980 unsigned work = 1000;
981
982 cpw8(Cmd, CmdReset);
983
984 while (work--) {
985 if (!(cpr8(Cmd) & CmdReset))
986 return;
987
988 schedule_timeout_uninterruptible(10);
989 }
990
991 netdev_err(cp->dev, "hardware reset timeout\n");
992 }
993
994 static inline void cp_start_hw (struct cp_private *cp)
995 {
996 cpw16(CpCmd, cp->cpcmd);
997 cpw8(Cmd, RxOn | TxOn);
998 }
999
1000 static void cp_enable_irq(struct cp_private *cp)
1001 {
1002 cpw16_f(IntrMask, cp_intr_mask);
1003 }
1004
1005 static void cp_init_hw (struct cp_private *cp)
1006 {
1007 struct net_device *dev = cp->dev;
1008 dma_addr_t ring_dma;
1009
1010 cp_reset_hw(cp);
1011
1012 cpw8_f (Cfg9346, Cfg9346_Unlock);
1013
1014 /* Restore our idea of the MAC address. */
1015 cpw32_f (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1016 cpw32_f (MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
1017
1018 cp_start_hw(cp);
1019 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
1020
1021 __cp_set_rx_mode(dev);
1022 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
1023
1024 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
1025 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
1026 cpw8(Config3, PARMEnable);
1027 cp->wol_enabled = 0;
1028
1029 cpw8(Config5, cpr8(Config5) & PMEStatus);
1030
1031 cpw32_f(HiTxRingAddr, 0);
1032 cpw32_f(HiTxRingAddr + 4, 0);
1033
1034 ring_dma = cp->ring_dma;
1035 cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
1036 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
1037
1038 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
1039 cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
1040 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
1041
1042 cpw16(MultiIntr, 0);
1043
1044 cpw8_f(Cfg9346, Cfg9346_Lock);
1045 }
1046
1047 static int cp_refill_rx(struct cp_private *cp)
1048 {
1049 struct net_device *dev = cp->dev;
1050 unsigned i;
1051
1052 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1053 struct sk_buff *skb;
1054 dma_addr_t mapping;
1055
1056 skb = netdev_alloc_skb_ip_align(dev, cp->rx_buf_sz);
1057 if (!skb)
1058 goto err_out;
1059
1060 mapping = dma_map_single(&cp->pdev->dev, skb->data,
1061 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1062 if (dma_mapping_error(&cp->pdev->dev, mapping)) {
1063 kfree_skb(skb);
1064 goto err_out;
1065 }
1066 cp->rx_skb[i] = skb;
1067
1068 cp->rx_ring[i].opts2 = 0;
1069 cp->rx_ring[i].addr = cpu_to_le64(mapping);
1070 if (i == (CP_RX_RING_SIZE - 1))
1071 cp->rx_ring[i].opts1 =
1072 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
1073 else
1074 cp->rx_ring[i].opts1 =
1075 cpu_to_le32(DescOwn | cp->rx_buf_sz);
1076 }
1077
1078 return 0;
1079
1080 err_out:
1081 cp_clean_rings(cp);
1082 return -ENOMEM;
1083 }
1084
1085 static void cp_init_rings_index (struct cp_private *cp)
1086 {
1087 cp->rx_tail = 0;
1088 cp->tx_head = cp->tx_tail = 0;
1089 }
1090
1091 static int cp_init_rings (struct cp_private *cp)
1092 {
1093 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1094 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
1095
1096 cp_init_rings_index(cp);
1097
1098 return cp_refill_rx (cp);
1099 }
1100
1101 static int cp_alloc_rings (struct cp_private *cp)
1102 {
1103 void *mem;
1104
1105 mem = dma_alloc_coherent(&cp->pdev->dev, CP_RING_BYTES,
1106 &cp->ring_dma, GFP_KERNEL);
1107 if (!mem)
1108 return -ENOMEM;
1109
1110 cp->rx_ring = mem;
1111 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
1112
1113 return cp_init_rings(cp);
1114 }
1115
1116 static void cp_clean_rings (struct cp_private *cp)
1117 {
1118 struct cp_desc *desc;
1119 unsigned i;
1120
1121 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1122 if (cp->rx_skb[i]) {
1123 desc = cp->rx_ring + i;
1124 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
1125 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1126 dev_kfree_skb(cp->rx_skb[i]);
1127 }
1128 }
1129
1130 for (i = 0; i < CP_TX_RING_SIZE; i++) {
1131 if (cp->tx_skb[i]) {
1132 struct sk_buff *skb = cp->tx_skb[i];
1133
1134 desc = cp->tx_ring + i;
1135 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
1136 le32_to_cpu(desc->opts1) & 0xffff,
1137 PCI_DMA_TODEVICE);
1138 if (le32_to_cpu(desc->opts1) & LastFrag)
1139 dev_kfree_skb(skb);
1140 cp->dev->stats.tx_dropped++;
1141 }
1142 }
1143 netdev_reset_queue(cp->dev);
1144
1145 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1146 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1147
1148 memset(cp->rx_skb, 0, sizeof(struct sk_buff *) * CP_RX_RING_SIZE);
1149 memset(cp->tx_skb, 0, sizeof(struct sk_buff *) * CP_TX_RING_SIZE);
1150 }
1151
1152 static void cp_free_rings (struct cp_private *cp)
1153 {
1154 cp_clean_rings(cp);
1155 dma_free_coherent(&cp->pdev->dev, CP_RING_BYTES, cp->rx_ring,
1156 cp->ring_dma);
1157 cp->rx_ring = NULL;
1158 cp->tx_ring = NULL;
1159 }
1160
1161 static int cp_open (struct net_device *dev)
1162 {
1163 struct cp_private *cp = netdev_priv(dev);
1164 int rc;
1165
1166 netif_dbg(cp, ifup, dev, "enabling interface\n");
1167
1168 rc = cp_alloc_rings(cp);
1169 if (rc)
1170 return rc;
1171
1172 napi_enable(&cp->napi);
1173
1174 cp_init_hw(cp);
1175
1176 rc = request_irq(dev->irq, cp_interrupt, IRQF_SHARED, dev->name, dev);
1177 if (rc)
1178 goto err_out_hw;
1179
1180 cp_enable_irq(cp);
1181
1182 netif_carrier_off(dev);
1183 mii_check_media(&cp->mii_if, netif_msg_link(cp), true);
1184 netif_start_queue(dev);
1185
1186 return 0;
1187
1188 err_out_hw:
1189 napi_disable(&cp->napi);
1190 cp_stop_hw(cp);
1191 cp_free_rings(cp);
1192 return rc;
1193 }
1194
1195 static int cp_close (struct net_device *dev)
1196 {
1197 struct cp_private *cp = netdev_priv(dev);
1198 unsigned long flags;
1199
1200 napi_disable(&cp->napi);
1201
1202 netif_dbg(cp, ifdown, dev, "disabling interface\n");
1203
1204 spin_lock_irqsave(&cp->lock, flags);
1205
1206 netif_stop_queue(dev);
1207 netif_carrier_off(dev);
1208
1209 cp_stop_hw(cp);
1210
1211 spin_unlock_irqrestore(&cp->lock, flags);
1212
1213 free_irq(dev->irq, dev);
1214
1215 cp_free_rings(cp);
1216 return 0;
1217 }
1218
1219 static void cp_tx_timeout(struct net_device *dev)
1220 {
1221 struct cp_private *cp = netdev_priv(dev);
1222 unsigned long flags;
1223 int rc;
1224
1225 netdev_warn(dev, "Transmit timeout, status %2x %4x %4x %4x\n",
1226 cpr8(Cmd), cpr16(CpCmd),
1227 cpr16(IntrStatus), cpr16(IntrMask));
1228
1229 spin_lock_irqsave(&cp->lock, flags);
1230
1231 cp_stop_hw(cp);
1232 cp_clean_rings(cp);
1233 rc = cp_init_rings(cp);
1234 cp_start_hw(cp);
1235 cp_enable_irq(cp);
1236
1237 netif_wake_queue(dev);
1238
1239 spin_unlock_irqrestore(&cp->lock, flags);
1240 }
1241
1242 #ifdef BROKEN
1243 static int cp_change_mtu(struct net_device *dev, int new_mtu)
1244 {
1245 struct cp_private *cp = netdev_priv(dev);
1246 int rc;
1247 unsigned long flags;
1248
1249 /* check for invalid MTU, according to hardware limits */
1250 if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
1251 return -EINVAL;
1252
1253 /* if network interface not up, no need for complexity */
1254 if (!netif_running(dev)) {
1255 dev->mtu = new_mtu;
1256 cp_set_rxbufsize(cp); /* set new rx buf size */
1257 return 0;
1258 }
1259
1260 spin_lock_irqsave(&cp->lock, flags);
1261
1262 cp_stop_hw(cp); /* stop h/w and free rings */
1263 cp_clean_rings(cp);
1264
1265 dev->mtu = new_mtu;
1266 cp_set_rxbufsize(cp); /* set new rx buf size */
1267
1268 rc = cp_init_rings(cp); /* realloc and restart h/w */
1269 cp_start_hw(cp);
1270
1271 spin_unlock_irqrestore(&cp->lock, flags);
1272
1273 return rc;
1274 }
1275 #endif /* BROKEN */
1276
1277 static const char mii_2_8139_map[8] = {
1278 BasicModeCtrl,
1279 BasicModeStatus,
1280 0,
1281 0,
1282 NWayAdvert,
1283 NWayLPAR,
1284 NWayExpansion,
1285 0
1286 };
1287
1288 static int mdio_read(struct net_device *dev, int phy_id, int location)
1289 {
1290 struct cp_private *cp = netdev_priv(dev);
1291
1292 return location < 8 && mii_2_8139_map[location] ?
1293 readw(cp->regs + mii_2_8139_map[location]) : 0;
1294 }
1295
1296
1297 static void mdio_write(struct net_device *dev, int phy_id, int location,
1298 int value)
1299 {
1300 struct cp_private *cp = netdev_priv(dev);
1301
1302 if (location == 0) {
1303 cpw8(Cfg9346, Cfg9346_Unlock);
1304 cpw16(BasicModeCtrl, value);
1305 cpw8(Cfg9346, Cfg9346_Lock);
1306 } else if (location < 8 && mii_2_8139_map[location])
1307 cpw16(mii_2_8139_map[location], value);
1308 }
1309
1310 /* Set the ethtool Wake-on-LAN settings */
1311 static int netdev_set_wol (struct cp_private *cp,
1312 const struct ethtool_wolinfo *wol)
1313 {
1314 u8 options;
1315
1316 options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
1317 /* If WOL is being disabled, no need for complexity */
1318 if (wol->wolopts) {
1319 if (wol->wolopts & WAKE_PHY) options |= LinkUp;
1320 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
1321 }
1322
1323 cpw8 (Cfg9346, Cfg9346_Unlock);
1324 cpw8 (Config3, options);
1325 cpw8 (Cfg9346, Cfg9346_Lock);
1326
1327 options = 0; /* Paranoia setting */
1328 options = cpr8 (Config5) & ~(UWF | MWF | BWF);
1329 /* If WOL is being disabled, no need for complexity */
1330 if (wol->wolopts) {
1331 if (wol->wolopts & WAKE_UCAST) options |= UWF;
1332 if (wol->wolopts & WAKE_BCAST) options |= BWF;
1333 if (wol->wolopts & WAKE_MCAST) options |= MWF;
1334 }
1335
1336 cpw8 (Config5, options);
1337
1338 cp->wol_enabled = (wol->wolopts) ? 1 : 0;
1339
1340 return 0;
1341 }
1342
1343 /* Get the ethtool Wake-on-LAN settings */
1344 static void netdev_get_wol (struct cp_private *cp,
1345 struct ethtool_wolinfo *wol)
1346 {
1347 u8 options;
1348
1349 wol->wolopts = 0; /* Start from scratch */
1350 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
1351 WAKE_MCAST | WAKE_UCAST;
1352 /* We don't need to go on if WOL is disabled */
1353 if (!cp->wol_enabled) return;
1354
1355 options = cpr8 (Config3);
1356 if (options & LinkUp) wol->wolopts |= WAKE_PHY;
1357 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
1358
1359 options = 0; /* Paranoia setting */
1360 options = cpr8 (Config5);
1361 if (options & UWF) wol->wolopts |= WAKE_UCAST;
1362 if (options & BWF) wol->wolopts |= WAKE_BCAST;
1363 if (options & MWF) wol->wolopts |= WAKE_MCAST;
1364 }
1365
1366 static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1367 {
1368 struct cp_private *cp = netdev_priv(dev);
1369
1370 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1371 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1372 strlcpy(info->bus_info, pci_name(cp->pdev), sizeof(info->bus_info));
1373 }
1374
1375 static void cp_get_ringparam(struct net_device *dev,
1376 struct ethtool_ringparam *ring)
1377 {
1378 ring->rx_max_pending = CP_RX_RING_SIZE;
1379 ring->tx_max_pending = CP_TX_RING_SIZE;
1380 ring->rx_pending = CP_RX_RING_SIZE;
1381 ring->tx_pending = CP_TX_RING_SIZE;
1382 }
1383
1384 static int cp_get_regs_len(struct net_device *dev)
1385 {
1386 return CP_REGS_SIZE;
1387 }
1388
1389 static int cp_get_sset_count (struct net_device *dev, int sset)
1390 {
1391 switch (sset) {
1392 case ETH_SS_STATS:
1393 return CP_NUM_STATS;
1394 default:
1395 return -EOPNOTSUPP;
1396 }
1397 }
1398
1399 static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1400 {
1401 struct cp_private *cp = netdev_priv(dev);
1402 int rc;
1403 unsigned long flags;
1404
1405 spin_lock_irqsave(&cp->lock, flags);
1406 rc = mii_ethtool_gset(&cp->mii_if, cmd);
1407 spin_unlock_irqrestore(&cp->lock, flags);
1408
1409 return rc;
1410 }
1411
1412 static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1413 {
1414 struct cp_private *cp = netdev_priv(dev);
1415 int rc;
1416 unsigned long flags;
1417
1418 spin_lock_irqsave(&cp->lock, flags);
1419 rc = mii_ethtool_sset(&cp->mii_if, cmd);
1420 spin_unlock_irqrestore(&cp->lock, flags);
1421
1422 return rc;
1423 }
1424
1425 static int cp_nway_reset(struct net_device *dev)
1426 {
1427 struct cp_private *cp = netdev_priv(dev);
1428 return mii_nway_restart(&cp->mii_if);
1429 }
1430
1431 static u32 cp_get_msglevel(struct net_device *dev)
1432 {
1433 struct cp_private *cp = netdev_priv(dev);
1434 return cp->msg_enable;
1435 }
1436
1437 static void cp_set_msglevel(struct net_device *dev, u32 value)
1438 {
1439 struct cp_private *cp = netdev_priv(dev);
1440 cp->msg_enable = value;
1441 }
1442
1443 static int cp_set_features(struct net_device *dev, netdev_features_t features)
1444 {
1445 struct cp_private *cp = netdev_priv(dev);
1446 unsigned long flags;
1447
1448 if (!((dev->features ^ features) & NETIF_F_RXCSUM))
1449 return 0;
1450
1451 spin_lock_irqsave(&cp->lock, flags);
1452
1453 if (features & NETIF_F_RXCSUM)
1454 cp->cpcmd |= RxChkSum;
1455 else
1456 cp->cpcmd &= ~RxChkSum;
1457
1458 if (features & NETIF_F_HW_VLAN_RX)
1459 cp->cpcmd |= RxVlanOn;
1460 else
1461 cp->cpcmd &= ~RxVlanOn;
1462
1463 cpw16_f(CpCmd, cp->cpcmd);
1464 spin_unlock_irqrestore(&cp->lock, flags);
1465
1466 return 0;
1467 }
1468
1469 static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1470 void *p)
1471 {
1472 struct cp_private *cp = netdev_priv(dev);
1473 unsigned long flags;
1474
1475 if (regs->len < CP_REGS_SIZE)
1476 return /* -EINVAL */;
1477
1478 regs->version = CP_REGS_VER;
1479
1480 spin_lock_irqsave(&cp->lock, flags);
1481 memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
1482 spin_unlock_irqrestore(&cp->lock, flags);
1483 }
1484
1485 static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1486 {
1487 struct cp_private *cp = netdev_priv(dev);
1488 unsigned long flags;
1489
1490 spin_lock_irqsave (&cp->lock, flags);
1491 netdev_get_wol (cp, wol);
1492 spin_unlock_irqrestore (&cp->lock, flags);
1493 }
1494
1495 static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1496 {
1497 struct cp_private *cp = netdev_priv(dev);
1498 unsigned long flags;
1499 int rc;
1500
1501 spin_lock_irqsave (&cp->lock, flags);
1502 rc = netdev_set_wol (cp, wol);
1503 spin_unlock_irqrestore (&cp->lock, flags);
1504
1505 return rc;
1506 }
1507
1508 static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
1509 {
1510 switch (stringset) {
1511 case ETH_SS_STATS:
1512 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
1513 break;
1514 default:
1515 BUG();
1516 break;
1517 }
1518 }
1519
1520 static void cp_get_ethtool_stats (struct net_device *dev,
1521 struct ethtool_stats *estats, u64 *tmp_stats)
1522 {
1523 struct cp_private *cp = netdev_priv(dev);
1524 struct cp_dma_stats *nic_stats;
1525 dma_addr_t dma;
1526 int i;
1527
1528 nic_stats = dma_alloc_coherent(&cp->pdev->dev, sizeof(*nic_stats),
1529 &dma, GFP_KERNEL);
1530 if (!nic_stats)
1531 return;
1532
1533 /* begin NIC statistics dump */
1534 cpw32(StatsAddr + 4, (u64)dma >> 32);
1535 cpw32(StatsAddr, ((u64)dma & DMA_BIT_MASK(32)) | DumpStats);
1536 cpr32(StatsAddr);
1537
1538 for (i = 0; i < 1000; i++) {
1539 if ((cpr32(StatsAddr) & DumpStats) == 0)
1540 break;
1541 udelay(10);
1542 }
1543 cpw32(StatsAddr, 0);
1544 cpw32(StatsAddr + 4, 0);
1545 cpr32(StatsAddr);
1546
1547 i = 0;
1548 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_ok);
1549 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok);
1550 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_err);
1551 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_err);
1552 tmp_stats[i++] = le16_to_cpu(nic_stats->rx_fifo);
1553 tmp_stats[i++] = le16_to_cpu(nic_stats->frame_align);
1554 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_1col);
1555 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_mcol);
1556 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_phys);
1557 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_bcast);
1558 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_ok_mcast);
1559 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_abort);
1560 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_underrun);
1561 tmp_stats[i++] = cp->cp_stats.rx_frags;
1562 BUG_ON(i != CP_NUM_STATS);
1563
1564 dma_free_coherent(&cp->pdev->dev, sizeof(*nic_stats), nic_stats, dma);
1565 }
1566
1567 static const struct ethtool_ops cp_ethtool_ops = {
1568 .get_drvinfo = cp_get_drvinfo,
1569 .get_regs_len = cp_get_regs_len,
1570 .get_sset_count = cp_get_sset_count,
1571 .get_settings = cp_get_settings,
1572 .set_settings = cp_set_settings,
1573 .nway_reset = cp_nway_reset,
1574 .get_link = ethtool_op_get_link,
1575 .get_msglevel = cp_get_msglevel,
1576 .set_msglevel = cp_set_msglevel,
1577 .get_regs = cp_get_regs,
1578 .get_wol = cp_get_wol,
1579 .set_wol = cp_set_wol,
1580 .get_strings = cp_get_strings,
1581 .get_ethtool_stats = cp_get_ethtool_stats,
1582 .get_eeprom_len = cp_get_eeprom_len,
1583 .get_eeprom = cp_get_eeprom,
1584 .set_eeprom = cp_set_eeprom,
1585 .get_ringparam = cp_get_ringparam,
1586 };
1587
1588 static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1589 {
1590 struct cp_private *cp = netdev_priv(dev);
1591 int rc;
1592 unsigned long flags;
1593
1594 if (!netif_running(dev))
1595 return -EINVAL;
1596
1597 spin_lock_irqsave(&cp->lock, flags);
1598 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
1599 spin_unlock_irqrestore(&cp->lock, flags);
1600 return rc;
1601 }
1602
1603 static int cp_set_mac_address(struct net_device *dev, void *p)
1604 {
1605 struct cp_private *cp = netdev_priv(dev);
1606 struct sockaddr *addr = p;
1607
1608 if (!is_valid_ether_addr(addr->sa_data))
1609 return -EADDRNOTAVAIL;
1610
1611 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1612
1613 spin_lock_irq(&cp->lock);
1614
1615 cpw8_f(Cfg9346, Cfg9346_Unlock);
1616 cpw32_f(MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1617 cpw32_f(MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
1618 cpw8_f(Cfg9346, Cfg9346_Lock);
1619
1620 spin_unlock_irq(&cp->lock);
1621
1622 return 0;
1623 }
1624
1625 /* Serial EEPROM section. */
1626
1627 /* EEPROM_Ctrl bits. */
1628 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1629 #define EE_CS 0x08 /* EEPROM chip select. */
1630 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1631 #define EE_WRITE_0 0x00
1632 #define EE_WRITE_1 0x02
1633 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1634 #define EE_ENB (0x80 | EE_CS)
1635
1636 /* Delay between EEPROM clock transitions.
1637 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1638 */
1639
1640 #define eeprom_delay() readb(ee_addr)
1641
1642 /* The EEPROM commands include the alway-set leading bit. */
1643 #define EE_EXTEND_CMD (4)
1644 #define EE_WRITE_CMD (5)
1645 #define EE_READ_CMD (6)
1646 #define EE_ERASE_CMD (7)
1647
1648 #define EE_EWDS_ADDR (0)
1649 #define EE_WRAL_ADDR (1)
1650 #define EE_ERAL_ADDR (2)
1651 #define EE_EWEN_ADDR (3)
1652
1653 #define CP_EEPROM_MAGIC PCI_DEVICE_ID_REALTEK_8139
1654
1655 static void eeprom_cmd_start(void __iomem *ee_addr)
1656 {
1657 writeb (EE_ENB & ~EE_CS, ee_addr);
1658 writeb (EE_ENB, ee_addr);
1659 eeprom_delay ();
1660 }
1661
1662 static void eeprom_cmd(void __iomem *ee_addr, int cmd, int cmd_len)
1663 {
1664 int i;
1665
1666 /* Shift the command bits out. */
1667 for (i = cmd_len - 1; i >= 0; i--) {
1668 int dataval = (cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1669 writeb (EE_ENB | dataval, ee_addr);
1670 eeprom_delay ();
1671 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1672 eeprom_delay ();
1673 }
1674 writeb (EE_ENB, ee_addr);
1675 eeprom_delay ();
1676 }
1677
1678 static void eeprom_cmd_end(void __iomem *ee_addr)
1679 {
1680 writeb (~EE_CS, ee_addr);
1681 eeprom_delay ();
1682 }
1683
1684 static void eeprom_extend_cmd(void __iomem *ee_addr, int extend_cmd,
1685 int addr_len)
1686 {
1687 int cmd = (EE_EXTEND_CMD << addr_len) | (extend_cmd << (addr_len - 2));
1688
1689 eeprom_cmd_start(ee_addr);
1690 eeprom_cmd(ee_addr, cmd, 3 + addr_len);
1691 eeprom_cmd_end(ee_addr);
1692 }
1693
1694 static u16 read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1695 {
1696 int i;
1697 u16 retval = 0;
1698 void __iomem *ee_addr = ioaddr + Cfg9346;
1699 int read_cmd = location | (EE_READ_CMD << addr_len);
1700
1701 eeprom_cmd_start(ee_addr);
1702 eeprom_cmd(ee_addr, read_cmd, 3 + addr_len);
1703
1704 for (i = 16; i > 0; i--) {
1705 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1706 eeprom_delay ();
1707 retval =
1708 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1709 0);
1710 writeb (EE_ENB, ee_addr);
1711 eeprom_delay ();
1712 }
1713
1714 eeprom_cmd_end(ee_addr);
1715
1716 return retval;
1717 }
1718
1719 static void write_eeprom(void __iomem *ioaddr, int location, u16 val,
1720 int addr_len)
1721 {
1722 int i;
1723 void __iomem *ee_addr = ioaddr + Cfg9346;
1724 int write_cmd = location | (EE_WRITE_CMD << addr_len);
1725
1726 eeprom_extend_cmd(ee_addr, EE_EWEN_ADDR, addr_len);
1727
1728 eeprom_cmd_start(ee_addr);
1729 eeprom_cmd(ee_addr, write_cmd, 3 + addr_len);
1730 eeprom_cmd(ee_addr, val, 16);
1731 eeprom_cmd_end(ee_addr);
1732
1733 eeprom_cmd_start(ee_addr);
1734 for (i = 0; i < 20000; i++)
1735 if (readb(ee_addr) & EE_DATA_READ)
1736 break;
1737 eeprom_cmd_end(ee_addr);
1738
1739 eeprom_extend_cmd(ee_addr, EE_EWDS_ADDR, addr_len);
1740 }
1741
1742 static int cp_get_eeprom_len(struct net_device *dev)
1743 {
1744 struct cp_private *cp = netdev_priv(dev);
1745 int size;
1746
1747 spin_lock_irq(&cp->lock);
1748 size = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 256 : 128;
1749 spin_unlock_irq(&cp->lock);
1750
1751 return size;
1752 }
1753
1754 static int cp_get_eeprom(struct net_device *dev,
1755 struct ethtool_eeprom *eeprom, u8 *data)
1756 {
1757 struct cp_private *cp = netdev_priv(dev);
1758 unsigned int addr_len;
1759 u16 val;
1760 u32 offset = eeprom->offset >> 1;
1761 u32 len = eeprom->len;
1762 u32 i = 0;
1763
1764 eeprom->magic = CP_EEPROM_MAGIC;
1765
1766 spin_lock_irq(&cp->lock);
1767
1768 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1769
1770 if (eeprom->offset & 1) {
1771 val = read_eeprom(cp->regs, offset, addr_len);
1772 data[i++] = (u8)(val >> 8);
1773 offset++;
1774 }
1775
1776 while (i < len - 1) {
1777 val = read_eeprom(cp->regs, offset, addr_len);
1778 data[i++] = (u8)val;
1779 data[i++] = (u8)(val >> 8);
1780 offset++;
1781 }
1782
1783 if (i < len) {
1784 val = read_eeprom(cp->regs, offset, addr_len);
1785 data[i] = (u8)val;
1786 }
1787
1788 spin_unlock_irq(&cp->lock);
1789 return 0;
1790 }
1791
1792 static int cp_set_eeprom(struct net_device *dev,
1793 struct ethtool_eeprom *eeprom, u8 *data)
1794 {
1795 struct cp_private *cp = netdev_priv(dev);
1796 unsigned int addr_len;
1797 u16 val;
1798 u32 offset = eeprom->offset >> 1;
1799 u32 len = eeprom->len;
1800 u32 i = 0;
1801
1802 if (eeprom->magic != CP_EEPROM_MAGIC)
1803 return -EINVAL;
1804
1805 spin_lock_irq(&cp->lock);
1806
1807 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1808
1809 if (eeprom->offset & 1) {
1810 val = read_eeprom(cp->regs, offset, addr_len) & 0xff;
1811 val |= (u16)data[i++] << 8;
1812 write_eeprom(cp->regs, offset, val, addr_len);
1813 offset++;
1814 }
1815
1816 while (i < len - 1) {
1817 val = (u16)data[i++];
1818 val |= (u16)data[i++] << 8;
1819 write_eeprom(cp->regs, offset, val, addr_len);
1820 offset++;
1821 }
1822
1823 if (i < len) {
1824 val = read_eeprom(cp->regs, offset, addr_len) & 0xff00;
1825 val |= (u16)data[i];
1826 write_eeprom(cp->regs, offset, val, addr_len);
1827 }
1828
1829 spin_unlock_irq(&cp->lock);
1830 return 0;
1831 }
1832
1833 /* Put the board into D3cold state and wait for WakeUp signal */
1834 static void cp_set_d3_state (struct cp_private *cp)
1835 {
1836 pci_enable_wake (cp->pdev, 0, 1); /* Enable PME# generation */
1837 pci_set_power_state (cp->pdev, PCI_D3hot);
1838 }
1839
1840 static const struct net_device_ops cp_netdev_ops = {
1841 .ndo_open = cp_open,
1842 .ndo_stop = cp_close,
1843 .ndo_validate_addr = eth_validate_addr,
1844 .ndo_set_mac_address = cp_set_mac_address,
1845 .ndo_set_rx_mode = cp_set_rx_mode,
1846 .ndo_get_stats = cp_get_stats,
1847 .ndo_do_ioctl = cp_ioctl,
1848 .ndo_start_xmit = cp_start_xmit,
1849 .ndo_tx_timeout = cp_tx_timeout,
1850 .ndo_set_features = cp_set_features,
1851 #ifdef BROKEN
1852 .ndo_change_mtu = cp_change_mtu,
1853 #endif
1854
1855 #ifdef CONFIG_NET_POLL_CONTROLLER
1856 .ndo_poll_controller = cp_poll_controller,
1857 #endif
1858 };
1859
1860 static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1861 {
1862 struct net_device *dev;
1863 struct cp_private *cp;
1864 int rc;
1865 void __iomem *regs;
1866 resource_size_t pciaddr;
1867 unsigned int addr_len, i, pci_using_dac;
1868
1869 #ifndef MODULE
1870 static int version_printed;
1871 if (version_printed++ == 0)
1872 pr_info("%s", version);
1873 #endif
1874
1875 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
1876 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision < 0x20) {
1877 dev_info(&pdev->dev,
1878 "This (id %04x:%04x rev %02x) is not an 8139C+ compatible chip, use 8139too\n",
1879 pdev->vendor, pdev->device, pdev->revision);
1880 return -ENODEV;
1881 }
1882
1883 dev = alloc_etherdev(sizeof(struct cp_private));
1884 if (!dev)
1885 return -ENOMEM;
1886 SET_NETDEV_DEV(dev, &pdev->dev);
1887
1888 cp = netdev_priv(dev);
1889 cp->pdev = pdev;
1890 cp->dev = dev;
1891 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
1892 spin_lock_init (&cp->lock);
1893 cp->mii_if.dev = dev;
1894 cp->mii_if.mdio_read = mdio_read;
1895 cp->mii_if.mdio_write = mdio_write;
1896 cp->mii_if.phy_id = CP_INTERNAL_PHY;
1897 cp->mii_if.phy_id_mask = 0x1f;
1898 cp->mii_if.reg_num_mask = 0x1f;
1899 cp_set_rxbufsize(cp);
1900
1901 rc = pci_enable_device(pdev);
1902 if (rc)
1903 goto err_out_free;
1904
1905 rc = pci_set_mwi(pdev);
1906 if (rc)
1907 goto err_out_disable;
1908
1909 rc = pci_request_regions(pdev, DRV_NAME);
1910 if (rc)
1911 goto err_out_mwi;
1912
1913 pciaddr = pci_resource_start(pdev, 1);
1914 if (!pciaddr) {
1915 rc = -EIO;
1916 dev_err(&pdev->dev, "no MMIO resource\n");
1917 goto err_out_res;
1918 }
1919 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1920 rc = -EIO;
1921 dev_err(&pdev->dev, "MMIO resource (%llx) too small\n",
1922 (unsigned long long)pci_resource_len(pdev, 1));
1923 goto err_out_res;
1924 }
1925
1926 /* Configure DMA attributes. */
1927 if ((sizeof(dma_addr_t) > 4) &&
1928 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) &&
1929 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1930 pci_using_dac = 1;
1931 } else {
1932 pci_using_dac = 0;
1933
1934 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1935 if (rc) {
1936 dev_err(&pdev->dev,
1937 "No usable DMA configuration, aborting\n");
1938 goto err_out_res;
1939 }
1940 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1941 if (rc) {
1942 dev_err(&pdev->dev,
1943 "No usable consistent DMA configuration, aborting\n");
1944 goto err_out_res;
1945 }
1946 }
1947
1948 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
1949 PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
1950
1951 dev->features |= NETIF_F_RXCSUM;
1952 dev->hw_features |= NETIF_F_RXCSUM;
1953
1954 regs = ioremap(pciaddr, CP_REGS_SIZE);
1955 if (!regs) {
1956 rc = -EIO;
1957 dev_err(&pdev->dev, "Cannot map PCI MMIO (%Lx@%Lx)\n",
1958 (unsigned long long)pci_resource_len(pdev, 1),
1959 (unsigned long long)pciaddr);
1960 goto err_out_res;
1961 }
1962 dev->base_addr = (unsigned long) regs;
1963 cp->regs = regs;
1964
1965 cp_stop_hw(cp);
1966
1967 /* read MAC address from EEPROM */
1968 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
1969 for (i = 0; i < 3; i++)
1970 ((__le16 *) (dev->dev_addr))[i] =
1971 cpu_to_le16(read_eeprom (regs, i + 7, addr_len));
1972 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1973
1974 dev->netdev_ops = &cp_netdev_ops;
1975 netif_napi_add(dev, &cp->napi, cp_rx_poll, 16);
1976 dev->ethtool_ops = &cp_ethtool_ops;
1977 dev->watchdog_timeo = TX_TIMEOUT;
1978
1979 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1980
1981 if (pci_using_dac)
1982 dev->features |= NETIF_F_HIGHDMA;
1983
1984 /* disabled by default until verified */
1985 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
1986 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1987 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
1988 NETIF_F_HIGHDMA;
1989
1990 dev->irq = pdev->irq;
1991
1992 rc = register_netdev(dev);
1993 if (rc)
1994 goto err_out_iomap;
1995
1996 netdev_info(dev, "RTL-8139C+ at 0x%lx, %pM, IRQ %d\n",
1997 dev->base_addr, dev->dev_addr, dev->irq);
1998
1999 pci_set_drvdata(pdev, dev);
2000
2001 /* enable busmastering and memory-write-invalidate */
2002 pci_set_master(pdev);
2003
2004 if (cp->wol_enabled)
2005 cp_set_d3_state (cp);
2006
2007 return 0;
2008
2009 err_out_iomap:
2010 iounmap(regs);
2011 err_out_res:
2012 pci_release_regions(pdev);
2013 err_out_mwi:
2014 pci_clear_mwi(pdev);
2015 err_out_disable:
2016 pci_disable_device(pdev);
2017 err_out_free:
2018 free_netdev(dev);
2019 return rc;
2020 }
2021
2022 static void cp_remove_one (struct pci_dev *pdev)
2023 {
2024 struct net_device *dev = pci_get_drvdata(pdev);
2025 struct cp_private *cp = netdev_priv(dev);
2026
2027 unregister_netdev(dev);
2028 iounmap(cp->regs);
2029 if (cp->wol_enabled)
2030 pci_set_power_state (pdev, PCI_D0);
2031 pci_release_regions(pdev);
2032 pci_clear_mwi(pdev);
2033 pci_disable_device(pdev);
2034 pci_set_drvdata(pdev, NULL);
2035 free_netdev(dev);
2036 }
2037
2038 #ifdef CONFIG_PM
2039 static int cp_suspend (struct pci_dev *pdev, pm_message_t state)
2040 {
2041 struct net_device *dev = pci_get_drvdata(pdev);
2042 struct cp_private *cp = netdev_priv(dev);
2043 unsigned long flags;
2044
2045 if (!netif_running(dev))
2046 return 0;
2047
2048 netif_device_detach (dev);
2049 netif_stop_queue (dev);
2050
2051 spin_lock_irqsave (&cp->lock, flags);
2052
2053 /* Disable Rx and Tx */
2054 cpw16 (IntrMask, 0);
2055 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
2056
2057 spin_unlock_irqrestore (&cp->lock, flags);
2058
2059 pci_save_state(pdev);
2060 pci_enable_wake(pdev, pci_choose_state(pdev, state), cp->wol_enabled);
2061 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2062
2063 return 0;
2064 }
2065
2066 static int cp_resume (struct pci_dev *pdev)
2067 {
2068 struct net_device *dev = pci_get_drvdata (pdev);
2069 struct cp_private *cp = netdev_priv(dev);
2070 unsigned long flags;
2071
2072 if (!netif_running(dev))
2073 return 0;
2074
2075 netif_device_attach (dev);
2076
2077 pci_set_power_state(pdev, PCI_D0);
2078 pci_restore_state(pdev);
2079 pci_enable_wake(pdev, PCI_D0, 0);
2080
2081 /* FIXME: sh*t may happen if the Rx ring buffer is depleted */
2082 cp_init_rings_index (cp);
2083 cp_init_hw (cp);
2084 cp_enable_irq(cp);
2085 netif_start_queue (dev);
2086
2087 spin_lock_irqsave (&cp->lock, flags);
2088
2089 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
2090
2091 spin_unlock_irqrestore (&cp->lock, flags);
2092
2093 return 0;
2094 }
2095 #endif /* CONFIG_PM */
2096
2097 static struct pci_driver cp_driver = {
2098 .name = DRV_NAME,
2099 .id_table = cp_pci_tbl,
2100 .probe = cp_init_one,
2101 .remove = cp_remove_one,
2102 #ifdef CONFIG_PM
2103 .resume = cp_resume,
2104 .suspend = cp_suspend,
2105 #endif
2106 };
2107
2108 static int __init cp_init (void)
2109 {
2110 #ifdef MODULE
2111 pr_info("%s", version);
2112 #endif
2113 return pci_register_driver(&cp_driver);
2114 }
2115
2116 static void __exit cp_exit (void)
2117 {
2118 pci_unregister_driver (&cp_driver);
2119 }
2120
2121 module_init(cp_init);
2122 module_exit(cp_exit);
Linux with added FPC-III support