?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 3.4.102
[linux/fpc-iii.git] / drivers / net / ethernet / realtek / r8169.c
blob2a59e7a7106ff9194a17a04a22bf77d81ffff156
1 /*
2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
9 */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/firmware.h>
29 #include <linux/pci-aspm.h>
30 #include <linux/prefetch.h>
31
32 #include <asm/io.h>
33 #include <asm/irq.h>
34
35 #define RTL8169_VERSION "2.3LK-NAPI"
36 #define MODULENAME "r8169"
37 #define PFX MODULENAME ": "
38
39 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
41 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
43 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
44 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
45 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
46 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
47
48 #ifdef RTL8169_DEBUG
49 #define assert(expr) \
50 if (!(expr)) { \
51 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
52 #expr,__FILE__,__func__,__LINE__); \
53 }
54 #define dprintk(fmt, args...) \
55 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
56 #else
57 #define assert(expr) do {} while (0)
58 #define dprintk(fmt, args...) do {} while (0)
59 #endif /* RTL8169_DEBUG */
60
61 #define R8169_MSG_DEFAULT \
62 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
63
64 #define TX_SLOTS_AVAIL(tp) \
65 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
66
67 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
68 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
69 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
70
71 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
72 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
73 static const int multicast_filter_limit = 32;
74
75 #define MAX_READ_REQUEST_SHIFT 12
76 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
77 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
78 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
79
80 #define R8169_REGS_SIZE 256
81 #define R8169_NAPI_WEIGHT 64
82 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
83 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
84 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
85 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
86 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
87
88 #define RTL8169_TX_TIMEOUT (6*HZ)
89 #define RTL8169_PHY_TIMEOUT (10*HZ)
90
91 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
92 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
93 #define RTL_EEPROM_SIG_ADDR 0x0000
94
95 /* write/read MMIO register */
96 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
97 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
98 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
99 #define RTL_R8(reg) readb (ioaddr + (reg))
100 #define RTL_R16(reg) readw (ioaddr + (reg))
101 #define RTL_R32(reg) readl (ioaddr + (reg))
102
103 enum mac_version {
104 RTL_GIGA_MAC_VER_01 = 0,
105 RTL_GIGA_MAC_VER_02,
106 RTL_GIGA_MAC_VER_03,
107 RTL_GIGA_MAC_VER_04,
108 RTL_GIGA_MAC_VER_05,
109 RTL_GIGA_MAC_VER_06,
110 RTL_GIGA_MAC_VER_07,
111 RTL_GIGA_MAC_VER_08,
112 RTL_GIGA_MAC_VER_09,
113 RTL_GIGA_MAC_VER_10,
114 RTL_GIGA_MAC_VER_11,
115 RTL_GIGA_MAC_VER_12,
116 RTL_GIGA_MAC_VER_13,
117 RTL_GIGA_MAC_VER_14,
118 RTL_GIGA_MAC_VER_15,
119 RTL_GIGA_MAC_VER_16,
120 RTL_GIGA_MAC_VER_17,
121 RTL_GIGA_MAC_VER_18,
122 RTL_GIGA_MAC_VER_19,
123 RTL_GIGA_MAC_VER_20,
124 RTL_GIGA_MAC_VER_21,
125 RTL_GIGA_MAC_VER_22,
126 RTL_GIGA_MAC_VER_23,
127 RTL_GIGA_MAC_VER_24,
128 RTL_GIGA_MAC_VER_25,
129 RTL_GIGA_MAC_VER_26,
130 RTL_GIGA_MAC_VER_27,
131 RTL_GIGA_MAC_VER_28,
132 RTL_GIGA_MAC_VER_29,
133 RTL_GIGA_MAC_VER_30,
134 RTL_GIGA_MAC_VER_31,
135 RTL_GIGA_MAC_VER_32,
136 RTL_GIGA_MAC_VER_33,
137 RTL_GIGA_MAC_VER_34,
138 RTL_GIGA_MAC_VER_35,
139 RTL_GIGA_MAC_VER_36,
140 RTL_GIGA_MAC_NONE = 0xff,
141 };
142
143 enum rtl_tx_desc_version {
144 RTL_TD_0 = 0,
145 RTL_TD_1 = 1,
146 };
147
148 #define JUMBO_1K ETH_DATA_LEN
149 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
150 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
151 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
152 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
153
154 #define _R(NAME,TD,FW,SZ,B) { \
155 .name = NAME, \
156 .txd_version = TD, \
157 .fw_name = FW, \
158 .jumbo_max = SZ, \
159 .jumbo_tx_csum = B \
160 }
161
162 static const struct {
163 const char *name;
164 enum rtl_tx_desc_version txd_version;
165 const char *fw_name;
166 u16 jumbo_max;
167 bool jumbo_tx_csum;
168 } rtl_chip_infos[] = {
169 /* PCI devices. */
170 [RTL_GIGA_MAC_VER_01] =
171 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
172 [RTL_GIGA_MAC_VER_02] =
173 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
174 [RTL_GIGA_MAC_VER_03] =
175 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
176 [RTL_GIGA_MAC_VER_04] =
177 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
178 [RTL_GIGA_MAC_VER_05] =
179 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
180 [RTL_GIGA_MAC_VER_06] =
181 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
182 /* PCI-E devices. */
183 [RTL_GIGA_MAC_VER_07] =
184 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
185 [RTL_GIGA_MAC_VER_08] =
186 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
187 [RTL_GIGA_MAC_VER_09] =
188 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
189 [RTL_GIGA_MAC_VER_10] =
190 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
191 [RTL_GIGA_MAC_VER_11] =
192 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
193 [RTL_GIGA_MAC_VER_12] =
194 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
195 [RTL_GIGA_MAC_VER_13] =
196 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
197 [RTL_GIGA_MAC_VER_14] =
198 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
199 [RTL_GIGA_MAC_VER_15] =
200 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
201 [RTL_GIGA_MAC_VER_16] =
202 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
203 [RTL_GIGA_MAC_VER_17] =
204 _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false),
205 [RTL_GIGA_MAC_VER_18] =
206 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
207 [RTL_GIGA_MAC_VER_19] =
208 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
209 [RTL_GIGA_MAC_VER_20] =
210 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
211 [RTL_GIGA_MAC_VER_21] =
212 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
213 [RTL_GIGA_MAC_VER_22] =
214 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
215 [RTL_GIGA_MAC_VER_23] =
216 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
217 [RTL_GIGA_MAC_VER_24] =
218 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
219 [RTL_GIGA_MAC_VER_25] =
220 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
221 JUMBO_9K, false),
222 [RTL_GIGA_MAC_VER_26] =
223 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
224 JUMBO_9K, false),
225 [RTL_GIGA_MAC_VER_27] =
226 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
227 [RTL_GIGA_MAC_VER_28] =
228 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
229 [RTL_GIGA_MAC_VER_29] =
230 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
231 JUMBO_1K, true),
232 [RTL_GIGA_MAC_VER_30] =
233 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
234 JUMBO_1K, true),
235 [RTL_GIGA_MAC_VER_31] =
236 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
237 [RTL_GIGA_MAC_VER_32] =
238 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
239 JUMBO_9K, false),
240 [RTL_GIGA_MAC_VER_33] =
241 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
242 JUMBO_9K, false),
243 [RTL_GIGA_MAC_VER_34] =
244 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
245 JUMBO_9K, false),
246 [RTL_GIGA_MAC_VER_35] =
247 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
248 JUMBO_9K, false),
249 [RTL_GIGA_MAC_VER_36] =
250 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
251 JUMBO_9K, false),
252 };
253 #undef _R
254
255 enum cfg_version {
256 RTL_CFG_0 = 0x00,
257 RTL_CFG_1,
258 RTL_CFG_2
259 };
260
261 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
262 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
263 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
264 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
265 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
266 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
267 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
268 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
269 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
270 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
271 { PCI_VENDOR_ID_LINKSYS, 0x1032,
272 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
273 { 0x0001, 0x8168,
274 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
275 {0,},
276 };
277
278 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
279
280 static int rx_buf_sz = 16383;
281 static int use_dac;
282 static struct {
283 u32 msg_enable;
284 } debug = { -1 };
285
286 enum rtl_registers {
287 MAC0 = 0, /* Ethernet hardware address. */
288 MAC4 = 4,
289 MAR0 = 8, /* Multicast filter. */
290 CounterAddrLow = 0x10,
291 CounterAddrHigh = 0x14,
292 TxDescStartAddrLow = 0x20,
293 TxDescStartAddrHigh = 0x24,
294 TxHDescStartAddrLow = 0x28,
295 TxHDescStartAddrHigh = 0x2c,
296 FLASH = 0x30,
297 ERSR = 0x36,
298 ChipCmd = 0x37,
299 TxPoll = 0x38,
300 IntrMask = 0x3c,
301 IntrStatus = 0x3e,
302
303 TxConfig = 0x40,
304 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
305 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
306
307 RxConfig = 0x44,
308 #define RX128_INT_EN (1 << 15) /* 8111c and later */
309 #define RX_MULTI_EN (1 << 14) /* 8111c only */
310 #define RXCFG_FIFO_SHIFT 13
311 /* No threshold before first PCI xfer */
312 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
313 #define RXCFG_DMA_SHIFT 8
314 /* Unlimited maximum PCI burst. */
315 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
316
317 RxMissed = 0x4c,
318 Cfg9346 = 0x50,
319 Config0 = 0x51,
320 Config1 = 0x52,
321 Config2 = 0x53,
322 #define PME_SIGNAL (1 << 5) /* 8168c and later */
323
324 Config3 = 0x54,
325 Config4 = 0x55,
326 Config5 = 0x56,
327 MultiIntr = 0x5c,
328 PHYAR = 0x60,
329 PHYstatus = 0x6c,
330 RxMaxSize = 0xda,
331 CPlusCmd = 0xe0,
332 IntrMitigate = 0xe2,
333 RxDescAddrLow = 0xe4,
334 RxDescAddrHigh = 0xe8,
335 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
336
337 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
338
339 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
340
341 #define TxPacketMax (8064 >> 7)
342 #define EarlySize 0x27
343
344 FuncEvent = 0xf0,
345 FuncEventMask = 0xf4,
346 FuncPresetState = 0xf8,
347 FuncForceEvent = 0xfc,
348 };
349
350 enum rtl8110_registers {
351 TBICSR = 0x64,
352 TBI_ANAR = 0x68,
353 TBI_LPAR = 0x6a,
354 };
355
356 enum rtl8168_8101_registers {
357 CSIDR = 0x64,
358 CSIAR = 0x68,
359 #define CSIAR_FLAG 0x80000000
360 #define CSIAR_WRITE_CMD 0x80000000
361 #define CSIAR_BYTE_ENABLE 0x0f
362 #define CSIAR_BYTE_ENABLE_SHIFT 12
363 #define CSIAR_ADDR_MASK 0x0fff
364 PMCH = 0x6f,
365 EPHYAR = 0x80,
366 #define EPHYAR_FLAG 0x80000000
367 #define EPHYAR_WRITE_CMD 0x80000000
368 #define EPHYAR_REG_MASK 0x1f
369 #define EPHYAR_REG_SHIFT 16
370 #define EPHYAR_DATA_MASK 0xffff
371 DLLPR = 0xd0,
372 #define PFM_EN (1 << 6)
373 DBG_REG = 0xd1,
374 #define FIX_NAK_1 (1 << 4)
375 #define FIX_NAK_2 (1 << 3)
376 TWSI = 0xd2,
377 MCU = 0xd3,
378 #define NOW_IS_OOB (1 << 7)
379 #define EN_NDP (1 << 3)
380 #define EN_OOB_RESET (1 << 2)
381 EFUSEAR = 0xdc,
382 #define EFUSEAR_FLAG 0x80000000
383 #define EFUSEAR_WRITE_CMD 0x80000000
384 #define EFUSEAR_READ_CMD 0x00000000
385 #define EFUSEAR_REG_MASK 0x03ff
386 #define EFUSEAR_REG_SHIFT 8
387 #define EFUSEAR_DATA_MASK 0xff
388 };
389
390 enum rtl8168_registers {
391 LED_FREQ = 0x1a,
392 EEE_LED = 0x1b,
393 ERIDR = 0x70,
394 ERIAR = 0x74,
395 #define ERIAR_FLAG 0x80000000
396 #define ERIAR_WRITE_CMD 0x80000000
397 #define ERIAR_READ_CMD 0x00000000
398 #define ERIAR_ADDR_BYTE_ALIGN 4
399 #define ERIAR_TYPE_SHIFT 16
400 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
401 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
402 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
403 #define ERIAR_MASK_SHIFT 12
404 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
405 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
406 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
407 EPHY_RXER_NUM = 0x7c,
408 OCPDR = 0xb0, /* OCP GPHY access */
409 #define OCPDR_WRITE_CMD 0x80000000
410 #define OCPDR_READ_CMD 0x00000000
411 #define OCPDR_REG_MASK 0x7f
412 #define OCPDR_GPHY_REG_SHIFT 16
413 #define OCPDR_DATA_MASK 0xffff
414 OCPAR = 0xb4,
415 #define OCPAR_FLAG 0x80000000
416 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
417 #define OCPAR_GPHY_READ_CMD 0x0000f060
418 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
419 MISC = 0xf0, /* 8168e only. */
420 #define TXPLA_RST (1 << 29)
421 #define PWM_EN (1 << 22)
422 };
423
424 enum rtl_register_content {
425 /* InterruptStatusBits */
426 SYSErr = 0x8000,
427 PCSTimeout = 0x4000,
428 SWInt = 0x0100,
429 TxDescUnavail = 0x0080,
430 RxFIFOOver = 0x0040,
431 LinkChg = 0x0020,
432 RxOverflow = 0x0010,
433 TxErr = 0x0008,
434 TxOK = 0x0004,
435 RxErr = 0x0002,
436 RxOK = 0x0001,
437
438 /* RxStatusDesc */
439 RxBOVF = (1 << 24),
440 RxFOVF = (1 << 23),
441 RxRWT = (1 << 22),
442 RxRES = (1 << 21),
443 RxRUNT = (1 << 20),
444 RxCRC = (1 << 19),
445
446 /* ChipCmdBits */
447 StopReq = 0x80,
448 CmdReset = 0x10,
449 CmdRxEnb = 0x08,
450 CmdTxEnb = 0x04,
451 RxBufEmpty = 0x01,
452
453 /* TXPoll register p.5 */
454 HPQ = 0x80, /* Poll cmd on the high prio queue */
455 NPQ = 0x40, /* Poll cmd on the low prio queue */
456 FSWInt = 0x01, /* Forced software interrupt */
457
458 /* Cfg9346Bits */
459 Cfg9346_Lock = 0x00,
460 Cfg9346_Unlock = 0xc0,
461
462 /* rx_mode_bits */
463 AcceptErr = 0x20,
464 AcceptRunt = 0x10,
465 AcceptBroadcast = 0x08,
466 AcceptMulticast = 0x04,
467 AcceptMyPhys = 0x02,
468 AcceptAllPhys = 0x01,
469 #define RX_CONFIG_ACCEPT_MASK 0x3f
470
471 /* TxConfigBits */
472 TxInterFrameGapShift = 24,
473 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
474
475 /* Config1 register p.24 */
476 LEDS1 = (1 << 7),
477 LEDS0 = (1 << 6),
478 Speed_down = (1 << 4),
479 MEMMAP = (1 << 3),
480 IOMAP = (1 << 2),
481 VPD = (1 << 1),
482 PMEnable = (1 << 0), /* Power Management Enable */
483
484 /* Config2 register p. 25 */
485 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
486 PCI_Clock_66MHz = 0x01,
487 PCI_Clock_33MHz = 0x00,
488
489 /* Config3 register p.25 */
490 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
491 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
492 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
493 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
494
495 /* Config4 register */
496 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
497
498 /* Config5 register p.27 */
499 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
500 MWF = (1 << 5), /* Accept Multicast wakeup frame */
501 UWF = (1 << 4), /* Accept Unicast wakeup frame */
502 Spi_en = (1 << 3),
503 LanWake = (1 << 1), /* LanWake enable/disable */
504 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
505
506 /* TBICSR p.28 */
507 TBIReset = 0x80000000,
508 TBILoopback = 0x40000000,
509 TBINwEnable = 0x20000000,
510 TBINwRestart = 0x10000000,
511 TBILinkOk = 0x02000000,
512 TBINwComplete = 0x01000000,
513
514 /* CPlusCmd p.31 */
515 EnableBist = (1 << 15), // 8168 8101
516 Mac_dbgo_oe = (1 << 14), // 8168 8101
517 Normal_mode = (1 << 13), // unused
518 Force_half_dup = (1 << 12), // 8168 8101
519 Force_rxflow_en = (1 << 11), // 8168 8101
520 Force_txflow_en = (1 << 10), // 8168 8101
521 Cxpl_dbg_sel = (1 << 9), // 8168 8101
522 ASF = (1 << 8), // 8168 8101
523 PktCntrDisable = (1 << 7), // 8168 8101
524 Mac_dbgo_sel = 0x001c, // 8168
525 RxVlan = (1 << 6),
526 RxChkSum = (1 << 5),
527 PCIDAC = (1 << 4),
528 PCIMulRW = (1 << 3),
529 INTT_0 = 0x0000, // 8168
530 INTT_1 = 0x0001, // 8168
531 INTT_2 = 0x0002, // 8168
532 INTT_3 = 0x0003, // 8168
533
534 /* rtl8169_PHYstatus */
535 TBI_Enable = 0x80,
536 TxFlowCtrl = 0x40,
537 RxFlowCtrl = 0x20,
538 _1000bpsF = 0x10,
539 _100bps = 0x08,
540 _10bps = 0x04,
541 LinkStatus = 0x02,
542 FullDup = 0x01,
543
544 /* _TBICSRBit */
545 TBILinkOK = 0x02000000,
546
547 /* DumpCounterCommand */
548 CounterDump = 0x8,
549 };
550
551 enum rtl_desc_bit {
552 /* First doubleword. */
553 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
554 RingEnd = (1 << 30), /* End of descriptor ring */
555 FirstFrag = (1 << 29), /* First segment of a packet */
556 LastFrag = (1 << 28), /* Final segment of a packet */
557 };
558
559 /* Generic case. */
560 enum rtl_tx_desc_bit {
561 /* First doubleword. */
562 TD_LSO = (1 << 27), /* Large Send Offload */
563 #define TD_MSS_MAX 0x07ffu /* MSS value */
564
565 /* Second doubleword. */
566 TxVlanTag = (1 << 17), /* Add VLAN tag */
567 };
568
569 /* 8169, 8168b and 810x except 8102e. */
570 enum rtl_tx_desc_bit_0 {
571 /* First doubleword. */
572 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
573 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
574 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
575 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
576 };
577
578 /* 8102e, 8168c and beyond. */
579 enum rtl_tx_desc_bit_1 {
580 /* Second doubleword. */
581 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
582 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
583 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
584 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
585 };
586
587 static const struct rtl_tx_desc_info {
588 struct {
589 u32 udp;
590 u32 tcp;
591 } checksum;
592 u16 mss_shift;
593 u16 opts_offset;
594 } tx_desc_info [] = {
595 [RTL_TD_0] = {
596 .checksum = {
597 .udp = TD0_IP_CS | TD0_UDP_CS,
598 .tcp = TD0_IP_CS | TD0_TCP_CS
599 },
600 .mss_shift = TD0_MSS_SHIFT,
601 .opts_offset = 0
602 },
603 [RTL_TD_1] = {
604 .checksum = {
605 .udp = TD1_IP_CS | TD1_UDP_CS,
606 .tcp = TD1_IP_CS | TD1_TCP_CS
607 },
608 .mss_shift = TD1_MSS_SHIFT,
609 .opts_offset = 1
610 }
611 };
612
613 enum rtl_rx_desc_bit {
614 /* Rx private */
615 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
616 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
617
618 #define RxProtoUDP (PID1)
619 #define RxProtoTCP (PID0)
620 #define RxProtoIP (PID1 | PID0)
621 #define RxProtoMask RxProtoIP
622
623 IPFail = (1 << 16), /* IP checksum failed */
624 UDPFail = (1 << 15), /* UDP/IP checksum failed */
625 TCPFail = (1 << 14), /* TCP/IP checksum failed */
626 RxVlanTag = (1 << 16), /* VLAN tag available */
627 };
628
629 #define RsvdMask 0x3fffc000
630
631 struct TxDesc {
632 __le32 opts1;
633 __le32 opts2;
634 __le64 addr;
635 };
636
637 struct RxDesc {
638 __le32 opts1;
639 __le32 opts2;
640 __le64 addr;
641 };
642
643 struct ring_info {
644 struct sk_buff *skb;
645 u32 len;
646 u8 __pad[sizeof(void *) - sizeof(u32)];
647 };
648
649 enum features {
650 RTL_FEATURE_WOL = (1 << 0),
651 RTL_FEATURE_MSI = (1 << 1),
652 RTL_FEATURE_GMII = (1 << 2),
653 };
654
655 struct rtl8169_counters {
656 __le64 tx_packets;
657 __le64 rx_packets;
658 __le64 tx_errors;
659 __le32 rx_errors;
660 __le16 rx_missed;
661 __le16 align_errors;
662 __le32 tx_one_collision;
663 __le32 tx_multi_collision;
664 __le64 rx_unicast;
665 __le64 rx_broadcast;
666 __le32 rx_multicast;
667 __le16 tx_aborted;
668 __le16 tx_underun;
669 };
670
671 enum rtl_flag {
672 RTL_FLAG_TASK_ENABLED,
673 RTL_FLAG_TASK_SLOW_PENDING,
674 RTL_FLAG_TASK_RESET_PENDING,
675 RTL_FLAG_TASK_PHY_PENDING,
676 RTL_FLAG_MAX
677 };
678
679 struct rtl8169_stats {
680 u64 packets;
681 u64 bytes;
682 struct u64_stats_sync syncp;
683 };
684
685 struct rtl8169_private {
686 void __iomem *mmio_addr; /* memory map physical address */
687 struct pci_dev *pci_dev;
688 struct net_device *dev;
689 struct napi_struct napi;
690 u32 msg_enable;
691 u16 txd_version;
692 u16 mac_version;
693 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
694 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
695 u32 dirty_rx;
696 u32 dirty_tx;
697 struct rtl8169_stats rx_stats;
698 struct rtl8169_stats tx_stats;
699 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
700 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
701 dma_addr_t TxPhyAddr;
702 dma_addr_t RxPhyAddr;
703 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
704 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
705 struct timer_list timer;
706 u16 cp_cmd;
707
708 u16 event_slow;
709
710 struct mdio_ops {
711 void (*write)(void __iomem *, int, int);
712 int (*read)(void __iomem *, int);
713 } mdio_ops;
714
715 struct pll_power_ops {
716 void (*down)(struct rtl8169_private *);
717 void (*up)(struct rtl8169_private *);
718 } pll_power_ops;
719
720 struct jumbo_ops {
721 void (*enable)(struct rtl8169_private *);
722 void (*disable)(struct rtl8169_private *);
723 } jumbo_ops;
724
725 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
726 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
727 void (*phy_reset_enable)(struct rtl8169_private *tp);
728 void (*hw_start)(struct net_device *);
729 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
730 unsigned int (*link_ok)(void __iomem *);
731 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
732
733 struct {
734 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
735 struct mutex mutex;
736 struct work_struct work;
737 } wk;
738
739 unsigned features;
740
741 struct mii_if_info mii;
742 struct rtl8169_counters counters;
743 u32 saved_wolopts;
744 u32 opts1_mask;
745
746 struct rtl_fw {
747 const struct firmware *fw;
748
749 #define RTL_VER_SIZE 32
750
751 char version[RTL_VER_SIZE];
752
753 struct rtl_fw_phy_action {
754 __le32 *code;
755 size_t size;
756 } phy_action;
757 } *rtl_fw;
758 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
759 };
760
761 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
762 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
763 module_param(use_dac, int, 0);
764 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
765 module_param_named(debug, debug.msg_enable, int, 0);
766 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
767 MODULE_LICENSE("GPL");
768 MODULE_VERSION(RTL8169_VERSION);
769 MODULE_FIRMWARE(FIRMWARE_8168D_1);
770 MODULE_FIRMWARE(FIRMWARE_8168D_2);
771 MODULE_FIRMWARE(FIRMWARE_8168E_1);
772 MODULE_FIRMWARE(FIRMWARE_8168E_2);
773 MODULE_FIRMWARE(FIRMWARE_8168E_3);
774 MODULE_FIRMWARE(FIRMWARE_8105E_1);
775 MODULE_FIRMWARE(FIRMWARE_8168F_1);
776 MODULE_FIRMWARE(FIRMWARE_8168F_2);
777
778 static void rtl_lock_work(struct rtl8169_private *tp)
779 {
780 mutex_lock(&tp->wk.mutex);
781 }
782
783 static void rtl_unlock_work(struct rtl8169_private *tp)
784 {
785 mutex_unlock(&tp->wk.mutex);
786 }
787
788 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
789 {
790 int cap = pci_pcie_cap(pdev);
791
792 if (cap) {
793 u16 ctl;
794
795 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
796 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
797 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
798 }
799 }
800
801 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
802 {
803 void __iomem *ioaddr = tp->mmio_addr;
804 int i;
805
806 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
807 for (i = 0; i < 20; i++) {
808 udelay(100);
809 if (RTL_R32(OCPAR) & OCPAR_FLAG)
810 break;
811 }
812 return RTL_R32(OCPDR);
813 }
814
815 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
816 {
817 void __iomem *ioaddr = tp->mmio_addr;
818 int i;
819
820 RTL_W32(OCPDR, data);
821 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
822 for (i = 0; i < 20; i++) {
823 udelay(100);
824 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
825 break;
826 }
827 }
828
829 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
830 {
831 void __iomem *ioaddr = tp->mmio_addr;
832 int i;
833
834 RTL_W8(ERIDR, cmd);
835 RTL_W32(ERIAR, 0x800010e8);
836 msleep(2);
837 for (i = 0; i < 5; i++) {
838 udelay(100);
839 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
840 break;
841 }
842
843 ocp_write(tp, 0x1, 0x30, 0x00000001);
844 }
845
846 #define OOB_CMD_RESET 0x00
847 #define OOB_CMD_DRIVER_START 0x05
848 #define OOB_CMD_DRIVER_STOP 0x06
849
850 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
851 {
852 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
853 }
854
855 static void rtl8168_driver_start(struct rtl8169_private *tp)
856 {
857 u16 reg;
858 int i;
859
860 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
861
862 reg = rtl8168_get_ocp_reg(tp);
863
864 for (i = 0; i < 10; i++) {
865 msleep(10);
866 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
867 break;
868 }
869 }
870
871 static void rtl8168_driver_stop(struct rtl8169_private *tp)
872 {
873 u16 reg;
874 int i;
875
876 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
877
878 reg = rtl8168_get_ocp_reg(tp);
879
880 for (i = 0; i < 10; i++) {
881 msleep(10);
882 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
883 break;
884 }
885 }
886
887 static int r8168dp_check_dash(struct rtl8169_private *tp)
888 {
889 u16 reg = rtl8168_get_ocp_reg(tp);
890
891 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
892 }
893
894 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
895 {
896 int i;
897
898 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
899
900 for (i = 20; i > 0; i--) {
901 /*
902 * Check if the RTL8169 has completed writing to the specified
903 * MII register.
904 */
905 if (!(RTL_R32(PHYAR) & 0x80000000))
906 break;
907 udelay(25);
908 }
909 /*
910 * According to hardware specs a 20us delay is required after write
911 * complete indication, but before sending next command.
912 */
913 udelay(20);
914 }
915
916 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
917 {
918 int i, value = -1;
919
920 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
921
922 for (i = 20; i > 0; i--) {
923 /*
924 * Check if the RTL8169 has completed retrieving data from
925 * the specified MII register.
926 */
927 if (RTL_R32(PHYAR) & 0x80000000) {
928 value = RTL_R32(PHYAR) & 0xffff;
929 break;
930 }
931 udelay(25);
932 }
933 /*
934 * According to hardware specs a 20us delay is required after read
935 * complete indication, but before sending next command.
936 */
937 udelay(20);
938
939 return value;
940 }
941
942 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
943 {
944 int i;
945
946 RTL_W32(OCPDR, data |
947 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
948 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
949 RTL_W32(EPHY_RXER_NUM, 0);
950
951 for (i = 0; i < 100; i++) {
952 mdelay(1);
953 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
954 break;
955 }
956 }
957
958 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
959 {
960 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
961 (value & OCPDR_DATA_MASK));
962 }
963
964 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
965 {
966 int i;
967
968 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
969
970 mdelay(1);
971 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
972 RTL_W32(EPHY_RXER_NUM, 0);
973
974 for (i = 0; i < 100; i++) {
975 mdelay(1);
976 if (RTL_R32(OCPAR) & OCPAR_FLAG)
977 break;
978 }
979
980 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
981 }
982
983 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
984
985 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
986 {
987 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
988 }
989
990 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
991 {
992 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
993 }
994
995 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
996 {
997 r8168dp_2_mdio_start(ioaddr);
998
999 r8169_mdio_write(ioaddr, reg_addr, value);
1000
1001 r8168dp_2_mdio_stop(ioaddr);
1002 }
1003
1004 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
1005 {
1006 int value;
1007
1008 r8168dp_2_mdio_start(ioaddr);
1009
1010 value = r8169_mdio_read(ioaddr, reg_addr);
1011
1012 r8168dp_2_mdio_stop(ioaddr);
1013
1014 return value;
1015 }
1016
1017 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1018 {
1019 tp->mdio_ops.write(tp->mmio_addr, location, val);
1020 }
1021
1022 static int rtl_readphy(struct rtl8169_private *tp, int location)
1023 {
1024 return tp->mdio_ops.read(tp->mmio_addr, location);
1025 }
1026
1027 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1028 {
1029 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1030 }
1031
1032 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1033 {
1034 int val;
1035
1036 val = rtl_readphy(tp, reg_addr);
1037 rtl_writephy(tp, reg_addr, (val | p) & ~m);
1038 }
1039
1040 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1041 int val)
1042 {
1043 struct rtl8169_private *tp = netdev_priv(dev);
1044
1045 rtl_writephy(tp, location, val);
1046 }
1047
1048 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1049 {
1050 struct rtl8169_private *tp = netdev_priv(dev);
1051
1052 return rtl_readphy(tp, location);
1053 }
1054
1055 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
1056 {
1057 unsigned int i;
1058
1059 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1060 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1061
1062 for (i = 0; i < 100; i++) {
1063 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
1064 break;
1065 udelay(10);
1066 }
1067 }
1068
1069 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1070 {
1071 u16 value = 0xffff;
1072 unsigned int i;
1073
1074 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1075
1076 for (i = 0; i < 100; i++) {
1077 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1078 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1079 break;
1080 }
1081 udelay(10);
1082 }
1083
1084 return value;
1085 }
1086
1087 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1088 {
1089 unsigned int i;
1090
1091 RTL_W32(CSIDR, value);
1092 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1093 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1094
1095 for (i = 0; i < 100; i++) {
1096 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1097 break;
1098 udelay(10);
1099 }
1100 }
1101
1102 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1103 {
1104 u32 value = ~0x00;
1105 unsigned int i;
1106
1107 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1108 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1109
1110 for (i = 0; i < 100; i++) {
1111 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1112 value = RTL_R32(CSIDR);
1113 break;
1114 }
1115 udelay(10);
1116 }
1117
1118 return value;
1119 }
1120
1121 static
1122 void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1123 {
1124 unsigned int i;
1125
1126 BUG_ON((addr & 3) || (mask == 0));
1127 RTL_W32(ERIDR, val);
1128 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1129
1130 for (i = 0; i < 100; i++) {
1131 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1132 break;
1133 udelay(100);
1134 }
1135 }
1136
1137 static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1138 {
1139 u32 value = ~0x00;
1140 unsigned int i;
1141
1142 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1143
1144 for (i = 0; i < 100; i++) {
1145 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1146 value = RTL_R32(ERIDR);
1147 break;
1148 }
1149 udelay(100);
1150 }
1151
1152 return value;
1153 }
1154
1155 static void
1156 rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1157 {
1158 u32 val;
1159
1160 val = rtl_eri_read(ioaddr, addr, type);
1161 rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1162 }
1163
1164 struct exgmac_reg {
1165 u16 addr;
1166 u16 mask;
1167 u32 val;
1168 };
1169
1170 static void rtl_write_exgmac_batch(void __iomem *ioaddr,
1171 const struct exgmac_reg *r, int len)
1172 {
1173 while (len-- > 0) {
1174 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1175 r++;
1176 }
1177 }
1178
1179 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1180 {
1181 u8 value = 0xff;
1182 unsigned int i;
1183
1184 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1185
1186 for (i = 0; i < 300; i++) {
1187 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1188 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1189 break;
1190 }
1191 udelay(100);
1192 }
1193
1194 return value;
1195 }
1196
1197 static u16 rtl_get_events(struct rtl8169_private *tp)
1198 {
1199 void __iomem *ioaddr = tp->mmio_addr;
1200
1201 return RTL_R16(IntrStatus);
1202 }
1203
1204 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1205 {
1206 void __iomem *ioaddr = tp->mmio_addr;
1207
1208 RTL_W16(IntrStatus, bits);
1209 mmiowb();
1210 }
1211
1212 static void rtl_irq_disable(struct rtl8169_private *tp)
1213 {
1214 void __iomem *ioaddr = tp->mmio_addr;
1215
1216 RTL_W16(IntrMask, 0);
1217 mmiowb();
1218 }
1219
1220 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1221 {
1222 void __iomem *ioaddr = tp->mmio_addr;
1223
1224 RTL_W16(IntrMask, bits);
1225 }
1226
1227 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1228 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1229 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1230
1231 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1232 {
1233 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1234 }
1235
1236 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1237 {
1238 void __iomem *ioaddr = tp->mmio_addr;
1239
1240 rtl_irq_disable(tp);
1241 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1242 RTL_R8(ChipCmd);
1243 }
1244
1245 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1246 {
1247 void __iomem *ioaddr = tp->mmio_addr;
1248
1249 return RTL_R32(TBICSR) & TBIReset;
1250 }
1251
1252 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1253 {
1254 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1255 }
1256
1257 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1258 {
1259 return RTL_R32(TBICSR) & TBILinkOk;
1260 }
1261
1262 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1263 {
1264 return RTL_R8(PHYstatus) & LinkStatus;
1265 }
1266
1267 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1268 {
1269 void __iomem *ioaddr = tp->mmio_addr;
1270
1271 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1272 }
1273
1274 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1275 {
1276 unsigned int val;
1277
1278 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1279 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1280 }
1281
1282 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1283 {
1284 void __iomem *ioaddr = tp->mmio_addr;
1285 struct net_device *dev = tp->dev;
1286
1287 if (!netif_running(dev))
1288 return;
1289
1290 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1291 if (RTL_R8(PHYstatus) & _1000bpsF) {
1292 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1293 0x00000011, ERIAR_EXGMAC);
1294 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1295 0x00000005, ERIAR_EXGMAC);
1296 } else if (RTL_R8(PHYstatus) & _100bps) {
1297 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1298 0x0000001f, ERIAR_EXGMAC);
1299 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1300 0x00000005, ERIAR_EXGMAC);
1301 } else {
1302 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1303 0x0000001f, ERIAR_EXGMAC);
1304 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1305 0x0000003f, ERIAR_EXGMAC);
1306 }
1307 /* Reset packet filter */
1308 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1309 ERIAR_EXGMAC);
1310 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1311 ERIAR_EXGMAC);
1312 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1313 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1314 if (RTL_R8(PHYstatus) & _1000bpsF) {
1315 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1316 0x00000011, ERIAR_EXGMAC);
1317 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1318 0x00000005, ERIAR_EXGMAC);
1319 } else {
1320 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1321 0x0000001f, ERIAR_EXGMAC);
1322 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1323 0x0000003f, ERIAR_EXGMAC);
1324 }
1325 }
1326 }
1327
1328 static void __rtl8169_check_link_status(struct net_device *dev,
1329 struct rtl8169_private *tp,
1330 void __iomem *ioaddr, bool pm)
1331 {
1332 if (tp->link_ok(ioaddr)) {
1333 rtl_link_chg_patch(tp);
1334 /* This is to cancel a scheduled suspend if there's one. */
1335 if (pm)
1336 pm_request_resume(&tp->pci_dev->dev);
1337 netif_carrier_on(dev);
1338 if (net_ratelimit())
1339 netif_info(tp, ifup, dev, "link up\n");
1340 } else {
1341 netif_carrier_off(dev);
1342 netif_info(tp, ifdown, dev, "link down\n");
1343 if (pm)
1344 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1345 }
1346 }
1347
1348 static void rtl8169_check_link_status(struct net_device *dev,
1349 struct rtl8169_private *tp,
1350 void __iomem *ioaddr)
1351 {
1352 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1353 }
1354
1355 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1356
1357 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1358 {
1359 void __iomem *ioaddr = tp->mmio_addr;
1360 u8 options;
1361 u32 wolopts = 0;
1362
1363 options = RTL_R8(Config1);
1364 if (!(options & PMEnable))
1365 return 0;
1366
1367 options = RTL_R8(Config3);
1368 if (options & LinkUp)
1369 wolopts |= WAKE_PHY;
1370 if (options & MagicPacket)
1371 wolopts |= WAKE_MAGIC;
1372
1373 options = RTL_R8(Config5);
1374 if (options & UWF)
1375 wolopts |= WAKE_UCAST;
1376 if (options & BWF)
1377 wolopts |= WAKE_BCAST;
1378 if (options & MWF)
1379 wolopts |= WAKE_MCAST;
1380
1381 return wolopts;
1382 }
1383
1384 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1385 {
1386 struct rtl8169_private *tp = netdev_priv(dev);
1387
1388 rtl_lock_work(tp);
1389
1390 wol->supported = WAKE_ANY;
1391 wol->wolopts = __rtl8169_get_wol(tp);
1392
1393 rtl_unlock_work(tp);
1394 }
1395
1396 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1397 {
1398 void __iomem *ioaddr = tp->mmio_addr;
1399 unsigned int i;
1400 static const struct {
1401 u32 opt;
1402 u16 reg;
1403 u8 mask;
1404 } cfg[] = {
1405 { WAKE_PHY, Config3, LinkUp },
1406 { WAKE_MAGIC, Config3, MagicPacket },
1407 { WAKE_UCAST, Config5, UWF },
1408 { WAKE_BCAST, Config5, BWF },
1409 { WAKE_MCAST, Config5, MWF },
1410 { WAKE_ANY, Config5, LanWake }
1411 };
1412 u8 options;
1413
1414 RTL_W8(Cfg9346, Cfg9346_Unlock);
1415
1416 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1417 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1418 if (wolopts & cfg[i].opt)
1419 options |= cfg[i].mask;
1420 RTL_W8(cfg[i].reg, options);
1421 }
1422
1423 switch (tp->mac_version) {
1424 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1425 options = RTL_R8(Config1) & ~PMEnable;
1426 if (wolopts)
1427 options |= PMEnable;
1428 RTL_W8(Config1, options);
1429 break;
1430 default:
1431 options = RTL_R8(Config2) & ~PME_SIGNAL;
1432 if (wolopts)
1433 options |= PME_SIGNAL;
1434 RTL_W8(Config2, options);
1435 break;
1436 }
1437
1438 RTL_W8(Cfg9346, Cfg9346_Lock);
1439 }
1440
1441 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1442 {
1443 struct rtl8169_private *tp = netdev_priv(dev);
1444
1445 rtl_lock_work(tp);
1446
1447 if (wol->wolopts)
1448 tp->features |= RTL_FEATURE_WOL;
1449 else
1450 tp->features &= ~RTL_FEATURE_WOL;
1451 __rtl8169_set_wol(tp, wol->wolopts);
1452
1453 rtl_unlock_work(tp);
1454
1455 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1456
1457 return 0;
1458 }
1459
1460 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1461 {
1462 return rtl_chip_infos[tp->mac_version].fw_name;
1463 }
1464
1465 static void rtl8169_get_drvinfo(struct net_device *dev,
1466 struct ethtool_drvinfo *info)
1467 {
1468 struct rtl8169_private *tp = netdev_priv(dev);
1469 struct rtl_fw *rtl_fw = tp->rtl_fw;
1470
1471 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1472 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1473 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1474 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1475 if (!IS_ERR_OR_NULL(rtl_fw))
1476 strlcpy(info->fw_version, rtl_fw->version,
1477 sizeof(info->fw_version));
1478 }
1479
1480 static int rtl8169_get_regs_len(struct net_device *dev)
1481 {
1482 return R8169_REGS_SIZE;
1483 }
1484
1485 static int rtl8169_set_speed_tbi(struct net_device *dev,
1486 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1487 {
1488 struct rtl8169_private *tp = netdev_priv(dev);
1489 void __iomem *ioaddr = tp->mmio_addr;
1490 int ret = 0;
1491 u32 reg;
1492
1493 reg = RTL_R32(TBICSR);
1494 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1495 (duplex == DUPLEX_FULL)) {
1496 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1497 } else if (autoneg == AUTONEG_ENABLE)
1498 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1499 else {
1500 netif_warn(tp, link, dev,
1501 "incorrect speed setting refused in TBI mode\n");
1502 ret = -EOPNOTSUPP;
1503 }
1504
1505 return ret;
1506 }
1507
1508 static int rtl8169_set_speed_xmii(struct net_device *dev,
1509 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1510 {
1511 struct rtl8169_private *tp = netdev_priv(dev);
1512 int giga_ctrl, bmcr;
1513 int rc = -EINVAL;
1514
1515 rtl_writephy(tp, 0x1f, 0x0000);
1516
1517 if (autoneg == AUTONEG_ENABLE) {
1518 int auto_nego;
1519
1520 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1521 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1522 ADVERTISE_100HALF | ADVERTISE_100FULL);
1523
1524 if (adv & ADVERTISED_10baseT_Half)
1525 auto_nego |= ADVERTISE_10HALF;
1526 if (adv & ADVERTISED_10baseT_Full)
1527 auto_nego |= ADVERTISE_10FULL;
1528 if (adv & ADVERTISED_100baseT_Half)
1529 auto_nego |= ADVERTISE_100HALF;
1530 if (adv & ADVERTISED_100baseT_Full)
1531 auto_nego |= ADVERTISE_100FULL;
1532
1533 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1534
1535 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1536 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1537
1538 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1539 if (tp->mii.supports_gmii) {
1540 if (adv & ADVERTISED_1000baseT_Half)
1541 giga_ctrl |= ADVERTISE_1000HALF;
1542 if (adv & ADVERTISED_1000baseT_Full)
1543 giga_ctrl |= ADVERTISE_1000FULL;
1544 } else if (adv & (ADVERTISED_1000baseT_Half |
1545 ADVERTISED_1000baseT_Full)) {
1546 netif_info(tp, link, dev,
1547 "PHY does not support 1000Mbps\n");
1548 goto out;
1549 }
1550
1551 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1552
1553 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1554 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1555 } else {
1556 giga_ctrl = 0;
1557
1558 if (speed == SPEED_10)
1559 bmcr = 0;
1560 else if (speed == SPEED_100)
1561 bmcr = BMCR_SPEED100;
1562 else
1563 goto out;
1564
1565 if (duplex == DUPLEX_FULL)
1566 bmcr |= BMCR_FULLDPLX;
1567 }
1568
1569 rtl_writephy(tp, MII_BMCR, bmcr);
1570
1571 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1572 tp->mac_version == RTL_GIGA_MAC_VER_03) {
1573 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1574 rtl_writephy(tp, 0x17, 0x2138);
1575 rtl_writephy(tp, 0x0e, 0x0260);
1576 } else {
1577 rtl_writephy(tp, 0x17, 0x2108);
1578 rtl_writephy(tp, 0x0e, 0x0000);
1579 }
1580 }
1581
1582 rc = 0;
1583 out:
1584 return rc;
1585 }
1586
1587 static int rtl8169_set_speed(struct net_device *dev,
1588 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1589 {
1590 struct rtl8169_private *tp = netdev_priv(dev);
1591 int ret;
1592
1593 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1594 if (ret < 0)
1595 goto out;
1596
1597 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1598 (advertising & ADVERTISED_1000baseT_Full)) {
1599 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1600 }
1601 out:
1602 return ret;
1603 }
1604
1605 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1606 {
1607 struct rtl8169_private *tp = netdev_priv(dev);
1608 int ret;
1609
1610 del_timer_sync(&tp->timer);
1611
1612 rtl_lock_work(tp);
1613 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1614 cmd->duplex, cmd->advertising);
1615 rtl_unlock_work(tp);
1616
1617 return ret;
1618 }
1619
1620 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1621 netdev_features_t features)
1622 {
1623 struct rtl8169_private *tp = netdev_priv(dev);
1624
1625 if (dev->mtu > TD_MSS_MAX)
1626 features &= ~NETIF_F_ALL_TSO;
1627
1628 if (dev->mtu > JUMBO_1K &&
1629 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1630 features &= ~NETIF_F_IP_CSUM;
1631
1632 return features;
1633 }
1634
1635 static void __rtl8169_set_features(struct net_device *dev,
1636 netdev_features_t features)
1637 {
1638 struct rtl8169_private *tp = netdev_priv(dev);
1639 netdev_features_t changed = features ^ dev->features;
1640 void __iomem *ioaddr = tp->mmio_addr;
1641
1642 if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
1643 return;
1644
1645 if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
1646 if (features & NETIF_F_RXCSUM)
1647 tp->cp_cmd |= RxChkSum;
1648 else
1649 tp->cp_cmd &= ~RxChkSum;
1650
1651 if (dev->features & NETIF_F_HW_VLAN_RX)
1652 tp->cp_cmd |= RxVlan;
1653 else
1654 tp->cp_cmd &= ~RxVlan;
1655
1656 RTL_W16(CPlusCmd, tp->cp_cmd);
1657 RTL_R16(CPlusCmd);
1658 }
1659 if (changed & NETIF_F_RXALL) {
1660 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1661 if (features & NETIF_F_RXALL)
1662 tmp |= (AcceptErr | AcceptRunt);
1663 RTL_W32(RxConfig, tmp);
1664 }
1665 }
1666
1667 static int rtl8169_set_features(struct net_device *dev,
1668 netdev_features_t features)
1669 {
1670 struct rtl8169_private *tp = netdev_priv(dev);
1671
1672 rtl_lock_work(tp);
1673 __rtl8169_set_features(dev, features);
1674 rtl_unlock_work(tp);
1675
1676 return 0;
1677 }
1678
1679
1680 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1681 struct sk_buff *skb)
1682 {
1683 return (vlan_tx_tag_present(skb)) ?
1684 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1685 }
1686
1687 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1688 {
1689 u32 opts2 = le32_to_cpu(desc->opts2);
1690
1691 if (opts2 & RxVlanTag)
1692 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1693 }
1694
1695 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1696 {
1697 struct rtl8169_private *tp = netdev_priv(dev);
1698 void __iomem *ioaddr = tp->mmio_addr;
1699 u32 status;
1700
1701 cmd->supported =
1702 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1703 cmd->port = PORT_FIBRE;
1704 cmd->transceiver = XCVR_INTERNAL;
1705
1706 status = RTL_R32(TBICSR);
1707 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1708 cmd->autoneg = !!(status & TBINwEnable);
1709
1710 ethtool_cmd_speed_set(cmd, SPEED_1000);
1711 cmd->duplex = DUPLEX_FULL; /* Always set */
1712
1713 return 0;
1714 }
1715
1716 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1717 {
1718 struct rtl8169_private *tp = netdev_priv(dev);
1719
1720 return mii_ethtool_gset(&tp->mii, cmd);
1721 }
1722
1723 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1724 {
1725 struct rtl8169_private *tp = netdev_priv(dev);
1726 int rc;
1727
1728 rtl_lock_work(tp);
1729 rc = tp->get_settings(dev, cmd);
1730 rtl_unlock_work(tp);
1731
1732 return rc;
1733 }
1734
1735 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1736 void *p)
1737 {
1738 struct rtl8169_private *tp = netdev_priv(dev);
1739
1740 if (regs->len > R8169_REGS_SIZE)
1741 regs->len = R8169_REGS_SIZE;
1742
1743 rtl_lock_work(tp);
1744 memcpy_fromio(p, tp->mmio_addr, regs->len);
1745 rtl_unlock_work(tp);
1746 }
1747
1748 static u32 rtl8169_get_msglevel(struct net_device *dev)
1749 {
1750 struct rtl8169_private *tp = netdev_priv(dev);
1751
1752 return tp->msg_enable;
1753 }
1754
1755 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1756 {
1757 struct rtl8169_private *tp = netdev_priv(dev);
1758
1759 tp->msg_enable = value;
1760 }
1761
1762 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1763 "tx_packets",
1764 "rx_packets",
1765 "tx_errors",
1766 "rx_errors",
1767 "rx_missed",
1768 "align_errors",
1769 "tx_single_collisions",
1770 "tx_multi_collisions",
1771 "unicast",
1772 "broadcast",
1773 "multicast",
1774 "tx_aborted",
1775 "tx_underrun",
1776 };
1777
1778 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1779 {
1780 switch (sset) {
1781 case ETH_SS_STATS:
1782 return ARRAY_SIZE(rtl8169_gstrings);
1783 default:
1784 return -EOPNOTSUPP;
1785 }
1786 }
1787
1788 static void rtl8169_update_counters(struct net_device *dev)
1789 {
1790 struct rtl8169_private *tp = netdev_priv(dev);
1791 void __iomem *ioaddr = tp->mmio_addr;
1792 struct device *d = &tp->pci_dev->dev;
1793 struct rtl8169_counters *counters;
1794 dma_addr_t paddr;
1795 u32 cmd;
1796 int wait = 1000;
1797
1798 /*
1799 * Some chips are unable to dump tally counters when the receiver
1800 * is disabled.
1801 */
1802 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1803 return;
1804
1805 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1806 if (!counters)
1807 return;
1808
1809 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1810 cmd = (u64)paddr & DMA_BIT_MASK(32);
1811 RTL_W32(CounterAddrLow, cmd);
1812 RTL_W32(CounterAddrLow, cmd | CounterDump);
1813
1814 while (wait--) {
1815 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1816 memcpy(&tp->counters, counters, sizeof(*counters));
1817 break;
1818 }
1819 udelay(10);
1820 }
1821
1822 RTL_W32(CounterAddrLow, 0);
1823 RTL_W32(CounterAddrHigh, 0);
1824
1825 dma_free_coherent(d, sizeof(*counters), counters, paddr);
1826 }
1827
1828 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1829 struct ethtool_stats *stats, u64 *data)
1830 {
1831 struct rtl8169_private *tp = netdev_priv(dev);
1832
1833 ASSERT_RTNL();
1834
1835 rtl8169_update_counters(dev);
1836
1837 data[0] = le64_to_cpu(tp->counters.tx_packets);
1838 data[1] = le64_to_cpu(tp->counters.rx_packets);
1839 data[2] = le64_to_cpu(tp->counters.tx_errors);
1840 data[3] = le32_to_cpu(tp->counters.rx_errors);
1841 data[4] = le16_to_cpu(tp->counters.rx_missed);
1842 data[5] = le16_to_cpu(tp->counters.align_errors);
1843 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1844 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1845 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1846 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1847 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1848 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1849 data[12] = le16_to_cpu(tp->counters.tx_underun);
1850 }
1851
1852 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1853 {
1854 switch(stringset) {
1855 case ETH_SS_STATS:
1856 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1857 break;
1858 }
1859 }
1860
1861 static const struct ethtool_ops rtl8169_ethtool_ops = {
1862 .get_drvinfo = rtl8169_get_drvinfo,
1863 .get_regs_len = rtl8169_get_regs_len,
1864 .get_link = ethtool_op_get_link,
1865 .get_settings = rtl8169_get_settings,
1866 .set_settings = rtl8169_set_settings,
1867 .get_msglevel = rtl8169_get_msglevel,
1868 .set_msglevel = rtl8169_set_msglevel,
1869 .get_regs = rtl8169_get_regs,
1870 .get_wol = rtl8169_get_wol,
1871 .set_wol = rtl8169_set_wol,
1872 .get_strings = rtl8169_get_strings,
1873 .get_sset_count = rtl8169_get_sset_count,
1874 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1875 };
1876
1877 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1878 struct net_device *dev, u8 default_version)
1879 {
1880 void __iomem *ioaddr = tp->mmio_addr;
1881 /*
1882 * The driver currently handles the 8168Bf and the 8168Be identically
1883 * but they can be identified more specifically through the test below
1884 * if needed:
1885 *
1886 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1887 *
1888 * Same thing for the 8101Eb and the 8101Ec:
1889 *
1890 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1891 */
1892 static const struct rtl_mac_info {
1893 u32 mask;
1894 u32 val;
1895 int mac_version;
1896 } mac_info[] = {
1897 /* 8168F family. */
1898 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
1899 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
1900
1901 /* 8168E family. */
1902 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
1903 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
1904 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
1905 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
1906
1907 /* 8168D family. */
1908 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1909 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1910 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
1911
1912 /* 8168DP family. */
1913 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1914 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
1915 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
1916
1917 /* 8168C family. */
1918 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
1919 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
1920 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1921 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
1922 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1923 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1924 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
1925 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
1926 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
1927
1928 /* 8168B family. */
1929 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1930 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1931 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1932 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1933
1934 /* 8101 family. */
1935 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
1936 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1937 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1938 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
1939 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1940 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1941 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1942 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1943 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1944 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1945 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1946 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1947 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1948 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1949 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1950 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1951 /* FIXME: where did these entries come from ? -- FR */
1952 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1953 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1954
1955 /* 8110 family. */
1956 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1957 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1958 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1959 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1960 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1961 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1962
1963 /* Catch-all */
1964 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1965 };
1966 const struct rtl_mac_info *p = mac_info;
1967 u32 reg;
1968
1969 reg = RTL_R32(TxConfig);
1970 while ((reg & p->mask) != p->val)
1971 p++;
1972 tp->mac_version = p->mac_version;
1973
1974 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1975 netif_notice(tp, probe, dev,
1976 "unknown MAC, using family default\n");
1977 tp->mac_version = default_version;
1978 }
1979 }
1980
1981 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1982 {
1983 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1984 }
1985
1986 struct phy_reg {
1987 u16 reg;
1988 u16 val;
1989 };
1990
1991 static void rtl_writephy_batch(struct rtl8169_private *tp,
1992 const struct phy_reg *regs, int len)
1993 {
1994 while (len-- > 0) {
1995 rtl_writephy(tp, regs->reg, regs->val);
1996 regs++;
1997 }
1998 }
1999
2000 #define PHY_READ 0x00000000
2001 #define PHY_DATA_OR 0x10000000
2002 #define PHY_DATA_AND 0x20000000
2003 #define PHY_BJMPN 0x30000000
2004 #define PHY_READ_EFUSE 0x40000000
2005 #define PHY_READ_MAC_BYTE 0x50000000
2006 #define PHY_WRITE_MAC_BYTE 0x60000000
2007 #define PHY_CLEAR_READCOUNT 0x70000000
2008 #define PHY_WRITE 0x80000000
2009 #define PHY_READCOUNT_EQ_SKIP 0x90000000
2010 #define PHY_COMP_EQ_SKIPN 0xa0000000
2011 #define PHY_COMP_NEQ_SKIPN 0xb0000000
2012 #define PHY_WRITE_PREVIOUS 0xc0000000
2013 #define PHY_SKIPN 0xd0000000
2014 #define PHY_DELAY_MS 0xe0000000
2015 #define PHY_WRITE_ERI_WORD 0xf0000000
2016
2017 struct fw_info {
2018 u32 magic;
2019 char version[RTL_VER_SIZE];
2020 __le32 fw_start;
2021 __le32 fw_len;
2022 u8 chksum;
2023 } __packed;
2024
2025 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2026
2027 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2028 {
2029 const struct firmware *fw = rtl_fw->fw;
2030 struct fw_info *fw_info = (struct fw_info *)fw->data;
2031 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2032 char *version = rtl_fw->version;
2033 bool rc = false;
2034
2035 if (fw->size < FW_OPCODE_SIZE)
2036 goto out;
2037
2038 if (!fw_info->magic) {
2039 size_t i, size, start;
2040 u8 checksum = 0;
2041
2042 if (fw->size < sizeof(*fw_info))
2043 goto out;
2044
2045 for (i = 0; i < fw->size; i++)
2046 checksum += fw->data[i];
2047 if (checksum != 0)
2048 goto out;
2049
2050 start = le32_to_cpu(fw_info->fw_start);
2051 if (start > fw->size)
2052 goto out;
2053
2054 size = le32_to_cpu(fw_info->fw_len);
2055 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2056 goto out;
2057
2058 memcpy(version, fw_info->version, RTL_VER_SIZE);
2059
2060 pa->code = (__le32 *)(fw->data + start);
2061 pa->size = size;
2062 } else {
2063 if (fw->size % FW_OPCODE_SIZE)
2064 goto out;
2065
2066 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2067
2068 pa->code = (__le32 *)fw->data;
2069 pa->size = fw->size / FW_OPCODE_SIZE;
2070 }
2071 version[RTL_VER_SIZE - 1] = 0;
2072
2073 rc = true;
2074 out:
2075 return rc;
2076 }
2077
2078 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2079 struct rtl_fw_phy_action *pa)
2080 {
2081 bool rc = false;
2082 size_t index;
2083
2084 for (index = 0; index < pa->size; index++) {
2085 u32 action = le32_to_cpu(pa->code[index]);
2086 u32 regno = (action & 0x0fff0000) >> 16;
2087
2088 switch(action & 0xf0000000) {
2089 case PHY_READ:
2090 case PHY_DATA_OR:
2091 case PHY_DATA_AND:
2092 case PHY_READ_EFUSE:
2093 case PHY_CLEAR_READCOUNT:
2094 case PHY_WRITE:
2095 case PHY_WRITE_PREVIOUS:
2096 case PHY_DELAY_MS:
2097 break;
2098
2099 case PHY_BJMPN:
2100 if (regno > index) {
2101 netif_err(tp, ifup, tp->dev,
2102 "Out of range of firmware\n");
2103 goto out;
2104 }
2105 break;
2106 case PHY_READCOUNT_EQ_SKIP:
2107 if (index + 2 >= pa->size) {
2108 netif_err(tp, ifup, tp->dev,
2109 "Out of range of firmware\n");
2110 goto out;
2111 }
2112 break;
2113 case PHY_COMP_EQ_SKIPN:
2114 case PHY_COMP_NEQ_SKIPN:
2115 case PHY_SKIPN:
2116 if (index + 1 + regno >= pa->size) {
2117 netif_err(tp, ifup, tp->dev,
2118 "Out of range of firmware\n");
2119 goto out;
2120 }
2121 break;
2122
2123 case PHY_READ_MAC_BYTE:
2124 case PHY_WRITE_MAC_BYTE:
2125 case PHY_WRITE_ERI_WORD:
2126 default:
2127 netif_err(tp, ifup, tp->dev,
2128 "Invalid action 0x%08x\n", action);
2129 goto out;
2130 }
2131 }
2132 rc = true;
2133 out:
2134 return rc;
2135 }
2136
2137 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2138 {
2139 struct net_device *dev = tp->dev;
2140 int rc = -EINVAL;
2141
2142 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2143 netif_err(tp, ifup, dev, "invalid firwmare\n");
2144 goto out;
2145 }
2146
2147 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2148 rc = 0;
2149 out:
2150 return rc;
2151 }
2152
2153 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2154 {
2155 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2156 u32 predata, count;
2157 size_t index;
2158
2159 predata = count = 0;
2160
2161 for (index = 0; index < pa->size; ) {
2162 u32 action = le32_to_cpu(pa->code[index]);
2163 u32 data = action & 0x0000ffff;
2164 u32 regno = (action & 0x0fff0000) >> 16;
2165
2166 if (!action)
2167 break;
2168
2169 switch(action & 0xf0000000) {
2170 case PHY_READ:
2171 predata = rtl_readphy(tp, regno);
2172 count++;
2173 index++;
2174 break;
2175 case PHY_DATA_OR:
2176 predata |= data;
2177 index++;
2178 break;
2179 case PHY_DATA_AND:
2180 predata &= data;
2181 index++;
2182 break;
2183 case PHY_BJMPN:
2184 index -= regno;
2185 break;
2186 case PHY_READ_EFUSE:
2187 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2188 index++;
2189 break;
2190 case PHY_CLEAR_READCOUNT:
2191 count = 0;
2192 index++;
2193 break;
2194 case PHY_WRITE:
2195 rtl_writephy(tp, regno, data);
2196 index++;
2197 break;
2198 case PHY_READCOUNT_EQ_SKIP:
2199 index += (count == data) ? 2 : 1;
2200 break;
2201 case PHY_COMP_EQ_SKIPN:
2202 if (predata == data)
2203 index += regno;
2204 index++;
2205 break;
2206 case PHY_COMP_NEQ_SKIPN:
2207 if (predata != data)
2208 index += regno;
2209 index++;
2210 break;
2211 case PHY_WRITE_PREVIOUS:
2212 rtl_writephy(tp, regno, predata);
2213 index++;
2214 break;
2215 case PHY_SKIPN:
2216 index += regno + 1;
2217 break;
2218 case PHY_DELAY_MS:
2219 mdelay(data);
2220 index++;
2221 break;
2222
2223 case PHY_READ_MAC_BYTE:
2224 case PHY_WRITE_MAC_BYTE:
2225 case PHY_WRITE_ERI_WORD:
2226 default:
2227 BUG();
2228 }
2229 }
2230 }
2231
2232 static void rtl_release_firmware(struct rtl8169_private *tp)
2233 {
2234 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2235 release_firmware(tp->rtl_fw->fw);
2236 kfree(tp->rtl_fw);
2237 }
2238 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2239 }
2240
2241 static void rtl_apply_firmware(struct rtl8169_private *tp)
2242 {
2243 struct rtl_fw *rtl_fw = tp->rtl_fw;
2244
2245 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2246 if (!IS_ERR_OR_NULL(rtl_fw))
2247 rtl_phy_write_fw(tp, rtl_fw);
2248 }
2249
2250 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2251 {
2252 if (rtl_readphy(tp, reg) != val)
2253 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2254 else
2255 rtl_apply_firmware(tp);
2256 }
2257
2258 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2259 {
2260 static const struct phy_reg phy_reg_init[] = {
2261 { 0x1f, 0x0001 },
2262 { 0x06, 0x006e },
2263 { 0x08, 0x0708 },
2264 { 0x15, 0x4000 },
2265 { 0x18, 0x65c7 },
2266
2267 { 0x1f, 0x0001 },
2268 { 0x03, 0x00a1 },
2269 { 0x02, 0x0008 },
2270 { 0x01, 0x0120 },
2271 { 0x00, 0x1000 },
2272 { 0x04, 0x0800 },
2273 { 0x04, 0x0000 },
2274
2275 { 0x03, 0xff41 },
2276 { 0x02, 0xdf60 },
2277 { 0x01, 0x0140 },
2278 { 0x00, 0x0077 },
2279 { 0x04, 0x7800 },
2280 { 0x04, 0x7000 },
2281
2282 { 0x03, 0x802f },
2283 { 0x02, 0x4f02 },
2284 { 0x01, 0x0409 },
2285 { 0x00, 0xf0f9 },
2286 { 0x04, 0x9800 },
2287 { 0x04, 0x9000 },
2288
2289 { 0x03, 0xdf01 },
2290 { 0x02, 0xdf20 },
2291 { 0x01, 0xff95 },
2292 { 0x00, 0xba00 },
2293 { 0x04, 0xa800 },
2294 { 0x04, 0xa000 },
2295
2296 { 0x03, 0xff41 },
2297 { 0x02, 0xdf20 },
2298 { 0x01, 0x0140 },
2299 { 0x00, 0x00bb },
2300 { 0x04, 0xb800 },
2301 { 0x04, 0xb000 },
2302
2303 { 0x03, 0xdf41 },
2304 { 0x02, 0xdc60 },
2305 { 0x01, 0x6340 },
2306 { 0x00, 0x007d },
2307 { 0x04, 0xd800 },
2308 { 0x04, 0xd000 },
2309
2310 { 0x03, 0xdf01 },
2311 { 0x02, 0xdf20 },
2312 { 0x01, 0x100a },
2313 { 0x00, 0xa0ff },
2314 { 0x04, 0xf800 },
2315 { 0x04, 0xf000 },
2316
2317 { 0x1f, 0x0000 },
2318 { 0x0b, 0x0000 },
2319 { 0x00, 0x9200 }
2320 };
2321
2322 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2323 }
2324
2325 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2326 {
2327 static const struct phy_reg phy_reg_init[] = {
2328 { 0x1f, 0x0002 },
2329 { 0x01, 0x90d0 },
2330 { 0x1f, 0x0000 }
2331 };
2332
2333 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2334 }
2335
2336 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2337 {
2338 struct pci_dev *pdev = tp->pci_dev;
2339
2340 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2341 (pdev->subsystem_device != 0xe000))
2342 return;
2343
2344 rtl_writephy(tp, 0x1f, 0x0001);
2345 rtl_writephy(tp, 0x10, 0xf01b);
2346 rtl_writephy(tp, 0x1f, 0x0000);
2347 }
2348
2349 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2350 {
2351 static const struct phy_reg phy_reg_init[] = {
2352 { 0x1f, 0x0001 },
2353 { 0x04, 0x0000 },
2354 { 0x03, 0x00a1 },
2355 { 0x02, 0x0008 },
2356 { 0x01, 0x0120 },
2357 { 0x00, 0x1000 },
2358 { 0x04, 0x0800 },
2359 { 0x04, 0x9000 },
2360 { 0x03, 0x802f },
2361 { 0x02, 0x4f02 },
2362 { 0x01, 0x0409 },
2363 { 0x00, 0xf099 },
2364 { 0x04, 0x9800 },
2365 { 0x04, 0xa000 },
2366 { 0x03, 0xdf01 },
2367 { 0x02, 0xdf20 },
2368 { 0x01, 0xff95 },
2369 { 0x00, 0xba00 },
2370 { 0x04, 0xa800 },
2371 { 0x04, 0xf000 },
2372 { 0x03, 0xdf01 },
2373 { 0x02, 0xdf20 },
2374 { 0x01, 0x101a },
2375 { 0x00, 0xa0ff },
2376 { 0x04, 0xf800 },
2377 { 0x04, 0x0000 },
2378 { 0x1f, 0x0000 },
2379
2380 { 0x1f, 0x0001 },
2381 { 0x10, 0xf41b },
2382 { 0x14, 0xfb54 },
2383 { 0x18, 0xf5c7 },
2384 { 0x1f, 0x0000 },
2385
2386 { 0x1f, 0x0001 },
2387 { 0x17, 0x0cc0 },
2388 { 0x1f, 0x0000 }
2389 };
2390
2391 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2392
2393 rtl8169scd_hw_phy_config_quirk(tp);
2394 }
2395
2396 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2397 {
2398 static const struct phy_reg phy_reg_init[] = {
2399 { 0x1f, 0x0001 },
2400 { 0x04, 0x0000 },
2401 { 0x03, 0x00a1 },
2402 { 0x02, 0x0008 },
2403 { 0x01, 0x0120 },
2404 { 0x00, 0x1000 },
2405 { 0x04, 0x0800 },
2406 { 0x04, 0x9000 },
2407 { 0x03, 0x802f },
2408 { 0x02, 0x4f02 },
2409 { 0x01, 0x0409 },
2410 { 0x00, 0xf099 },
2411 { 0x04, 0x9800 },
2412 { 0x04, 0xa000 },
2413 { 0x03, 0xdf01 },
2414 { 0x02, 0xdf20 },
2415 { 0x01, 0xff95 },
2416 { 0x00, 0xba00 },
2417 { 0x04, 0xa800 },
2418 { 0x04, 0xf000 },
2419 { 0x03, 0xdf01 },
2420 { 0x02, 0xdf20 },
2421 { 0x01, 0x101a },
2422 { 0x00, 0xa0ff },
2423 { 0x04, 0xf800 },
2424 { 0x04, 0x0000 },
2425 { 0x1f, 0x0000 },
2426
2427 { 0x1f, 0x0001 },
2428 { 0x0b, 0x8480 },
2429 { 0x1f, 0x0000 },
2430
2431 { 0x1f, 0x0001 },
2432 { 0x18, 0x67c7 },
2433 { 0x04, 0x2000 },
2434 { 0x03, 0x002f },
2435 { 0x02, 0x4360 },
2436 { 0x01, 0x0109 },
2437 { 0x00, 0x3022 },
2438 { 0x04, 0x2800 },
2439 { 0x1f, 0x0000 },
2440
2441 { 0x1f, 0x0001 },
2442 { 0x17, 0x0cc0 },
2443 { 0x1f, 0x0000 }
2444 };
2445
2446 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2447 }
2448
2449 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2450 {
2451 static const struct phy_reg phy_reg_init[] = {
2452 { 0x10, 0xf41b },
2453 { 0x1f, 0x0000 }
2454 };
2455
2456 rtl_writephy(tp, 0x1f, 0x0001);
2457 rtl_patchphy(tp, 0x16, 1 << 0);
2458
2459 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2460 }
2461
2462 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2463 {
2464 static const struct phy_reg phy_reg_init[] = {
2465 { 0x1f, 0x0001 },
2466 { 0x10, 0xf41b },
2467 { 0x1f, 0x0000 }
2468 };
2469
2470 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2471 }
2472
2473 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2474 {
2475 static const struct phy_reg phy_reg_init[] = {
2476 { 0x1f, 0x0000 },
2477 { 0x1d, 0x0f00 },
2478 { 0x1f, 0x0002 },
2479 { 0x0c, 0x1ec8 },
2480 { 0x1f, 0x0000 }
2481 };
2482
2483 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2484 }
2485
2486 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2487 {
2488 static const struct phy_reg phy_reg_init[] = {
2489 { 0x1f, 0x0001 },
2490 { 0x1d, 0x3d98 },
2491 { 0x1f, 0x0000 }
2492 };
2493
2494 rtl_writephy(tp, 0x1f, 0x0000);
2495 rtl_patchphy(tp, 0x14, 1 << 5);
2496 rtl_patchphy(tp, 0x0d, 1 << 5);
2497
2498 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2499 }
2500
2501 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2502 {
2503 static const struct phy_reg phy_reg_init[] = {
2504 { 0x1f, 0x0001 },
2505 { 0x12, 0x2300 },
2506 { 0x1f, 0x0002 },
2507 { 0x00, 0x88d4 },
2508 { 0x01, 0x82b1 },
2509 { 0x03, 0x7002 },
2510 { 0x08, 0x9e30 },
2511 { 0x09, 0x01f0 },
2512 { 0x0a, 0x5500 },
2513 { 0x0c, 0x00c8 },
2514 { 0x1f, 0x0003 },
2515 { 0x12, 0xc096 },
2516 { 0x16, 0x000a },
2517 { 0x1f, 0x0000 },
2518 { 0x1f, 0x0000 },
2519 { 0x09, 0x2000 },
2520 { 0x09, 0x0000 }
2521 };
2522
2523 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2524
2525 rtl_patchphy(tp, 0x14, 1 << 5);
2526 rtl_patchphy(tp, 0x0d, 1 << 5);
2527 rtl_writephy(tp, 0x1f, 0x0000);
2528 }
2529
2530 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2531 {
2532 static const struct phy_reg phy_reg_init[] = {
2533 { 0x1f, 0x0001 },
2534 { 0x12, 0x2300 },
2535 { 0x03, 0x802f },
2536 { 0x02, 0x4f02 },
2537 { 0x01, 0x0409 },
2538 { 0x00, 0xf099 },
2539 { 0x04, 0x9800 },
2540 { 0x04, 0x9000 },
2541 { 0x1d, 0x3d98 },
2542 { 0x1f, 0x0002 },
2543 { 0x0c, 0x7eb8 },
2544 { 0x06, 0x0761 },
2545 { 0x1f, 0x0003 },
2546 { 0x16, 0x0f0a },
2547 { 0x1f, 0x0000 }
2548 };
2549
2550 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2551
2552 rtl_patchphy(tp, 0x16, 1 << 0);
2553 rtl_patchphy(tp, 0x14, 1 << 5);
2554 rtl_patchphy(tp, 0x0d, 1 << 5);
2555 rtl_writephy(tp, 0x1f, 0x0000);
2556 }
2557
2558 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2559 {
2560 static const struct phy_reg phy_reg_init[] = {
2561 { 0x1f, 0x0001 },
2562 { 0x12, 0x2300 },
2563 { 0x1d, 0x3d98 },
2564 { 0x1f, 0x0002 },
2565 { 0x0c, 0x7eb8 },
2566 { 0x06, 0x5461 },
2567 { 0x1f, 0x0003 },
2568 { 0x16, 0x0f0a },
2569 { 0x1f, 0x0000 }
2570 };
2571
2572 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2573
2574 rtl_patchphy(tp, 0x16, 1 << 0);
2575 rtl_patchphy(tp, 0x14, 1 << 5);
2576 rtl_patchphy(tp, 0x0d, 1 << 5);
2577 rtl_writephy(tp, 0x1f, 0x0000);
2578 }
2579
2580 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2581 {
2582 rtl8168c_3_hw_phy_config(tp);
2583 }
2584
2585 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2586 {
2587 static const struct phy_reg phy_reg_init_0[] = {
2588 /* Channel Estimation */
2589 { 0x1f, 0x0001 },
2590 { 0x06, 0x4064 },
2591 { 0x07, 0x2863 },
2592 { 0x08, 0x059c },
2593 { 0x09, 0x26b4 },
2594 { 0x0a, 0x6a19 },
2595 { 0x0b, 0xdcc8 },
2596 { 0x10, 0xf06d },
2597 { 0x14, 0x7f68 },
2598 { 0x18, 0x7fd9 },
2599 { 0x1c, 0xf0ff },
2600 { 0x1d, 0x3d9c },
2601 { 0x1f, 0x0003 },
2602 { 0x12, 0xf49f },
2603 { 0x13, 0x070b },
2604 { 0x1a, 0x05ad },
2605 { 0x14, 0x94c0 },
2606
2607 /*
2608 * Tx Error Issue
2609 * Enhance line driver power
2610 */
2611 { 0x1f, 0x0002 },
2612 { 0x06, 0x5561 },
2613 { 0x1f, 0x0005 },
2614 { 0x05, 0x8332 },
2615 { 0x06, 0x5561 },
2616
2617 /*
2618 * Can not link to 1Gbps with bad cable
2619 * Decrease SNR threshold form 21.07dB to 19.04dB
2620 */
2621 { 0x1f, 0x0001 },
2622 { 0x17, 0x0cc0 },
2623
2624 { 0x1f, 0x0000 },
2625 { 0x0d, 0xf880 }
2626 };
2627 void __iomem *ioaddr = tp->mmio_addr;
2628
2629 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2630
2631 /*
2632 * Rx Error Issue
2633 * Fine Tune Switching regulator parameter
2634 */
2635 rtl_writephy(tp, 0x1f, 0x0002);
2636 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2637 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2638
2639 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2640 static const struct phy_reg phy_reg_init[] = {
2641 { 0x1f, 0x0002 },
2642 { 0x05, 0x669a },
2643 { 0x1f, 0x0005 },
2644 { 0x05, 0x8330 },
2645 { 0x06, 0x669a },
2646 { 0x1f, 0x0002 }
2647 };
2648 int val;
2649
2650 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2651
2652 val = rtl_readphy(tp, 0x0d);
2653
2654 if ((val & 0x00ff) != 0x006c) {
2655 static const u32 set[] = {
2656 0x0065, 0x0066, 0x0067, 0x0068,
2657 0x0069, 0x006a, 0x006b, 0x006c
2658 };
2659 int i;
2660
2661 rtl_writephy(tp, 0x1f, 0x0002);
2662
2663 val &= 0xff00;
2664 for (i = 0; i < ARRAY_SIZE(set); i++)
2665 rtl_writephy(tp, 0x0d, val | set[i]);
2666 }
2667 } else {
2668 static const struct phy_reg phy_reg_init[] = {
2669 { 0x1f, 0x0002 },
2670 { 0x05, 0x6662 },
2671 { 0x1f, 0x0005 },
2672 { 0x05, 0x8330 },
2673 { 0x06, 0x6662 }
2674 };
2675
2676 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2677 }
2678
2679 /* RSET couple improve */
2680 rtl_writephy(tp, 0x1f, 0x0002);
2681 rtl_patchphy(tp, 0x0d, 0x0300);
2682 rtl_patchphy(tp, 0x0f, 0x0010);
2683
2684 /* Fine tune PLL performance */
2685 rtl_writephy(tp, 0x1f, 0x0002);
2686 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2687 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2688
2689 rtl_writephy(tp, 0x1f, 0x0005);
2690 rtl_writephy(tp, 0x05, 0x001b);
2691
2692 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2693
2694 rtl_writephy(tp, 0x1f, 0x0000);
2695 }
2696
2697 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2698 {
2699 static const struct phy_reg phy_reg_init_0[] = {
2700 /* Channel Estimation */
2701 { 0x1f, 0x0001 },
2702 { 0x06, 0x4064 },
2703 { 0x07, 0x2863 },
2704 { 0x08, 0x059c },
2705 { 0x09, 0x26b4 },
2706 { 0x0a, 0x6a19 },
2707 { 0x0b, 0xdcc8 },
2708 { 0x10, 0xf06d },
2709 { 0x14, 0x7f68 },
2710 { 0x18, 0x7fd9 },
2711 { 0x1c, 0xf0ff },
2712 { 0x1d, 0x3d9c },
2713 { 0x1f, 0x0003 },
2714 { 0x12, 0xf49f },
2715 { 0x13, 0x070b },
2716 { 0x1a, 0x05ad },
2717 { 0x14, 0x94c0 },
2718
2719 /*
2720 * Tx Error Issue
2721 * Enhance line driver power
2722 */
2723 { 0x1f, 0x0002 },
2724 { 0x06, 0x5561 },
2725 { 0x1f, 0x0005 },
2726 { 0x05, 0x8332 },
2727 { 0x06, 0x5561 },
2728
2729 /*
2730 * Can not link to 1Gbps with bad cable
2731 * Decrease SNR threshold form 21.07dB to 19.04dB
2732 */
2733 { 0x1f, 0x0001 },
2734 { 0x17, 0x0cc0 },
2735
2736 { 0x1f, 0x0000 },
2737 { 0x0d, 0xf880 }
2738 };
2739 void __iomem *ioaddr = tp->mmio_addr;
2740
2741 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2742
2743 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2744 static const struct phy_reg phy_reg_init[] = {
2745 { 0x1f, 0x0002 },
2746 { 0x05, 0x669a },
2747 { 0x1f, 0x0005 },
2748 { 0x05, 0x8330 },
2749 { 0x06, 0x669a },
2750
2751 { 0x1f, 0x0002 }
2752 };
2753 int val;
2754
2755 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2756
2757 val = rtl_readphy(tp, 0x0d);
2758 if ((val & 0x00ff) != 0x006c) {
2759 static const u32 set[] = {
2760 0x0065, 0x0066, 0x0067, 0x0068,
2761 0x0069, 0x006a, 0x006b, 0x006c
2762 };
2763 int i;
2764
2765 rtl_writephy(tp, 0x1f, 0x0002);
2766
2767 val &= 0xff00;
2768 for (i = 0; i < ARRAY_SIZE(set); i++)
2769 rtl_writephy(tp, 0x0d, val | set[i]);
2770 }
2771 } else {
2772 static const struct phy_reg phy_reg_init[] = {
2773 { 0x1f, 0x0002 },
2774 { 0x05, 0x2642 },
2775 { 0x1f, 0x0005 },
2776 { 0x05, 0x8330 },
2777 { 0x06, 0x2642 }
2778 };
2779
2780 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2781 }
2782
2783 /* Fine tune PLL performance */
2784 rtl_writephy(tp, 0x1f, 0x0002);
2785 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2786 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2787
2788 /* Switching regulator Slew rate */
2789 rtl_writephy(tp, 0x1f, 0x0002);
2790 rtl_patchphy(tp, 0x0f, 0x0017);
2791
2792 rtl_writephy(tp, 0x1f, 0x0005);
2793 rtl_writephy(tp, 0x05, 0x001b);
2794
2795 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2796
2797 rtl_writephy(tp, 0x1f, 0x0000);
2798 }
2799
2800 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2801 {
2802 static const struct phy_reg phy_reg_init[] = {
2803 { 0x1f, 0x0002 },
2804 { 0x10, 0x0008 },
2805 { 0x0d, 0x006c },
2806
2807 { 0x1f, 0x0000 },
2808 { 0x0d, 0xf880 },
2809
2810 { 0x1f, 0x0001 },
2811 { 0x17, 0x0cc0 },
2812
2813 { 0x1f, 0x0001 },
2814 { 0x0b, 0xa4d8 },
2815 { 0x09, 0x281c },
2816 { 0x07, 0x2883 },
2817 { 0x0a, 0x6b35 },
2818 { 0x1d, 0x3da4 },
2819 { 0x1c, 0xeffd },
2820 { 0x14, 0x7f52 },
2821 { 0x18, 0x7fc6 },
2822 { 0x08, 0x0601 },
2823 { 0x06, 0x4063 },
2824 { 0x10, 0xf074 },
2825 { 0x1f, 0x0003 },
2826 { 0x13, 0x0789 },
2827 { 0x12, 0xf4bd },
2828 { 0x1a, 0x04fd },
2829 { 0x14, 0x84b0 },
2830 { 0x1f, 0x0000 },
2831 { 0x00, 0x9200 },
2832
2833 { 0x1f, 0x0005 },
2834 { 0x01, 0x0340 },
2835 { 0x1f, 0x0001 },
2836 { 0x04, 0x4000 },
2837 { 0x03, 0x1d21 },
2838 { 0x02, 0x0c32 },
2839 { 0x01, 0x0200 },
2840 { 0x00, 0x5554 },
2841 { 0x04, 0x4800 },
2842 { 0x04, 0x4000 },
2843 { 0x04, 0xf000 },
2844 { 0x03, 0xdf01 },
2845 { 0x02, 0xdf20 },
2846 { 0x01, 0x101a },
2847 { 0x00, 0xa0ff },
2848 { 0x04, 0xf800 },
2849 { 0x04, 0xf000 },
2850 { 0x1f, 0x0000 },
2851
2852 { 0x1f, 0x0007 },
2853 { 0x1e, 0x0023 },
2854 { 0x16, 0x0000 },
2855 { 0x1f, 0x0000 }
2856 };
2857
2858 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2859 }
2860
2861 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2862 {
2863 static const struct phy_reg phy_reg_init[] = {
2864 { 0x1f, 0x0001 },
2865 { 0x17, 0x0cc0 },
2866
2867 { 0x1f, 0x0007 },
2868 { 0x1e, 0x002d },
2869 { 0x18, 0x0040 },
2870 { 0x1f, 0x0000 }
2871 };
2872
2873 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2874 rtl_patchphy(tp, 0x0d, 1 << 5);
2875 }
2876
2877 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2878 {
2879 static const struct phy_reg phy_reg_init[] = {
2880 /* Enable Delay cap */
2881 { 0x1f, 0x0005 },
2882 { 0x05, 0x8b80 },
2883 { 0x06, 0xc896 },
2884 { 0x1f, 0x0000 },
2885
2886 /* Channel estimation fine tune */
2887 { 0x1f, 0x0001 },
2888 { 0x0b, 0x6c20 },
2889 { 0x07, 0x2872 },
2890 { 0x1c, 0xefff },
2891 { 0x1f, 0x0003 },
2892 { 0x14, 0x6420 },
2893 { 0x1f, 0x0000 },
2894
2895 /* Update PFM & 10M TX idle timer */
2896 { 0x1f, 0x0007 },
2897 { 0x1e, 0x002f },
2898 { 0x15, 0x1919 },
2899 { 0x1f, 0x0000 },
2900
2901 { 0x1f, 0x0007 },
2902 { 0x1e, 0x00ac },
2903 { 0x18, 0x0006 },
2904 { 0x1f, 0x0000 }
2905 };
2906
2907 rtl_apply_firmware(tp);
2908
2909 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2910
2911 /* DCO enable for 10M IDLE Power */
2912 rtl_writephy(tp, 0x1f, 0x0007);
2913 rtl_writephy(tp, 0x1e, 0x0023);
2914 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2915 rtl_writephy(tp, 0x1f, 0x0000);
2916
2917 /* For impedance matching */
2918 rtl_writephy(tp, 0x1f, 0x0002);
2919 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2920 rtl_writephy(tp, 0x1f, 0x0000);
2921
2922 /* PHY auto speed down */
2923 rtl_writephy(tp, 0x1f, 0x0007);
2924 rtl_writephy(tp, 0x1e, 0x002d);
2925 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2926 rtl_writephy(tp, 0x1f, 0x0000);
2927 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2928
2929 rtl_writephy(tp, 0x1f, 0x0005);
2930 rtl_writephy(tp, 0x05, 0x8b86);
2931 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2932 rtl_writephy(tp, 0x1f, 0x0000);
2933
2934 rtl_writephy(tp, 0x1f, 0x0005);
2935 rtl_writephy(tp, 0x05, 0x8b85);
2936 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2937 rtl_writephy(tp, 0x1f, 0x0007);
2938 rtl_writephy(tp, 0x1e, 0x0020);
2939 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2940 rtl_writephy(tp, 0x1f, 0x0006);
2941 rtl_writephy(tp, 0x00, 0x5a00);
2942 rtl_writephy(tp, 0x1f, 0x0000);
2943 rtl_writephy(tp, 0x0d, 0x0007);
2944 rtl_writephy(tp, 0x0e, 0x003c);
2945 rtl_writephy(tp, 0x0d, 0x4007);
2946 rtl_writephy(tp, 0x0e, 0x0000);
2947 rtl_writephy(tp, 0x0d, 0x0000);
2948 }
2949
2950 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2951 {
2952 static const struct phy_reg phy_reg_init[] = {
2953 /* Enable Delay cap */
2954 { 0x1f, 0x0004 },
2955 { 0x1f, 0x0007 },
2956 { 0x1e, 0x00ac },
2957 { 0x18, 0x0006 },
2958 { 0x1f, 0x0002 },
2959 { 0x1f, 0x0000 },
2960 { 0x1f, 0x0000 },
2961
2962 /* Channel estimation fine tune */
2963 { 0x1f, 0x0003 },
2964 { 0x09, 0xa20f },
2965 { 0x1f, 0x0000 },
2966 { 0x1f, 0x0000 },
2967
2968 /* Green Setting */
2969 { 0x1f, 0x0005 },
2970 { 0x05, 0x8b5b },
2971 { 0x06, 0x9222 },
2972 { 0x05, 0x8b6d },
2973 { 0x06, 0x8000 },
2974 { 0x05, 0x8b76 },
2975 { 0x06, 0x8000 },
2976 { 0x1f, 0x0000 }
2977 };
2978
2979 rtl_apply_firmware(tp);
2980
2981 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2982
2983 /* For 4-corner performance improve */
2984 rtl_writephy(tp, 0x1f, 0x0005);
2985 rtl_writephy(tp, 0x05, 0x8b80);
2986 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2987 rtl_writephy(tp, 0x1f, 0x0000);
2988
2989 /* PHY auto speed down */
2990 rtl_writephy(tp, 0x1f, 0x0004);
2991 rtl_writephy(tp, 0x1f, 0x0007);
2992 rtl_writephy(tp, 0x1e, 0x002d);
2993 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2994 rtl_writephy(tp, 0x1f, 0x0002);
2995 rtl_writephy(tp, 0x1f, 0x0000);
2996 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2997
2998 /* improve 10M EEE waveform */
2999 rtl_writephy(tp, 0x1f, 0x0005);
3000 rtl_writephy(tp, 0x05, 0x8b86);
3001 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3002 rtl_writephy(tp, 0x1f, 0x0000);
3003
3004 /* Improve 2-pair detection performance */
3005 rtl_writephy(tp, 0x1f, 0x0005);
3006 rtl_writephy(tp, 0x05, 0x8b85);
3007 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3008 rtl_writephy(tp, 0x1f, 0x0000);
3009
3010 /* EEE setting */
3011 rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
3012 ERIAR_EXGMAC);
3013 rtl_writephy(tp, 0x1f, 0x0005);
3014 rtl_writephy(tp, 0x05, 0x8b85);
3015 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3016 rtl_writephy(tp, 0x1f, 0x0004);
3017 rtl_writephy(tp, 0x1f, 0x0007);
3018 rtl_writephy(tp, 0x1e, 0x0020);
3019 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3020 rtl_writephy(tp, 0x1f, 0x0002);
3021 rtl_writephy(tp, 0x1f, 0x0000);
3022 rtl_writephy(tp, 0x0d, 0x0007);
3023 rtl_writephy(tp, 0x0e, 0x003c);
3024 rtl_writephy(tp, 0x0d, 0x4007);
3025 rtl_writephy(tp, 0x0e, 0x0000);
3026 rtl_writephy(tp, 0x0d, 0x0000);
3027
3028 /* Green feature */
3029 rtl_writephy(tp, 0x1f, 0x0003);
3030 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3031 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3032 rtl_writephy(tp, 0x1f, 0x0000);
3033 }
3034
3035 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3036 {
3037 static const struct phy_reg phy_reg_init[] = {
3038 /* Channel estimation fine tune */
3039 { 0x1f, 0x0003 },
3040 { 0x09, 0xa20f },
3041 { 0x1f, 0x0000 },
3042
3043 /* Modify green table for giga & fnet */
3044 { 0x1f, 0x0005 },
3045 { 0x05, 0x8b55 },
3046 { 0x06, 0x0000 },
3047 { 0x05, 0x8b5e },
3048 { 0x06, 0x0000 },
3049 { 0x05, 0x8b67 },
3050 { 0x06, 0x0000 },
3051 { 0x05, 0x8b70 },
3052 { 0x06, 0x0000 },
3053 { 0x1f, 0x0000 },
3054 { 0x1f, 0x0007 },
3055 { 0x1e, 0x0078 },
3056 { 0x17, 0x0000 },
3057 { 0x19, 0x00fb },
3058 { 0x1f, 0x0000 },
3059
3060 /* Modify green table for 10M */
3061 { 0x1f, 0x0005 },
3062 { 0x05, 0x8b79 },
3063 { 0x06, 0xaa00 },
3064 { 0x1f, 0x0000 },
3065
3066 /* Disable hiimpedance detection (RTCT) */
3067 { 0x1f, 0x0003 },
3068 { 0x01, 0x328a },
3069 { 0x1f, 0x0000 }
3070 };
3071
3072 rtl_apply_firmware(tp);
3073
3074 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3075
3076 /* For 4-corner performance improve */
3077 rtl_writephy(tp, 0x1f, 0x0005);
3078 rtl_writephy(tp, 0x05, 0x8b80);
3079 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3080 rtl_writephy(tp, 0x1f, 0x0000);
3081
3082 /* PHY auto speed down */
3083 rtl_writephy(tp, 0x1f, 0x0007);
3084 rtl_writephy(tp, 0x1e, 0x002d);
3085 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3086 rtl_writephy(tp, 0x1f, 0x0000);
3087 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3088
3089 /* Improve 10M EEE waveform */
3090 rtl_writephy(tp, 0x1f, 0x0005);
3091 rtl_writephy(tp, 0x05, 0x8b86);
3092 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3093 rtl_writephy(tp, 0x1f, 0x0000);
3094
3095 /* Improve 2-pair detection performance */
3096 rtl_writephy(tp, 0x1f, 0x0005);
3097 rtl_writephy(tp, 0x05, 0x8b85);
3098 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3099 rtl_writephy(tp, 0x1f, 0x0000);
3100 }
3101
3102 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3103 {
3104 rtl_apply_firmware(tp);
3105
3106 /* For 4-corner performance improve */
3107 rtl_writephy(tp, 0x1f, 0x0005);
3108 rtl_writephy(tp, 0x05, 0x8b80);
3109 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3110 rtl_writephy(tp, 0x1f, 0x0000);
3111
3112 /* PHY auto speed down */
3113 rtl_writephy(tp, 0x1f, 0x0007);
3114 rtl_writephy(tp, 0x1e, 0x002d);
3115 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3116 rtl_writephy(tp, 0x1f, 0x0000);
3117 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3118
3119 /* Improve 10M EEE waveform */
3120 rtl_writephy(tp, 0x1f, 0x0005);
3121 rtl_writephy(tp, 0x05, 0x8b86);
3122 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3123 rtl_writephy(tp, 0x1f, 0x0000);
3124 }
3125
3126 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3127 {
3128 static const struct phy_reg phy_reg_init[] = {
3129 { 0x1f, 0x0003 },
3130 { 0x08, 0x441d },
3131 { 0x01, 0x9100 },
3132 { 0x1f, 0x0000 }
3133 };
3134
3135 rtl_writephy(tp, 0x1f, 0x0000);
3136 rtl_patchphy(tp, 0x11, 1 << 12);
3137 rtl_patchphy(tp, 0x19, 1 << 13);
3138 rtl_patchphy(tp, 0x10, 1 << 15);
3139
3140 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3141 }
3142
3143 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3144 {
3145 static const struct phy_reg phy_reg_init[] = {
3146 { 0x1f, 0x0005 },
3147 { 0x1a, 0x0000 },
3148 { 0x1f, 0x0000 },
3149
3150 { 0x1f, 0x0004 },
3151 { 0x1c, 0x0000 },
3152 { 0x1f, 0x0000 },
3153
3154 { 0x1f, 0x0001 },
3155 { 0x15, 0x7701 },
3156 { 0x1f, 0x0000 }
3157 };
3158
3159 /* Disable ALDPS before ram code */
3160 rtl_writephy(tp, 0x1f, 0x0000);
3161 rtl_writephy(tp, 0x18, 0x0310);
3162 msleep(100);
3163
3164 rtl_apply_firmware(tp);
3165
3166 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3167 }
3168
3169 static void rtl_hw_phy_config(struct net_device *dev)
3170 {
3171 struct rtl8169_private *tp = netdev_priv(dev);
3172
3173 rtl8169_print_mac_version(tp);
3174
3175 switch (tp->mac_version) {
3176 case RTL_GIGA_MAC_VER_01:
3177 break;
3178 case RTL_GIGA_MAC_VER_02:
3179 case RTL_GIGA_MAC_VER_03:
3180 rtl8169s_hw_phy_config(tp);
3181 break;
3182 case RTL_GIGA_MAC_VER_04:
3183 rtl8169sb_hw_phy_config(tp);
3184 break;
3185 case RTL_GIGA_MAC_VER_05:
3186 rtl8169scd_hw_phy_config(tp);
3187 break;
3188 case RTL_GIGA_MAC_VER_06:
3189 rtl8169sce_hw_phy_config(tp);
3190 break;
3191 case RTL_GIGA_MAC_VER_07:
3192 case RTL_GIGA_MAC_VER_08:
3193 case RTL_GIGA_MAC_VER_09:
3194 rtl8102e_hw_phy_config(tp);
3195 break;
3196 case RTL_GIGA_MAC_VER_11:
3197 rtl8168bb_hw_phy_config(tp);
3198 break;
3199 case RTL_GIGA_MAC_VER_12:
3200 rtl8168bef_hw_phy_config(tp);
3201 break;
3202 case RTL_GIGA_MAC_VER_17:
3203 rtl8168bef_hw_phy_config(tp);
3204 break;
3205 case RTL_GIGA_MAC_VER_18:
3206 rtl8168cp_1_hw_phy_config(tp);
3207 break;
3208 case RTL_GIGA_MAC_VER_19:
3209 rtl8168c_1_hw_phy_config(tp);
3210 break;
3211 case RTL_GIGA_MAC_VER_20:
3212 rtl8168c_2_hw_phy_config(tp);
3213 break;
3214 case RTL_GIGA_MAC_VER_21:
3215 rtl8168c_3_hw_phy_config(tp);
3216 break;
3217 case RTL_GIGA_MAC_VER_22:
3218 rtl8168c_4_hw_phy_config(tp);
3219 break;
3220 case RTL_GIGA_MAC_VER_23:
3221 case RTL_GIGA_MAC_VER_24:
3222 rtl8168cp_2_hw_phy_config(tp);
3223 break;
3224 case RTL_GIGA_MAC_VER_25:
3225 rtl8168d_1_hw_phy_config(tp);
3226 break;
3227 case RTL_GIGA_MAC_VER_26:
3228 rtl8168d_2_hw_phy_config(tp);
3229 break;
3230 case RTL_GIGA_MAC_VER_27:
3231 rtl8168d_3_hw_phy_config(tp);
3232 break;
3233 case RTL_GIGA_MAC_VER_28:
3234 rtl8168d_4_hw_phy_config(tp);
3235 break;
3236 case RTL_GIGA_MAC_VER_29:
3237 case RTL_GIGA_MAC_VER_30:
3238 rtl8105e_hw_phy_config(tp);
3239 break;
3240 case RTL_GIGA_MAC_VER_31:
3241 /* None. */
3242 break;
3243 case RTL_GIGA_MAC_VER_32:
3244 case RTL_GIGA_MAC_VER_33:
3245 rtl8168e_1_hw_phy_config(tp);
3246 break;
3247 case RTL_GIGA_MAC_VER_34:
3248 rtl8168e_2_hw_phy_config(tp);
3249 break;
3250 case RTL_GIGA_MAC_VER_35:
3251 rtl8168f_1_hw_phy_config(tp);
3252 break;
3253 case RTL_GIGA_MAC_VER_36:
3254 rtl8168f_2_hw_phy_config(tp);
3255 break;
3256
3257 default:
3258 break;
3259 }
3260 }
3261
3262 static void rtl_phy_work(struct rtl8169_private *tp)
3263 {
3264 struct timer_list *timer = &tp->timer;
3265 void __iomem *ioaddr = tp->mmio_addr;
3266 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3267
3268 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3269
3270 if (tp->phy_reset_pending(tp)) {
3271 /*
3272 * A busy loop could burn quite a few cycles on nowadays CPU.
3273 * Let's delay the execution of the timer for a few ticks.
3274 */
3275 timeout = HZ/10;
3276 goto out_mod_timer;
3277 }
3278
3279 if (tp->link_ok(ioaddr))
3280 return;
3281
3282 netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
3283
3284 tp->phy_reset_enable(tp);
3285
3286 out_mod_timer:
3287 mod_timer(timer, jiffies + timeout);
3288 }
3289
3290 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3291 {
3292 if (!test_and_set_bit(flag, tp->wk.flags))
3293 schedule_work(&tp->wk.work);
3294 }
3295
3296 static void rtl8169_phy_timer(unsigned long __opaque)
3297 {
3298 struct net_device *dev = (struct net_device *)__opaque;
3299 struct rtl8169_private *tp = netdev_priv(dev);
3300
3301 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
3302 }
3303
3304 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3305 void __iomem *ioaddr)
3306 {
3307 iounmap(ioaddr);
3308 pci_release_regions(pdev);
3309 pci_clear_mwi(pdev);
3310 pci_disable_device(pdev);
3311 free_netdev(dev);
3312 }
3313
3314 static void rtl8169_phy_reset(struct net_device *dev,
3315 struct rtl8169_private *tp)
3316 {
3317 unsigned int i;
3318
3319 tp->phy_reset_enable(tp);
3320 for (i = 0; i < 100; i++) {
3321 if (!tp->phy_reset_pending(tp))
3322 return;
3323 msleep(1);
3324 }
3325 netif_err(tp, link, dev, "PHY reset failed\n");
3326 }
3327
3328 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3329 {
3330 void __iomem *ioaddr = tp->mmio_addr;
3331
3332 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3333 (RTL_R8(PHYstatus) & TBI_Enable);
3334 }
3335
3336 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3337 {
3338 void __iomem *ioaddr = tp->mmio_addr;
3339
3340 rtl_hw_phy_config(dev);
3341
3342 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3343 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3344 RTL_W8(0x82, 0x01);
3345 }
3346
3347 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3348
3349 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3350 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3351
3352 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3353 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3354 RTL_W8(0x82, 0x01);
3355 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3356 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3357 }
3358
3359 rtl8169_phy_reset(dev, tp);
3360
3361 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3362 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3363 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3364 (tp->mii.supports_gmii ?
3365 ADVERTISED_1000baseT_Half |
3366 ADVERTISED_1000baseT_Full : 0));
3367
3368 if (rtl_tbi_enabled(tp))
3369 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3370 }
3371
3372 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3373 {
3374 void __iomem *ioaddr = tp->mmio_addr;
3375 u32 high;
3376 u32 low;
3377
3378 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3379 high = addr[4] | (addr[5] << 8);
3380
3381 rtl_lock_work(tp);
3382
3383 RTL_W8(Cfg9346, Cfg9346_Unlock);
3384
3385 RTL_W32(MAC4, high);
3386 RTL_R32(MAC4);
3387
3388 RTL_W32(MAC0, low);
3389 RTL_R32(MAC0);
3390
3391 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3392 const struct exgmac_reg e[] = {
3393 { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3394 { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3395 { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3396 { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3397 low >> 16 },
3398 };
3399
3400 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e));
3401 }
3402
3403 RTL_W8(Cfg9346, Cfg9346_Lock);
3404
3405 rtl_unlock_work(tp);
3406 }
3407
3408 static int rtl_set_mac_address(struct net_device *dev, void *p)
3409 {
3410 struct rtl8169_private *tp = netdev_priv(dev);
3411 struct sockaddr *addr = p;
3412
3413 if (!is_valid_ether_addr(addr->sa_data))
3414 return -EADDRNOTAVAIL;
3415
3416 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3417
3418 rtl_rar_set(tp, dev->dev_addr);
3419
3420 return 0;
3421 }
3422
3423 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3424 {
3425 struct rtl8169_private *tp = netdev_priv(dev);
3426 struct mii_ioctl_data *data = if_mii(ifr);
3427
3428 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3429 }
3430
3431 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3432 struct mii_ioctl_data *data, int cmd)
3433 {
3434 switch (cmd) {
3435 case SIOCGMIIPHY:
3436 data->phy_id = 32; /* Internal PHY */
3437 return 0;
3438
3439 case SIOCGMIIREG:
3440 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3441 return 0;
3442
3443 case SIOCSMIIREG:
3444 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3445 return 0;
3446 }
3447 return -EOPNOTSUPP;
3448 }
3449
3450 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3451 {
3452 return -EOPNOTSUPP;
3453 }
3454
3455 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3456 {
3457 if (tp->features & RTL_FEATURE_MSI) {
3458 pci_disable_msi(pdev);
3459 tp->features &= ~RTL_FEATURE_MSI;
3460 }
3461 }
3462
3463 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3464 {
3465 struct mdio_ops *ops = &tp->mdio_ops;
3466
3467 switch (tp->mac_version) {
3468 case RTL_GIGA_MAC_VER_27:
3469 ops->write = r8168dp_1_mdio_write;
3470 ops->read = r8168dp_1_mdio_read;
3471 break;
3472 case RTL_GIGA_MAC_VER_28:
3473 case RTL_GIGA_MAC_VER_31:
3474 ops->write = r8168dp_2_mdio_write;
3475 ops->read = r8168dp_2_mdio_read;
3476 break;
3477 default:
3478 ops->write = r8169_mdio_write;
3479 ops->read = r8169_mdio_read;
3480 break;
3481 }
3482 }
3483
3484 static void rtl_speed_down(struct rtl8169_private *tp)
3485 {
3486 u32 adv;
3487 int lpa;
3488
3489 rtl_writephy(tp, 0x1f, 0x0000);
3490 lpa = rtl_readphy(tp, MII_LPA);
3491
3492 if (lpa & (LPA_10HALF | LPA_10FULL))
3493 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
3494 else if (lpa & (LPA_100HALF | LPA_100FULL))
3495 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3496 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
3497 else
3498 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3499 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3500 (tp->mii.supports_gmii ?
3501 ADVERTISED_1000baseT_Half |
3502 ADVERTISED_1000baseT_Full : 0);
3503
3504 rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3505 adv);
3506 }
3507
3508 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3509 {
3510 void __iomem *ioaddr = tp->mmio_addr;
3511
3512 switch (tp->mac_version) {
3513 case RTL_GIGA_MAC_VER_25:
3514 case RTL_GIGA_MAC_VER_26:
3515 case RTL_GIGA_MAC_VER_29:
3516 case RTL_GIGA_MAC_VER_30:
3517 case RTL_GIGA_MAC_VER_32:
3518 case RTL_GIGA_MAC_VER_33:
3519 case RTL_GIGA_MAC_VER_34:
3520 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3521 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3522 break;
3523 default:
3524 break;
3525 }
3526 }
3527
3528 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3529 {
3530 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3531 return false;
3532
3533 rtl_speed_down(tp);
3534 rtl_wol_suspend_quirk(tp);
3535
3536 return true;
3537 }
3538
3539 static void r810x_phy_power_down(struct rtl8169_private *tp)
3540 {
3541 rtl_writephy(tp, 0x1f, 0x0000);
3542 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3543 }
3544
3545 static void r810x_phy_power_up(struct rtl8169_private *tp)
3546 {
3547 rtl_writephy(tp, 0x1f, 0x0000);
3548 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3549 }
3550
3551 static void r810x_pll_power_down(struct rtl8169_private *tp)
3552 {
3553 if (rtl_wol_pll_power_down(tp))
3554 return;
3555
3556 r810x_phy_power_down(tp);
3557 }
3558
3559 static void r810x_pll_power_up(struct rtl8169_private *tp)
3560 {
3561 r810x_phy_power_up(tp);
3562 }
3563
3564 static void r8168_phy_power_up(struct rtl8169_private *tp)
3565 {
3566 rtl_writephy(tp, 0x1f, 0x0000);
3567 switch (tp->mac_version) {
3568 case RTL_GIGA_MAC_VER_11:
3569 case RTL_GIGA_MAC_VER_12:
3570 case RTL_GIGA_MAC_VER_17:
3571 case RTL_GIGA_MAC_VER_18:
3572 case RTL_GIGA_MAC_VER_19:
3573 case RTL_GIGA_MAC_VER_20:
3574 case RTL_GIGA_MAC_VER_21:
3575 case RTL_GIGA_MAC_VER_22:
3576 case RTL_GIGA_MAC_VER_23:
3577 case RTL_GIGA_MAC_VER_24:
3578 case RTL_GIGA_MAC_VER_25:
3579 case RTL_GIGA_MAC_VER_26:
3580 case RTL_GIGA_MAC_VER_27:
3581 case RTL_GIGA_MAC_VER_28:
3582 case RTL_GIGA_MAC_VER_31:
3583 rtl_writephy(tp, 0x0e, 0x0000);
3584 break;
3585 default:
3586 break;
3587 }
3588 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3589 }
3590
3591 static void r8168_phy_power_down(struct rtl8169_private *tp)
3592 {
3593 rtl_writephy(tp, 0x1f, 0x0000);
3594 switch (tp->mac_version) {
3595 case RTL_GIGA_MAC_VER_32:
3596 case RTL_GIGA_MAC_VER_33:
3597 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3598 break;
3599
3600 case RTL_GIGA_MAC_VER_11:
3601 case RTL_GIGA_MAC_VER_12:
3602 case RTL_GIGA_MAC_VER_17:
3603 case RTL_GIGA_MAC_VER_18:
3604 case RTL_GIGA_MAC_VER_19:
3605 case RTL_GIGA_MAC_VER_20:
3606 case RTL_GIGA_MAC_VER_21:
3607 case RTL_GIGA_MAC_VER_22:
3608 case RTL_GIGA_MAC_VER_23:
3609 case RTL_GIGA_MAC_VER_24:
3610 case RTL_GIGA_MAC_VER_25:
3611 case RTL_GIGA_MAC_VER_26:
3612 case RTL_GIGA_MAC_VER_27:
3613 case RTL_GIGA_MAC_VER_28:
3614 case RTL_GIGA_MAC_VER_31:
3615 rtl_writephy(tp, 0x0e, 0x0200);
3616 default:
3617 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3618 break;
3619 }
3620 }
3621
3622 static void r8168_pll_power_down(struct rtl8169_private *tp)
3623 {
3624 void __iomem *ioaddr = tp->mmio_addr;
3625
3626 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3627 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3628 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3629 r8168dp_check_dash(tp)) {
3630 return;
3631 }
3632
3633 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3634 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3635 (RTL_R16(CPlusCmd) & ASF)) {
3636 return;
3637 }
3638
3639 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3640 tp->mac_version == RTL_GIGA_MAC_VER_33)
3641 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3642
3643 if (rtl_wol_pll_power_down(tp))
3644 return;
3645
3646 r8168_phy_power_down(tp);
3647
3648 switch (tp->mac_version) {
3649 case RTL_GIGA_MAC_VER_25:
3650 case RTL_GIGA_MAC_VER_26:
3651 case RTL_GIGA_MAC_VER_27:
3652 case RTL_GIGA_MAC_VER_28:
3653 case RTL_GIGA_MAC_VER_31:
3654 case RTL_GIGA_MAC_VER_32:
3655 case RTL_GIGA_MAC_VER_33:
3656 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3657 break;
3658 }
3659 }
3660
3661 static void r8168_pll_power_up(struct rtl8169_private *tp)
3662 {
3663 void __iomem *ioaddr = tp->mmio_addr;
3664
3665 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3666 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3667 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3668 r8168dp_check_dash(tp)) {
3669 return;
3670 }
3671
3672 switch (tp->mac_version) {
3673 case RTL_GIGA_MAC_VER_25:
3674 case RTL_GIGA_MAC_VER_26:
3675 case RTL_GIGA_MAC_VER_27:
3676 case RTL_GIGA_MAC_VER_28:
3677 case RTL_GIGA_MAC_VER_31:
3678 case RTL_GIGA_MAC_VER_32:
3679 case RTL_GIGA_MAC_VER_33:
3680 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3681 break;
3682 }
3683
3684 r8168_phy_power_up(tp);
3685 }
3686
3687 static void rtl_generic_op(struct rtl8169_private *tp,
3688 void (*op)(struct rtl8169_private *))
3689 {
3690 if (op)
3691 op(tp);
3692 }
3693
3694 static void rtl_pll_power_down(struct rtl8169_private *tp)
3695 {
3696 rtl_generic_op(tp, tp->pll_power_ops.down);
3697 }
3698
3699 static void rtl_pll_power_up(struct rtl8169_private *tp)
3700 {
3701 rtl_generic_op(tp, tp->pll_power_ops.up);
3702 }
3703
3704 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3705 {
3706 struct pll_power_ops *ops = &tp->pll_power_ops;
3707
3708 switch (tp->mac_version) {
3709 case RTL_GIGA_MAC_VER_07:
3710 case RTL_GIGA_MAC_VER_08:
3711 case RTL_GIGA_MAC_VER_09:
3712 case RTL_GIGA_MAC_VER_10:
3713 case RTL_GIGA_MAC_VER_16:
3714 case RTL_GIGA_MAC_VER_29:
3715 case RTL_GIGA_MAC_VER_30:
3716 ops->down = r810x_pll_power_down;
3717 ops->up = r810x_pll_power_up;
3718 break;
3719
3720 case RTL_GIGA_MAC_VER_11:
3721 case RTL_GIGA_MAC_VER_12:
3722 case RTL_GIGA_MAC_VER_17:
3723 case RTL_GIGA_MAC_VER_18:
3724 case RTL_GIGA_MAC_VER_19:
3725 case RTL_GIGA_MAC_VER_20:
3726 case RTL_GIGA_MAC_VER_21:
3727 case RTL_GIGA_MAC_VER_22:
3728 case RTL_GIGA_MAC_VER_23:
3729 case RTL_GIGA_MAC_VER_24:
3730 case RTL_GIGA_MAC_VER_25:
3731 case RTL_GIGA_MAC_VER_26:
3732 case RTL_GIGA_MAC_VER_27:
3733 case RTL_GIGA_MAC_VER_28:
3734 case RTL_GIGA_MAC_VER_31:
3735 case RTL_GIGA_MAC_VER_32:
3736 case RTL_GIGA_MAC_VER_33:
3737 case RTL_GIGA_MAC_VER_34:
3738 case RTL_GIGA_MAC_VER_35:
3739 case RTL_GIGA_MAC_VER_36:
3740 ops->down = r8168_pll_power_down;
3741 ops->up = r8168_pll_power_up;
3742 break;
3743
3744 default:
3745 ops->down = NULL;
3746 ops->up = NULL;
3747 break;
3748 }
3749 }
3750
3751 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3752 {
3753 void __iomem *ioaddr = tp->mmio_addr;
3754
3755 switch (tp->mac_version) {
3756 case RTL_GIGA_MAC_VER_01:
3757 case RTL_GIGA_MAC_VER_02:
3758 case RTL_GIGA_MAC_VER_03:
3759 case RTL_GIGA_MAC_VER_04:
3760 case RTL_GIGA_MAC_VER_05:
3761 case RTL_GIGA_MAC_VER_06:
3762 case RTL_GIGA_MAC_VER_10:
3763 case RTL_GIGA_MAC_VER_11:
3764 case RTL_GIGA_MAC_VER_12:
3765 case RTL_GIGA_MAC_VER_13:
3766 case RTL_GIGA_MAC_VER_14:
3767 case RTL_GIGA_MAC_VER_15:
3768 case RTL_GIGA_MAC_VER_16:
3769 case RTL_GIGA_MAC_VER_17:
3770 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3771 break;
3772 case RTL_GIGA_MAC_VER_18:
3773 case RTL_GIGA_MAC_VER_19:
3774 case RTL_GIGA_MAC_VER_20:
3775 case RTL_GIGA_MAC_VER_21:
3776 case RTL_GIGA_MAC_VER_22:
3777 case RTL_GIGA_MAC_VER_23:
3778 case RTL_GIGA_MAC_VER_24:
3779 case RTL_GIGA_MAC_VER_34:
3780 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3781 break;
3782 default:
3783 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3784 break;
3785 }
3786 }
3787
3788 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3789 {
3790 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3791 }
3792
3793 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3794 {
3795 void __iomem *ioaddr = tp->mmio_addr;
3796
3797 RTL_W8(Cfg9346, Cfg9346_Unlock);
3798 rtl_generic_op(tp, tp->jumbo_ops.enable);
3799 RTL_W8(Cfg9346, Cfg9346_Lock);
3800 }
3801
3802 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3803 {
3804 void __iomem *ioaddr = tp->mmio_addr;
3805
3806 RTL_W8(Cfg9346, Cfg9346_Unlock);
3807 rtl_generic_op(tp, tp->jumbo_ops.disable);
3808 RTL_W8(Cfg9346, Cfg9346_Lock);
3809 }
3810
3811 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3812 {
3813 void __iomem *ioaddr = tp->mmio_addr;
3814
3815 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3816 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
3817 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3818 }
3819
3820 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3821 {
3822 void __iomem *ioaddr = tp->mmio_addr;
3823
3824 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3825 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
3826 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3827 }
3828
3829 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3830 {
3831 void __iomem *ioaddr = tp->mmio_addr;
3832
3833 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3834 }
3835
3836 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3837 {
3838 void __iomem *ioaddr = tp->mmio_addr;
3839
3840 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3841 }
3842
3843 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3844 {
3845 void __iomem *ioaddr = tp->mmio_addr;
3846
3847 RTL_W8(MaxTxPacketSize, 0x3f);
3848 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3849 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
3850 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3851 }
3852
3853 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3854 {
3855 void __iomem *ioaddr = tp->mmio_addr;
3856
3857 RTL_W8(MaxTxPacketSize, 0x0c);
3858 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3859 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
3860 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3861 }
3862
3863 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3864 {
3865 rtl_tx_performance_tweak(tp->pci_dev,
3866 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3867 }
3868
3869 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3870 {
3871 rtl_tx_performance_tweak(tp->pci_dev,
3872 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3873 }
3874
3875 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3876 {
3877 void __iomem *ioaddr = tp->mmio_addr;
3878
3879 r8168b_0_hw_jumbo_enable(tp);
3880
3881 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
3882 }
3883
3884 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3885 {
3886 void __iomem *ioaddr = tp->mmio_addr;
3887
3888 r8168b_0_hw_jumbo_disable(tp);
3889
3890 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3891 }
3892
3893 static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
3894 {
3895 struct jumbo_ops *ops = &tp->jumbo_ops;
3896
3897 switch (tp->mac_version) {
3898 case RTL_GIGA_MAC_VER_11:
3899 ops->disable = r8168b_0_hw_jumbo_disable;
3900 ops->enable = r8168b_0_hw_jumbo_enable;
3901 break;
3902 case RTL_GIGA_MAC_VER_12:
3903 case RTL_GIGA_MAC_VER_17:
3904 ops->disable = r8168b_1_hw_jumbo_disable;
3905 ops->enable = r8168b_1_hw_jumbo_enable;
3906 break;
3907 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
3908 case RTL_GIGA_MAC_VER_19:
3909 case RTL_GIGA_MAC_VER_20:
3910 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
3911 case RTL_GIGA_MAC_VER_22:
3912 case RTL_GIGA_MAC_VER_23:
3913 case RTL_GIGA_MAC_VER_24:
3914 case RTL_GIGA_MAC_VER_25:
3915 case RTL_GIGA_MAC_VER_26:
3916 ops->disable = r8168c_hw_jumbo_disable;
3917 ops->enable = r8168c_hw_jumbo_enable;
3918 break;
3919 case RTL_GIGA_MAC_VER_27:
3920 case RTL_GIGA_MAC_VER_28:
3921 ops->disable = r8168dp_hw_jumbo_disable;
3922 ops->enable = r8168dp_hw_jumbo_enable;
3923 break;
3924 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
3925 case RTL_GIGA_MAC_VER_32:
3926 case RTL_GIGA_MAC_VER_33:
3927 case RTL_GIGA_MAC_VER_34:
3928 ops->disable = r8168e_hw_jumbo_disable;
3929 ops->enable = r8168e_hw_jumbo_enable;
3930 break;
3931
3932 /*
3933 * No action needed for jumbo frames with 8169.
3934 * No jumbo for 810x at all.
3935 */
3936 default:
3937 ops->disable = NULL;
3938 ops->enable = NULL;
3939 break;
3940 }
3941 }
3942
3943 static void rtl_hw_reset(struct rtl8169_private *tp)
3944 {
3945 void __iomem *ioaddr = tp->mmio_addr;
3946 int i;
3947
3948 /* Soft reset the chip. */
3949 RTL_W8(ChipCmd, CmdReset);
3950
3951 /* Check that the chip has finished the reset. */
3952 for (i = 0; i < 100; i++) {
3953 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3954 break;
3955 udelay(100);
3956 }
3957 }
3958
3959 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
3960 {
3961 struct rtl_fw *rtl_fw;
3962 const char *name;
3963 int rc = -ENOMEM;
3964
3965 name = rtl_lookup_firmware_name(tp);
3966 if (!name)
3967 goto out_no_firmware;
3968
3969 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
3970 if (!rtl_fw)
3971 goto err_warn;
3972
3973 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
3974 if (rc < 0)
3975 goto err_free;
3976
3977 rc = rtl_check_firmware(tp, rtl_fw);
3978 if (rc < 0)
3979 goto err_release_firmware;
3980
3981 tp->rtl_fw = rtl_fw;
3982 out:
3983 return;
3984
3985 err_release_firmware:
3986 release_firmware(rtl_fw->fw);
3987 err_free:
3988 kfree(rtl_fw);
3989 err_warn:
3990 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
3991 name, rc);
3992 out_no_firmware:
3993 tp->rtl_fw = NULL;
3994 goto out;
3995 }
3996
3997 static void rtl_request_firmware(struct rtl8169_private *tp)
3998 {
3999 if (IS_ERR(tp->rtl_fw))
4000 rtl_request_uncached_firmware(tp);
4001 }
4002
4003 static void rtl_rx_close(struct rtl8169_private *tp)
4004 {
4005 void __iomem *ioaddr = tp->mmio_addr;
4006
4007 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4008 }
4009
4010 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4011 {
4012 void __iomem *ioaddr = tp->mmio_addr;
4013
4014 /* Disable interrupts */
4015 rtl8169_irq_mask_and_ack(tp);
4016
4017 rtl_rx_close(tp);
4018
4019 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4020 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4021 tp->mac_version == RTL_GIGA_MAC_VER_31) {
4022 while (RTL_R8(TxPoll) & NPQ)
4023 udelay(20);
4024 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4025 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4026 tp->mac_version == RTL_GIGA_MAC_VER_36) {
4027 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4028 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
4029 udelay(100);
4030 } else {
4031 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4032 udelay(100);
4033 }
4034
4035 rtl_hw_reset(tp);
4036 }
4037
4038 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4039 {
4040 void __iomem *ioaddr = tp->mmio_addr;
4041
4042 /* Set DMA burst size and Interframe Gap Time */
4043 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4044 (InterFrameGap << TxInterFrameGapShift));
4045 }
4046
4047 static void rtl_hw_start(struct net_device *dev)
4048 {
4049 struct rtl8169_private *tp = netdev_priv(dev);
4050
4051 tp->hw_start(dev);
4052
4053 rtl_irq_enable_all(tp);
4054 }
4055
4056 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4057 void __iomem *ioaddr)
4058 {
4059 /*
4060 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4061 * register to be written before TxDescAddrLow to work.
4062 * Switching from MMIO to I/O access fixes the issue as well.
4063 */
4064 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4065 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4066 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4067 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4068 }
4069
4070 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4071 {
4072 u16 cmd;
4073
4074 cmd = RTL_R16(CPlusCmd);
4075 RTL_W16(CPlusCmd, cmd);
4076 return cmd;
4077 }
4078
4079 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4080 {
4081 /* Low hurts. Let's disable the filtering. */
4082 RTL_W16(RxMaxSize, rx_buf_sz + 1);
4083 }
4084
4085 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4086 {
4087 static const struct rtl_cfg2_info {
4088 u32 mac_version;
4089 u32 clk;
4090 u32 val;
4091 } cfg2_info [] = {
4092 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4093 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4094 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4095 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4096 };
4097 const struct rtl_cfg2_info *p = cfg2_info;
4098 unsigned int i;
4099 u32 clk;
4100
4101 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4102 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4103 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4104 RTL_W32(0x7c, p->val);
4105 break;
4106 }
4107 }
4108 }
4109
4110 static void rtl_set_rx_mode(struct net_device *dev)
4111 {
4112 struct rtl8169_private *tp = netdev_priv(dev);
4113 void __iomem *ioaddr = tp->mmio_addr;
4114 u32 mc_filter[2]; /* Multicast hash filter */
4115 int rx_mode;
4116 u32 tmp = 0;
4117
4118 if (dev->flags & IFF_PROMISC) {
4119 /* Unconditionally log net taps. */
4120 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4121 rx_mode =
4122 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4123 AcceptAllPhys;
4124 mc_filter[1] = mc_filter[0] = 0xffffffff;
4125 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4126 (dev->flags & IFF_ALLMULTI)) {
4127 /* Too many to filter perfectly -- accept all multicasts. */
4128 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4129 mc_filter[1] = mc_filter[0] = 0xffffffff;
4130 } else {
4131 struct netdev_hw_addr *ha;
4132
4133 rx_mode = AcceptBroadcast | AcceptMyPhys;
4134 mc_filter[1] = mc_filter[0] = 0;
4135 netdev_for_each_mc_addr(ha, dev) {
4136 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4137 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4138 rx_mode |= AcceptMulticast;
4139 }
4140 }
4141
4142 if (dev->features & NETIF_F_RXALL)
4143 rx_mode |= (AcceptErr | AcceptRunt);
4144
4145 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4146
4147 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4148 u32 data = mc_filter[0];
4149
4150 mc_filter[0] = swab32(mc_filter[1]);
4151 mc_filter[1] = swab32(data);
4152 }
4153
4154 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4155 mc_filter[1] = mc_filter[0] = 0xffffffff;
4156
4157 RTL_W32(MAR0 + 4, mc_filter[1]);
4158 RTL_W32(MAR0 + 0, mc_filter[0]);
4159
4160 RTL_W32(RxConfig, tmp);
4161 }
4162
4163 static void rtl_hw_start_8169(struct net_device *dev)
4164 {
4165 struct rtl8169_private *tp = netdev_priv(dev);
4166 void __iomem *ioaddr = tp->mmio_addr;
4167 struct pci_dev *pdev = tp->pci_dev;
4168
4169 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4170 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4171 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4172 }
4173
4174 RTL_W8(Cfg9346, Cfg9346_Unlock);
4175 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4176 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4177 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4178 tp->mac_version == RTL_GIGA_MAC_VER_04)
4179 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4180
4181 rtl_init_rxcfg(tp);
4182
4183 RTL_W8(EarlyTxThres, NoEarlyTx);
4184
4185 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4186
4187 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4188 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4189 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4190 tp->mac_version == RTL_GIGA_MAC_VER_04)
4191 rtl_set_rx_tx_config_registers(tp);
4192
4193 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4194
4195 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4196 tp->mac_version == RTL_GIGA_MAC_VER_03) {
4197 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4198 "Bit-3 and bit-14 MUST be 1\n");
4199 tp->cp_cmd |= (1 << 14);
4200 }
4201
4202 RTL_W16(CPlusCmd, tp->cp_cmd);
4203
4204 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4205
4206 /*
4207 * Undocumented corner. Supposedly:
4208 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4209 */
4210 RTL_W16(IntrMitigate, 0x0000);
4211
4212 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4213
4214 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4215 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4216 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4217 tp->mac_version != RTL_GIGA_MAC_VER_04) {
4218 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4219 rtl_set_rx_tx_config_registers(tp);
4220 }
4221
4222 RTL_W8(Cfg9346, Cfg9346_Lock);
4223
4224 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4225 RTL_R8(IntrMask);
4226
4227 RTL_W32(RxMissed, 0);
4228
4229 rtl_set_rx_mode(dev);
4230
4231 /* no early-rx interrupts */
4232 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4233 }
4234
4235 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
4236 {
4237 u32 csi;
4238
4239 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
4240 rtl_csi_write(ioaddr, 0x070c, csi | bits);
4241 }
4242
4243 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4244 {
4245 rtl_csi_access_enable(ioaddr, 0x17000000);
4246 }
4247
4248 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4249 {
4250 rtl_csi_access_enable(ioaddr, 0x27000000);
4251 }
4252
4253 struct ephy_info {
4254 unsigned int offset;
4255 u16 mask;
4256 u16 bits;
4257 };
4258
4259 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
4260 {
4261 u16 w;
4262
4263 while (len-- > 0) {
4264 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4265 rtl_ephy_write(ioaddr, e->offset, w);
4266 e++;
4267 }
4268 }
4269
4270 static void rtl_disable_clock_request(struct pci_dev *pdev)
4271 {
4272 int cap = pci_pcie_cap(pdev);
4273
4274 if (cap) {
4275 u16 ctl;
4276
4277 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4278 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4279 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4280 }
4281 }
4282
4283 static void rtl_enable_clock_request(struct pci_dev *pdev)
4284 {
4285 int cap = pci_pcie_cap(pdev);
4286
4287 if (cap) {
4288 u16 ctl;
4289
4290 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4291 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4292 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4293 }
4294 }
4295
4296 #define R8168_CPCMD_QUIRK_MASK (\
4297 EnableBist | \
4298 Mac_dbgo_oe | \
4299 Force_half_dup | \
4300 Force_rxflow_en | \
4301 Force_txflow_en | \
4302 Cxpl_dbg_sel | \
4303 ASF | \
4304 PktCntrDisable | \
4305 Mac_dbgo_sel)
4306
4307 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4308 {
4309 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4310
4311 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4312
4313 rtl_tx_performance_tweak(pdev,
4314 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4315 }
4316
4317 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4318 {
4319 rtl_hw_start_8168bb(ioaddr, pdev);
4320
4321 RTL_W8(MaxTxPacketSize, TxPacketMax);
4322
4323 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4324 }
4325
4326 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4327 {
4328 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4329
4330 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4331
4332 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4333
4334 rtl_disable_clock_request(pdev);
4335
4336 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4337 }
4338
4339 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
4340 {
4341 static const struct ephy_info e_info_8168cp[] = {
4342 { 0x01, 0, 0x0001 },
4343 { 0x02, 0x0800, 0x1000 },
4344 { 0x03, 0, 0x0042 },
4345 { 0x06, 0x0080, 0x0000 },
4346 { 0x07, 0, 0x2000 }
4347 };
4348
4349 rtl_csi_access_enable_2(ioaddr);
4350
4351 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4352
4353 __rtl_hw_start_8168cp(ioaddr, pdev);
4354 }
4355
4356 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4357 {
4358 rtl_csi_access_enable_2(ioaddr);
4359
4360 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4361
4362 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4363
4364 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4365 }
4366
4367 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4368 {
4369 rtl_csi_access_enable_2(ioaddr);
4370
4371 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4372
4373 /* Magic. */
4374 RTL_W8(DBG_REG, 0x20);
4375
4376 RTL_W8(MaxTxPacketSize, TxPacketMax);
4377
4378 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4379
4380 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4381 }
4382
4383 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4384 {
4385 static const struct ephy_info e_info_8168c_1[] = {
4386 { 0x02, 0x0800, 0x1000 },
4387 { 0x03, 0, 0x0002 },
4388 { 0x06, 0x0080, 0x0000 }
4389 };
4390
4391 rtl_csi_access_enable_2(ioaddr);
4392
4393 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4394
4395 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4396
4397 __rtl_hw_start_8168cp(ioaddr, pdev);
4398 }
4399
4400 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4401 {
4402 static const struct ephy_info e_info_8168c_2[] = {
4403 { 0x01, 0, 0x0001 },
4404 { 0x03, 0x0400, 0x0220 }
4405 };
4406
4407 rtl_csi_access_enable_2(ioaddr);
4408
4409 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4410
4411 __rtl_hw_start_8168cp(ioaddr, pdev);
4412 }
4413
4414 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4415 {
4416 rtl_hw_start_8168c_2(ioaddr, pdev);
4417 }
4418
4419 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4420 {
4421 rtl_csi_access_enable_2(ioaddr);
4422
4423 __rtl_hw_start_8168cp(ioaddr, pdev);
4424 }
4425
4426 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4427 {
4428 rtl_csi_access_enable_2(ioaddr);
4429
4430 rtl_disable_clock_request(pdev);
4431
4432 RTL_W8(MaxTxPacketSize, TxPacketMax);
4433
4434 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4435
4436 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4437 }
4438
4439 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4440 {
4441 rtl_csi_access_enable_1(ioaddr);
4442
4443 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4444
4445 RTL_W8(MaxTxPacketSize, TxPacketMax);
4446
4447 rtl_disable_clock_request(pdev);
4448 }
4449
4450 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4451 {
4452 static const struct ephy_info e_info_8168d_4[] = {
4453 { 0x0b, ~0, 0x48 },
4454 { 0x19, 0x20, 0x50 },
4455 { 0x0c, ~0, 0x20 }
4456 };
4457 int i;
4458
4459 rtl_csi_access_enable_1(ioaddr);
4460
4461 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4462
4463 RTL_W8(MaxTxPacketSize, TxPacketMax);
4464
4465 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4466 const struct ephy_info *e = e_info_8168d_4 + i;
4467 u16 w;
4468
4469 w = rtl_ephy_read(ioaddr, e->offset);
4470 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4471 }
4472
4473 rtl_enable_clock_request(pdev);
4474 }
4475
4476 static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4477 {
4478 static const struct ephy_info e_info_8168e_1[] = {
4479 { 0x00, 0x0200, 0x0100 },
4480 { 0x00, 0x0000, 0x0004 },
4481 { 0x06, 0x0002, 0x0001 },
4482 { 0x06, 0x0000, 0x0030 },
4483 { 0x07, 0x0000, 0x2000 },
4484 { 0x00, 0x0000, 0x0020 },
4485 { 0x03, 0x5800, 0x2000 },
4486 { 0x03, 0x0000, 0x0001 },
4487 { 0x01, 0x0800, 0x1000 },
4488 { 0x07, 0x0000, 0x4000 },
4489 { 0x1e, 0x0000, 0x2000 },
4490 { 0x19, 0xffff, 0xfe6c },
4491 { 0x0a, 0x0000, 0x0040 }
4492 };
4493
4494 rtl_csi_access_enable_2(ioaddr);
4495
4496 rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4497
4498 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4499
4500 RTL_W8(MaxTxPacketSize, TxPacketMax);
4501
4502 rtl_disable_clock_request(pdev);
4503
4504 /* Reset tx FIFO pointer */
4505 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4506 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4507
4508 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4509 }
4510
4511 static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4512 {
4513 static const struct ephy_info e_info_8168e_2[] = {
4514 { 0x09, 0x0000, 0x0080 },
4515 { 0x19, 0x0000, 0x0224 }
4516 };
4517
4518 rtl_csi_access_enable_1(ioaddr);
4519
4520 rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4521
4522 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4523
4524 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4525 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4526 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4527 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4528 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4529 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4530 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4531 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4532 ERIAR_EXGMAC);
4533
4534 RTL_W8(MaxTxPacketSize, EarlySize);
4535
4536 rtl_disable_clock_request(pdev);
4537
4538 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4539 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4540
4541 /* Adjust EEE LED frequency */
4542 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4543
4544 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4545 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4546 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4547 }
4548
4549 static void rtl_hw_start_8168f_1(void __iomem *ioaddr, struct pci_dev *pdev)
4550 {
4551 static const struct ephy_info e_info_8168f_1[] = {
4552 { 0x06, 0x00c0, 0x0020 },
4553 { 0x08, 0x0001, 0x0002 },
4554 { 0x09, 0x0000, 0x0080 },
4555 { 0x19, 0x0000, 0x0224 }
4556 };
4557
4558 rtl_csi_access_enable_1(ioaddr);
4559
4560 rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
4561
4562 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4563
4564 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4565 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4566 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4567 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4568 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
4569 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
4570 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4571 rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4572 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4573 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
4574 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4575 ERIAR_EXGMAC);
4576
4577 RTL_W8(MaxTxPacketSize, EarlySize);
4578
4579 rtl_disable_clock_request(pdev);
4580
4581 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4582 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4583
4584 /* Adjust EEE LED frequency */
4585 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4586
4587 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4588 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4589 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4590 }
4591
4592 static void rtl_hw_start_8168(struct net_device *dev)
4593 {
4594 struct rtl8169_private *tp = netdev_priv(dev);
4595 void __iomem *ioaddr = tp->mmio_addr;
4596 struct pci_dev *pdev = tp->pci_dev;
4597
4598 RTL_W8(Cfg9346, Cfg9346_Unlock);
4599
4600 RTL_W8(MaxTxPacketSize, TxPacketMax);
4601
4602 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4603
4604 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4605
4606 RTL_W16(CPlusCmd, tp->cp_cmd);
4607
4608 RTL_W16(IntrMitigate, 0x5151);
4609
4610 /* Work around for RxFIFO overflow. */
4611 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
4612 tp->event_slow |= RxFIFOOver | PCSTimeout;
4613 tp->event_slow &= ~RxOverflow;
4614 }
4615
4616 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4617
4618 rtl_set_rx_mode(dev);
4619
4620 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4621 (InterFrameGap << TxInterFrameGapShift));
4622
4623 RTL_R8(IntrMask);
4624
4625 switch (tp->mac_version) {
4626 case RTL_GIGA_MAC_VER_11:
4627 rtl_hw_start_8168bb(ioaddr, pdev);
4628 break;
4629
4630 case RTL_GIGA_MAC_VER_12:
4631 case RTL_GIGA_MAC_VER_17:
4632 rtl_hw_start_8168bef(ioaddr, pdev);
4633 break;
4634
4635 case RTL_GIGA_MAC_VER_18:
4636 rtl_hw_start_8168cp_1(ioaddr, pdev);
4637 break;
4638
4639 case RTL_GIGA_MAC_VER_19:
4640 rtl_hw_start_8168c_1(ioaddr, pdev);
4641 break;
4642
4643 case RTL_GIGA_MAC_VER_20:
4644 rtl_hw_start_8168c_2(ioaddr, pdev);
4645 break;
4646
4647 case RTL_GIGA_MAC_VER_21:
4648 rtl_hw_start_8168c_3(ioaddr, pdev);
4649 break;
4650
4651 case RTL_GIGA_MAC_VER_22:
4652 rtl_hw_start_8168c_4(ioaddr, pdev);
4653 break;
4654
4655 case RTL_GIGA_MAC_VER_23:
4656 rtl_hw_start_8168cp_2(ioaddr, pdev);
4657 break;
4658
4659 case RTL_GIGA_MAC_VER_24:
4660 rtl_hw_start_8168cp_3(ioaddr, pdev);
4661 break;
4662
4663 case RTL_GIGA_MAC_VER_25:
4664 case RTL_GIGA_MAC_VER_26:
4665 case RTL_GIGA_MAC_VER_27:
4666 rtl_hw_start_8168d(ioaddr, pdev);
4667 break;
4668
4669 case RTL_GIGA_MAC_VER_28:
4670 rtl_hw_start_8168d_4(ioaddr, pdev);
4671 break;
4672
4673 case RTL_GIGA_MAC_VER_31:
4674 rtl_hw_start_8168dp(ioaddr, pdev);
4675 break;
4676
4677 case RTL_GIGA_MAC_VER_32:
4678 case RTL_GIGA_MAC_VER_33:
4679 rtl_hw_start_8168e_1(ioaddr, pdev);
4680 break;
4681 case RTL_GIGA_MAC_VER_34:
4682 rtl_hw_start_8168e_2(ioaddr, pdev);
4683 break;
4684
4685 case RTL_GIGA_MAC_VER_35:
4686 case RTL_GIGA_MAC_VER_36:
4687 rtl_hw_start_8168f_1(ioaddr, pdev);
4688 break;
4689
4690 default:
4691 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4692 dev->name, tp->mac_version);
4693 break;
4694 }
4695
4696 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4697
4698 RTL_W8(Cfg9346, Cfg9346_Lock);
4699
4700 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4701 }
4702
4703 #define R810X_CPCMD_QUIRK_MASK (\
4704 EnableBist | \
4705 Mac_dbgo_oe | \
4706 Force_half_dup | \
4707 Force_rxflow_en | \
4708 Force_txflow_en | \
4709 Cxpl_dbg_sel | \
4710 ASF | \
4711 PktCntrDisable | \
4712 Mac_dbgo_sel)
4713
4714 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4715 {
4716 static const struct ephy_info e_info_8102e_1[] = {
4717 { 0x01, 0, 0x6e65 },
4718 { 0x02, 0, 0x091f },
4719 { 0x03, 0, 0xc2f9 },
4720 { 0x06, 0, 0xafb5 },
4721 { 0x07, 0, 0x0e00 },
4722 { 0x19, 0, 0xec80 },
4723 { 0x01, 0, 0x2e65 },
4724 { 0x01, 0, 0x6e65 }
4725 };
4726 u8 cfg1;
4727
4728 rtl_csi_access_enable_2(ioaddr);
4729
4730 RTL_W8(DBG_REG, FIX_NAK_1);
4731
4732 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4733
4734 RTL_W8(Config1,
4735 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4736 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4737
4738 cfg1 = RTL_R8(Config1);
4739 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4740 RTL_W8(Config1, cfg1 & ~LEDS0);
4741
4742 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4743 }
4744
4745 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4746 {
4747 rtl_csi_access_enable_2(ioaddr);
4748
4749 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4750
4751 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4752 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4753 }
4754
4755 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4756 {
4757 rtl_hw_start_8102e_2(ioaddr, pdev);
4758
4759 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4760 }
4761
4762 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4763 {
4764 static const struct ephy_info e_info_8105e_1[] = {
4765 { 0x07, 0, 0x4000 },
4766 { 0x19, 0, 0x0200 },
4767 { 0x19, 0, 0x0020 },
4768 { 0x1e, 0, 0x2000 },
4769 { 0x03, 0, 0x0001 },
4770 { 0x19, 0, 0x0100 },
4771 { 0x19, 0, 0x0004 },
4772 { 0x0a, 0, 0x0020 }
4773 };
4774
4775 /* Force LAN exit from ASPM if Rx/Tx are not idle */
4776 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4777
4778 /* Disable Early Tally Counter */
4779 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4780
4781 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4782 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4783
4784 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4785 }
4786
4787 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4788 {
4789 rtl_hw_start_8105e_1(ioaddr, pdev);
4790 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4791 }
4792
4793 static void rtl_hw_start_8101(struct net_device *dev)
4794 {
4795 struct rtl8169_private *tp = netdev_priv(dev);
4796 void __iomem *ioaddr = tp->mmio_addr;
4797 struct pci_dev *pdev = tp->pci_dev;
4798
4799 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
4800 tp->event_slow &= ~RxFIFOOver;
4801
4802 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4803 tp->mac_version == RTL_GIGA_MAC_VER_16) {
4804 int cap = pci_pcie_cap(pdev);
4805
4806 if (cap) {
4807 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4808 PCI_EXP_DEVCTL_NOSNOOP_EN);
4809 }
4810 }
4811
4812 RTL_W8(Cfg9346, Cfg9346_Unlock);
4813
4814 switch (tp->mac_version) {
4815 case RTL_GIGA_MAC_VER_07:
4816 rtl_hw_start_8102e_1(ioaddr, pdev);
4817 break;
4818
4819 case RTL_GIGA_MAC_VER_08:
4820 rtl_hw_start_8102e_3(ioaddr, pdev);
4821 break;
4822
4823 case RTL_GIGA_MAC_VER_09:
4824 rtl_hw_start_8102e_2(ioaddr, pdev);
4825 break;
4826
4827 case RTL_GIGA_MAC_VER_29:
4828 rtl_hw_start_8105e_1(ioaddr, pdev);
4829 break;
4830 case RTL_GIGA_MAC_VER_30:
4831 rtl_hw_start_8105e_2(ioaddr, pdev);
4832 break;
4833 }
4834
4835 RTL_W8(Cfg9346, Cfg9346_Lock);
4836
4837 RTL_W8(MaxTxPacketSize, TxPacketMax);
4838
4839 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4840
4841 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4842 RTL_W16(CPlusCmd, tp->cp_cmd);
4843
4844 RTL_W16(IntrMitigate, 0x0000);
4845
4846 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4847
4848 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4849 rtl_set_rx_tx_config_registers(tp);
4850
4851 RTL_R8(IntrMask);
4852
4853 rtl_set_rx_mode(dev);
4854
4855 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4856 }
4857
4858 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4859 {
4860 struct rtl8169_private *tp = netdev_priv(dev);
4861
4862 if (new_mtu < ETH_ZLEN ||
4863 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
4864 return -EINVAL;
4865
4866 if (new_mtu > ETH_DATA_LEN)
4867 rtl_hw_jumbo_enable(tp);
4868 else
4869 rtl_hw_jumbo_disable(tp);
4870
4871 dev->mtu = new_mtu;
4872 netdev_update_features(dev);
4873
4874 return 0;
4875 }
4876
4877 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4878 {
4879 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4880 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4881 }
4882
4883 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4884 void **data_buff, struct RxDesc *desc)
4885 {
4886 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4887 DMA_FROM_DEVICE);
4888
4889 kfree(*data_buff);
4890 *data_buff = NULL;
4891 rtl8169_make_unusable_by_asic(desc);
4892 }
4893
4894 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4895 {
4896 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4897
4898 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4899 }
4900
4901 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4902 u32 rx_buf_sz)
4903 {
4904 desc->addr = cpu_to_le64(mapping);
4905 wmb();
4906 rtl8169_mark_to_asic(desc, rx_buf_sz);
4907 }
4908
4909 static inline void *rtl8169_align(void *data)
4910 {
4911 return (void *)ALIGN((long)data, 16);
4912 }
4913
4914 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4915 struct RxDesc *desc)
4916 {
4917 void *data;
4918 dma_addr_t mapping;
4919 struct device *d = &tp->pci_dev->dev;
4920 struct net_device *dev = tp->dev;
4921 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4922
4923 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4924 if (!data)
4925 return NULL;
4926
4927 if (rtl8169_align(data) != data) {
4928 kfree(data);
4929 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4930 if (!data)
4931 return NULL;
4932 }
4933
4934 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4935 DMA_FROM_DEVICE);
4936 if (unlikely(dma_mapping_error(d, mapping))) {
4937 if (net_ratelimit())
4938 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4939 goto err_out;
4940 }
4941
4942 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4943 return data;
4944
4945 err_out:
4946 kfree(data);
4947 return NULL;
4948 }
4949
4950 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4951 {
4952 unsigned int i;
4953
4954 for (i = 0; i < NUM_RX_DESC; i++) {
4955 if (tp->Rx_databuff[i]) {
4956 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4957 tp->RxDescArray + i);
4958 }
4959 }
4960 }
4961
4962 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4963 {
4964 desc->opts1 |= cpu_to_le32(RingEnd);
4965 }
4966
4967 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4968 {
4969 unsigned int i;
4970
4971 for (i = 0; i < NUM_RX_DESC; i++) {
4972 void *data;
4973
4974 if (tp->Rx_databuff[i])
4975 continue;
4976
4977 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4978 if (!data) {
4979 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4980 goto err_out;
4981 }
4982 tp->Rx_databuff[i] = data;
4983 }
4984
4985 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4986 return 0;
4987
4988 err_out:
4989 rtl8169_rx_clear(tp);
4990 return -ENOMEM;
4991 }
4992
4993 static int rtl8169_init_ring(struct net_device *dev)
4994 {
4995 struct rtl8169_private *tp = netdev_priv(dev);
4996
4997 rtl8169_init_ring_indexes(tp);
4998
4999 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
5000 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
5001
5002 return rtl8169_rx_fill(tp);
5003 }
5004
5005 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5006 struct TxDesc *desc)
5007 {
5008 unsigned int len = tx_skb->len;
5009
5010 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5011
5012 desc->opts1 = 0x00;
5013 desc->opts2 = 0x00;
5014 desc->addr = 0x00;
5015 tx_skb->len = 0;
5016 }
5017
5018 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5019 unsigned int n)
5020 {
5021 unsigned int i;
5022
5023 for (i = 0; i < n; i++) {
5024 unsigned int entry = (start + i) % NUM_TX_DESC;
5025 struct ring_info *tx_skb = tp->tx_skb + entry;
5026 unsigned int len = tx_skb->len;
5027
5028 if (len) {
5029 struct sk_buff *skb = tx_skb->skb;
5030
5031 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5032 tp->TxDescArray + entry);
5033 if (skb) {
5034 tp->dev->stats.tx_dropped++;
5035 dev_kfree_skb(skb);
5036 tx_skb->skb = NULL;
5037 }
5038 }
5039 }
5040 }
5041
5042 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5043 {
5044 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5045 tp->cur_tx = tp->dirty_tx = 0;
5046 }
5047
5048 static void rtl_reset_work(struct rtl8169_private *tp)
5049 {
5050 struct net_device *dev = tp->dev;
5051 int i;
5052
5053 napi_disable(&tp->napi);
5054 netif_stop_queue(dev);
5055 synchronize_sched();
5056
5057 rtl8169_hw_reset(tp);
5058
5059 for (i = 0; i < NUM_RX_DESC; i++)
5060 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5061
5062 rtl8169_tx_clear(tp);
5063 rtl8169_init_ring_indexes(tp);
5064
5065 napi_enable(&tp->napi);
5066 rtl_hw_start(dev);
5067 netif_wake_queue(dev);
5068 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5069 }
5070
5071 static void rtl8169_tx_timeout(struct net_device *dev)
5072 {
5073 struct rtl8169_private *tp = netdev_priv(dev);
5074
5075 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5076 }
5077
5078 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5079 u32 *opts)
5080 {
5081 struct skb_shared_info *info = skb_shinfo(skb);
5082 unsigned int cur_frag, entry;
5083 struct TxDesc * uninitialized_var(txd);
5084 struct device *d = &tp->pci_dev->dev;
5085
5086 entry = tp->cur_tx;
5087 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5088 const skb_frag_t *frag = info->frags + cur_frag;
5089 dma_addr_t mapping;
5090 u32 status, len;
5091 void *addr;
5092
5093 entry = (entry + 1) % NUM_TX_DESC;
5094
5095 txd = tp->TxDescArray + entry;
5096 len = skb_frag_size(frag);
5097 addr = skb_frag_address(frag);
5098 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5099 if (unlikely(dma_mapping_error(d, mapping))) {
5100 if (net_ratelimit())
5101 netif_err(tp, drv, tp->dev,
5102 "Failed to map TX fragments DMA!\n");
5103 goto err_out;
5104 }
5105
5106 /* Anti gcc 2.95.3 bugware (sic) */
5107 status = opts[0] | len |
5108 (RingEnd * !((entry + 1) % NUM_TX_DESC));
5109
5110 txd->opts1 = cpu_to_le32(status);
5111 txd->opts2 = cpu_to_le32(opts[1]);
5112 txd->addr = cpu_to_le64(mapping);
5113
5114 tp->tx_skb[entry].len = len;
5115 }
5116
5117 if (cur_frag) {
5118 tp->tx_skb[entry].skb = skb;
5119 txd->opts1 |= cpu_to_le32(LastFrag);
5120 }
5121
5122 return cur_frag;
5123
5124 err_out:
5125 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5126 return -EIO;
5127 }
5128
5129 static bool rtl_skb_pad(struct sk_buff *skb)
5130 {
5131 if (skb_padto(skb, ETH_ZLEN))
5132 return false;
5133 skb_put(skb, ETH_ZLEN - skb->len);
5134 return true;
5135 }
5136
5137 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5138 {
5139 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5140 }
5141
5142 static inline bool rtl8169_tso_csum(struct rtl8169_private *tp,
5143 struct sk_buff *skb, u32 *opts)
5144 {
5145 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5146 u32 mss = skb_shinfo(skb)->gso_size;
5147 int offset = info->opts_offset;
5148
5149 if (mss) {
5150 opts[0] |= TD_LSO;
5151 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5152 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5153 const struct iphdr *ip = ip_hdr(skb);
5154
5155 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5156 return skb_checksum_help(skb) == 0 && rtl_skb_pad(skb);
5157
5158 if (ip->protocol == IPPROTO_TCP)
5159 opts[offset] |= info->checksum.tcp;
5160 else if (ip->protocol == IPPROTO_UDP)
5161 opts[offset] |= info->checksum.udp;
5162 else
5163 WARN_ON_ONCE(1);
5164 } else {
5165 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5166 return rtl_skb_pad(skb);
5167 }
5168 return true;
5169 }
5170
5171 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5172 struct net_device *dev)
5173 {
5174 struct rtl8169_private *tp = netdev_priv(dev);
5175 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5176 struct TxDesc *txd = tp->TxDescArray + entry;
5177 void __iomem *ioaddr = tp->mmio_addr;
5178 struct device *d = &tp->pci_dev->dev;
5179 dma_addr_t mapping;
5180 u32 status, len;
5181 u32 opts[2];
5182 int frags;
5183
5184 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
5185 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5186 goto err_stop_0;
5187 }
5188
5189 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5190 goto err_stop_0;
5191
5192 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5193 opts[0] = DescOwn;
5194
5195 if (!rtl8169_tso_csum(tp, skb, opts))
5196 goto err_update_stats;
5197
5198 len = skb_headlen(skb);
5199 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5200 if (unlikely(dma_mapping_error(d, mapping))) {
5201 if (net_ratelimit())
5202 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5203 goto err_dma_0;
5204 }
5205
5206 tp->tx_skb[entry].len = len;
5207 txd->addr = cpu_to_le64(mapping);
5208
5209 frags = rtl8169_xmit_frags(tp, skb, opts);
5210 if (frags < 0)
5211 goto err_dma_1;
5212 else if (frags)
5213 opts[0] |= FirstFrag;
5214 else {
5215 opts[0] |= FirstFrag | LastFrag;
5216 tp->tx_skb[entry].skb = skb;
5217 }
5218
5219 txd->opts2 = cpu_to_le32(opts[1]);
5220
5221 skb_tx_timestamp(skb);
5222
5223 wmb();
5224
5225 /* Anti gcc 2.95.3 bugware (sic) */
5226 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5227 txd->opts1 = cpu_to_le32(status);
5228
5229 tp->cur_tx += frags + 1;
5230
5231 wmb();
5232
5233 RTL_W8(TxPoll, NPQ);
5234
5235 mmiowb();
5236
5237 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
5238 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5239 * not miss a ring update when it notices a stopped queue.
5240 */
5241 smp_wmb();
5242 netif_stop_queue(dev);
5243 /* Sync with rtl_tx:
5244 * - publish queue status and cur_tx ring index (write barrier)
5245 * - refresh dirty_tx ring index (read barrier).
5246 * May the current thread have a pessimistic view of the ring
5247 * status and forget to wake up queue, a racing rtl_tx thread
5248 * can't.
5249 */
5250 smp_mb();
5251 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
5252 netif_wake_queue(dev);
5253 }
5254
5255 return NETDEV_TX_OK;
5256
5257 err_dma_1:
5258 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5259 err_dma_0:
5260 dev_kfree_skb(skb);
5261 err_update_stats:
5262 dev->stats.tx_dropped++;
5263 return NETDEV_TX_OK;
5264
5265 err_stop_0:
5266 netif_stop_queue(dev);
5267 dev->stats.tx_dropped++;
5268 return NETDEV_TX_BUSY;
5269 }
5270
5271 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5272 {
5273 struct rtl8169_private *tp = netdev_priv(dev);
5274 struct pci_dev *pdev = tp->pci_dev;
5275 u16 pci_status, pci_cmd;
5276
5277 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5278 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5279
5280 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5281 pci_cmd, pci_status);
5282
5283 /*
5284 * The recovery sequence below admits a very elaborated explanation:
5285 * - it seems to work;
5286 * - I did not see what else could be done;
5287 * - it makes iop3xx happy.
5288 *
5289 * Feel free to adjust to your needs.
5290 */
5291 if (pdev->broken_parity_status)
5292 pci_cmd &= ~PCI_COMMAND_PARITY;
5293 else
5294 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5295
5296 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5297
5298 pci_write_config_word(pdev, PCI_STATUS,
5299 pci_status & (PCI_STATUS_DETECTED_PARITY |
5300 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5301 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5302
5303 /* The infamous DAC f*ckup only happens at boot time */
5304 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
5305 void __iomem *ioaddr = tp->mmio_addr;
5306
5307 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5308 tp->cp_cmd &= ~PCIDAC;
5309 RTL_W16(CPlusCmd, tp->cp_cmd);
5310 dev->features &= ~NETIF_F_HIGHDMA;
5311 }
5312
5313 rtl8169_hw_reset(tp);
5314
5315 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5316 }
5317
5318 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
5319 {
5320 unsigned int dirty_tx, tx_left;
5321
5322 dirty_tx = tp->dirty_tx;
5323 smp_rmb();
5324 tx_left = tp->cur_tx - dirty_tx;
5325
5326 while (tx_left > 0) {
5327 unsigned int entry = dirty_tx % NUM_TX_DESC;
5328 struct ring_info *tx_skb = tp->tx_skb + entry;
5329 u32 status;
5330
5331 rmb();
5332 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5333 if (status & DescOwn)
5334 break;
5335
5336 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5337 tp->TxDescArray + entry);
5338 if (status & LastFrag) {
5339 u64_stats_update_begin(&tp->tx_stats.syncp);
5340 tp->tx_stats.packets++;
5341 tp->tx_stats.bytes += tx_skb->skb->len;
5342 u64_stats_update_end(&tp->tx_stats.syncp);
5343 dev_kfree_skb(tx_skb->skb);
5344 tx_skb->skb = NULL;
5345 }
5346 dirty_tx++;
5347 tx_left--;
5348 }
5349
5350 if (tp->dirty_tx != dirty_tx) {
5351 tp->dirty_tx = dirty_tx;
5352 /* Sync with rtl8169_start_xmit:
5353 * - publish dirty_tx ring index (write barrier)
5354 * - refresh cur_tx ring index and queue status (read barrier)
5355 * May the current thread miss the stopped queue condition,
5356 * a racing xmit thread can only have a right view of the
5357 * ring status.
5358 */
5359 smp_mb();
5360 if (netif_queue_stopped(dev) &&
5361 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
5362 netif_wake_queue(dev);
5363 }
5364 /*
5365 * 8168 hack: TxPoll requests are lost when the Tx packets are
5366 * too close. Let's kick an extra TxPoll request when a burst
5367 * of start_xmit activity is detected (if it is not detected,
5368 * it is slow enough). -- FR
5369 */
5370 if (tp->cur_tx != dirty_tx) {
5371 void __iomem *ioaddr = tp->mmio_addr;
5372
5373 RTL_W8(TxPoll, NPQ);
5374 }
5375 }
5376 }
5377
5378 static inline int rtl8169_fragmented_frame(u32 status)
5379 {
5380 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5381 }
5382
5383 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5384 {
5385 u32 status = opts1 & RxProtoMask;
5386
5387 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5388 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5389 skb->ip_summed = CHECKSUM_UNNECESSARY;
5390 else
5391 skb_checksum_none_assert(skb);
5392 }
5393
5394 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5395 struct rtl8169_private *tp,
5396 int pkt_size,
5397 dma_addr_t addr)
5398 {
5399 struct sk_buff *skb;
5400 struct device *d = &tp->pci_dev->dev;
5401
5402 data = rtl8169_align(data);
5403 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5404 prefetch(data);
5405 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5406 if (skb)
5407 memcpy(skb->data, data, pkt_size);
5408 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5409
5410 return skb;
5411 }
5412
5413 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
5414 {
5415 unsigned int cur_rx, rx_left;
5416 unsigned int count;
5417
5418 cur_rx = tp->cur_rx;
5419 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5420 rx_left = min(rx_left, budget);
5421
5422 for (; rx_left > 0; rx_left--, cur_rx++) {
5423 unsigned int entry = cur_rx % NUM_RX_DESC;
5424 struct RxDesc *desc = tp->RxDescArray + entry;
5425 u32 status;
5426
5427 rmb();
5428 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
5429
5430 if (status & DescOwn)
5431 break;
5432 if (unlikely(status & RxRES)) {
5433 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5434 status);
5435 dev->stats.rx_errors++;
5436 if (status & (RxRWT | RxRUNT))
5437 dev->stats.rx_length_errors++;
5438 if (status & RxCRC)
5439 dev->stats.rx_crc_errors++;
5440 if (status & RxFOVF) {
5441 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5442 dev->stats.rx_fifo_errors++;
5443 }
5444 if ((status & (RxRUNT | RxCRC)) &&
5445 !(status & (RxRWT | RxFOVF)) &&
5446 (dev->features & NETIF_F_RXALL))
5447 goto process_pkt;
5448 } else {
5449 struct sk_buff *skb;
5450 dma_addr_t addr;
5451 int pkt_size;
5452
5453 process_pkt:
5454 addr = le64_to_cpu(desc->addr);
5455 if (likely(!(dev->features & NETIF_F_RXFCS)))
5456 pkt_size = (status & 0x00003fff) - 4;
5457 else
5458 pkt_size = status & 0x00003fff;
5459
5460 /*
5461 * The driver does not support incoming fragmented
5462 * frames. They are seen as a symptom of over-mtu
5463 * sized frames.
5464 */
5465 if (unlikely(rtl8169_fragmented_frame(status))) {
5466 dev->stats.rx_dropped++;
5467 dev->stats.rx_length_errors++;
5468 goto release_descriptor;
5469 }
5470
5471 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5472 tp, pkt_size, addr);
5473 if (!skb) {
5474 dev->stats.rx_dropped++;
5475 goto release_descriptor;
5476 }
5477
5478 rtl8169_rx_csum(skb, status);
5479 skb_put(skb, pkt_size);
5480 skb->protocol = eth_type_trans(skb, dev);
5481
5482 rtl8169_rx_vlan_tag(desc, skb);
5483
5484 napi_gro_receive(&tp->napi, skb);
5485
5486 u64_stats_update_begin(&tp->rx_stats.syncp);
5487 tp->rx_stats.packets++;
5488 tp->rx_stats.bytes += pkt_size;
5489 u64_stats_update_end(&tp->rx_stats.syncp);
5490 }
5491 release_descriptor:
5492 desc->opts2 = 0;
5493 wmb();
5494 rtl8169_mark_to_asic(desc, rx_buf_sz);
5495 }
5496
5497 count = cur_rx - tp->cur_rx;
5498 tp->cur_rx = cur_rx;
5499
5500 tp->dirty_rx += count;
5501
5502 return count;
5503 }
5504
5505 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5506 {
5507 struct net_device *dev = dev_instance;
5508 struct rtl8169_private *tp = netdev_priv(dev);
5509 int handled = 0;
5510 u16 status;
5511
5512 status = rtl_get_events(tp);
5513 if (status && status != 0xffff) {
5514 status &= RTL_EVENT_NAPI | tp->event_slow;
5515 if (status) {
5516 handled = 1;
5517
5518 rtl_irq_disable(tp);
5519 napi_schedule(&tp->napi);
5520 }
5521 }
5522 return IRQ_RETVAL(handled);
5523 }
5524
5525 /*
5526 * Workqueue context.
5527 */
5528 static void rtl_slow_event_work(struct rtl8169_private *tp)
5529 {
5530 struct net_device *dev = tp->dev;
5531 u16 status;
5532
5533 status = rtl_get_events(tp) & tp->event_slow;
5534 rtl_ack_events(tp, status);
5535
5536 if (unlikely(status & RxFIFOOver)) {
5537 switch (tp->mac_version) {
5538 /* Work around for rx fifo overflow */
5539 case RTL_GIGA_MAC_VER_11:
5540 netif_stop_queue(dev);
5541 /* XXX - Hack alert. See rtl_task(). */
5542 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
5543 default:
5544 break;
5545 }
5546 }
5547
5548 if (unlikely(status & SYSErr))
5549 rtl8169_pcierr_interrupt(dev);
5550
5551 if (status & LinkChg)
5552 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
5553
5554 rtl_irq_enable_all(tp);
5555 }
5556
5557 static void rtl_task(struct work_struct *work)
5558 {
5559 static const struct {
5560 int bitnr;
5561 void (*action)(struct rtl8169_private *);
5562 } rtl_work[] = {
5563 /* XXX - keep rtl_slow_event_work() as first element. */
5564 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
5565 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
5566 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
5567 };
5568 struct rtl8169_private *tp =
5569 container_of(work, struct rtl8169_private, wk.work);
5570 struct net_device *dev = tp->dev;
5571 int i;
5572
5573 rtl_lock_work(tp);
5574
5575 if (!netif_running(dev) ||
5576 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
5577 goto out_unlock;
5578
5579 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
5580 bool pending;
5581
5582 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
5583 if (pending)
5584 rtl_work[i].action(tp);
5585 }
5586
5587 out_unlock:
5588 rtl_unlock_work(tp);
5589 }
5590
5591 static int rtl8169_poll(struct napi_struct *napi, int budget)
5592 {
5593 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5594 struct net_device *dev = tp->dev;
5595 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
5596 int work_done= 0;
5597 u16 status;
5598
5599 status = rtl_get_events(tp);
5600 rtl_ack_events(tp, status & ~tp->event_slow);
5601
5602 if (status & RTL_EVENT_NAPI_RX)
5603 work_done = rtl_rx(dev, tp, (u32) budget);
5604
5605 if (status & RTL_EVENT_NAPI_TX)
5606 rtl_tx(dev, tp);
5607
5608 if (status & tp->event_slow) {
5609 enable_mask &= ~tp->event_slow;
5610
5611 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
5612 }
5613
5614 if (work_done < budget) {
5615 napi_complete(napi);
5616
5617 rtl_irq_enable(tp, enable_mask);
5618 mmiowb();
5619 }
5620
5621 return work_done;
5622 }
5623
5624 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5625 {
5626 struct rtl8169_private *tp = netdev_priv(dev);
5627
5628 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5629 return;
5630
5631 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5632 RTL_W32(RxMissed, 0);
5633 }
5634
5635 static void rtl8169_down(struct net_device *dev)
5636 {
5637 struct rtl8169_private *tp = netdev_priv(dev);
5638 void __iomem *ioaddr = tp->mmio_addr;
5639
5640 del_timer_sync(&tp->timer);
5641
5642 napi_disable(&tp->napi);
5643 netif_stop_queue(dev);
5644
5645 rtl8169_hw_reset(tp);
5646 /*
5647 * At this point device interrupts can not be enabled in any function,
5648 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
5649 * and napi is disabled (rtl8169_poll).
5650 */
5651 rtl8169_rx_missed(dev, ioaddr);
5652
5653 /* Give a racing hard_start_xmit a few cycles to complete. */
5654 synchronize_sched();
5655
5656 rtl8169_tx_clear(tp);
5657
5658 rtl8169_rx_clear(tp);
5659
5660 rtl_pll_power_down(tp);
5661 }
5662
5663 static int rtl8169_close(struct net_device *dev)
5664 {
5665 struct rtl8169_private *tp = netdev_priv(dev);
5666 struct pci_dev *pdev = tp->pci_dev;
5667
5668 pm_runtime_get_sync(&pdev->dev);
5669
5670 /* Update counters before going down */
5671 rtl8169_update_counters(dev);
5672
5673 rtl_lock_work(tp);
5674 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5675
5676 rtl8169_down(dev);
5677 rtl_unlock_work(tp);
5678
5679 free_irq(pdev->irq, dev);
5680
5681 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5682 tp->RxPhyAddr);
5683 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5684 tp->TxPhyAddr);
5685 tp->TxDescArray = NULL;
5686 tp->RxDescArray = NULL;
5687
5688 pm_runtime_put_sync(&pdev->dev);
5689
5690 return 0;
5691 }
5692
5693 #ifdef CONFIG_NET_POLL_CONTROLLER
5694 static void rtl8169_netpoll(struct net_device *dev)
5695 {
5696 struct rtl8169_private *tp = netdev_priv(dev);
5697
5698 rtl8169_interrupt(tp->pci_dev->irq, dev);
5699 }
5700 #endif
5701
5702 static int rtl_open(struct net_device *dev)
5703 {
5704 struct rtl8169_private *tp = netdev_priv(dev);
5705 void __iomem *ioaddr = tp->mmio_addr;
5706 struct pci_dev *pdev = tp->pci_dev;
5707 int retval = -ENOMEM;
5708
5709 pm_runtime_get_sync(&pdev->dev);
5710
5711 /*
5712 * Rx and Tx desscriptors needs 256 bytes alignment.
5713 * dma_alloc_coherent provides more.
5714 */
5715 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
5716 &tp->TxPhyAddr, GFP_KERNEL);
5717 if (!tp->TxDescArray)
5718 goto err_pm_runtime_put;
5719
5720 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
5721 &tp->RxPhyAddr, GFP_KERNEL);
5722 if (!tp->RxDescArray)
5723 goto err_free_tx_0;
5724
5725 retval = rtl8169_init_ring(dev);
5726 if (retval < 0)
5727 goto err_free_rx_1;
5728
5729 INIT_WORK(&tp->wk.work, rtl_task);
5730
5731 smp_mb();
5732
5733 rtl_request_firmware(tp);
5734
5735 retval = request_irq(pdev->irq, rtl8169_interrupt,
5736 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
5737 dev->name, dev);
5738 if (retval < 0)
5739 goto err_release_fw_2;
5740
5741 rtl_lock_work(tp);
5742
5743 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5744
5745 napi_enable(&tp->napi);
5746
5747 rtl8169_init_phy(dev, tp);
5748
5749 __rtl8169_set_features(dev, dev->features);
5750
5751 rtl_pll_power_up(tp);
5752
5753 rtl_hw_start(dev);
5754
5755 netif_start_queue(dev);
5756
5757 rtl_unlock_work(tp);
5758
5759 tp->saved_wolopts = 0;
5760 pm_runtime_put_noidle(&pdev->dev);
5761
5762 rtl8169_check_link_status(dev, tp, ioaddr);
5763 out:
5764 return retval;
5765
5766 err_release_fw_2:
5767 rtl_release_firmware(tp);
5768 rtl8169_rx_clear(tp);
5769 err_free_rx_1:
5770 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5771 tp->RxPhyAddr);
5772 tp->RxDescArray = NULL;
5773 err_free_tx_0:
5774 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5775 tp->TxPhyAddr);
5776 tp->TxDescArray = NULL;
5777 err_pm_runtime_put:
5778 pm_runtime_put_noidle(&pdev->dev);
5779 goto out;
5780 }
5781
5782 static struct rtnl_link_stats64 *
5783 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
5784 {
5785 struct rtl8169_private *tp = netdev_priv(dev);
5786 void __iomem *ioaddr = tp->mmio_addr;
5787 unsigned int start;
5788
5789 if (netif_running(dev))
5790 rtl8169_rx_missed(dev, ioaddr);
5791
5792 do {
5793 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
5794 stats->rx_packets = tp->rx_stats.packets;
5795 stats->rx_bytes = tp->rx_stats.bytes;
5796 } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
5797
5798
5799 do {
5800 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
5801 stats->tx_packets = tp->tx_stats.packets;
5802 stats->tx_bytes = tp->tx_stats.bytes;
5803 } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
5804
5805 stats->rx_dropped = dev->stats.rx_dropped;
5806 stats->tx_dropped = dev->stats.tx_dropped;
5807 stats->rx_length_errors = dev->stats.rx_length_errors;
5808 stats->rx_errors = dev->stats.rx_errors;
5809 stats->rx_crc_errors = dev->stats.rx_crc_errors;
5810 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
5811 stats->rx_missed_errors = dev->stats.rx_missed_errors;
5812
5813 return stats;
5814 }
5815
5816 static void rtl8169_net_suspend(struct net_device *dev)
5817 {
5818 struct rtl8169_private *tp = netdev_priv(dev);
5819
5820 if (!netif_running(dev))
5821 return;
5822
5823 netif_device_detach(dev);
5824 netif_stop_queue(dev);
5825
5826 rtl_lock_work(tp);
5827 napi_disable(&tp->napi);
5828 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5829 rtl_unlock_work(tp);
5830
5831 rtl_pll_power_down(tp);
5832 }
5833
5834 #ifdef CONFIG_PM
5835
5836 static int rtl8169_suspend(struct device *device)
5837 {
5838 struct pci_dev *pdev = to_pci_dev(device);
5839 struct net_device *dev = pci_get_drvdata(pdev);
5840
5841 rtl8169_net_suspend(dev);
5842
5843 return 0;
5844 }
5845
5846 static void __rtl8169_resume(struct net_device *dev)
5847 {
5848 struct rtl8169_private *tp = netdev_priv(dev);
5849
5850 netif_device_attach(dev);
5851
5852 rtl_pll_power_up(tp);
5853
5854 rtl_lock_work(tp);
5855 napi_enable(&tp->napi);
5856 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5857 rtl_unlock_work(tp);
5858
5859 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5860 }
5861
5862 static int rtl8169_resume(struct device *device)
5863 {
5864 struct pci_dev *pdev = to_pci_dev(device);
5865 struct net_device *dev = pci_get_drvdata(pdev);
5866 struct rtl8169_private *tp = netdev_priv(dev);
5867
5868 rtl8169_init_phy(dev, tp);
5869
5870 if (netif_running(dev))
5871 __rtl8169_resume(dev);
5872
5873 return 0;
5874 }
5875
5876 static int rtl8169_runtime_suspend(struct device *device)
5877 {
5878 struct pci_dev *pdev = to_pci_dev(device);
5879 struct net_device *dev = pci_get_drvdata(pdev);
5880 struct rtl8169_private *tp = netdev_priv(dev);
5881
5882 if (!tp->TxDescArray)
5883 return 0;
5884
5885 rtl_lock_work(tp);
5886 tp->saved_wolopts = __rtl8169_get_wol(tp);
5887 __rtl8169_set_wol(tp, WAKE_ANY);
5888 rtl_unlock_work(tp);
5889
5890 rtl8169_net_suspend(dev);
5891
5892 return 0;
5893 }
5894
5895 static int rtl8169_runtime_resume(struct device *device)
5896 {
5897 struct pci_dev *pdev = to_pci_dev(device);
5898 struct net_device *dev = pci_get_drvdata(pdev);
5899 struct rtl8169_private *tp = netdev_priv(dev);
5900
5901 if (!tp->TxDescArray)
5902 return 0;
5903
5904 rtl_lock_work(tp);
5905 __rtl8169_set_wol(tp, tp->saved_wolopts);
5906 tp->saved_wolopts = 0;
5907 rtl_unlock_work(tp);
5908
5909 rtl8169_init_phy(dev, tp);
5910
5911 __rtl8169_resume(dev);
5912
5913 return 0;
5914 }
5915
5916 static int rtl8169_runtime_idle(struct device *device)
5917 {
5918 struct pci_dev *pdev = to_pci_dev(device);
5919 struct net_device *dev = pci_get_drvdata(pdev);
5920 struct rtl8169_private *tp = netdev_priv(dev);
5921
5922 return tp->TxDescArray ? -EBUSY : 0;
5923 }
5924
5925 static const struct dev_pm_ops rtl8169_pm_ops = {
5926 .suspend = rtl8169_suspend,
5927 .resume = rtl8169_resume,
5928 .freeze = rtl8169_suspend,
5929 .thaw = rtl8169_resume,
5930 .poweroff = rtl8169_suspend,
5931 .restore = rtl8169_resume,
5932 .runtime_suspend = rtl8169_runtime_suspend,
5933 .runtime_resume = rtl8169_runtime_resume,
5934 .runtime_idle = rtl8169_runtime_idle,
5935 };
5936
5937 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
5938
5939 #else /* !CONFIG_PM */
5940
5941 #define RTL8169_PM_OPS NULL
5942
5943 #endif /* !CONFIG_PM */
5944
5945 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
5946 {
5947 void __iomem *ioaddr = tp->mmio_addr;
5948
5949 /* WoL fails with 8168b when the receiver is disabled. */
5950 switch (tp->mac_version) {
5951 case RTL_GIGA_MAC_VER_11:
5952 case RTL_GIGA_MAC_VER_12:
5953 case RTL_GIGA_MAC_VER_17:
5954 pci_clear_master(tp->pci_dev);
5955
5956 RTL_W8(ChipCmd, CmdRxEnb);
5957 /* PCI commit */
5958 RTL_R8(ChipCmd);
5959 break;
5960 default:
5961 break;
5962 }
5963 }
5964
5965 static void rtl_shutdown(struct pci_dev *pdev)
5966 {
5967 struct net_device *dev = pci_get_drvdata(pdev);
5968 struct rtl8169_private *tp = netdev_priv(dev);
5969 struct device *d = &pdev->dev;
5970
5971 pm_runtime_get_sync(d);
5972
5973 rtl8169_net_suspend(dev);
5974
5975 /* Restore original MAC address */
5976 rtl_rar_set(tp, dev->perm_addr);
5977
5978 rtl8169_hw_reset(tp);
5979
5980 if (system_state == SYSTEM_POWER_OFF) {
5981 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
5982 rtl_wol_suspend_quirk(tp);
5983 rtl_wol_shutdown_quirk(tp);
5984 }
5985
5986 pci_wake_from_d3(pdev, true);
5987 pci_set_power_state(pdev, PCI_D3hot);
5988 }
5989
5990 pm_runtime_put_noidle(d);
5991 }
5992
5993 static void __devexit rtl_remove_one(struct pci_dev *pdev)
5994 {
5995 struct net_device *dev = pci_get_drvdata(pdev);
5996 struct rtl8169_private *tp = netdev_priv(dev);
5997
5998 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
5999 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6000 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6001 rtl8168_driver_stop(tp);
6002 }
6003
6004 cancel_work_sync(&tp->wk.work);
6005
6006 netif_napi_del(&tp->napi);
6007
6008 unregister_netdev(dev);
6009
6010 rtl_release_firmware(tp);
6011
6012 if (pci_dev_run_wake(pdev))
6013 pm_runtime_get_noresume(&pdev->dev);
6014
6015 /* restore original MAC address */
6016 rtl_rar_set(tp, dev->perm_addr);
6017
6018 rtl_disable_msi(pdev, tp);
6019 rtl8169_release_board(pdev, dev, tp->mmio_addr);
6020 pci_set_drvdata(pdev, NULL);
6021 }
6022
6023 static const struct net_device_ops rtl_netdev_ops = {
6024 .ndo_open = rtl_open,
6025 .ndo_stop = rtl8169_close,
6026 .ndo_get_stats64 = rtl8169_get_stats64,
6027 .ndo_start_xmit = rtl8169_start_xmit,
6028 .ndo_tx_timeout = rtl8169_tx_timeout,
6029 .ndo_validate_addr = eth_validate_addr,
6030 .ndo_change_mtu = rtl8169_change_mtu,
6031 .ndo_fix_features = rtl8169_fix_features,
6032 .ndo_set_features = rtl8169_set_features,
6033 .ndo_set_mac_address = rtl_set_mac_address,
6034 .ndo_do_ioctl = rtl8169_ioctl,
6035 .ndo_set_rx_mode = rtl_set_rx_mode,
6036 #ifdef CONFIG_NET_POLL_CONTROLLER
6037 .ndo_poll_controller = rtl8169_netpoll,
6038 #endif
6039
6040 };
6041
6042 static const struct rtl_cfg_info {
6043 void (*hw_start)(struct net_device *);
6044 unsigned int region;
6045 unsigned int align;
6046 u16 event_slow;
6047 unsigned features;
6048 u8 default_ver;
6049 } rtl_cfg_infos [] = {
6050 [RTL_CFG_0] = {
6051 .hw_start = rtl_hw_start_8169,
6052 .region = 1,
6053 .align = 0,
6054 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6055 .features = RTL_FEATURE_GMII,
6056 .default_ver = RTL_GIGA_MAC_VER_01,
6057 },
6058 [RTL_CFG_1] = {
6059 .hw_start = rtl_hw_start_8168,
6060 .region = 2,
6061 .align = 8,
6062 .event_slow = SYSErr | LinkChg | RxOverflow,
6063 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
6064 .default_ver = RTL_GIGA_MAC_VER_11,
6065 },
6066 [RTL_CFG_2] = {
6067 .hw_start = rtl_hw_start_8101,
6068 .region = 2,
6069 .align = 8,
6070 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
6071 PCSTimeout,
6072 .features = RTL_FEATURE_MSI,
6073 .default_ver = RTL_GIGA_MAC_VER_13,
6074 }
6075 };
6076
6077 /* Cfg9346_Unlock assumed. */
6078 static unsigned rtl_try_msi(struct rtl8169_private *tp,
6079 const struct rtl_cfg_info *cfg)
6080 {
6081 void __iomem *ioaddr = tp->mmio_addr;
6082 unsigned msi = 0;
6083 u8 cfg2;
6084
6085 cfg2 = RTL_R8(Config2) & ~MSIEnable;
6086 if (cfg->features & RTL_FEATURE_MSI) {
6087 if (pci_enable_msi(tp->pci_dev)) {
6088 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6089 } else {
6090 cfg2 |= MSIEnable;
6091 msi = RTL_FEATURE_MSI;
6092 }
6093 }
6094 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6095 RTL_W8(Config2, cfg2);
6096 return msi;
6097 }
6098
6099 static int __devinit
6100 rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6101 {
6102 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6103 const unsigned int region = cfg->region;
6104 struct rtl8169_private *tp;
6105 struct mii_if_info *mii;
6106 struct net_device *dev;
6107 void __iomem *ioaddr;
6108 int chipset, i;
6109 int rc;
6110
6111 if (netif_msg_drv(&debug)) {
6112 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6113 MODULENAME, RTL8169_VERSION);
6114 }
6115
6116 dev = alloc_etherdev(sizeof (*tp));
6117 if (!dev) {
6118 rc = -ENOMEM;
6119 goto out;
6120 }
6121
6122 SET_NETDEV_DEV(dev, &pdev->dev);
6123 dev->netdev_ops = &rtl_netdev_ops;
6124 tp = netdev_priv(dev);
6125 tp->dev = dev;
6126 tp->pci_dev = pdev;
6127 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6128
6129 mii = &tp->mii;
6130 mii->dev = dev;
6131 mii->mdio_read = rtl_mdio_read;
6132 mii->mdio_write = rtl_mdio_write;
6133 mii->phy_id_mask = 0x1f;
6134 mii->reg_num_mask = 0x1f;
6135 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6136
6137 /* disable ASPM completely as that cause random device stop working
6138 * problems as well as full system hangs for some PCIe devices users */
6139 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6140 PCIE_LINK_STATE_CLKPM);
6141
6142 /* enable device (incl. PCI PM wakeup and hotplug setup) */
6143 rc = pci_enable_device(pdev);
6144 if (rc < 0) {
6145 netif_err(tp, probe, dev, "enable failure\n");
6146 goto err_out_free_dev_1;
6147 }
6148
6149 if (pci_set_mwi(pdev) < 0)
6150 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
6151
6152 /* make sure PCI base addr 1 is MMIO */
6153 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
6154 netif_err(tp, probe, dev,
6155 "region #%d not an MMIO resource, aborting\n",
6156 region);
6157 rc = -ENODEV;
6158 goto err_out_mwi_2;
6159 }
6160
6161 /* check for weird/broken PCI region reporting */
6162 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6163 netif_err(tp, probe, dev,
6164 "Invalid PCI region size(s), aborting\n");
6165 rc = -ENODEV;
6166 goto err_out_mwi_2;
6167 }
6168
6169 rc = pci_request_regions(pdev, MODULENAME);
6170 if (rc < 0) {
6171 netif_err(tp, probe, dev, "could not request regions\n");
6172 goto err_out_mwi_2;
6173 }
6174
6175 tp->cp_cmd = RxChkSum;
6176
6177 if ((sizeof(dma_addr_t) > 4) &&
6178 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
6179 tp->cp_cmd |= PCIDAC;
6180 dev->features |= NETIF_F_HIGHDMA;
6181 } else {
6182 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6183 if (rc < 0) {
6184 netif_err(tp, probe, dev, "DMA configuration failed\n");
6185 goto err_out_free_res_3;
6186 }
6187 }
6188
6189 /* ioremap MMIO region */
6190 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
6191 if (!ioaddr) {
6192 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
6193 rc = -EIO;
6194 goto err_out_free_res_3;
6195 }
6196 tp->mmio_addr = ioaddr;
6197
6198 if (!pci_is_pcie(pdev))
6199 netif_info(tp, probe, dev, "not PCI Express\n");
6200
6201 /* Identify chip attached to board */
6202 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
6203
6204 rtl_init_rxcfg(tp);
6205
6206 rtl_irq_disable(tp);
6207
6208 rtl_hw_reset(tp);
6209
6210 rtl_ack_events(tp, 0xffff);
6211
6212 pci_set_master(pdev);
6213
6214 /*
6215 * Pretend we are using VLANs; This bypasses a nasty bug where
6216 * Interrupts stop flowing on high load on 8110SCd controllers.
6217 */
6218 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6219 tp->cp_cmd |= RxVlan;
6220
6221 rtl_init_mdio_ops(tp);
6222 rtl_init_pll_power_ops(tp);
6223 rtl_init_jumbo_ops(tp);
6224
6225 rtl8169_print_mac_version(tp);
6226
6227 chipset = tp->mac_version;
6228 tp->txd_version = rtl_chip_infos[chipset].txd_version;
6229
6230 RTL_W8(Cfg9346, Cfg9346_Unlock);
6231 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
6232 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
6233 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
6234 tp->features |= RTL_FEATURE_WOL;
6235 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
6236 tp->features |= RTL_FEATURE_WOL;
6237 tp->features |= rtl_try_msi(tp, cfg);
6238 RTL_W8(Cfg9346, Cfg9346_Lock);
6239
6240 if (rtl_tbi_enabled(tp)) {
6241 tp->set_speed = rtl8169_set_speed_tbi;
6242 tp->get_settings = rtl8169_gset_tbi;
6243 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
6244 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
6245 tp->link_ok = rtl8169_tbi_link_ok;
6246 tp->do_ioctl = rtl_tbi_ioctl;
6247 } else {
6248 tp->set_speed = rtl8169_set_speed_xmii;
6249 tp->get_settings = rtl8169_gset_xmii;
6250 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
6251 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
6252 tp->link_ok = rtl8169_xmii_link_ok;
6253 tp->do_ioctl = rtl_xmii_ioctl;
6254 }
6255
6256 mutex_init(&tp->wk.mutex);
6257
6258 /* Get MAC address */
6259 for (i = 0; i < ETH_ALEN; i++)
6260 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6261 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
6262
6263 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
6264 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
6265
6266 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
6267
6268 /* don't enable SG, IP_CSUM and TSO by default - it might not work
6269 * properly for all devices */
6270 dev->features |= NETIF_F_RXCSUM |
6271 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6272
6273 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6274 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6275 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6276 NETIF_F_HIGHDMA;
6277
6278 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6279 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
6280 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
6281
6282 dev->hw_features |= NETIF_F_RXALL;
6283 dev->hw_features |= NETIF_F_RXFCS;
6284
6285 tp->hw_start = cfg->hw_start;
6286 tp->event_slow = cfg->event_slow;
6287
6288 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
6289 ~(RxBOVF | RxFOVF) : ~0;
6290
6291 init_timer(&tp->timer);
6292 tp->timer.data = (unsigned long) dev;
6293 tp->timer.function = rtl8169_phy_timer;
6294
6295 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
6296
6297 rc = register_netdev(dev);
6298 if (rc < 0)
6299 goto err_out_msi_4;
6300
6301 pci_set_drvdata(pdev, dev);
6302
6303 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
6304 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
6305 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
6306 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
6307 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
6308 "tx checksumming: %s]\n",
6309 rtl_chip_infos[chipset].jumbo_max,
6310 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
6311 }
6312
6313 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6314 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6315 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6316 rtl8168_driver_start(tp);
6317 }
6318
6319 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
6320
6321 if (pci_dev_run_wake(pdev))
6322 pm_runtime_put_noidle(&pdev->dev);
6323
6324 netif_carrier_off(dev);
6325
6326 out:
6327 return rc;
6328
6329 err_out_msi_4:
6330 netif_napi_del(&tp->napi);
6331 rtl_disable_msi(pdev, tp);
6332 iounmap(ioaddr);
6333 err_out_free_res_3:
6334 pci_release_regions(pdev);
6335 err_out_mwi_2:
6336 pci_clear_mwi(pdev);
6337 pci_disable_device(pdev);
6338 err_out_free_dev_1:
6339 free_netdev(dev);
6340 goto out;
6341 }
6342
6343 static struct pci_driver rtl8169_pci_driver = {
6344 .name = MODULENAME,
6345 .id_table = rtl8169_pci_tbl,
6346 .probe = rtl_init_one,
6347 .remove = __devexit_p(rtl_remove_one),
6348 .shutdown = rtl_shutdown,
6349 .driver.pm = RTL8169_PM_OPS,
6350 };
6351
6352 static int __init rtl8169_init_module(void)
6353 {
6354 return pci_register_driver(&rtl8169_pci_driver);
6355 }
6356
6357 static void __exit rtl8169_cleanup_module(void)
6358 {
6359 pci_unregister_driver(&rtl8169_pci_driver);
6360 }
6361
6362 module_init(rtl8169_init_module);
6363 module_exit(rtl8169_cleanup_module);
Linux with added FPC-III support