drivers/net/ethernet/sgi/meth.h

   1
   2 /*
   3  * snull.h -- definitions for the network module
   4  *
   5  * Copyright (C) 2001 Alessandro Rubini and Jonathan Corbet
   6  * Copyright (C) 2001 O'Reilly & Associates
   7  *
   8  * The source code in this file can be freely used, adapted,
   9  * and redistributed in source or binary form, so long as an
  10  * acknowledgment appears in derived source files.  The citation
  11  * should list that the code comes from the book "Linux Device
  12  * Drivers" by Alessandro Rubini and Jonathan Corbet, published
  13  * by O'Reilly & Associates.   No warranty is attached;
  14  * we cannot take responsibility for errors or fitness for use.
  15  */
  16
  17 /* version dependencies have been confined to a separate file */
  18
  19 /* Tunable parameters */
  20 #define TX_RING_ENTRIES 64      /* 64-512?*/
  21
  22 #define RX_RING_ENTRIES 16 /* Do not change */
  23 /* Internal constants */
  24 #define TX_RING_BUFFER_SIZE     (TX_RING_ENTRIES*sizeof(tx_packet))
  25 #define RX_BUFFER_SIZE 1546 /* ethenet packet size */
  26 #define METH_RX_BUFF_SIZE 4096
  27 #define METH_RX_HEAD 34 /* status + 3 quad garbage-fill + 2 byte zero-pad */
  28 #define RX_BUFFER_OFFSET (sizeof(rx_status_vector)+2) /* staus vector + 2 bytes of padding */
  29 #define RX_BUCKET_SIZE 256
  30
  31 /* For more detailed explanations of what each field menas,
  32    see Nick's great comments to #defines below (or docs, if
  33    you are lucky enough toget hold of them :)*/
  34
  35 /* tx status vector is written over tx command header upon
  36    dma completion. */
  37
  38 typedef struct tx_status_vector {
  39         u64             sent:1; /* always set to 1...*/
  40         u64             pad0:34;/* always set to 0 */
  41         u64             flags:9;                        /*I'm too lazy to specify each one separately at the moment*/
  42         u64             col_retry_cnt:4;        /*collision retry count*/
  43         u64             len:16;                         /*Transmit length in bytes*/
  44 } tx_status_vector;
  45
  46 /*
  47  * Each packet is 128 bytes long.
  48  * It consists of header, 0-3 concatination
  49  * buffer pointers and up to 120 data bytes.
  50  */
  51 typedef struct tx_packet_hdr {
  52         u64             pad1:36; /*should be filled with 0 */
  53         u64             cat_ptr3_valid:1,       /*Concatination pointer valid flags*/
  54                         cat_ptr2_valid:1,
  55                         cat_ptr1_valid:1;
  56         u64             tx_int_flag:1;          /*Generate TX intrrupt when packet has been sent*/
  57         u64             term_dma_flag:1;        /*Terminate transmit DMA on transmit abort conditions*/
  58         u64             data_offset:7;          /*Starting byte offset in ring data block*/
  59         u64             data_len:16;            /*Length of valid data in bytes-1*/
  60 } tx_packet_hdr;
  61 typedef union tx_cat_ptr {
  62         struct {
  63                 u64             pad2:16; /* should be 0 */
  64                 u64             len:16;                         /*length of buffer data - 1*/
  65                 u64             start_addr:29;          /*Physical starting address*/
  66                 u64             pad1:3; /* should be zero */
  67         } form;
  68         u64 raw;
  69 } tx_cat_ptr;
  70
  71 typedef struct tx_packet {
  72         union {
  73                 tx_packet_hdr header;
  74                 tx_status_vector res;
  75                 u64 raw;
  76         }header;
  77         union {
  78                 tx_cat_ptr cat_buf[3];
  79                 char dt[120];
  80         } data;
  81 } tx_packet;
  82
  83 typedef union rx_status_vector {
  84         volatile struct {
  85                 u64             pad1:1;/*fill it with ones*/
  86                 u64             pad2:15;/*fill with 0*/
  87                 u64             ip_chk_sum:16;
  88                 u64             seq_num:5;
  89                 u64             mac_addr_match:1;
  90                 u64             mcast_addr_match:1;
  91                 u64             carrier_event_seen:1;
  92                 u64             bad_packet:1;
  93                 u64             long_event_seen:1;
  94                 u64             invalid_preamble:1;
  95                 u64             broadcast:1;
  96                 u64             multicast:1;
  97                 u64             crc_error:1;
  98                 u64             huh:1;/*???*/
  99                 u64             rx_code_violation:1;
 100                 u64             rx_len:16;
 101         } parsed;
 102         volatile u64 raw;
 103 } rx_status_vector;
 104
 105 typedef struct rx_packet {
 106         rx_status_vector status;
 107         u64 pad[3]; /* For whatever reason, there needs to be 4 double-word offset */
 108         u16 pad2;
 109         char buf[METH_RX_BUFF_SIZE-sizeof(rx_status_vector)-3*sizeof(u64)-sizeof(u16)];/* data */
 110 } rx_packet;
 111
 112 #define TX_INFO_RPTR    0x00FF0000
 113 #define TX_INFO_WPTR    0x000000FF
 114
 115         /* Bits in METH_MAC */
 116
 117 #define SGI_MAC_RESET           BIT(0)  /* 0: MAC110 active in run mode, 1: Global reset signal to MAC110 core is active */
 118 #define METH_PHY_FDX            BIT(1) /* 0: Disable full duplex, 1: Enable full duplex */
 119 #define METH_PHY_LOOP   BIT(2) /* 0: Normal operation, follows 10/100mbit and M10T/MII select, 1: loops internal MII bus */
 120                                        /*    selects ignored */
 121 #define METH_100MBIT            BIT(3) /* 0: 10meg mode, 1: 100meg mode */
 122 #define METH_PHY_MII            BIT(4) /* 0: MII selected, 1: SIA selected */
 123                                        /*   Note: when loopback is set this bit becomes collision control.  Setting this bit will */
 124                                        /*         cause a collision to be reported. */
 125
 126                                        /* Bits 5 and 6 are used to determine the Destination address filter mode */
 127 #define METH_ACCEPT_MY 0                        /* 00: Accept PHY address only */
 128 #define METH_ACCEPT_MCAST 0x20  /* 01: Accept physical, broadcast, and multicast filter matches only */
 129 #define METH_ACCEPT_AMCAST 0x40 /* 10: Accept physical, broadcast, and all multicast packets */
 130 #define METH_PROMISC 0x60               /* 11: Promiscious mode */
 131
 132 #define METH_PHY_LINK_FAIL      BIT(7) /* 0: Link failure detection disabled, 1: Hardware scans for link failure in PHY */
 133
 134 #define METH_MAC_IPG    0x1ffff00
 135
 136 #define METH_DEFAULT_IPG ((17<<15) | (11<<22) | (21<<8))
 137                                                 /* 0x172e5c00 */ /* 23, 23, 23 */ /*0x54A9500 *//*21,21,21*/
 138                                        /* Bits 8 through 14 are used to determine Inter-Packet Gap between "Back to Back" packets */
 139                                        /* The gap depends on the clock speed of the link, 80ns per increment for 100baseT, 800ns  */
 140                                        /* per increment for 10BaseT */
 141
 142                                        /* Bits 15 through 21 are used to determine IPGR1 */
 143
 144                                        /* Bits 22 through 28 are used to determine IPGR2 */
 145
 146 #define METH_REV_SHIFT 29       /* Bits 29 through 31 are used to determine the revision */
 147                                        /* 000: Initial revision */
 148                                        /* 001: First revision, Improved TX concatenation */
 149
 150
 151 /* DMA control bits */
 152 #define METH_RX_OFFSET_SHIFT 12 /* Bits 12:14 of DMA control register indicate starting offset of packet data for RX operation */
 153 #define METH_RX_DEPTH_SHIFT 4 /* Bits 8:4 define RX fifo depth -- when # of RX fifo entries != depth, interrupt is generted */
 154
 155 #define METH_DMA_TX_EN BIT(1) /* enable TX DMA */
 156 #define METH_DMA_TX_INT_EN BIT(0) /* enable TX Buffer Empty interrupt */
 157 #define METH_DMA_RX_EN BIT(15) /* Enable RX */
 158 #define METH_DMA_RX_INT_EN BIT(9) /* Enable interrupt on RX packet */
 159
 160 /* RX FIFO MCL Info bits */
 161 #define METH_RX_FIFO_WPTR(x)   (((x)>>16)&0xf)
 162 #define METH_RX_FIFO_RPTR(x)   (((x)>>8)&0xf)
 163 #define METH_RX_FIFO_DEPTH(x)  ((x)&0x1f)
 164
 165 /* RX status bits */
 166
 167 #define METH_RX_ST_VALID BIT(63)
 168 #define METH_RX_ST_RCV_CODE_VIOLATION BIT(16)
 169 #define METH_RX_ST_DRBL_NBL BIT(17)
 170 #define METH_RX_ST_CRC_ERR BIT(18)
 171 #define METH_RX_ST_MCAST_PKT BIT(19)
 172 #define METH_RX_ST_BCAST_PKT BIT(20)
 173 #define METH_RX_ST_INV_PREAMBLE_CTX BIT(21)
 174 #define METH_RX_ST_LONG_EVT_SEEN BIT(22)
 175 #define METH_RX_ST_BAD_PACKET BIT(23)
 176 #define METH_RX_ST_CARRIER_EVT_SEEN BIT(24)
 177 #define METH_RX_ST_MCAST_FILTER_MATCH BIT(25)
 178 #define METH_RX_ST_PHYS_ADDR_MATCH BIT(26)
 179
 180 #define METH_RX_STATUS_ERRORS \
 181         ( \
 182         METH_RX_ST_RCV_CODE_VIOLATION| \
 183         METH_RX_ST_CRC_ERR| \
 184         METH_RX_ST_INV_PREAMBLE_CTX| \
 185         METH_RX_ST_LONG_EVT_SEEN| \
 186         METH_RX_ST_BAD_PACKET| \
 187         METH_RX_ST_CARRIER_EVT_SEEN \
 188         )
 189         /* Bits in METH_INT */
 190         /* Write _1_ to corresponding bit to clear */
 191 #define METH_INT_TX_EMPTY       BIT(0)  /* 0: No interrupt pending, 1: The TX ring buffer is empty */
 192 #define METH_INT_TX_PKT         BIT(1)  /* 0: No interrupt pending */
 193                                                 /* 1: A TX message had the INT request bit set, the packet has been sent. */
 194 #define METH_INT_TX_LINK_FAIL   BIT(2)  /* 0: No interrupt pending, 1: PHY has reported a link failure */
 195 #define METH_INT_MEM_ERROR      BIT(3)  /* 0: No interrupt pending */
 196                                                 /* 1: A memory error occurred during DMA, DMA stopped, Fatal */
 197 #define METH_INT_TX_ABORT               BIT(4)  /* 0: No interrupt pending, 1: The TX aborted operation, DMA stopped, FATAL */
 198 #define METH_INT_RX_THRESHOLD   BIT(5)  /* 0: No interrupt pending, 1: Selected receive threshold condition Valid */
 199 #define METH_INT_RX_UNDERFLOW   BIT(6)  /* 0: No interrupt pending, 1: FIFO was empty, packet could not be queued */
 200 #define METH_INT_RX_OVERFLOW            BIT(7)  /* 0: No interrupt pending, 1: DMA FIFO Overflow, DMA stopped, FATAL */
 201
 202 /*#define METH_INT_RX_RPTR_MASK 0x0001F00*/             /* Bits 8 through 12 alias of RX read-pointer */
 203 #define METH_INT_RX_RPTR_MASK 0x0000F00         /* Bits 8 through 11 alias of RX read-pointer - so, is Rx FIFO 16 or 32 entry?*/
 204
 205                                                 /* Bits 13 through 15 are always 0. */
 206
 207 #define METH_INT_TX_RPTR_MASK   0x1FF0000        /* Bits 16 through 24 alias of TX read-pointer */
 208
 209 #define METH_INT_RX_SEQ_MASK    0x2E000000      /* Bits 25 through 29 are the starting seq number for the message at the */
 210
 211                                                 /* top of the queue */
 212
 213 #define METH_INT_ERROR  (METH_INT_TX_LINK_FAIL| \
 214                         METH_INT_MEM_ERROR| \
 215                         METH_INT_TX_ABORT| \
 216                         METH_INT_RX_OVERFLOW| \
 217                         METH_INT_RX_UNDERFLOW)
 218
 219 #define METH_INT_MCAST_HASH             BIT(30) /* If RX DMA is enabled the hash select logic output is latched here */
 220
 221 /* TX status bits */
 222 #define METH_TX_ST_DONE      BIT(63) /* TX complete */
 223 #define METH_TX_ST_SUCCESS   BIT(23) /* Packet was transmitted successfully */
 224 #define METH_TX_ST_TOOLONG   BIT(24) /* TX abort due to excessive length */
 225 #define METH_TX_ST_UNDERRUN  BIT(25) /* TX abort due to underrun (?) */
 226 #define METH_TX_ST_EXCCOLL   BIT(26) /* TX abort due to excess collisions */
 227 #define METH_TX_ST_DEFER     BIT(27) /* TX abort due to excess deferals */
 228 #define METH_TX_ST_LATECOLL  BIT(28) /* TX abort due to late collision */
 229
 230
 231 /* Tx command header bits */
 232 #define METH_TX_CMD_INT_EN BIT(24) /* Generate TX interrupt when packet is sent */
 233
 234 /* Phy MDIO interface busy flag */
 235 #define MDIO_BUSY    BIT(16)
 236 #define MDIO_DATA_MASK 0xFFFF
 237 /* PHY defines */
 238 #define PHY_QS6612X    0x0181441    /* Quality TX */
 239 #define PHY_ICS1889    0x0015F41    /* ICS FX */
 240 #define PHY_ICS1890    0x0015F42    /* ICS TX */
 241 #define PHY_DP83840    0x20005C0    /* National TX */
 242
 243 #define ADVANCE_RX_PTR(x)  x=(x+1)&(RX_RING_ENTRIES-1)