drivers/net/ethernet/smsc/smc91x.h

   1 /*------------------------------------------------------------------------
   2  . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
   3  .
   4  . Copyright (C) 1996 by Erik Stahlman
   5  . Copyright (C) 2001 Standard Microsystems Corporation
   6  .      Developed by Simple Network Magic Corporation
   7  . Copyright (C) 2003 Monta Vista Software, Inc.
   8  .      Unified SMC91x driver by Nicolas Pitre
   9  .
  10  . This program is free software; you can redistribute it and/or modify
  11  . it under the terms of the GNU General Public License as published by
  12  . the Free Software Foundation; either version 2 of the License, or
  13  . (at your option) any later version.
  14  .
  15  . This program is distributed in the hope that it will be useful,
  16  . but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  . GNU General Public License for more details.
  19  .
  20  . You should have received a copy of the GNU General Public License
  21  . along with this program; if not, write to the Free Software
  22  . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  23  .
  24  . Information contained in this file was obtained from the LAN91C111
  25  . manual from SMC.  To get a copy, if you really want one, you can find
  26  . information under www.smsc.com.
  27  .
  28  . Authors
  29  .      Erik Stahlman           <erik@vt.edu>
  30  .      Daris A Nevil           <dnevil@snmc.com>
  31  .      Nicolas Pitre           <nico@fluxnic.net>
  32  .
  33  ---------------------------------------------------------------------------*/
  34 #ifndef _SMC91X_H_
  35 #define _SMC91X_H_
  36
  37 #include <linux/smc91x.h>
  38
  39 /*
  40  * Define your architecture specific bus configuration parameters here.
  41  */
  42
  43 #if defined(CONFIG_ARCH_LUBBOCK) ||\
  44     defined(CONFIG_MACH_MAINSTONE) ||\
  45     defined(CONFIG_MACH_ZYLONITE) ||\
  46     defined(CONFIG_MACH_LITTLETON) ||\
  47     defined(CONFIG_MACH_ZYLONITE2) ||\
  48     defined(CONFIG_ARCH_VIPER) ||\
  49     defined(CONFIG_MACH_STARGATE2) ||\
  50     defined(CONFIG_ARCH_VERSATILE)
  51
  52 #include <asm/mach-types.h>
  53
  54 /* Now the bus width is specified in the platform data
  55  * pretend here to support all I/O access types
  56  */
  57 #define SMC_CAN_USE_8BIT        1
  58 #define SMC_CAN_USE_16BIT       1
  59 #define SMC_CAN_USE_32BIT       1
  60 #define SMC_NOWAIT              1
  61
  62 #define SMC_IO_SHIFT            (lp->io_shift)
  63
  64 #define SMC_inb(a, r)           readb((a) + (r))
  65 #define SMC_inw(a, r)           readw((a) + (r))
  66 #define SMC_inl(a, r)           readl((a) + (r))
  67 #define SMC_outb(v, a, r)       writeb(v, (a) + (r))
  68 #define SMC_outl(v, a, r)       writel(v, (a) + (r))
  69 #define SMC_insw(a, r, p, l)    readsw((a) + (r), p, l)
  70 #define SMC_outsw(a, r, p, l)   writesw((a) + (r), p, l)
  71 #define SMC_insl(a, r, p, l)    readsl((a) + (r), p, l)
  72 #define SMC_outsl(a, r, p, l)   writesl((a) + (r), p, l)
  73 #define SMC_IRQ_FLAGS           (-1)    /* from resource */
  74
  75 /* We actually can't write halfwords properly if not word aligned */
  76 static inline void SMC_outw(u16 val, void __iomem *ioaddr, int reg)
  77 {
  78         if ((machine_is_mainstone() || machine_is_stargate2()) && reg & 2) {
  79                 unsigned int v = val << 16;
  80                 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
  81                 writel(v, ioaddr + (reg & ~2));
  82         } else {
  83                 writew(val, ioaddr + reg);
  84         }
  85 }
  86
  87 #elif defined(CONFIG_SA1100_PLEB)
  88 /* We can only do 16-bit reads and writes in the static memory space. */
  89 #define SMC_CAN_USE_8BIT        1
  90 #define SMC_CAN_USE_16BIT       1
  91 #define SMC_CAN_USE_32BIT       0
  92 #define SMC_IO_SHIFT            0
  93 #define SMC_NOWAIT              1
  94
  95 #define SMC_inb(a, r)           readb((a) + (r))
  96 #define SMC_insb(a, r, p, l)    readsb((a) + (r), p, (l))
  97 #define SMC_inw(a, r)           readw((a) + (r))
  98 #define SMC_insw(a, r, p, l)    readsw((a) + (r), p, l)
  99 #define SMC_outb(v, a, r)       writeb(v, (a) + (r))
 100 #define SMC_outsb(a, r, p, l)   writesb((a) + (r), p, (l))
 101 #define SMC_outw(v, a, r)       writew(v, (a) + (r))
 102 #define SMC_outsw(a, r, p, l)   writesw((a) + (r), p, l)
 103
 104 #define SMC_IRQ_FLAGS           (-1)
 105
 106 #elif defined(CONFIG_SA1100_ASSABET)
 107
 108 #include <mach/neponset.h>
 109
 110 /* We can only do 8-bit reads and writes in the static memory space. */
 111 #define SMC_CAN_USE_8BIT        1
 112 #define SMC_CAN_USE_16BIT       0
 113 #define SMC_CAN_USE_32BIT       0
 114 #define SMC_NOWAIT              1
 115
 116 /* The first two address lines aren't connected... */
 117 #define SMC_IO_SHIFT            2
 118
 119 #define SMC_inb(a, r)           readb((a) + (r))
 120 #define SMC_outb(v, a, r)       writeb(v, (a) + (r))
 121 #define SMC_insb(a, r, p, l)    readsb((a) + (r), p, (l))
 122 #define SMC_outsb(a, r, p, l)   writesb((a) + (r), p, (l))
 123 #define SMC_IRQ_FLAGS           (-1)    /* from resource */
 124
 125 #elif   defined(CONFIG_MACH_LOGICPD_PXA270) ||  \
 126         defined(CONFIG_MACH_NOMADIK_8815NHK)
 127
 128 #define SMC_CAN_USE_8BIT        0
 129 #define SMC_CAN_USE_16BIT       1
 130 #define SMC_CAN_USE_32BIT       0
 131 #define SMC_IO_SHIFT            0
 132 #define SMC_NOWAIT              1
 133
 134 #define SMC_inw(a, r)           readw((a) + (r))
 135 #define SMC_outw(v, a, r)       writew(v, (a) + (r))
 136 #define SMC_insw(a, r, p, l)    readsw((a) + (r), p, l)
 137 #define SMC_outsw(a, r, p, l)   writesw((a) + (r), p, l)
 138
 139 #elif   defined(CONFIG_ARCH_INNOKOM) || \
 140         defined(CONFIG_ARCH_PXA_IDP) || \
 141         defined(CONFIG_ARCH_RAMSES) || \
 142         defined(CONFIG_ARCH_PCM027)
 143
 144 #define SMC_CAN_USE_8BIT        1
 145 #define SMC_CAN_USE_16BIT       1
 146 #define SMC_CAN_USE_32BIT       1
 147 #define SMC_IO_SHIFT            0
 148 #define SMC_NOWAIT              1
 149 #define SMC_USE_PXA_DMA         1
 150
 151 #define SMC_inb(a, r)           readb((a) + (r))
 152 #define SMC_inw(a, r)           readw((a) + (r))
 153 #define SMC_inl(a, r)           readl((a) + (r))
 154 #define SMC_outb(v, a, r)       writeb(v, (a) + (r))
 155 #define SMC_outl(v, a, r)       writel(v, (a) + (r))
 156 #define SMC_insl(a, r, p, l)    readsl((a) + (r), p, l)
 157 #define SMC_outsl(a, r, p, l)   writesl((a) + (r), p, l)
 158 #define SMC_insw(a, r, p, l)    readsw((a) + (r), p, l)
 159 #define SMC_outsw(a, r, p, l)   writesw((a) + (r), p, l)
 160 #define SMC_IRQ_FLAGS           (-1)    /* from resource */
 161
 162 /* We actually can't write halfwords properly if not word aligned */
 163 static inline void
 164 SMC_outw(u16 val, void __iomem *ioaddr, int reg)
 165 {
 166         if (reg & 2) {
 167                 unsigned int v = val << 16;
 168                 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
 169                 writel(v, ioaddr + (reg & ~2));
 170         } else {
 171                 writew(val, ioaddr + reg);
 172         }
 173 }
 174
 175 #elif   defined(CONFIG_SH_SH4202_MICRODEV)
 176
 177 #define SMC_CAN_USE_8BIT        0
 178 #define SMC_CAN_USE_16BIT       1
 179 #define SMC_CAN_USE_32BIT       0
 180
 181 #define SMC_inb(a, r)           inb((a) + (r) - 0xa0000000)
 182 #define SMC_inw(a, r)           inw((a) + (r) - 0xa0000000)
 183 #define SMC_inl(a, r)           inl((a) + (r) - 0xa0000000)
 184 #define SMC_outb(v, a, r)       outb(v, (a) + (r) - 0xa0000000)
 185 #define SMC_outw(v, a, r)       outw(v, (a) + (r) - 0xa0000000)
 186 #define SMC_outl(v, a, r)       outl(v, (a) + (r) - 0xa0000000)
 187 #define SMC_insl(a, r, p, l)    insl((a) + (r) - 0xa0000000, p, l)
 188 #define SMC_outsl(a, r, p, l)   outsl((a) + (r) - 0xa0000000, p, l)
 189 #define SMC_insw(a, r, p, l)    insw((a) + (r) - 0xa0000000, p, l)
 190 #define SMC_outsw(a, r, p, l)   outsw((a) + (r) - 0xa0000000, p, l)
 191
 192 #define SMC_IRQ_FLAGS           (0)
 193
 194 #elif   defined(CONFIG_M32R)
 195
 196 #define SMC_CAN_USE_8BIT        0
 197 #define SMC_CAN_USE_16BIT       1
 198 #define SMC_CAN_USE_32BIT       0
 199
 200 #define SMC_inb(a, r)           inb(((u32)a) + (r))
 201 #define SMC_inw(a, r)           inw(((u32)a) + (r))
 202 #define SMC_outb(v, a, r)       outb(v, ((u32)a) + (r))
 203 #define SMC_outw(v, a, r)       outw(v, ((u32)a) + (r))
 204 #define SMC_insw(a, r, p, l)    insw(((u32)a) + (r), p, l)
 205 #define SMC_outsw(a, r, p, l)   outsw(((u32)a) + (r), p, l)
 206
 207 #define SMC_IRQ_FLAGS           (0)
 208
 209 #define RPC_LSA_DEFAULT         RPC_LED_TX_RX
 210 #define RPC_LSB_DEFAULT         RPC_LED_100_10
 211
 212 #elif defined(CONFIG_MN10300)
 213
 214 /*
 215  * MN10300/AM33 configuration
 216  */
 217
 218 #include <unit/smc91111.h>
 219
 220 #elif defined(CONFIG_ARCH_MSM)
 221
 222 #define SMC_CAN_USE_8BIT        0
 223 #define SMC_CAN_USE_16BIT       1
 224 #define SMC_CAN_USE_32BIT       0
 225 #define SMC_NOWAIT              1
 226
 227 #define SMC_inw(a, r)           readw((a) + (r))
 228 #define SMC_outw(v, a, r)       writew(v, (a) + (r))
 229 #define SMC_insw(a, r, p, l)    readsw((a) + (r), p, l)
 230 #define SMC_outsw(a, r, p, l)   writesw((a) + (r), p, l)
 231
 232 #define SMC_IRQ_FLAGS           IRQF_TRIGGER_HIGH
 233
 234 #elif defined(CONFIG_COLDFIRE)
 235
 236 #define SMC_CAN_USE_8BIT        0
 237 #define SMC_CAN_USE_16BIT       1
 238 #define SMC_CAN_USE_32BIT       0
 239 #define SMC_NOWAIT              1
 240
 241 static inline void mcf_insw(void *a, unsigned char *p, int l)
 242 {
 243         u16 *wp = (u16 *) p;
 244         while (l-- > 0)
 245                 *wp++ = readw(a);
 246 }
 247
 248 static inline void mcf_outsw(void *a, unsigned char *p, int l)
 249 {
 250         u16 *wp = (u16 *) p;
 251         while (l-- > 0)
 252                 writew(*wp++, a);
 253 }
 254
 255 #define SMC_inw(a, r)           _swapw(readw((a) + (r)))
 256 #define SMC_outw(v, a, r)       writew(_swapw(v), (a) + (r))
 257 #define SMC_insw(a, r, p, l)    mcf_insw(a + r, p, l)
 258 #define SMC_outsw(a, r, p, l)   mcf_outsw(a + r, p, l)
 259
 260 #define SMC_IRQ_FLAGS           (IRQF_DISABLED)
 261
 262 #else
 263
 264 /*
 265  * Default configuration
 266  */
 267
 268 #define SMC_CAN_USE_8BIT        1
 269 #define SMC_CAN_USE_16BIT       1
 270 #define SMC_CAN_USE_32BIT       1
 271 #define SMC_NOWAIT              1
 272
 273 #define SMC_IO_SHIFT            (lp->io_shift)
 274
 275 #define SMC_inb(a, r)           readb((a) + (r))
 276 #define SMC_inw(a, r)           readw((a) + (r))
 277 #define SMC_inl(a, r)           readl((a) + (r))
 278 #define SMC_outb(v, a, r)       writeb(v, (a) + (r))
 279 #define SMC_outw(v, a, r)       writew(v, (a) + (r))
 280 #define SMC_outl(v, a, r)       writel(v, (a) + (r))
 281 #define SMC_insw(a, r, p, l)    readsw((a) + (r), p, l)
 282 #define SMC_outsw(a, r, p, l)   writesw((a) + (r), p, l)
 283 #define SMC_insl(a, r, p, l)    readsl((a) + (r), p, l)
 284 #define SMC_outsl(a, r, p, l)   writesl((a) + (r), p, l)
 285
 286 #define RPC_LSA_DEFAULT         RPC_LED_100_10
 287 #define RPC_LSB_DEFAULT         RPC_LED_TX_RX
 288
 289 #endif
 290
 291
 292 /* store this information for the driver.. */
 293 struct smc_local {
 294         /*
 295          * If I have to wait until memory is available to send a
 296          * packet, I will store the skbuff here, until I get the
 297          * desired memory.  Then, I'll send it out and free it.
 298          */
 299         struct sk_buff *pending_tx_skb;
 300         struct tasklet_struct tx_task;
 301
 302         /* version/revision of the SMC91x chip */
 303         int     version;
 304
 305         /* Contains the current active transmission mode */
 306         int     tcr_cur_mode;
 307
 308         /* Contains the current active receive mode */
 309         int     rcr_cur_mode;
 310
 311         /* Contains the current active receive/phy mode */
 312         int     rpc_cur_mode;
 313         int     ctl_rfduplx;
 314         int     ctl_rspeed;
 315
 316         u32     msg_enable;
 317         u32     phy_type;
 318         struct mii_if_info mii;
 319
 320         /* work queue */
 321         struct work_struct phy_configure;
 322         struct net_device *dev;
 323         int     work_pending;
 324
 325         spinlock_t lock;
 326
 327 #ifdef CONFIG_ARCH_PXA
 328         /* DMA needs the physical address of the chip */
 329         u_long physaddr;
 330         struct device *device;
 331 #endif
 332         void __iomem *base;
 333         void __iomem *datacs;
 334
 335         /* the low address lines on some platforms aren't connected... */
 336         int     io_shift;
 337
 338         struct smc91x_platdata cfg;
 339 };
 340
 341 #define SMC_8BIT(p)     ((p)->cfg.flags & SMC91X_USE_8BIT)
 342 #define SMC_16BIT(p)    ((p)->cfg.flags & SMC91X_USE_16BIT)
 343 #define SMC_32BIT(p)    ((p)->cfg.flags & SMC91X_USE_32BIT)
 344
 345 #ifdef CONFIG_ARCH_PXA
 346 /*
 347  * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
 348  * always happening in irq context so no need to worry about races.  TX is
 349  * different and probably not worth it for that reason, and not as critical
 350  * as RX which can overrun memory and lose packets.
 351  */
 352 #include <linux/dma-mapping.h>
 353 #include <mach/dma.h>
 354
 355 #ifdef SMC_insl
 356 #undef SMC_insl
 357 #define SMC_insl(a, r, p, l) \
 358         smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
 359 static inline void
 360 smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
 361                  u_char *buf, int len)
 362 {
 363         u_long physaddr = lp->physaddr;
 364         dma_addr_t dmabuf;
 365
 366         /* fallback if no DMA available */
 367         if (dma == (unsigned char)-1) {
 368                 readsl(ioaddr + reg, buf, len);
 369                 return;
 370         }
 371
 372         /* 64 bit alignment is required for memory to memory DMA */
 373         if ((long)buf & 4) {
 374                 *((u32 *)buf) = SMC_inl(ioaddr, reg);
 375                 buf += 4;
 376                 len--;
 377         }
 378
 379         len *= 4;
 380         dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
 381         DCSR(dma) = DCSR_NODESC;
 382         DTADR(dma) = dmabuf;
 383         DSADR(dma) = physaddr + reg;
 384         DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
 385                      DCMD_WIDTH4 | (DCMD_LENGTH & len));
 386         DCSR(dma) = DCSR_NODESC | DCSR_RUN;
 387         while (!(DCSR(dma) & DCSR_STOPSTATE))
 388                 cpu_relax();
 389         DCSR(dma) = 0;
 390         dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
 391 }
 392 #endif
 393
 394 #ifdef SMC_insw
 395 #undef SMC_insw
 396 #define SMC_insw(a, r, p, l) \
 397         smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
 398 static inline void
 399 smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
 400                  u_char *buf, int len)
 401 {
 402         u_long physaddr = lp->physaddr;
 403         dma_addr_t dmabuf;
 404
 405         /* fallback if no DMA available */
 406         if (dma == (unsigned char)-1) {
 407                 readsw(ioaddr + reg, buf, len);
 408                 return;
 409         }
 410
 411         /* 64 bit alignment is required for memory to memory DMA */
 412         while ((long)buf & 6) {
 413                 *((u16 *)buf) = SMC_inw(ioaddr, reg);
 414                 buf += 2;
 415                 len--;
 416         }
 417
 418         len *= 2;
 419         dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
 420         DCSR(dma) = DCSR_NODESC;
 421         DTADR(dma) = dmabuf;
 422         DSADR(dma) = physaddr + reg;
 423         DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
 424                      DCMD_WIDTH2 | (DCMD_LENGTH & len));
 425         DCSR(dma) = DCSR_NODESC | DCSR_RUN;
 426         while (!(DCSR(dma) & DCSR_STOPSTATE))
 427                 cpu_relax();
 428         DCSR(dma) = 0;
 429         dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
 430 }
 431 #endif
 432
 433 static void
 434 smc_pxa_dma_irq(int dma, void *dummy)
 435 {
 436         DCSR(dma) = 0;
 437 }
 438 #endif  /* CONFIG_ARCH_PXA */
 439
 440
 441 /*
 442  * Everything a particular hardware setup needs should have been defined
 443  * at this point.  Add stubs for the undefined cases, mainly to avoid
 444  * compilation warnings since they'll be optimized away, or to prevent buggy
 445  * use of them.
 446  */
 447
 448 #if ! SMC_CAN_USE_32BIT
 449 #define SMC_inl(ioaddr, reg)            ({ BUG(); 0; })
 450 #define SMC_outl(x, ioaddr, reg)        BUG()
 451 #define SMC_insl(a, r, p, l)            BUG()
 452 #define SMC_outsl(a, r, p, l)           BUG()
 453 #endif
 454
 455 #if !defined(SMC_insl) || !defined(SMC_outsl)
 456 #define SMC_insl(a, r, p, l)            BUG()
 457 #define SMC_outsl(a, r, p, l)           BUG()
 458 #endif
 459
 460 #if ! SMC_CAN_USE_16BIT
 461
 462 /*
 463  * Any 16-bit access is performed with two 8-bit accesses if the hardware
 464  * can't do it directly. Most registers are 16-bit so those are mandatory.
 465  */
 466 #define SMC_outw(x, ioaddr, reg)                                        \
 467         do {                                                            \
 468                 unsigned int __val16 = (x);                             \
 469                 SMC_outb( __val16, ioaddr, reg );                       \
 470                 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
 471         } while (0)
 472 #define SMC_inw(ioaddr, reg)                                            \
 473         ({                                                              \
 474                 unsigned int __val16;                                   \
 475                 __val16 =  SMC_inb( ioaddr, reg );                      \
 476                 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
 477                 __val16;                                                \
 478         })
 479
 480 #define SMC_insw(a, r, p, l)            BUG()
 481 #define SMC_outsw(a, r, p, l)           BUG()
 482
 483 #endif
 484
 485 #if !defined(SMC_insw) || !defined(SMC_outsw)
 486 #define SMC_insw(a, r, p, l)            BUG()
 487 #define SMC_outsw(a, r, p, l)           BUG()
 488 #endif
 489
 490 #if ! SMC_CAN_USE_8BIT
 491 #define SMC_inb(ioaddr, reg)            ({ BUG(); 0; })
 492 #define SMC_outb(x, ioaddr, reg)        BUG()
 493 #define SMC_insb(a, r, p, l)            BUG()
 494 #define SMC_outsb(a, r, p, l)           BUG()
 495 #endif
 496
 497 #if !defined(SMC_insb) || !defined(SMC_outsb)
 498 #define SMC_insb(a, r, p, l)            BUG()
 499 #define SMC_outsb(a, r, p, l)           BUG()
 500 #endif
 501
 502 #ifndef SMC_CAN_USE_DATACS
 503 #define SMC_CAN_USE_DATACS      0
 504 #endif
 505
 506 #ifndef SMC_IO_SHIFT
 507 #define SMC_IO_SHIFT    0
 508 #endif
 509
 510 #ifndef SMC_IRQ_FLAGS
 511 #define SMC_IRQ_FLAGS           IRQF_TRIGGER_RISING
 512 #endif
 513
 514 #ifndef SMC_INTERRUPT_PREAMBLE
 515 #define SMC_INTERRUPT_PREAMBLE
 516 #endif
 517
 518
 519 /* Because of bank switching, the LAN91x uses only 16 I/O ports */
 520 #define SMC_IO_EXTENT   (16 << SMC_IO_SHIFT)
 521 #define SMC_DATA_EXTENT (4)
 522
 523 /*
 524  . Bank Select Register:
 525  .
 526  .              yyyy yyyy 0000 00xx
 527  .              xx              = bank number
 528  .              yyyy yyyy       = 0x33, for identification purposes.
 529 */
 530 #define BANK_SELECT             (14 << SMC_IO_SHIFT)
 531
 532
 533 // Transmit Control Register
 534 /* BANK 0  */
 535 #define TCR_REG(lp)     SMC_REG(lp, 0x0000, 0)
 536 #define TCR_ENABLE      0x0001  // When 1 we can transmit
 537 #define TCR_LOOP        0x0002  // Controls output pin LBK
 538 #define TCR_FORCOL      0x0004  // When 1 will force a collision
 539 #define TCR_PAD_EN      0x0080  // When 1 will pad tx frames < 64 bytes w/0
 540 #define TCR_NOCRC       0x0100  // When 1 will not append CRC to tx frames
 541 #define TCR_MON_CSN     0x0400  // When 1 tx monitors carrier
 542 #define TCR_FDUPLX      0x0800  // When 1 enables full duplex operation
 543 #define TCR_STP_SQET    0x1000  // When 1 stops tx if Signal Quality Error
 544 #define TCR_EPH_LOOP    0x2000  // When 1 enables EPH block loopback
 545 #define TCR_SWFDUP      0x8000  // When 1 enables Switched Full Duplex mode
 546
 547 #define TCR_CLEAR       0       /* do NOTHING */
 548 /* the default settings for the TCR register : */
 549 #define TCR_DEFAULT     (TCR_ENABLE | TCR_PAD_EN)
 550
 551
 552 // EPH Status Register
 553 /* BANK 0  */
 554 #define EPH_STATUS_REG(lp)      SMC_REG(lp, 0x0002, 0)
 555 #define ES_TX_SUC       0x0001  // Last TX was successful
 556 #define ES_SNGL_COL     0x0002  // Single collision detected for last tx
 557 #define ES_MUL_COL      0x0004  // Multiple collisions detected for last tx
 558 #define ES_LTX_MULT     0x0008  // Last tx was a multicast
 559 #define ES_16COL        0x0010  // 16 Collisions Reached
 560 #define ES_SQET         0x0020  // Signal Quality Error Test
 561 #define ES_LTXBRD       0x0040  // Last tx was a broadcast
 562 #define ES_TXDEFR       0x0080  // Transmit Deferred
 563 #define ES_LATCOL       0x0200  // Late collision detected on last tx
 564 #define ES_LOSTCARR     0x0400  // Lost Carrier Sense
 565 #define ES_EXC_DEF      0x0800  // Excessive Deferral
 566 #define ES_CTR_ROL      0x1000  // Counter Roll Over indication
 567 #define ES_LINK_OK      0x4000  // Driven by inverted value of nLNK pin
 568 #define ES_TXUNRN       0x8000  // Tx Underrun
 569
 570
 571 // Receive Control Register
 572 /* BANK 0  */
 573 #define RCR_REG(lp)             SMC_REG(lp, 0x0004, 0)
 574 #define RCR_RX_ABORT    0x0001  // Set if a rx frame was aborted
 575 #define RCR_PRMS        0x0002  // Enable promiscuous mode
 576 #define RCR_ALMUL       0x0004  // When set accepts all multicast frames
 577 #define RCR_RXEN        0x0100  // IFF this is set, we can receive packets
 578 #define RCR_STRIP_CRC   0x0200  // When set strips CRC from rx packets
 579 #define RCR_ABORT_ENB   0x0200  // When set will abort rx on collision
 580 #define RCR_FILT_CAR    0x0400  // When set filters leading 12 bit s of carrier
 581 #define RCR_SOFTRST     0x8000  // resets the chip
 582
 583 /* the normal settings for the RCR register : */
 584 #define RCR_DEFAULT     (RCR_STRIP_CRC | RCR_RXEN)
 585 #define RCR_CLEAR       0x0     // set it to a base state
 586
 587
 588 // Counter Register
 589 /* BANK 0  */
 590 #define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0)
 591
 592
 593 // Memory Information Register
 594 /* BANK 0  */
 595 #define MIR_REG(lp)             SMC_REG(lp, 0x0008, 0)
 596
 597
 598 // Receive/Phy Control Register
 599 /* BANK 0  */
 600 #define RPC_REG(lp)             SMC_REG(lp, 0x000A, 0)
 601 #define RPC_SPEED       0x2000  // When 1 PHY is in 100Mbps mode.
 602 #define RPC_DPLX        0x1000  // When 1 PHY is in Full-Duplex Mode
 603 #define RPC_ANEG        0x0800  // When 1 PHY is in Auto-Negotiate Mode
 604 #define RPC_LSXA_SHFT   5       // Bits to shift LS2A,LS1A,LS0A to lsb
 605 #define RPC_LSXB_SHFT   2       // Bits to get LS2B,LS1B,LS0B to lsb
 606
 607 #ifndef RPC_LSA_DEFAULT
 608 #define RPC_LSA_DEFAULT RPC_LED_100
 609 #endif
 610 #ifndef RPC_LSB_DEFAULT
 611 #define RPC_LSB_DEFAULT RPC_LED_FD
 612 #endif
 613
 614 #define RPC_DEFAULT (RPC_ANEG | RPC_SPEED | RPC_DPLX)
 615
 616
 617 /* Bank 0 0x0C is reserved */
 618
 619 // Bank Select Register
 620 /* All Banks */
 621 #define BSR_REG         0x000E
 622
 623
 624 // Configuration Reg
 625 /* BANK 1 */
 626 #define CONFIG_REG(lp)  SMC_REG(lp, 0x0000,     1)
 627 #define CONFIG_EXT_PHY  0x0200  // 1=external MII, 0=internal Phy
 628 #define CONFIG_GPCNTRL  0x0400  // Inverse value drives pin nCNTRL
 629 #define CONFIG_NO_WAIT  0x1000  // When 1 no extra wait states on ISA bus
 630 #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
 631
 632 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
 633 #define CONFIG_DEFAULT  (CONFIG_EPH_POWER_EN)
 634
 635
 636 // Base Address Register
 637 /* BANK 1 */
 638 #define BASE_REG(lp)    SMC_REG(lp, 0x0002, 1)
 639
 640
 641 // Individual Address Registers
 642 /* BANK 1 */
 643 #define ADDR0_REG(lp)   SMC_REG(lp, 0x0004, 1)
 644 #define ADDR1_REG(lp)   SMC_REG(lp, 0x0006, 1)
 645 #define ADDR2_REG(lp)   SMC_REG(lp, 0x0008, 1)
 646
 647
 648 // General Purpose Register
 649 /* BANK 1 */
 650 #define GP_REG(lp)              SMC_REG(lp, 0x000A, 1)
 651
 652
 653 // Control Register
 654 /* BANK 1 */
 655 #define CTL_REG(lp)             SMC_REG(lp, 0x000C, 1)
 656 #define CTL_RCV_BAD     0x4000 // When 1 bad CRC packets are received
 657 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
 658 #define CTL_LE_ENABLE   0x0080 // When 1 enables Link Error interrupt
 659 #define CTL_CR_ENABLE   0x0040 // When 1 enables Counter Rollover interrupt
 660 #define CTL_TE_ENABLE   0x0020 // When 1 enables Transmit Error interrupt
 661 #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
 662 #define CTL_RELOAD      0x0002 // When set reads EEPROM into registers
 663 #define CTL_STORE       0x0001 // When set stores registers into EEPROM
 664
 665
 666 // MMU Command Register
 667 /* BANK 2 */
 668 #define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2)
 669 #define MC_BUSY         1       // When 1 the last release has not completed
 670 #define MC_NOP          (0<<5)  // No Op
 671 #define MC_ALLOC        (1<<5)  // OR with number of 256 byte packets
 672 #define MC_RESET        (2<<5)  // Reset MMU to initial state
 673 #define MC_REMOVE       (3<<5)  // Remove the current rx packet
 674 #define MC_RELEASE      (4<<5)  // Remove and release the current rx packet
 675 #define MC_FREEPKT      (5<<5)  // Release packet in PNR register
 676 #define MC_ENQUEUE      (6<<5)  // Enqueue the packet for transmit
 677 #define MC_RSTTXFIFO    (7<<5)  // Reset the TX FIFOs
 678
 679
 680 // Packet Number Register
 681 /* BANK 2 */
 682 #define PN_REG(lp)              SMC_REG(lp, 0x0002, 2)
 683
 684
 685 // Allocation Result Register
 686 /* BANK 2 */
 687 #define AR_REG(lp)              SMC_REG(lp, 0x0003, 2)
 688 #define AR_FAILED       0x80    // Alocation Failed
 689
 690
 691 // TX FIFO Ports Register
 692 /* BANK 2 */
 693 #define TXFIFO_REG(lp)  SMC_REG(lp, 0x0004, 2)
 694 #define TXFIFO_TEMPTY   0x80    // TX FIFO Empty
 695
 696 // RX FIFO Ports Register
 697 /* BANK 2 */
 698 #define RXFIFO_REG(lp)  SMC_REG(lp, 0x0005, 2)
 699 #define RXFIFO_REMPTY   0x80    // RX FIFO Empty
 700
 701 #define FIFO_REG(lp)    SMC_REG(lp, 0x0004, 2)
 702
 703 // Pointer Register
 704 /* BANK 2 */
 705 #define PTR_REG(lp)             SMC_REG(lp, 0x0006, 2)
 706 #define PTR_RCV         0x8000 // 1=Receive area, 0=Transmit area
 707 #define PTR_AUTOINC     0x4000 // Auto increment the pointer on each access
 708 #define PTR_READ        0x2000 // When 1 the operation is a read
 709
 710
 711 // Data Register
 712 /* BANK 2 */
 713 #define DATA_REG(lp)    SMC_REG(lp, 0x0008, 2)
 714
 715
 716 // Interrupt Status/Acknowledge Register
 717 /* BANK 2 */
 718 #define INT_REG(lp)             SMC_REG(lp, 0x000C, 2)
 719
 720
 721 // Interrupt Mask Register
 722 /* BANK 2 */
 723 #define IM_REG(lp)              SMC_REG(lp, 0x000D, 2)
 724 #define IM_MDINT        0x80 // PHY MI Register 18 Interrupt
 725 #define IM_ERCV_INT     0x40 // Early Receive Interrupt
 726 #define IM_EPH_INT      0x20 // Set by Ethernet Protocol Handler section
 727 #define IM_RX_OVRN_INT  0x10 // Set by Receiver Overruns
 728 #define IM_ALLOC_INT    0x08 // Set when allocation request is completed
 729 #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
 730 #define IM_TX_INT       0x02 // Transmit Interrupt
 731 #define IM_RCV_INT      0x01 // Receive Interrupt
 732
 733
 734 // Multicast Table Registers
 735 /* BANK 3 */
 736 #define MCAST_REG1(lp)  SMC_REG(lp, 0x0000, 3)
 737 #define MCAST_REG2(lp)  SMC_REG(lp, 0x0002, 3)
 738 #define MCAST_REG3(lp)  SMC_REG(lp, 0x0004, 3)
 739 #define MCAST_REG4(lp)  SMC_REG(lp, 0x0006, 3)
 740
 741
 742 // Management Interface Register (MII)
 743 /* BANK 3 */
 744 #define MII_REG(lp)             SMC_REG(lp, 0x0008, 3)
 745 #define MII_MSK_CRS100  0x4000 // Disables CRS100 detection during tx half dup
 746 #define MII_MDOE        0x0008 // MII Output Enable
 747 #define MII_MCLK        0x0004 // MII Clock, pin MDCLK
 748 #define MII_MDI         0x0002 // MII Input, pin MDI
 749 #define MII_MDO         0x0001 // MII Output, pin MDO
 750
 751
 752 // Revision Register
 753 /* BANK 3 */
 754 /* ( hi: chip id   low: rev # ) */
 755 #define REV_REG(lp)             SMC_REG(lp, 0x000A, 3)
 756
 757
 758 // Early RCV Register
 759 /* BANK 3 */
 760 /* this is NOT on SMC9192 */
 761 #define ERCV_REG(lp)    SMC_REG(lp, 0x000C, 3)
 762 #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
 763 #define ERCV_THRESHOLD  0x001F // ERCV Threshold Mask
 764
 765
 766 // External Register
 767 /* BANK 7 */
 768 #define EXT_REG(lp)             SMC_REG(lp, 0x0000, 7)
 769
 770
 771 #define CHIP_9192       3
 772 #define CHIP_9194       4
 773 #define CHIP_9195       5
 774 #define CHIP_9196       6
 775 #define CHIP_91100      7
 776 #define CHIP_91100FD    8
 777 #define CHIP_91111FD    9
 778
 779 static const char * chip_ids[ 16 ] =  {
 780         NULL, NULL, NULL,
 781         /* 3 */ "SMC91C90/91C92",
 782         /* 4 */ "SMC91C94",
 783         /* 5 */ "SMC91C95",
 784         /* 6 */ "SMC91C96",
 785         /* 7 */ "SMC91C100",
 786         /* 8 */ "SMC91C100FD",
 787         /* 9 */ "SMC91C11xFD",
 788         NULL, NULL, NULL,
 789         NULL, NULL, NULL};
 790
 791
 792 /*
 793  . Receive status bits
 794 */
 795 #define RS_ALGNERR      0x8000
 796 #define RS_BRODCAST     0x4000
 797 #define RS_BADCRC       0x2000
 798 #define RS_ODDFRAME     0x1000
 799 #define RS_TOOLONG      0x0800
 800 #define RS_TOOSHORT     0x0400
 801 #define RS_MULTICAST    0x0001
 802 #define RS_ERRORS       (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
 803
 804
 805 /*
 806  * PHY IDs
 807  *  LAN83C183 == LAN91C111 Internal PHY
 808  */
 809 #define PHY_LAN83C183   0x0016f840
 810 #define PHY_LAN83C180   0x02821c50
 811
 812 /*
 813  * PHY Register Addresses (LAN91C111 Internal PHY)
 814  *
 815  * Generic PHY registers can be found in <linux/mii.h>
 816  *
 817  * These phy registers are specific to our on-board phy.
 818  */
 819
 820 // PHY Configuration Register 1
 821 #define PHY_CFG1_REG            0x10
 822 #define PHY_CFG1_LNKDIS         0x8000  // 1=Rx Link Detect Function disabled
 823 #define PHY_CFG1_XMTDIS         0x4000  // 1=TP Transmitter Disabled
 824 #define PHY_CFG1_XMTPDN         0x2000  // 1=TP Transmitter Powered Down
 825 #define PHY_CFG1_BYPSCR         0x0400  // 1=Bypass scrambler/descrambler
 826 #define PHY_CFG1_UNSCDS         0x0200  // 1=Unscramble Idle Reception Disable
 827 #define PHY_CFG1_EQLZR          0x0100  // 1=Rx Equalizer Disabled
 828 #define PHY_CFG1_CABLE          0x0080  // 1=STP(150ohm), 0=UTP(100ohm)
 829 #define PHY_CFG1_RLVL0          0x0040  // 1=Rx Squelch level reduced by 4.5db
 830 #define PHY_CFG1_TLVL_SHIFT     2       // Transmit Output Level Adjust
 831 #define PHY_CFG1_TLVL_MASK      0x003C
 832 #define PHY_CFG1_TRF_MASK       0x0003  // Transmitter Rise/Fall time
 833
 834
 835 // PHY Configuration Register 2
 836 #define PHY_CFG2_REG            0x11
 837 #define PHY_CFG2_APOLDIS        0x0020  // 1=Auto Polarity Correction disabled
 838 #define PHY_CFG2_JABDIS         0x0010  // 1=Jabber disabled
 839 #define PHY_CFG2_MREG           0x0008  // 1=Multiple register access (MII mgt)
 840 #define PHY_CFG2_INTMDIO        0x0004  // 1=Interrupt signaled with MDIO pulseo
 841
 842 // PHY Status Output (and Interrupt status) Register
 843 #define PHY_INT_REG             0x12    // Status Output (Interrupt Status)
 844 #define PHY_INT_INT             0x8000  // 1=bits have changed since last read
 845 #define PHY_INT_LNKFAIL         0x4000  // 1=Link Not detected
 846 #define PHY_INT_LOSSSYNC        0x2000  // 1=Descrambler has lost sync
 847 #define PHY_INT_CWRD            0x1000  // 1=Invalid 4B5B code detected on rx
 848 #define PHY_INT_SSD             0x0800  // 1=No Start Of Stream detected on rx
 849 #define PHY_INT_ESD             0x0400  // 1=No End Of Stream detected on rx
 850 #define PHY_INT_RPOL            0x0200  // 1=Reverse Polarity detected
 851 #define PHY_INT_JAB             0x0100  // 1=Jabber detected
 852 #define PHY_INT_SPDDET          0x0080  // 1=100Base-TX mode, 0=10Base-T mode
 853 #define PHY_INT_DPLXDET         0x0040  // 1=Device in Full Duplex
 854
 855 // PHY Interrupt/Status Mask Register
 856 #define PHY_MASK_REG            0x13    // Interrupt Mask
 857 // Uses the same bit definitions as PHY_INT_REG
 858
 859
 860 /*
 861  * SMC91C96 ethernet config and status registers.
 862  * These are in the "attribute" space.
 863  */
 864 #define ECOR                    0x8000
 865 #define ECOR_RESET              0x80
 866 #define ECOR_LEVEL_IRQ          0x40
 867 #define ECOR_WR_ATTRIB          0x04
 868 #define ECOR_ENABLE             0x01
 869
 870 #define ECSR                    0x8002
 871 #define ECSR_IOIS8              0x20
 872 #define ECSR_PWRDWN             0x04
 873 #define ECSR_INT                0x02
 874
 875 #define ATTRIB_SIZE             ((64*1024) << SMC_IO_SHIFT)
 876
 877
 878 /*
 879  * Macros to abstract register access according to the data bus
 880  * capabilities.  Please use those and not the in/out primitives.
 881  * Note: the following macros do *not* select the bank -- this must
 882  * be done separately as needed in the main code.  The SMC_REG() macro
 883  * only uses the bank argument for debugging purposes (when enabled).
 884  *
 885  * Note: despite inline functions being safer, everything leading to this
 886  * should preferably be macros to let BUG() display the line number in
 887  * the core source code since we're interested in the top call site
 888  * not in any inline function location.
 889  */
 890
 891 #if SMC_DEBUG > 0
 892 #define SMC_REG(lp, reg, bank)                                  \
 893         ({                                                              \
 894                 int __b = SMC_CURRENT_BANK(lp);                 \
 895                 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) {       \
 896                         printk( "%s: bank reg screwed (0x%04x)\n",      \
 897                                 CARDNAME, __b );                        \
 898                         BUG();                                          \
 899                 }                                                       \
 900                 reg<<SMC_IO_SHIFT;                                      \
 901         })
 902 #else
 903 #define SMC_REG(lp, reg, bank)  (reg<<SMC_IO_SHIFT)
 904 #endif
 905
 906 /*
 907  * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
 908  * aligned to a 32 bit boundary.  I tell you that does exist!
 909  * Fortunately the affected register accesses can be easily worked around
 910  * since we can write zeroes to the preceding 16 bits without adverse
 911  * effects and use a 32-bit access.
 912  *
 913  * Enforce it on any 32-bit capable setup for now.
 914  */
 915 #define SMC_MUST_ALIGN_WRITE(lp)        SMC_32BIT(lp)
 916
 917 #define SMC_GET_PN(lp)                                          \
 918         (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, PN_REG(lp))) \
 919                                 : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
 920
 921 #define SMC_SET_PN(lp, x)                                               \
 922         do {                                                            \
 923                 if (SMC_MUST_ALIGN_WRITE(lp))                           \
 924                         SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2));   \
 925                 else if (SMC_8BIT(lp))                          \
 926                         SMC_outb(x, ioaddr, PN_REG(lp));                \
 927                 else                                                    \
 928                         SMC_outw(x, ioaddr, PN_REG(lp));                \
 929         } while (0)
 930
 931 #define SMC_GET_AR(lp)                                          \
 932         (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, AR_REG(lp))) \
 933                                 : (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
 934
 935 #define SMC_GET_TXFIFO(lp)                                              \
 936         (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, TXFIFO_REG(lp)))     \
 937                                 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
 938
 939 #define SMC_GET_RXFIFO(lp)                                              \
 940         (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, RXFIFO_REG(lp)))     \
 941                                 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
 942
 943 #define SMC_GET_INT(lp)                                         \
 944         (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, INT_REG(lp)))        \
 945                                 : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
 946
 947 #define SMC_ACK_INT(lp, x)                                              \
 948         do {                                                            \
 949                 if (SMC_8BIT(lp))                                       \
 950                         SMC_outb(x, ioaddr, INT_REG(lp));               \
 951                 else {                                                  \
 952                         unsigned long __flags;                          \
 953                         int __mask;                                     \
 954                         local_irq_save(__flags);                        \
 955                         __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
 956                         SMC_outw(__mask | (x), ioaddr, INT_REG(lp));    \
 957                         local_irq_restore(__flags);                     \
 958                 }                                                       \
 959         } while (0)
 960
 961 #define SMC_GET_INT_MASK(lp)                                            \
 962         (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, IM_REG(lp))) \
 963                                 : (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
 964
 965 #define SMC_SET_INT_MASK(lp, x)                                 \
 966         do {                                                            \
 967                 if (SMC_8BIT(lp))                                       \
 968                         SMC_outb(x, ioaddr, IM_REG(lp));                \
 969                 else                                                    \
 970                         SMC_outw((x) << 8, ioaddr, INT_REG(lp));        \
 971         } while (0)
 972
 973 #define SMC_CURRENT_BANK(lp)    SMC_inw(ioaddr, BANK_SELECT)
 974
 975 #define SMC_SELECT_BANK(lp, x)                                  \
 976         do {                                                            \
 977                 if (SMC_MUST_ALIGN_WRITE(lp))                           \
 978                         SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT);    \
 979                 else                                                    \
 980                         SMC_outw(x, ioaddr, BANK_SELECT);               \
 981         } while (0)
 982
 983 #define SMC_GET_BASE(lp)                SMC_inw(ioaddr, BASE_REG(lp))
 984
 985 #define SMC_SET_BASE(lp, x)             SMC_outw(x, ioaddr, BASE_REG(lp))
 986
 987 #define SMC_GET_CONFIG(lp)      SMC_inw(ioaddr, CONFIG_REG(lp))
 988
 989 #define SMC_SET_CONFIG(lp, x)   SMC_outw(x, ioaddr, CONFIG_REG(lp))
 990
 991 #define SMC_GET_COUNTER(lp)     SMC_inw(ioaddr, COUNTER_REG(lp))
 992
 993 #define SMC_GET_CTL(lp)         SMC_inw(ioaddr, CTL_REG(lp))
 994
 995 #define SMC_SET_CTL(lp, x)              SMC_outw(x, ioaddr, CTL_REG(lp))
 996
 997 #define SMC_GET_MII(lp)         SMC_inw(ioaddr, MII_REG(lp))
 998
 999 #define SMC_GET_GP(lp)          SMC_inw(ioaddr, GP_REG(lp))
1000
1001 #define SMC_SET_GP(lp, x)                                               \
1002         do {                                                            \
1003                 if (SMC_MUST_ALIGN_WRITE(lp))                           \
1004                         SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 1));   \
1005                 else                                                    \
1006                         SMC_outw(x, ioaddr, GP_REG(lp));                \
1007         } while (0)
1008
1009 #define SMC_SET_MII(lp, x)              SMC_outw(x, ioaddr, MII_REG(lp))
1010
1011 #define SMC_GET_MIR(lp)         SMC_inw(ioaddr, MIR_REG(lp))
1012
1013 #define SMC_SET_MIR(lp, x)              SMC_outw(x, ioaddr, MIR_REG(lp))
1014
1015 #define SMC_GET_MMU_CMD(lp)     SMC_inw(ioaddr, MMU_CMD_REG(lp))
1016
1017 #define SMC_SET_MMU_CMD(lp, x)  SMC_outw(x, ioaddr, MMU_CMD_REG(lp))
1018
1019 #define SMC_GET_FIFO(lp)                SMC_inw(ioaddr, FIFO_REG(lp))
1020
1021 #define SMC_GET_PTR(lp)         SMC_inw(ioaddr, PTR_REG(lp))
1022
1023 #define SMC_SET_PTR(lp, x)                                              \
1024         do {                                                            \
1025                 if (SMC_MUST_ALIGN_WRITE(lp))                           \
1026                         SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2));   \
1027                 else                                                    \
1028                         SMC_outw(x, ioaddr, PTR_REG(lp));               \
1029         } while (0)
1030
1031 #define SMC_GET_EPH_STATUS(lp)  SMC_inw(ioaddr, EPH_STATUS_REG(lp))
1032
1033 #define SMC_GET_RCR(lp)         SMC_inw(ioaddr, RCR_REG(lp))
1034
1035 #define SMC_SET_RCR(lp, x)              SMC_outw(x, ioaddr, RCR_REG(lp))
1036
1037 #define SMC_GET_REV(lp)         SMC_inw(ioaddr, REV_REG(lp))
1038
1039 #define SMC_GET_RPC(lp)         SMC_inw(ioaddr, RPC_REG(lp))
1040
1041 #define SMC_SET_RPC(lp, x)                                              \
1042         do {                                                            \
1043                 if (SMC_MUST_ALIGN_WRITE(lp))                           \
1044                         SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0));   \
1045                 else                                                    \
1046                         SMC_outw(x, ioaddr, RPC_REG(lp));               \
1047         } while (0)
1048
1049 #define SMC_GET_TCR(lp)         SMC_inw(ioaddr, TCR_REG(lp))
1050
1051 #define SMC_SET_TCR(lp, x)              SMC_outw(x, ioaddr, TCR_REG(lp))
1052
1053 #ifndef SMC_GET_MAC_ADDR
1054 #define SMC_GET_MAC_ADDR(lp, addr)                                      \
1055         do {                                                            \
1056                 unsigned int __v;                                       \
1057                 __v = SMC_inw(ioaddr, ADDR0_REG(lp));                   \
1058                 addr[0] = __v; addr[1] = __v >> 8;                      \
1059                 __v = SMC_inw(ioaddr, ADDR1_REG(lp));                   \
1060                 addr[2] = __v; addr[3] = __v >> 8;                      \
1061                 __v = SMC_inw(ioaddr, ADDR2_REG(lp));                   \
1062                 addr[4] = __v; addr[5] = __v >> 8;                      \
1063         } while (0)
1064 #endif
1065
1066 #define SMC_SET_MAC_ADDR(lp, addr)                                      \
1067         do {                                                            \
1068                 SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
1069                 SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
1070                 SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
1071         } while (0)
1072
1073 #define SMC_SET_MCAST(lp, x)                                            \
1074         do {                                                            \
1075                 const unsigned char *mt = (x);                          \
1076                 SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
1077                 SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
1078                 SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
1079                 SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
1080         } while (0)
1081
1082 #define SMC_PUT_PKT_HDR(lp, status, length)                             \
1083         do {                                                            \
1084                 if (SMC_32BIT(lp))                                      \
1085                         SMC_outl((status) | (length)<<16, ioaddr,       \
1086                                  DATA_REG(lp));                 \
1087                 else {                                                  \
1088                         SMC_outw(status, ioaddr, DATA_REG(lp)); \
1089                         SMC_outw(length, ioaddr, DATA_REG(lp)); \
1090                 }                                                       \
1091         } while (0)
1092
1093 #define SMC_GET_PKT_HDR(lp, status, length)                             \
1094         do {                                                            \
1095                 if (SMC_32BIT(lp)) {                            \
1096                         unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
1097                         (status) = __val & 0xffff;                      \
1098                         (length) = __val >> 16;                         \
1099                 } else {                                                \
1100                         (status) = SMC_inw(ioaddr, DATA_REG(lp));       \
1101                         (length) = SMC_inw(ioaddr, DATA_REG(lp));       \
1102                 }                                                       \
1103         } while (0)
1104
1105 #define SMC_PUSH_DATA(lp, p, l)                                 \
1106         do {                                                            \
1107                 if (SMC_32BIT(lp)) {                            \
1108                         void *__ptr = (p);                              \
1109                         int __len = (l);                                \
1110                         void __iomem *__ioaddr = ioaddr;                \
1111                         if (__len >= 2 && (unsigned long)__ptr & 2) {   \
1112                                 __len -= 2;                             \
1113                                 SMC_outw(*(u16 *)__ptr, ioaddr,         \
1114                                         DATA_REG(lp));          \
1115                                 __ptr += 2;                             \
1116                         }                                               \
1117                         if (SMC_CAN_USE_DATACS && lp->datacs)           \
1118                                 __ioaddr = lp->datacs;                  \
1119                         SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1120                         if (__len & 2) {                                \
1121                                 __ptr += (__len & ~3);                  \
1122                                 SMC_outw(*((u16 *)__ptr), ioaddr,       \
1123                                          DATA_REG(lp));         \
1124                         }                                               \
1125                 } else if (SMC_16BIT(lp))                               \
1126                         SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1);   \
1127                 else if (SMC_8BIT(lp))                          \
1128                         SMC_outsb(ioaddr, DATA_REG(lp), p, l);  \
1129         } while (0)
1130
1131 #define SMC_PULL_DATA(lp, p, l)                                 \
1132         do {                                                            \
1133                 if (SMC_32BIT(lp)) {                            \
1134                         void *__ptr = (p);                              \
1135                         int __len = (l);                                \
1136                         void __iomem *__ioaddr = ioaddr;                \
1137                         if ((unsigned long)__ptr & 2) {                 \
1138                                 /*                                      \
1139                                  * We want 32bit alignment here.        \
1140                                  * Since some buses perform a full      \
1141                                  * 32bit fetch even for 16bit data      \
1142                                  * we can't use SMC_inw() here.         \
1143                                  * Back both source (on-chip) and       \
1144                                  * destination pointers of 2 bytes.     \
1145                                  * This is possible since the call to   \
1146                                  * SMC_GET_PKT_HDR() already advanced   \
1147                                  * the source pointer of 4 bytes, and   \
1148                                  * the skb_reserve(skb, 2) advanced     \
1149                                  * the destination pointer of 2 bytes.  \
1150                                  */                                     \
1151                                 __ptr -= 2;                             \
1152                                 __len += 2;                             \
1153                                 SMC_SET_PTR(lp,                 \
1154                                         2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
1155                         }                                               \
1156                         if (SMC_CAN_USE_DATACS && lp->datacs)           \
1157                                 __ioaddr = lp->datacs;                  \
1158                         __len += 2;                                     \
1159                         SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1160                 } else if (SMC_16BIT(lp))                               \
1161                         SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1);    \
1162                 else if (SMC_8BIT(lp))                          \
1163                         SMC_insb(ioaddr, DATA_REG(lp), p, l);           \
1164         } while (0)
1165
1166 #endif  /* _SMC91X_H_ */