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Linux 3.4.102
[linux/fpc-iii.git] / drivers / net / ethernet / sun / sungem.c
blob4ba969096717a7ce59e55eaa97f40bdc974ef8b2
1 /* $Id: sungem.c,v 1.44.2.22 2002/03/13 01:18:12 davem Exp $
2 * sungem.c: Sun GEM ethernet driver.
3 *
4 * Copyright (C) 2000, 2001, 2002, 2003 David S. Miller (davem@redhat.com)
5 *
6 * Support for Apple GMAC and assorted PHYs, WOL, Power Management
7 * (C) 2001,2002,2003 Benjamin Herrenscmidt (benh@kernel.crashing.org)
8 * (C) 2004,2005 Benjamin Herrenscmidt, IBM Corp.
9 *
10 * NAPI and NETPOLL support
11 * (C) 2004 by Eric Lemoine (eric.lemoine@gmail.com)
12 *
13 */
14
15 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/types.h>
20 #include <linux/fcntl.h>
21 #include <linux/interrupt.h>
22 #include <linux/ioport.h>
23 #include <linux/in.h>
24 #include <linux/sched.h>
25 #include <linux/string.h>
26 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/errno.h>
29 #include <linux/pci.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/mii.h>
35 #include <linux/ethtool.h>
36 #include <linux/crc32.h>
37 #include <linux/random.h>
38 #include <linux/workqueue.h>
39 #include <linux/if_vlan.h>
40 #include <linux/bitops.h>
41 #include <linux/mm.h>
42 #include <linux/gfp.h>
43
44 #include <asm/io.h>
45 #include <asm/byteorder.h>
46 #include <asm/uaccess.h>
47 #include <asm/irq.h>
48
49 #ifdef CONFIG_SPARC
50 #include <asm/idprom.h>
51 #include <asm/prom.h>
52 #endif
53
54 #ifdef CONFIG_PPC_PMAC
55 #include <asm/pci-bridge.h>
56 #include <asm/prom.h>
57 #include <asm/machdep.h>
58 #include <asm/pmac_feature.h>
59 #endif
60
61 #include <linux/sungem_phy.h>
62 #include "sungem.h"
63
64 /* Stripping FCS is causing problems, disabled for now */
65 #undef STRIP_FCS
66
67 #define DEFAULT_MSG (NETIF_MSG_DRV | \
68 NETIF_MSG_PROBE | \
69 NETIF_MSG_LINK)
70
71 #define ADVERTISE_MASK (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
72 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
73 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full | \
74 SUPPORTED_Pause | SUPPORTED_Autoneg)
75
76 #define DRV_NAME "sungem"
77 #define DRV_VERSION "1.0"
78 #define DRV_AUTHOR "David S. Miller <davem@redhat.com>"
79
80 static char version[] __devinitdata =
81 DRV_NAME ".c:v" DRV_VERSION " " DRV_AUTHOR "\n";
82
83 MODULE_AUTHOR(DRV_AUTHOR);
84 MODULE_DESCRIPTION("Sun GEM Gbit ethernet driver");
85 MODULE_LICENSE("GPL");
86
87 #define GEM_MODULE_NAME "gem"
88
89 static DEFINE_PCI_DEVICE_TABLE(gem_pci_tbl) = {
90 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_GEM,
91 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
92
93 /* These models only differ from the original GEM in
94 * that their tx/rx fifos are of a different size and
95 * they only support 10/100 speeds. -DaveM
96 *
97 * Apple's GMAC does support gigabit on machines with
98 * the BCM54xx PHYs. -BenH
99 */
100 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_RIO_GEM,
101 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
102 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC,
103 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
104 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMACP,
105 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
106 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC2,
107 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
108 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_GMAC,
109 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
110 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_SUNGEM,
111 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
112 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID2_GMAC,
113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
114 {0, }
115 };
116
117 MODULE_DEVICE_TABLE(pci, gem_pci_tbl);
118
119 static u16 __phy_read(struct gem *gp, int phy_addr, int reg)
120 {
121 u32 cmd;
122 int limit = 10000;
123
124 cmd = (1 << 30);
125 cmd |= (2 << 28);
126 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
127 cmd |= (reg << 18) & MIF_FRAME_REGAD;
128 cmd |= (MIF_FRAME_TAMSB);
129 writel(cmd, gp->regs + MIF_FRAME);
130
131 while (--limit) {
132 cmd = readl(gp->regs + MIF_FRAME);
133 if (cmd & MIF_FRAME_TALSB)
134 break;
135
136 udelay(10);
137 }
138
139 if (!limit)
140 cmd = 0xffff;
141
142 return cmd & MIF_FRAME_DATA;
143 }
144
145 static inline int _phy_read(struct net_device *dev, int mii_id, int reg)
146 {
147 struct gem *gp = netdev_priv(dev);
148 return __phy_read(gp, mii_id, reg);
149 }
150
151 static inline u16 phy_read(struct gem *gp, int reg)
152 {
153 return __phy_read(gp, gp->mii_phy_addr, reg);
154 }
155
156 static void __phy_write(struct gem *gp, int phy_addr, int reg, u16 val)
157 {
158 u32 cmd;
159 int limit = 10000;
160
161 cmd = (1 << 30);
162 cmd |= (1 << 28);
163 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
164 cmd |= (reg << 18) & MIF_FRAME_REGAD;
165 cmd |= (MIF_FRAME_TAMSB);
166 cmd |= (val & MIF_FRAME_DATA);
167 writel(cmd, gp->regs + MIF_FRAME);
168
169 while (limit--) {
170 cmd = readl(gp->regs + MIF_FRAME);
171 if (cmd & MIF_FRAME_TALSB)
172 break;
173
174 udelay(10);
175 }
176 }
177
178 static inline void _phy_write(struct net_device *dev, int mii_id, int reg, int val)
179 {
180 struct gem *gp = netdev_priv(dev);
181 __phy_write(gp, mii_id, reg, val & 0xffff);
182 }
183
184 static inline void phy_write(struct gem *gp, int reg, u16 val)
185 {
186 __phy_write(gp, gp->mii_phy_addr, reg, val);
187 }
188
189 static inline void gem_enable_ints(struct gem *gp)
190 {
191 /* Enable all interrupts but TXDONE */
192 writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
193 }
194
195 static inline void gem_disable_ints(struct gem *gp)
196 {
197 /* Disable all interrupts, including TXDONE */
198 writel(GREG_STAT_NAPI | GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
199 (void)readl(gp->regs + GREG_IMASK); /* write posting */
200 }
201
202 static void gem_get_cell(struct gem *gp)
203 {
204 BUG_ON(gp->cell_enabled < 0);
205 gp->cell_enabled++;
206 #ifdef CONFIG_PPC_PMAC
207 if (gp->cell_enabled == 1) {
208 mb();
209 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 1);
210 udelay(10);
211 }
212 #endif /* CONFIG_PPC_PMAC */
213 }
214
215 /* Turn off the chip's clock */
216 static void gem_put_cell(struct gem *gp)
217 {
218 BUG_ON(gp->cell_enabled <= 0);
219 gp->cell_enabled--;
220 #ifdef CONFIG_PPC_PMAC
221 if (gp->cell_enabled == 0) {
222 mb();
223 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 0);
224 udelay(10);
225 }
226 #endif /* CONFIG_PPC_PMAC */
227 }
228
229 static inline void gem_netif_stop(struct gem *gp)
230 {
231 gp->dev->trans_start = jiffies; /* prevent tx timeout */
232 napi_disable(&gp->napi);
233 netif_tx_disable(gp->dev);
234 }
235
236 static inline void gem_netif_start(struct gem *gp)
237 {
238 /* NOTE: unconditional netif_wake_queue is only
239 * appropriate so long as all callers are assured to
240 * have free tx slots.
241 */
242 netif_wake_queue(gp->dev);
243 napi_enable(&gp->napi);
244 }
245
246 static void gem_schedule_reset(struct gem *gp)
247 {
248 gp->reset_task_pending = 1;
249 schedule_work(&gp->reset_task);
250 }
251
252 static void gem_handle_mif_event(struct gem *gp, u32 reg_val, u32 changed_bits)
253 {
254 if (netif_msg_intr(gp))
255 printk(KERN_DEBUG "%s: mif interrupt\n", gp->dev->name);
256 }
257
258 static int gem_pcs_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
259 {
260 u32 pcs_istat = readl(gp->regs + PCS_ISTAT);
261 u32 pcs_miistat;
262
263 if (netif_msg_intr(gp))
264 printk(KERN_DEBUG "%s: pcs interrupt, pcs_istat: 0x%x\n",
265 gp->dev->name, pcs_istat);
266
267 if (!(pcs_istat & PCS_ISTAT_LSC)) {
268 netdev_err(dev, "PCS irq but no link status change???\n");
269 return 0;
270 }
271
272 /* The link status bit latches on zero, so you must
273 * read it twice in such a case to see a transition
274 * to the link being up.
275 */
276 pcs_miistat = readl(gp->regs + PCS_MIISTAT);
277 if (!(pcs_miistat & PCS_MIISTAT_LS))
278 pcs_miistat |=
279 (readl(gp->regs + PCS_MIISTAT) &
280 PCS_MIISTAT_LS);
281
282 if (pcs_miistat & PCS_MIISTAT_ANC) {
283 /* The remote-fault indication is only valid
284 * when autoneg has completed.
285 */
286 if (pcs_miistat & PCS_MIISTAT_RF)
287 netdev_info(dev, "PCS AutoNEG complete, RemoteFault\n");
288 else
289 netdev_info(dev, "PCS AutoNEG complete\n");
290 }
291
292 if (pcs_miistat & PCS_MIISTAT_LS) {
293 netdev_info(dev, "PCS link is now up\n");
294 netif_carrier_on(gp->dev);
295 } else {
296 netdev_info(dev, "PCS link is now down\n");
297 netif_carrier_off(gp->dev);
298 /* If this happens and the link timer is not running,
299 * reset so we re-negotiate.
300 */
301 if (!timer_pending(&gp->link_timer))
302 return 1;
303 }
304
305 return 0;
306 }
307
308 static int gem_txmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
309 {
310 u32 txmac_stat = readl(gp->regs + MAC_TXSTAT);
311
312 if (netif_msg_intr(gp))
313 printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n",
314 gp->dev->name, txmac_stat);
315
316 /* Defer timer expiration is quite normal,
317 * don't even log the event.
318 */
319 if ((txmac_stat & MAC_TXSTAT_DTE) &&
320 !(txmac_stat & ~MAC_TXSTAT_DTE))
321 return 0;
322
323 if (txmac_stat & MAC_TXSTAT_URUN) {
324 netdev_err(dev, "TX MAC xmit underrun\n");
325 dev->stats.tx_fifo_errors++;
326 }
327
328 if (txmac_stat & MAC_TXSTAT_MPE) {
329 netdev_err(dev, "TX MAC max packet size error\n");
330 dev->stats.tx_errors++;
331 }
332
333 /* The rest are all cases of one of the 16-bit TX
334 * counters expiring.
335 */
336 if (txmac_stat & MAC_TXSTAT_NCE)
337 dev->stats.collisions += 0x10000;
338
339 if (txmac_stat & MAC_TXSTAT_ECE) {
340 dev->stats.tx_aborted_errors += 0x10000;
341 dev->stats.collisions += 0x10000;
342 }
343
344 if (txmac_stat & MAC_TXSTAT_LCE) {
345 dev->stats.tx_aborted_errors += 0x10000;
346 dev->stats.collisions += 0x10000;
347 }
348
349 /* We do not keep track of MAC_TXSTAT_FCE and
350 * MAC_TXSTAT_PCE events.
351 */
352 return 0;
353 }
354
355 /* When we get a RX fifo overflow, the RX unit in GEM is probably hung
356 * so we do the following.
357 *
358 * If any part of the reset goes wrong, we return 1 and that causes the
359 * whole chip to be reset.
360 */
361 static int gem_rxmac_reset(struct gem *gp)
362 {
363 struct net_device *dev = gp->dev;
364 int limit, i;
365 u64 desc_dma;
366 u32 val;
367
368 /* First, reset & disable MAC RX. */
369 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
370 for (limit = 0; limit < 5000; limit++) {
371 if (!(readl(gp->regs + MAC_RXRST) & MAC_RXRST_CMD))
372 break;
373 udelay(10);
374 }
375 if (limit == 5000) {
376 netdev_err(dev, "RX MAC will not reset, resetting whole chip\n");
377 return 1;
378 }
379
380 writel(gp->mac_rx_cfg & ~MAC_RXCFG_ENAB,
381 gp->regs + MAC_RXCFG);
382 for (limit = 0; limit < 5000; limit++) {
383 if (!(readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB))
384 break;
385 udelay(10);
386 }
387 if (limit == 5000) {
388 netdev_err(dev, "RX MAC will not disable, resetting whole chip\n");
389 return 1;
390 }
391
392 /* Second, disable RX DMA. */
393 writel(0, gp->regs + RXDMA_CFG);
394 for (limit = 0; limit < 5000; limit++) {
395 if (!(readl(gp->regs + RXDMA_CFG) & RXDMA_CFG_ENABLE))
396 break;
397 udelay(10);
398 }
399 if (limit == 5000) {
400 netdev_err(dev, "RX DMA will not disable, resetting whole chip\n");
401 return 1;
402 }
403
404 udelay(5000);
405
406 /* Execute RX reset command. */
407 writel(gp->swrst_base | GREG_SWRST_RXRST,
408 gp->regs + GREG_SWRST);
409 for (limit = 0; limit < 5000; limit++) {
410 if (!(readl(gp->regs + GREG_SWRST) & GREG_SWRST_RXRST))
411 break;
412 udelay(10);
413 }
414 if (limit == 5000) {
415 netdev_err(dev, "RX reset command will not execute, resetting whole chip\n");
416 return 1;
417 }
418
419 /* Refresh the RX ring. */
420 for (i = 0; i < RX_RING_SIZE; i++) {
421 struct gem_rxd *rxd = &gp->init_block->rxd[i];
422
423 if (gp->rx_skbs[i] == NULL) {
424 netdev_err(dev, "Parts of RX ring empty, resetting whole chip\n");
425 return 1;
426 }
427
428 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
429 }
430 gp->rx_new = gp->rx_old = 0;
431
432 /* Now we must reprogram the rest of RX unit. */
433 desc_dma = (u64) gp->gblock_dvma;
434 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
435 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
436 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
437 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
438 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
439 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
440 writel(val, gp->regs + RXDMA_CFG);
441 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
442 writel(((5 & RXDMA_BLANK_IPKTS) |
443 ((8 << 12) & RXDMA_BLANK_ITIME)),
444 gp->regs + RXDMA_BLANK);
445 else
446 writel(((5 & RXDMA_BLANK_IPKTS) |
447 ((4 << 12) & RXDMA_BLANK_ITIME)),
448 gp->regs + RXDMA_BLANK);
449 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
450 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
451 writel(val, gp->regs + RXDMA_PTHRESH);
452 val = readl(gp->regs + RXDMA_CFG);
453 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
454 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
455 val = readl(gp->regs + MAC_RXCFG);
456 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
457
458 return 0;
459 }
460
461 static int gem_rxmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
462 {
463 u32 rxmac_stat = readl(gp->regs + MAC_RXSTAT);
464 int ret = 0;
465
466 if (netif_msg_intr(gp))
467 printk(KERN_DEBUG "%s: rxmac interrupt, rxmac_stat: 0x%x\n",
468 gp->dev->name, rxmac_stat);
469
470 if (rxmac_stat & MAC_RXSTAT_OFLW) {
471 u32 smac = readl(gp->regs + MAC_SMACHINE);
472
473 netdev_err(dev, "RX MAC fifo overflow smac[%08x]\n", smac);
474 dev->stats.rx_over_errors++;
475 dev->stats.rx_fifo_errors++;
476
477 ret = gem_rxmac_reset(gp);
478 }
479
480 if (rxmac_stat & MAC_RXSTAT_ACE)
481 dev->stats.rx_frame_errors += 0x10000;
482
483 if (rxmac_stat & MAC_RXSTAT_CCE)
484 dev->stats.rx_crc_errors += 0x10000;
485
486 if (rxmac_stat & MAC_RXSTAT_LCE)
487 dev->stats.rx_length_errors += 0x10000;
488
489 /* We do not track MAC_RXSTAT_FCE and MAC_RXSTAT_VCE
490 * events.
491 */
492 return ret;
493 }
494
495 static int gem_mac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
496 {
497 u32 mac_cstat = readl(gp->regs + MAC_CSTAT);
498
499 if (netif_msg_intr(gp))
500 printk(KERN_DEBUG "%s: mac interrupt, mac_cstat: 0x%x\n",
501 gp->dev->name, mac_cstat);
502
503 /* This interrupt is just for pause frame and pause
504 * tracking. It is useful for diagnostics and debug
505 * but probably by default we will mask these events.
506 */
507 if (mac_cstat & MAC_CSTAT_PS)
508 gp->pause_entered++;
509
510 if (mac_cstat & MAC_CSTAT_PRCV)
511 gp->pause_last_time_recvd = (mac_cstat >> 16);
512
513 return 0;
514 }
515
516 static int gem_mif_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
517 {
518 u32 mif_status = readl(gp->regs + MIF_STATUS);
519 u32 reg_val, changed_bits;
520
521 reg_val = (mif_status & MIF_STATUS_DATA) >> 16;
522 changed_bits = (mif_status & MIF_STATUS_STAT);
523
524 gem_handle_mif_event(gp, reg_val, changed_bits);
525
526 return 0;
527 }
528
529 static int gem_pci_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
530 {
531 u32 pci_estat = readl(gp->regs + GREG_PCIESTAT);
532
533 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
534 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
535 netdev_err(dev, "PCI error [%04x]", pci_estat);
536
537 if (pci_estat & GREG_PCIESTAT_BADACK)
538 pr_cont(" <No ACK64# during ABS64 cycle>");
539 if (pci_estat & GREG_PCIESTAT_DTRTO)
540 pr_cont(" <Delayed transaction timeout>");
541 if (pci_estat & GREG_PCIESTAT_OTHER)
542 pr_cont(" <other>");
543 pr_cont("\n");
544 } else {
545 pci_estat |= GREG_PCIESTAT_OTHER;
546 netdev_err(dev, "PCI error\n");
547 }
548
549 if (pci_estat & GREG_PCIESTAT_OTHER) {
550 u16 pci_cfg_stat;
551
552 /* Interrogate PCI config space for the
553 * true cause.
554 */
555 pci_read_config_word(gp->pdev, PCI_STATUS,
556 &pci_cfg_stat);
557 netdev_err(dev, "Read PCI cfg space status [%04x]\n",
558 pci_cfg_stat);
559 if (pci_cfg_stat & PCI_STATUS_PARITY)
560 netdev_err(dev, "PCI parity error detected\n");
561 if (pci_cfg_stat & PCI_STATUS_SIG_TARGET_ABORT)
562 netdev_err(dev, "PCI target abort\n");
563 if (pci_cfg_stat & PCI_STATUS_REC_TARGET_ABORT)
564 netdev_err(dev, "PCI master acks target abort\n");
565 if (pci_cfg_stat & PCI_STATUS_REC_MASTER_ABORT)
566 netdev_err(dev, "PCI master abort\n");
567 if (pci_cfg_stat & PCI_STATUS_SIG_SYSTEM_ERROR)
568 netdev_err(dev, "PCI system error SERR#\n");
569 if (pci_cfg_stat & PCI_STATUS_DETECTED_PARITY)
570 netdev_err(dev, "PCI parity error\n");
571
572 /* Write the error bits back to clear them. */
573 pci_cfg_stat &= (PCI_STATUS_PARITY |
574 PCI_STATUS_SIG_TARGET_ABORT |
575 PCI_STATUS_REC_TARGET_ABORT |
576 PCI_STATUS_REC_MASTER_ABORT |
577 PCI_STATUS_SIG_SYSTEM_ERROR |
578 PCI_STATUS_DETECTED_PARITY);
579 pci_write_config_word(gp->pdev,
580 PCI_STATUS, pci_cfg_stat);
581 }
582
583 /* For all PCI errors, we should reset the chip. */
584 return 1;
585 }
586
587 /* All non-normal interrupt conditions get serviced here.
588 * Returns non-zero if we should just exit the interrupt
589 * handler right now (ie. if we reset the card which invalidates
590 * all of the other original irq status bits).
591 */
592 static int gem_abnormal_irq(struct net_device *dev, struct gem *gp, u32 gem_status)
593 {
594 if (gem_status & GREG_STAT_RXNOBUF) {
595 /* Frame arrived, no free RX buffers available. */
596 if (netif_msg_rx_err(gp))
597 printk(KERN_DEBUG "%s: no buffer for rx frame\n",
598 gp->dev->name);
599 dev->stats.rx_dropped++;
600 }
601
602 if (gem_status & GREG_STAT_RXTAGERR) {
603 /* corrupt RX tag framing */
604 if (netif_msg_rx_err(gp))
605 printk(KERN_DEBUG "%s: corrupt rx tag framing\n",
606 gp->dev->name);
607 dev->stats.rx_errors++;
608
609 return 1;
610 }
611
612 if (gem_status & GREG_STAT_PCS) {
613 if (gem_pcs_interrupt(dev, gp, gem_status))
614 return 1;
615 }
616
617 if (gem_status & GREG_STAT_TXMAC) {
618 if (gem_txmac_interrupt(dev, gp, gem_status))
619 return 1;
620 }
621
622 if (gem_status & GREG_STAT_RXMAC) {
623 if (gem_rxmac_interrupt(dev, gp, gem_status))
624 return 1;
625 }
626
627 if (gem_status & GREG_STAT_MAC) {
628 if (gem_mac_interrupt(dev, gp, gem_status))
629 return 1;
630 }
631
632 if (gem_status & GREG_STAT_MIF) {
633 if (gem_mif_interrupt(dev, gp, gem_status))
634 return 1;
635 }
636
637 if (gem_status & GREG_STAT_PCIERR) {
638 if (gem_pci_interrupt(dev, gp, gem_status))
639 return 1;
640 }
641
642 return 0;
643 }
644
645 static __inline__ void gem_tx(struct net_device *dev, struct gem *gp, u32 gem_status)
646 {
647 int entry, limit;
648
649 entry = gp->tx_old;
650 limit = ((gem_status & GREG_STAT_TXNR) >> GREG_STAT_TXNR_SHIFT);
651 while (entry != limit) {
652 struct sk_buff *skb;
653 struct gem_txd *txd;
654 dma_addr_t dma_addr;
655 u32 dma_len;
656 int frag;
657
658 if (netif_msg_tx_done(gp))
659 printk(KERN_DEBUG "%s: tx done, slot %d\n",
660 gp->dev->name, entry);
661 skb = gp->tx_skbs[entry];
662 if (skb_shinfo(skb)->nr_frags) {
663 int last = entry + skb_shinfo(skb)->nr_frags;
664 int walk = entry;
665 int incomplete = 0;
666
667 last &= (TX_RING_SIZE - 1);
668 for (;;) {
669 walk = NEXT_TX(walk);
670 if (walk == limit)
671 incomplete = 1;
672 if (walk == last)
673 break;
674 }
675 if (incomplete)
676 break;
677 }
678 gp->tx_skbs[entry] = NULL;
679 dev->stats.tx_bytes += skb->len;
680
681 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
682 txd = &gp->init_block->txd[entry];
683
684 dma_addr = le64_to_cpu(txd->buffer);
685 dma_len = le64_to_cpu(txd->control_word) & TXDCTRL_BUFSZ;
686
687 pci_unmap_page(gp->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
688 entry = NEXT_TX(entry);
689 }
690
691 dev->stats.tx_packets++;
692 dev_kfree_skb(skb);
693 }
694 gp->tx_old = entry;
695
696 /* Need to make the tx_old update visible to gem_start_xmit()
697 * before checking for netif_queue_stopped(). Without the
698 * memory barrier, there is a small possibility that gem_start_xmit()
699 * will miss it and cause the queue to be stopped forever.
700 */
701 smp_mb();
702
703 if (unlikely(netif_queue_stopped(dev) &&
704 TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))) {
705 struct netdev_queue *txq = netdev_get_tx_queue(dev, 0);
706
707 __netif_tx_lock(txq, smp_processor_id());
708 if (netif_queue_stopped(dev) &&
709 TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))
710 netif_wake_queue(dev);
711 __netif_tx_unlock(txq);
712 }
713 }
714
715 static __inline__ void gem_post_rxds(struct gem *gp, int limit)
716 {
717 int cluster_start, curr, count, kick;
718
719 cluster_start = curr = (gp->rx_new & ~(4 - 1));
720 count = 0;
721 kick = -1;
722 wmb();
723 while (curr != limit) {
724 curr = NEXT_RX(curr);
725 if (++count == 4) {
726 struct gem_rxd *rxd =
727 &gp->init_block->rxd[cluster_start];
728 for (;;) {
729 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
730 rxd++;
731 cluster_start = NEXT_RX(cluster_start);
732 if (cluster_start == curr)
733 break;
734 }
735 kick = curr;
736 count = 0;
737 }
738 }
739 if (kick >= 0) {
740 mb();
741 writel(kick, gp->regs + RXDMA_KICK);
742 }
743 }
744
745 #define ALIGNED_RX_SKB_ADDR(addr) \
746 ((((unsigned long)(addr) + (64UL - 1UL)) & ~(64UL - 1UL)) - (unsigned long)(addr))
747 static __inline__ struct sk_buff *gem_alloc_skb(struct net_device *dev, int size,
748 gfp_t gfp_flags)
749 {
750 struct sk_buff *skb = alloc_skb(size + 64, gfp_flags);
751
752 if (likely(skb)) {
753 unsigned long offset = ALIGNED_RX_SKB_ADDR(skb->data);
754 skb_reserve(skb, offset);
755 skb->dev = dev;
756 }
757 return skb;
758 }
759
760 static int gem_rx(struct gem *gp, int work_to_do)
761 {
762 struct net_device *dev = gp->dev;
763 int entry, drops, work_done = 0;
764 u32 done;
765 __sum16 csum;
766
767 if (netif_msg_rx_status(gp))
768 printk(KERN_DEBUG "%s: rx interrupt, done: %d, rx_new: %d\n",
769 gp->dev->name, readl(gp->regs + RXDMA_DONE), gp->rx_new);
770
771 entry = gp->rx_new;
772 drops = 0;
773 done = readl(gp->regs + RXDMA_DONE);
774 for (;;) {
775 struct gem_rxd *rxd = &gp->init_block->rxd[entry];
776 struct sk_buff *skb;
777 u64 status = le64_to_cpu(rxd->status_word);
778 dma_addr_t dma_addr;
779 int len;
780
781 if ((status & RXDCTRL_OWN) != 0)
782 break;
783
784 if (work_done >= RX_RING_SIZE || work_done >= work_to_do)
785 break;
786
787 /* When writing back RX descriptor, GEM writes status
788 * then buffer address, possibly in separate transactions.
789 * If we don't wait for the chip to write both, we could
790 * post a new buffer to this descriptor then have GEM spam
791 * on the buffer address. We sync on the RX completion
792 * register to prevent this from happening.
793 */
794 if (entry == done) {
795 done = readl(gp->regs + RXDMA_DONE);
796 if (entry == done)
797 break;
798 }
799
800 /* We can now account for the work we're about to do */
801 work_done++;
802
803 skb = gp->rx_skbs[entry];
804
805 len = (status & RXDCTRL_BUFSZ) >> 16;
806 if ((len < ETH_ZLEN) || (status & RXDCTRL_BAD)) {
807 dev->stats.rx_errors++;
808 if (len < ETH_ZLEN)
809 dev->stats.rx_length_errors++;
810 if (len & RXDCTRL_BAD)
811 dev->stats.rx_crc_errors++;
812
813 /* We'll just return it to GEM. */
814 drop_it:
815 dev->stats.rx_dropped++;
816 goto next;
817 }
818
819 dma_addr = le64_to_cpu(rxd->buffer);
820 if (len > RX_COPY_THRESHOLD) {
821 struct sk_buff *new_skb;
822
823 new_skb = gem_alloc_skb(dev, RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
824 if (new_skb == NULL) {
825 drops++;
826 goto drop_it;
827 }
828 pci_unmap_page(gp->pdev, dma_addr,
829 RX_BUF_ALLOC_SIZE(gp),
830 PCI_DMA_FROMDEVICE);
831 gp->rx_skbs[entry] = new_skb;
832 skb_put(new_skb, (gp->rx_buf_sz + RX_OFFSET));
833 rxd->buffer = cpu_to_le64(pci_map_page(gp->pdev,
834 virt_to_page(new_skb->data),
835 offset_in_page(new_skb->data),
836 RX_BUF_ALLOC_SIZE(gp),
837 PCI_DMA_FROMDEVICE));
838 skb_reserve(new_skb, RX_OFFSET);
839
840 /* Trim the original skb for the netif. */
841 skb_trim(skb, len);
842 } else {
843 struct sk_buff *copy_skb = netdev_alloc_skb(dev, len + 2);
844
845 if (copy_skb == NULL) {
846 drops++;
847 goto drop_it;
848 }
849
850 skb_reserve(copy_skb, 2);
851 skb_put(copy_skb, len);
852 pci_dma_sync_single_for_cpu(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
853 skb_copy_from_linear_data(skb, copy_skb->data, len);
854 pci_dma_sync_single_for_device(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
855
856 /* We'll reuse the original ring buffer. */
857 skb = copy_skb;
858 }
859
860 csum = (__force __sum16)htons((status & RXDCTRL_TCPCSUM) ^ 0xffff);
861 skb->csum = csum_unfold(csum);
862 skb->ip_summed = CHECKSUM_COMPLETE;
863 skb->protocol = eth_type_trans(skb, gp->dev);
864
865 napi_gro_receive(&gp->napi, skb);
866
867 dev->stats.rx_packets++;
868 dev->stats.rx_bytes += len;
869
870 next:
871 entry = NEXT_RX(entry);
872 }
873
874 gem_post_rxds(gp, entry);
875
876 gp->rx_new = entry;
877
878 if (drops)
879 netdev_info(gp->dev, "Memory squeeze, deferring packet\n");
880
881 return work_done;
882 }
883
884 static int gem_poll(struct napi_struct *napi, int budget)
885 {
886 struct gem *gp = container_of(napi, struct gem, napi);
887 struct net_device *dev = gp->dev;
888 int work_done;
889
890 work_done = 0;
891 do {
892 /* Handle anomalies */
893 if (unlikely(gp->status & GREG_STAT_ABNORMAL)) {
894 struct netdev_queue *txq = netdev_get_tx_queue(dev, 0);
895 int reset;
896
897 /* We run the abnormal interrupt handling code with
898 * the Tx lock. It only resets the Rx portion of the
899 * chip, but we need to guard it against DMA being
900 * restarted by the link poll timer
901 */
902 __netif_tx_lock(txq, smp_processor_id());
903 reset = gem_abnormal_irq(dev, gp, gp->status);
904 __netif_tx_unlock(txq);
905 if (reset) {
906 gem_schedule_reset(gp);
907 napi_complete(napi);
908 return work_done;
909 }
910 }
911
912 /* Run TX completion thread */
913 gem_tx(dev, gp, gp->status);
914
915 /* Run RX thread. We don't use any locking here,
916 * code willing to do bad things - like cleaning the
917 * rx ring - must call napi_disable(), which
918 * schedule_timeout()'s if polling is already disabled.
919 */
920 work_done += gem_rx(gp, budget - work_done);
921
922 if (work_done >= budget)
923 return work_done;
924
925 gp->status = readl(gp->regs + GREG_STAT);
926 } while (gp->status & GREG_STAT_NAPI);
927
928 napi_complete(napi);
929 gem_enable_ints(gp);
930
931 return work_done;
932 }
933
934 static irqreturn_t gem_interrupt(int irq, void *dev_id)
935 {
936 struct net_device *dev = dev_id;
937 struct gem *gp = netdev_priv(dev);
938
939 if (napi_schedule_prep(&gp->napi)) {
940 u32 gem_status = readl(gp->regs + GREG_STAT);
941
942 if (unlikely(gem_status == 0)) {
943 napi_enable(&gp->napi);
944 return IRQ_NONE;
945 }
946 if (netif_msg_intr(gp))
947 printk(KERN_DEBUG "%s: gem_interrupt() gem_status: 0x%x\n",
948 gp->dev->name, gem_status);
949
950 gp->status = gem_status;
951 gem_disable_ints(gp);
952 __napi_schedule(&gp->napi);
953 }
954
955 /* If polling was disabled at the time we received that
956 * interrupt, we may return IRQ_HANDLED here while we
957 * should return IRQ_NONE. No big deal...
958 */
959 return IRQ_HANDLED;
960 }
961
962 #ifdef CONFIG_NET_POLL_CONTROLLER
963 static void gem_poll_controller(struct net_device *dev)
964 {
965 struct gem *gp = netdev_priv(dev);
966
967 disable_irq(gp->pdev->irq);
968 gem_interrupt(gp->pdev->irq, dev);
969 enable_irq(gp->pdev->irq);
970 }
971 #endif
972
973 static void gem_tx_timeout(struct net_device *dev)
974 {
975 struct gem *gp = netdev_priv(dev);
976
977 netdev_err(dev, "transmit timed out, resetting\n");
978
979 netdev_err(dev, "TX_STATE[%08x:%08x:%08x]\n",
980 readl(gp->regs + TXDMA_CFG),
981 readl(gp->regs + MAC_TXSTAT),
982 readl(gp->regs + MAC_TXCFG));
983 netdev_err(dev, "RX_STATE[%08x:%08x:%08x]\n",
984 readl(gp->regs + RXDMA_CFG),
985 readl(gp->regs + MAC_RXSTAT),
986 readl(gp->regs + MAC_RXCFG));
987
988 gem_schedule_reset(gp);
989 }
990
991 static __inline__ int gem_intme(int entry)
992 {
993 /* Algorithm: IRQ every 1/2 of descriptors. */
994 if (!(entry & ((TX_RING_SIZE>>1)-1)))
995 return 1;
996
997 return 0;
998 }
999
1000 static netdev_tx_t gem_start_xmit(struct sk_buff *skb,
1001 struct net_device *dev)
1002 {
1003 struct gem *gp = netdev_priv(dev);
1004 int entry;
1005 u64 ctrl;
1006
1007 ctrl = 0;
1008 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1009 const u64 csum_start_off = skb_checksum_start_offset(skb);
1010 const u64 csum_stuff_off = csum_start_off + skb->csum_offset;
1011
1012 ctrl = (TXDCTRL_CENAB |
1013 (csum_start_off << 15) |
1014 (csum_stuff_off << 21));
1015 }
1016
1017 if (unlikely(TX_BUFFS_AVAIL(gp) <= (skb_shinfo(skb)->nr_frags + 1))) {
1018 /* This is a hard error, log it. */
1019 if (!netif_queue_stopped(dev)) {
1020 netif_stop_queue(dev);
1021 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
1022 }
1023 return NETDEV_TX_BUSY;
1024 }
1025
1026 entry = gp->tx_new;
1027 gp->tx_skbs[entry] = skb;
1028
1029 if (skb_shinfo(skb)->nr_frags == 0) {
1030 struct gem_txd *txd = &gp->init_block->txd[entry];
1031 dma_addr_t mapping;
1032 u32 len;
1033
1034 len = skb->len;
1035 mapping = pci_map_page(gp->pdev,
1036 virt_to_page(skb->data),
1037 offset_in_page(skb->data),
1038 len, PCI_DMA_TODEVICE);
1039 ctrl |= TXDCTRL_SOF | TXDCTRL_EOF | len;
1040 if (gem_intme(entry))
1041 ctrl |= TXDCTRL_INTME;
1042 txd->buffer = cpu_to_le64(mapping);
1043 wmb();
1044 txd->control_word = cpu_to_le64(ctrl);
1045 entry = NEXT_TX(entry);
1046 } else {
1047 struct gem_txd *txd;
1048 u32 first_len;
1049 u64 intme;
1050 dma_addr_t first_mapping;
1051 int frag, first_entry = entry;
1052
1053 intme = 0;
1054 if (gem_intme(entry))
1055 intme |= TXDCTRL_INTME;
1056
1057 /* We must give this initial chunk to the device last.
1058 * Otherwise we could race with the device.
1059 */
1060 first_len = skb_headlen(skb);
1061 first_mapping = pci_map_page(gp->pdev, virt_to_page(skb->data),
1062 offset_in_page(skb->data),
1063 first_len, PCI_DMA_TODEVICE);
1064 entry = NEXT_TX(entry);
1065
1066 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1067 const skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1068 u32 len;
1069 dma_addr_t mapping;
1070 u64 this_ctrl;
1071
1072 len = skb_frag_size(this_frag);
1073 mapping = skb_frag_dma_map(&gp->pdev->dev, this_frag,
1074 0, len, DMA_TO_DEVICE);
1075 this_ctrl = ctrl;
1076 if (frag == skb_shinfo(skb)->nr_frags - 1)
1077 this_ctrl |= TXDCTRL_EOF;
1078
1079 txd = &gp->init_block->txd[entry];
1080 txd->buffer = cpu_to_le64(mapping);
1081 wmb();
1082 txd->control_word = cpu_to_le64(this_ctrl | len);
1083
1084 if (gem_intme(entry))
1085 intme |= TXDCTRL_INTME;
1086
1087 entry = NEXT_TX(entry);
1088 }
1089 txd = &gp->init_block->txd[first_entry];
1090 txd->buffer = cpu_to_le64(first_mapping);
1091 wmb();
1092 txd->control_word =
1093 cpu_to_le64(ctrl | TXDCTRL_SOF | intme | first_len);
1094 }
1095
1096 gp->tx_new = entry;
1097 if (unlikely(TX_BUFFS_AVAIL(gp) <= (MAX_SKB_FRAGS + 1))) {
1098 netif_stop_queue(dev);
1099
1100 /* netif_stop_queue() must be done before checking
1101 * checking tx index in TX_BUFFS_AVAIL() below, because
1102 * in gem_tx(), we update tx_old before checking for
1103 * netif_queue_stopped().
1104 */
1105 smp_mb();
1106 if (TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))
1107 netif_wake_queue(dev);
1108 }
1109 if (netif_msg_tx_queued(gp))
1110 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
1111 dev->name, entry, skb->len);
1112 mb();
1113 writel(gp->tx_new, gp->regs + TXDMA_KICK);
1114
1115 return NETDEV_TX_OK;
1116 }
1117
1118 static void gem_pcs_reset(struct gem *gp)
1119 {
1120 int limit;
1121 u32 val;
1122
1123 /* Reset PCS unit. */
1124 val = readl(gp->regs + PCS_MIICTRL);
1125 val |= PCS_MIICTRL_RST;
1126 writel(val, gp->regs + PCS_MIICTRL);
1127
1128 limit = 32;
1129 while (readl(gp->regs + PCS_MIICTRL) & PCS_MIICTRL_RST) {
1130 udelay(100);
1131 if (limit-- <= 0)
1132 break;
1133 }
1134 if (limit < 0)
1135 netdev_warn(gp->dev, "PCS reset bit would not clear\n");
1136 }
1137
1138 static void gem_pcs_reinit_adv(struct gem *gp)
1139 {
1140 u32 val;
1141
1142 /* Make sure PCS is disabled while changing advertisement
1143 * configuration.
1144 */
1145 val = readl(gp->regs + PCS_CFG);
1146 val &= ~(PCS_CFG_ENABLE | PCS_CFG_TO);
1147 writel(val, gp->regs + PCS_CFG);
1148
1149 /* Advertise all capabilities except asymmetric
1150 * pause.
1151 */
1152 val = readl(gp->regs + PCS_MIIADV);
1153 val |= (PCS_MIIADV_FD | PCS_MIIADV_HD |
1154 PCS_MIIADV_SP | PCS_MIIADV_AP);
1155 writel(val, gp->regs + PCS_MIIADV);
1156
1157 /* Enable and restart auto-negotiation, disable wrapback/loopback,
1158 * and re-enable PCS.
1159 */
1160 val = readl(gp->regs + PCS_MIICTRL);
1161 val |= (PCS_MIICTRL_RAN | PCS_MIICTRL_ANE);
1162 val &= ~PCS_MIICTRL_WB;
1163 writel(val, gp->regs + PCS_MIICTRL);
1164
1165 val = readl(gp->regs + PCS_CFG);
1166 val |= PCS_CFG_ENABLE;
1167 writel(val, gp->regs + PCS_CFG);
1168
1169 /* Make sure serialink loopback is off. The meaning
1170 * of this bit is logically inverted based upon whether
1171 * you are in Serialink or SERDES mode.
1172 */
1173 val = readl(gp->regs + PCS_SCTRL);
1174 if (gp->phy_type == phy_serialink)
1175 val &= ~PCS_SCTRL_LOOP;
1176 else
1177 val |= PCS_SCTRL_LOOP;
1178 writel(val, gp->regs + PCS_SCTRL);
1179 }
1180
1181 #define STOP_TRIES 32
1182
1183 static void gem_reset(struct gem *gp)
1184 {
1185 int limit;
1186 u32 val;
1187
1188 /* Make sure we won't get any more interrupts */
1189 writel(0xffffffff, gp->regs + GREG_IMASK);
1190
1191 /* Reset the chip */
1192 writel(gp->swrst_base | GREG_SWRST_TXRST | GREG_SWRST_RXRST,
1193 gp->regs + GREG_SWRST);
1194
1195 limit = STOP_TRIES;
1196
1197 do {
1198 udelay(20);
1199 val = readl(gp->regs + GREG_SWRST);
1200 if (limit-- <= 0)
1201 break;
1202 } while (val & (GREG_SWRST_TXRST | GREG_SWRST_RXRST));
1203
1204 if (limit < 0)
1205 netdev_err(gp->dev, "SW reset is ghetto\n");
1206
1207 if (gp->phy_type == phy_serialink || gp->phy_type == phy_serdes)
1208 gem_pcs_reinit_adv(gp);
1209 }
1210
1211 static void gem_start_dma(struct gem *gp)
1212 {
1213 u32 val;
1214
1215 /* We are ready to rock, turn everything on. */
1216 val = readl(gp->regs + TXDMA_CFG);
1217 writel(val | TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1218 val = readl(gp->regs + RXDMA_CFG);
1219 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1220 val = readl(gp->regs + MAC_TXCFG);
1221 writel(val | MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1222 val = readl(gp->regs + MAC_RXCFG);
1223 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1224
1225 (void) readl(gp->regs + MAC_RXCFG);
1226 udelay(100);
1227
1228 gem_enable_ints(gp);
1229
1230 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1231 }
1232
1233 /* DMA won't be actually stopped before about 4ms tho ...
1234 */
1235 static void gem_stop_dma(struct gem *gp)
1236 {
1237 u32 val;
1238
1239 /* We are done rocking, turn everything off. */
1240 val = readl(gp->regs + TXDMA_CFG);
1241 writel(val & ~TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1242 val = readl(gp->regs + RXDMA_CFG);
1243 writel(val & ~RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1244 val = readl(gp->regs + MAC_TXCFG);
1245 writel(val & ~MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1246 val = readl(gp->regs + MAC_RXCFG);
1247 writel(val & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1248
1249 (void) readl(gp->regs + MAC_RXCFG);
1250
1251 /* Need to wait a bit ... done by the caller */
1252 }
1253
1254
1255 // XXX dbl check what that function should do when called on PCS PHY
1256 static void gem_begin_auto_negotiation(struct gem *gp, struct ethtool_cmd *ep)
1257 {
1258 u32 advertise, features;
1259 int autoneg;
1260 int speed;
1261 int duplex;
1262
1263 if (gp->phy_type != phy_mii_mdio0 &&
1264 gp->phy_type != phy_mii_mdio1)
1265 goto non_mii;
1266
1267 /* Setup advertise */
1268 if (found_mii_phy(gp))
1269 features = gp->phy_mii.def->features;
1270 else
1271 features = 0;
1272
1273 advertise = features & ADVERTISE_MASK;
1274 if (gp->phy_mii.advertising != 0)
1275 advertise &= gp->phy_mii.advertising;
1276
1277 autoneg = gp->want_autoneg;
1278 speed = gp->phy_mii.speed;
1279 duplex = gp->phy_mii.duplex;
1280
1281 /* Setup link parameters */
1282 if (!ep)
1283 goto start_aneg;
1284 if (ep->autoneg == AUTONEG_ENABLE) {
1285 advertise = ep->advertising;
1286 autoneg = 1;
1287 } else {
1288 autoneg = 0;
1289 speed = ethtool_cmd_speed(ep);
1290 duplex = ep->duplex;
1291 }
1292
1293 start_aneg:
1294 /* Sanitize settings based on PHY capabilities */
1295 if ((features & SUPPORTED_Autoneg) == 0)
1296 autoneg = 0;
1297 if (speed == SPEED_1000 &&
1298 !(features & (SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)))
1299 speed = SPEED_100;
1300 if (speed == SPEED_100 &&
1301 !(features & (SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full)))
1302 speed = SPEED_10;
1303 if (duplex == DUPLEX_FULL &&
1304 !(features & (SUPPORTED_1000baseT_Full |
1305 SUPPORTED_100baseT_Full |
1306 SUPPORTED_10baseT_Full)))
1307 duplex = DUPLEX_HALF;
1308 if (speed == 0)
1309 speed = SPEED_10;
1310
1311 /* If we are asleep, we don't try to actually setup the PHY, we
1312 * just store the settings
1313 */
1314 if (!netif_device_present(gp->dev)) {
1315 gp->phy_mii.autoneg = gp->want_autoneg = autoneg;
1316 gp->phy_mii.speed = speed;
1317 gp->phy_mii.duplex = duplex;
1318 return;
1319 }
1320
1321 /* Configure PHY & start aneg */
1322 gp->want_autoneg = autoneg;
1323 if (autoneg) {
1324 if (found_mii_phy(gp))
1325 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, advertise);
1326 gp->lstate = link_aneg;
1327 } else {
1328 if (found_mii_phy(gp))
1329 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, speed, duplex);
1330 gp->lstate = link_force_ok;
1331 }
1332
1333 non_mii:
1334 gp->timer_ticks = 0;
1335 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1336 }
1337
1338 /* A link-up condition has occurred, initialize and enable the
1339 * rest of the chip.
1340 */
1341 static int gem_set_link_modes(struct gem *gp)
1342 {
1343 struct netdev_queue *txq = netdev_get_tx_queue(gp->dev, 0);
1344 int full_duplex, speed, pause;
1345 u32 val;
1346
1347 full_duplex = 0;
1348 speed = SPEED_10;
1349 pause = 0;
1350
1351 if (found_mii_phy(gp)) {
1352 if (gp->phy_mii.def->ops->read_link(&gp->phy_mii))
1353 return 1;
1354 full_duplex = (gp->phy_mii.duplex == DUPLEX_FULL);
1355 speed = gp->phy_mii.speed;
1356 pause = gp->phy_mii.pause;
1357 } else if (gp->phy_type == phy_serialink ||
1358 gp->phy_type == phy_serdes) {
1359 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1360
1361 if ((pcs_lpa & PCS_MIIADV_FD) || gp->phy_type == phy_serdes)
1362 full_duplex = 1;
1363 speed = SPEED_1000;
1364 }
1365
1366 netif_info(gp, link, gp->dev, "Link is up at %d Mbps, %s-duplex\n",
1367 speed, (full_duplex ? "full" : "half"));
1368
1369
1370 /* We take the tx queue lock to avoid collisions between
1371 * this code, the tx path and the NAPI-driven error path
1372 */
1373 __netif_tx_lock(txq, smp_processor_id());
1374
1375 val = (MAC_TXCFG_EIPG0 | MAC_TXCFG_NGU);
1376 if (full_duplex) {
1377 val |= (MAC_TXCFG_ICS | MAC_TXCFG_ICOLL);
1378 } else {
1379 /* MAC_TXCFG_NBO must be zero. */
1380 }
1381 writel(val, gp->regs + MAC_TXCFG);
1382
1383 val = (MAC_XIFCFG_OE | MAC_XIFCFG_LLED);
1384 if (!full_duplex &&
1385 (gp->phy_type == phy_mii_mdio0 ||
1386 gp->phy_type == phy_mii_mdio1)) {
1387 val |= MAC_XIFCFG_DISE;
1388 } else if (full_duplex) {
1389 val |= MAC_XIFCFG_FLED;
1390 }
1391
1392 if (speed == SPEED_1000)
1393 val |= (MAC_XIFCFG_GMII);
1394
1395 writel(val, gp->regs + MAC_XIFCFG);
1396
1397 /* If gigabit and half-duplex, enable carrier extension
1398 * mode. Else, disable it.
1399 */
1400 if (speed == SPEED_1000 && !full_duplex) {
1401 val = readl(gp->regs + MAC_TXCFG);
1402 writel(val | MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1403
1404 val = readl(gp->regs + MAC_RXCFG);
1405 writel(val | MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1406 } else {
1407 val = readl(gp->regs + MAC_TXCFG);
1408 writel(val & ~MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1409
1410 val = readl(gp->regs + MAC_RXCFG);
1411 writel(val & ~MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1412 }
1413
1414 if (gp->phy_type == phy_serialink ||
1415 gp->phy_type == phy_serdes) {
1416 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1417
1418 if (pcs_lpa & (PCS_MIIADV_SP | PCS_MIIADV_AP))
1419 pause = 1;
1420 }
1421
1422 if (!full_duplex)
1423 writel(512, gp->regs + MAC_STIME);
1424 else
1425 writel(64, gp->regs + MAC_STIME);
1426 val = readl(gp->regs + MAC_MCCFG);
1427 if (pause)
1428 val |= (MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1429 else
1430 val &= ~(MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1431 writel(val, gp->regs + MAC_MCCFG);
1432
1433 gem_start_dma(gp);
1434
1435 __netif_tx_unlock(txq);
1436
1437 if (netif_msg_link(gp)) {
1438 if (pause) {
1439 netdev_info(gp->dev,
1440 "Pause is enabled (rxfifo: %d off: %d on: %d)\n",
1441 gp->rx_fifo_sz,
1442 gp->rx_pause_off,
1443 gp->rx_pause_on);
1444 } else {
1445 netdev_info(gp->dev, "Pause is disabled\n");
1446 }
1447 }
1448
1449 return 0;
1450 }
1451
1452 static int gem_mdio_link_not_up(struct gem *gp)
1453 {
1454 switch (gp->lstate) {
1455 case link_force_ret:
1456 netif_info(gp, link, gp->dev,
1457 "Autoneg failed again, keeping forced mode\n");
1458 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii,
1459 gp->last_forced_speed, DUPLEX_HALF);
1460 gp->timer_ticks = 5;
1461 gp->lstate = link_force_ok;
1462 return 0;
1463 case link_aneg:
1464 /* We try forced modes after a failed aneg only on PHYs that don't
1465 * have "magic_aneg" bit set, which means they internally do the
1466 * while forced-mode thingy. On these, we just restart aneg
1467 */
1468 if (gp->phy_mii.def->magic_aneg)
1469 return 1;
1470 netif_info(gp, link, gp->dev, "switching to forced 100bt\n");
1471 /* Try forced modes. */
1472 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_100,
1473 DUPLEX_HALF);
1474 gp->timer_ticks = 5;
1475 gp->lstate = link_force_try;
1476 return 0;
1477 case link_force_try:
1478 /* Downgrade from 100 to 10 Mbps if necessary.
1479 * If already at 10Mbps, warn user about the
1480 * situation every 10 ticks.
1481 */
1482 if (gp->phy_mii.speed == SPEED_100) {
1483 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_10,
1484 DUPLEX_HALF);
1485 gp->timer_ticks = 5;
1486 netif_info(gp, link, gp->dev,
1487 "switching to forced 10bt\n");
1488 return 0;
1489 } else
1490 return 1;
1491 default:
1492 return 0;
1493 }
1494 }
1495
1496 static void gem_link_timer(unsigned long data)
1497 {
1498 struct gem *gp = (struct gem *) data;
1499 struct net_device *dev = gp->dev;
1500 int restart_aneg = 0;
1501
1502 /* There's no point doing anything if we're going to be reset */
1503 if (gp->reset_task_pending)
1504 return;
1505
1506 if (gp->phy_type == phy_serialink ||
1507 gp->phy_type == phy_serdes) {
1508 u32 val = readl(gp->regs + PCS_MIISTAT);
1509
1510 if (!(val & PCS_MIISTAT_LS))
1511 val = readl(gp->regs + PCS_MIISTAT);
1512
1513 if ((val & PCS_MIISTAT_LS) != 0) {
1514 if (gp->lstate == link_up)
1515 goto restart;
1516
1517 gp->lstate = link_up;
1518 netif_carrier_on(dev);
1519 (void)gem_set_link_modes(gp);
1520 }
1521 goto restart;
1522 }
1523 if (found_mii_phy(gp) && gp->phy_mii.def->ops->poll_link(&gp->phy_mii)) {
1524 /* Ok, here we got a link. If we had it due to a forced
1525 * fallback, and we were configured for autoneg, we do
1526 * retry a short autoneg pass. If you know your hub is
1527 * broken, use ethtool ;)
1528 */
1529 if (gp->lstate == link_force_try && gp->want_autoneg) {
1530 gp->lstate = link_force_ret;
1531 gp->last_forced_speed = gp->phy_mii.speed;
1532 gp->timer_ticks = 5;
1533 if (netif_msg_link(gp))
1534 netdev_info(dev,
1535 "Got link after fallback, retrying autoneg once...\n");
1536 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, gp->phy_mii.advertising);
1537 } else if (gp->lstate != link_up) {
1538 gp->lstate = link_up;
1539 netif_carrier_on(dev);
1540 if (gem_set_link_modes(gp))
1541 restart_aneg = 1;
1542 }
1543 } else {
1544 /* If the link was previously up, we restart the
1545 * whole process
1546 */
1547 if (gp->lstate == link_up) {
1548 gp->lstate = link_down;
1549 netif_info(gp, link, dev, "Link down\n");
1550 netif_carrier_off(dev);
1551 gem_schedule_reset(gp);
1552 /* The reset task will restart the timer */
1553 return;
1554 } else if (++gp->timer_ticks > 10) {
1555 if (found_mii_phy(gp))
1556 restart_aneg = gem_mdio_link_not_up(gp);
1557 else
1558 restart_aneg = 1;
1559 }
1560 }
1561 if (restart_aneg) {
1562 gem_begin_auto_negotiation(gp, NULL);
1563 return;
1564 }
1565 restart:
1566 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1567 }
1568
1569 static void gem_clean_rings(struct gem *gp)
1570 {
1571 struct gem_init_block *gb = gp->init_block;
1572 struct sk_buff *skb;
1573 int i;
1574 dma_addr_t dma_addr;
1575
1576 for (i = 0; i < RX_RING_SIZE; i++) {
1577 struct gem_rxd *rxd;
1578
1579 rxd = &gb->rxd[i];
1580 if (gp->rx_skbs[i] != NULL) {
1581 skb = gp->rx_skbs[i];
1582 dma_addr = le64_to_cpu(rxd->buffer);
1583 pci_unmap_page(gp->pdev, dma_addr,
1584 RX_BUF_ALLOC_SIZE(gp),
1585 PCI_DMA_FROMDEVICE);
1586 dev_kfree_skb_any(skb);
1587 gp->rx_skbs[i] = NULL;
1588 }
1589 rxd->status_word = 0;
1590 wmb();
1591 rxd->buffer = 0;
1592 }
1593
1594 for (i = 0; i < TX_RING_SIZE; i++) {
1595 if (gp->tx_skbs[i] != NULL) {
1596 struct gem_txd *txd;
1597 int frag;
1598
1599 skb = gp->tx_skbs[i];
1600 gp->tx_skbs[i] = NULL;
1601
1602 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1603 int ent = i & (TX_RING_SIZE - 1);
1604
1605 txd = &gb->txd[ent];
1606 dma_addr = le64_to_cpu(txd->buffer);
1607 pci_unmap_page(gp->pdev, dma_addr,
1608 le64_to_cpu(txd->control_word) &
1609 TXDCTRL_BUFSZ, PCI_DMA_TODEVICE);
1610
1611 if (frag != skb_shinfo(skb)->nr_frags)
1612 i++;
1613 }
1614 dev_kfree_skb_any(skb);
1615 }
1616 }
1617 }
1618
1619 static void gem_init_rings(struct gem *gp)
1620 {
1621 struct gem_init_block *gb = gp->init_block;
1622 struct net_device *dev = gp->dev;
1623 int i;
1624 dma_addr_t dma_addr;
1625
1626 gp->rx_new = gp->rx_old = gp->tx_new = gp->tx_old = 0;
1627
1628 gem_clean_rings(gp);
1629
1630 gp->rx_buf_sz = max(dev->mtu + ETH_HLEN + VLAN_HLEN,
1631 (unsigned)VLAN_ETH_FRAME_LEN);
1632
1633 for (i = 0; i < RX_RING_SIZE; i++) {
1634 struct sk_buff *skb;
1635 struct gem_rxd *rxd = &gb->rxd[i];
1636
1637 skb = gem_alloc_skb(dev, RX_BUF_ALLOC_SIZE(gp), GFP_KERNEL);
1638 if (!skb) {
1639 rxd->buffer = 0;
1640 rxd->status_word = 0;
1641 continue;
1642 }
1643
1644 gp->rx_skbs[i] = skb;
1645 skb_put(skb, (gp->rx_buf_sz + RX_OFFSET));
1646 dma_addr = pci_map_page(gp->pdev,
1647 virt_to_page(skb->data),
1648 offset_in_page(skb->data),
1649 RX_BUF_ALLOC_SIZE(gp),
1650 PCI_DMA_FROMDEVICE);
1651 rxd->buffer = cpu_to_le64(dma_addr);
1652 wmb();
1653 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
1654 skb_reserve(skb, RX_OFFSET);
1655 }
1656
1657 for (i = 0; i < TX_RING_SIZE; i++) {
1658 struct gem_txd *txd = &gb->txd[i];
1659
1660 txd->control_word = 0;
1661 wmb();
1662 txd->buffer = 0;
1663 }
1664 wmb();
1665 }
1666
1667 /* Init PHY interface and start link poll state machine */
1668 static void gem_init_phy(struct gem *gp)
1669 {
1670 u32 mifcfg;
1671
1672 /* Revert MIF CFG setting done on stop_phy */
1673 mifcfg = readl(gp->regs + MIF_CFG);
1674 mifcfg &= ~MIF_CFG_BBMODE;
1675 writel(mifcfg, gp->regs + MIF_CFG);
1676
1677 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
1678 int i;
1679
1680 /* Those delay sucks, the HW seem to love them though, I'll
1681 * serisouly consider breaking some locks here to be able
1682 * to schedule instead
1683 */
1684 for (i = 0; i < 3; i++) {
1685 #ifdef CONFIG_PPC_PMAC
1686 pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0);
1687 msleep(20);
1688 #endif
1689 /* Some PHYs used by apple have problem getting back to us,
1690 * we do an additional reset here
1691 */
1692 phy_write(gp, MII_BMCR, BMCR_RESET);
1693 msleep(20);
1694 if (phy_read(gp, MII_BMCR) != 0xffff)
1695 break;
1696 if (i == 2)
1697 netdev_warn(gp->dev, "GMAC PHY not responding !\n");
1698 }
1699 }
1700
1701 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
1702 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
1703 u32 val;
1704
1705 /* Init datapath mode register. */
1706 if (gp->phy_type == phy_mii_mdio0 ||
1707 gp->phy_type == phy_mii_mdio1) {
1708 val = PCS_DMODE_MGM;
1709 } else if (gp->phy_type == phy_serialink) {
1710 val = PCS_DMODE_SM | PCS_DMODE_GMOE;
1711 } else {
1712 val = PCS_DMODE_ESM;
1713 }
1714
1715 writel(val, gp->regs + PCS_DMODE);
1716 }
1717
1718 if (gp->phy_type == phy_mii_mdio0 ||
1719 gp->phy_type == phy_mii_mdio1) {
1720 /* Reset and detect MII PHY */
1721 sungem_phy_probe(&gp->phy_mii, gp->mii_phy_addr);
1722
1723 /* Init PHY */
1724 if (gp->phy_mii.def && gp->phy_mii.def->ops->init)
1725 gp->phy_mii.def->ops->init(&gp->phy_mii);
1726 } else {
1727 gem_pcs_reset(gp);
1728 gem_pcs_reinit_adv(gp);
1729 }
1730
1731 /* Default aneg parameters */
1732 gp->timer_ticks = 0;
1733 gp->lstate = link_down;
1734 netif_carrier_off(gp->dev);
1735
1736 /* Print things out */
1737 if (gp->phy_type == phy_mii_mdio0 ||
1738 gp->phy_type == phy_mii_mdio1)
1739 netdev_info(gp->dev, "Found %s PHY\n",
1740 gp->phy_mii.def ? gp->phy_mii.def->name : "no");
1741
1742 gem_begin_auto_negotiation(gp, NULL);
1743 }
1744
1745 static void gem_init_dma(struct gem *gp)
1746 {
1747 u64 desc_dma = (u64) gp->gblock_dvma;
1748 u32 val;
1749
1750 val = (TXDMA_CFG_BASE | (0x7ff << 10) | TXDMA_CFG_PMODE);
1751 writel(val, gp->regs + TXDMA_CFG);
1752
1753 writel(desc_dma >> 32, gp->regs + TXDMA_DBHI);
1754 writel(desc_dma & 0xffffffff, gp->regs + TXDMA_DBLOW);
1755 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
1756
1757 writel(0, gp->regs + TXDMA_KICK);
1758
1759 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
1760 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
1761 writel(val, gp->regs + RXDMA_CFG);
1762
1763 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
1764 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
1765
1766 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1767
1768 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
1769 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
1770 writel(val, gp->regs + RXDMA_PTHRESH);
1771
1772 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
1773 writel(((5 & RXDMA_BLANK_IPKTS) |
1774 ((8 << 12) & RXDMA_BLANK_ITIME)),
1775 gp->regs + RXDMA_BLANK);
1776 else
1777 writel(((5 & RXDMA_BLANK_IPKTS) |
1778 ((4 << 12) & RXDMA_BLANK_ITIME)),
1779 gp->regs + RXDMA_BLANK);
1780 }
1781
1782 static u32 gem_setup_multicast(struct gem *gp)
1783 {
1784 u32 rxcfg = 0;
1785 int i;
1786
1787 if ((gp->dev->flags & IFF_ALLMULTI) ||
1788 (netdev_mc_count(gp->dev) > 256)) {
1789 for (i=0; i<16; i++)
1790 writel(0xffff, gp->regs + MAC_HASH0 + (i << 2));
1791 rxcfg |= MAC_RXCFG_HFE;
1792 } else if (gp->dev->flags & IFF_PROMISC) {
1793 rxcfg |= MAC_RXCFG_PROM;
1794 } else {
1795 u16 hash_table[16];
1796 u32 crc;
1797 struct netdev_hw_addr *ha;
1798 int i;
1799
1800 memset(hash_table, 0, sizeof(hash_table));
1801 netdev_for_each_mc_addr(ha, gp->dev) {
1802 crc = ether_crc_le(6, ha->addr);
1803 crc >>= 24;
1804 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
1805 }
1806 for (i=0; i<16; i++)
1807 writel(hash_table[i], gp->regs + MAC_HASH0 + (i << 2));
1808 rxcfg |= MAC_RXCFG_HFE;
1809 }
1810
1811 return rxcfg;
1812 }
1813
1814 static void gem_init_mac(struct gem *gp)
1815 {
1816 unsigned char *e = &gp->dev->dev_addr[0];
1817
1818 writel(0x1bf0, gp->regs + MAC_SNDPAUSE);
1819
1820 writel(0x00, gp->regs + MAC_IPG0);
1821 writel(0x08, gp->regs + MAC_IPG1);
1822 writel(0x04, gp->regs + MAC_IPG2);
1823 writel(0x40, gp->regs + MAC_STIME);
1824 writel(0x40, gp->regs + MAC_MINFSZ);
1825
1826 /* Ethernet payload + header + FCS + optional VLAN tag. */
1827 writel(0x20000000 | (gp->rx_buf_sz + 4), gp->regs + MAC_MAXFSZ);
1828
1829 writel(0x07, gp->regs + MAC_PASIZE);
1830 writel(0x04, gp->regs + MAC_JAMSIZE);
1831 writel(0x10, gp->regs + MAC_ATTLIM);
1832 writel(0x8808, gp->regs + MAC_MCTYPE);
1833
1834 writel((e[5] | (e[4] << 8)) & 0x3ff, gp->regs + MAC_RANDSEED);
1835
1836 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
1837 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
1838 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
1839
1840 writel(0, gp->regs + MAC_ADDR3);
1841 writel(0, gp->regs + MAC_ADDR4);
1842 writel(0, gp->regs + MAC_ADDR5);
1843
1844 writel(0x0001, gp->regs + MAC_ADDR6);
1845 writel(0xc200, gp->regs + MAC_ADDR7);
1846 writel(0x0180, gp->regs + MAC_ADDR8);
1847
1848 writel(0, gp->regs + MAC_AFILT0);
1849 writel(0, gp->regs + MAC_AFILT1);
1850 writel(0, gp->regs + MAC_AFILT2);
1851 writel(0, gp->regs + MAC_AF21MSK);
1852 writel(0, gp->regs + MAC_AF0MSK);
1853
1854 gp->mac_rx_cfg = gem_setup_multicast(gp);
1855 #ifdef STRIP_FCS
1856 gp->mac_rx_cfg |= MAC_RXCFG_SFCS;
1857 #endif
1858 writel(0, gp->regs + MAC_NCOLL);
1859 writel(0, gp->regs + MAC_FASUCC);
1860 writel(0, gp->regs + MAC_ECOLL);
1861 writel(0, gp->regs + MAC_LCOLL);
1862 writel(0, gp->regs + MAC_DTIMER);
1863 writel(0, gp->regs + MAC_PATMPS);
1864 writel(0, gp->regs + MAC_RFCTR);
1865 writel(0, gp->regs + MAC_LERR);
1866 writel(0, gp->regs + MAC_AERR);
1867 writel(0, gp->regs + MAC_FCSERR);
1868 writel(0, gp->regs + MAC_RXCVERR);
1869
1870 /* Clear RX/TX/MAC/XIF config, we will set these up and enable
1871 * them once a link is established.
1872 */
1873 writel(0, gp->regs + MAC_TXCFG);
1874 writel(gp->mac_rx_cfg, gp->regs + MAC_RXCFG);
1875 writel(0, gp->regs + MAC_MCCFG);
1876 writel(0, gp->regs + MAC_XIFCFG);
1877
1878 /* Setup MAC interrupts. We want to get all of the interesting
1879 * counter expiration events, but we do not want to hear about
1880 * normal rx/tx as the DMA engine tells us that.
1881 */
1882 writel(MAC_TXSTAT_XMIT, gp->regs + MAC_TXMASK);
1883 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
1884
1885 /* Don't enable even the PAUSE interrupts for now, we
1886 * make no use of those events other than to record them.
1887 */
1888 writel(0xffffffff, gp->regs + MAC_MCMASK);
1889
1890 /* Don't enable GEM's WOL in normal operations
1891 */
1892 if (gp->has_wol)
1893 writel(0, gp->regs + WOL_WAKECSR);
1894 }
1895
1896 static void gem_init_pause_thresholds(struct gem *gp)
1897 {
1898 u32 cfg;
1899
1900 /* Calculate pause thresholds. Setting the OFF threshold to the
1901 * full RX fifo size effectively disables PAUSE generation which
1902 * is what we do for 10/100 only GEMs which have FIFOs too small
1903 * to make real gains from PAUSE.
1904 */
1905 if (gp->rx_fifo_sz <= (2 * 1024)) {
1906 gp->rx_pause_off = gp->rx_pause_on = gp->rx_fifo_sz;
1907 } else {
1908 int max_frame = (gp->rx_buf_sz + 4 + 64) & ~63;
1909 int off = (gp->rx_fifo_sz - (max_frame * 2));
1910 int on = off - max_frame;
1911
1912 gp->rx_pause_off = off;
1913 gp->rx_pause_on = on;
1914 }
1915
1916
1917 /* Configure the chip "burst" DMA mode & enable some
1918 * HW bug fixes on Apple version
1919 */
1920 cfg = 0;
1921 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE)
1922 cfg |= GREG_CFG_RONPAULBIT | GREG_CFG_ENBUG2FIX;
1923 #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
1924 cfg |= GREG_CFG_IBURST;
1925 #endif
1926 cfg |= ((31 << 1) & GREG_CFG_TXDMALIM);
1927 cfg |= ((31 << 6) & GREG_CFG_RXDMALIM);
1928 writel(cfg, gp->regs + GREG_CFG);
1929
1930 /* If Infinite Burst didn't stick, then use different
1931 * thresholds (and Apple bug fixes don't exist)
1932 */
1933 if (!(readl(gp->regs + GREG_CFG) & GREG_CFG_IBURST)) {
1934 cfg = ((2 << 1) & GREG_CFG_TXDMALIM);
1935 cfg |= ((8 << 6) & GREG_CFG_RXDMALIM);
1936 writel(cfg, gp->regs + GREG_CFG);
1937 }
1938 }
1939
1940 static int gem_check_invariants(struct gem *gp)
1941 {
1942 struct pci_dev *pdev = gp->pdev;
1943 u32 mif_cfg;
1944
1945 /* On Apple's sungem, we can't rely on registers as the chip
1946 * was been powered down by the firmware. The PHY is looked
1947 * up later on.
1948 */
1949 if (pdev->vendor == PCI_VENDOR_ID_APPLE) {
1950 gp->phy_type = phy_mii_mdio0;
1951 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
1952 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
1953 gp->swrst_base = 0;
1954
1955 mif_cfg = readl(gp->regs + MIF_CFG);
1956 mif_cfg &= ~(MIF_CFG_PSELECT|MIF_CFG_POLL|MIF_CFG_BBMODE|MIF_CFG_MDI1);
1957 mif_cfg |= MIF_CFG_MDI0;
1958 writel(mif_cfg, gp->regs + MIF_CFG);
1959 writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE);
1960 writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG);
1961
1962 /* We hard-code the PHY address so we can properly bring it out of
1963 * reset later on, we can't really probe it at this point, though
1964 * that isn't an issue.
1965 */
1966 if (gp->pdev->device == PCI_DEVICE_ID_APPLE_K2_GMAC)
1967 gp->mii_phy_addr = 1;
1968 else
1969 gp->mii_phy_addr = 0;
1970
1971 return 0;
1972 }
1973
1974 mif_cfg = readl(gp->regs + MIF_CFG);
1975
1976 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
1977 pdev->device == PCI_DEVICE_ID_SUN_RIO_GEM) {
1978 /* One of the MII PHYs _must_ be present
1979 * as this chip has no gigabit PHY.
1980 */
1981 if ((mif_cfg & (MIF_CFG_MDI0 | MIF_CFG_MDI1)) == 0) {
1982 pr_err("RIO GEM lacks MII phy, mif_cfg[%08x]\n",
1983 mif_cfg);
1984 return -1;
1985 }
1986 }
1987
1988 /* Determine initial PHY interface type guess. MDIO1 is the
1989 * external PHY and thus takes precedence over MDIO0.
1990 */
1991
1992 if (mif_cfg & MIF_CFG_MDI1) {
1993 gp->phy_type = phy_mii_mdio1;
1994 mif_cfg |= MIF_CFG_PSELECT;
1995 writel(mif_cfg, gp->regs + MIF_CFG);
1996 } else if (mif_cfg & MIF_CFG_MDI0) {
1997 gp->phy_type = phy_mii_mdio0;
1998 mif_cfg &= ~MIF_CFG_PSELECT;
1999 writel(mif_cfg, gp->regs + MIF_CFG);
2000 } else {
2001 #ifdef CONFIG_SPARC
2002 const char *p;
2003
2004 p = of_get_property(gp->of_node, "shared-pins", NULL);
2005 if (p && !strcmp(p, "serdes"))
2006 gp->phy_type = phy_serdes;
2007 else
2008 #endif
2009 gp->phy_type = phy_serialink;
2010 }
2011 if (gp->phy_type == phy_mii_mdio1 ||
2012 gp->phy_type == phy_mii_mdio0) {
2013 int i;
2014
2015 for (i = 0; i < 32; i++) {
2016 gp->mii_phy_addr = i;
2017 if (phy_read(gp, MII_BMCR) != 0xffff)
2018 break;
2019 }
2020 if (i == 32) {
2021 if (pdev->device != PCI_DEVICE_ID_SUN_GEM) {
2022 pr_err("RIO MII phy will not respond\n");
2023 return -1;
2024 }
2025 gp->phy_type = phy_serdes;
2026 }
2027 }
2028
2029 /* Fetch the FIFO configurations now too. */
2030 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
2031 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
2032
2033 if (pdev->vendor == PCI_VENDOR_ID_SUN) {
2034 if (pdev->device == PCI_DEVICE_ID_SUN_GEM) {
2035 if (gp->tx_fifo_sz != (9 * 1024) ||
2036 gp->rx_fifo_sz != (20 * 1024)) {
2037 pr_err("GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2038 gp->tx_fifo_sz, gp->rx_fifo_sz);
2039 return -1;
2040 }
2041 gp->swrst_base = 0;
2042 } else {
2043 if (gp->tx_fifo_sz != (2 * 1024) ||
2044 gp->rx_fifo_sz != (2 * 1024)) {
2045 pr_err("RIO GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2046 gp->tx_fifo_sz, gp->rx_fifo_sz);
2047 return -1;
2048 }
2049 gp->swrst_base = (64 / 4) << GREG_SWRST_CACHE_SHIFT;
2050 }
2051 }
2052
2053 return 0;
2054 }
2055
2056 static void gem_reinit_chip(struct gem *gp)
2057 {
2058 /* Reset the chip */
2059 gem_reset(gp);
2060
2061 /* Make sure ints are disabled */
2062 gem_disable_ints(gp);
2063
2064 /* Allocate & setup ring buffers */
2065 gem_init_rings(gp);
2066
2067 /* Configure pause thresholds */
2068 gem_init_pause_thresholds(gp);
2069
2070 /* Init DMA & MAC engines */
2071 gem_init_dma(gp);
2072 gem_init_mac(gp);
2073 }
2074
2075
2076 static void gem_stop_phy(struct gem *gp, int wol)
2077 {
2078 u32 mifcfg;
2079
2080 /* Let the chip settle down a bit, it seems that helps
2081 * for sleep mode on some models
2082 */
2083 msleep(10);
2084
2085 /* Make sure we aren't polling PHY status change. We
2086 * don't currently use that feature though
2087 */
2088 mifcfg = readl(gp->regs + MIF_CFG);
2089 mifcfg &= ~MIF_CFG_POLL;
2090 writel(mifcfg, gp->regs + MIF_CFG);
2091
2092 if (wol && gp->has_wol) {
2093 unsigned char *e = &gp->dev->dev_addr[0];
2094 u32 csr;
2095
2096 /* Setup wake-on-lan for MAGIC packet */
2097 writel(MAC_RXCFG_HFE | MAC_RXCFG_SFCS | MAC_RXCFG_ENAB,
2098 gp->regs + MAC_RXCFG);
2099 writel((e[4] << 8) | e[5], gp->regs + WOL_MATCH0);
2100 writel((e[2] << 8) | e[3], gp->regs + WOL_MATCH1);
2101 writel((e[0] << 8) | e[1], gp->regs + WOL_MATCH2);
2102
2103 writel(WOL_MCOUNT_N | WOL_MCOUNT_M, gp->regs + WOL_MCOUNT);
2104 csr = WOL_WAKECSR_ENABLE;
2105 if ((readl(gp->regs + MAC_XIFCFG) & MAC_XIFCFG_GMII) == 0)
2106 csr |= WOL_WAKECSR_MII;
2107 writel(csr, gp->regs + WOL_WAKECSR);
2108 } else {
2109 writel(0, gp->regs + MAC_RXCFG);
2110 (void)readl(gp->regs + MAC_RXCFG);
2111 /* Machine sleep will die in strange ways if we
2112 * dont wait a bit here, looks like the chip takes
2113 * some time to really shut down
2114 */
2115 msleep(10);
2116 }
2117
2118 writel(0, gp->regs + MAC_TXCFG);
2119 writel(0, gp->regs + MAC_XIFCFG);
2120 writel(0, gp->regs + TXDMA_CFG);
2121 writel(0, gp->regs + RXDMA_CFG);
2122
2123 if (!wol) {
2124 gem_reset(gp);
2125 writel(MAC_TXRST_CMD, gp->regs + MAC_TXRST);
2126 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
2127
2128 if (found_mii_phy(gp) && gp->phy_mii.def->ops->suspend)
2129 gp->phy_mii.def->ops->suspend(&gp->phy_mii);
2130
2131 /* According to Apple, we must set the MDIO pins to this begnign
2132 * state or we may 1) eat more current, 2) damage some PHYs
2133 */
2134 writel(mifcfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG);
2135 writel(0, gp->regs + MIF_BBCLK);
2136 writel(0, gp->regs + MIF_BBDATA);
2137 writel(0, gp->regs + MIF_BBOENAB);
2138 writel(MAC_XIFCFG_GMII | MAC_XIFCFG_LBCK, gp->regs + MAC_XIFCFG);
2139 (void) readl(gp->regs + MAC_XIFCFG);
2140 }
2141 }
2142
2143 static int gem_do_start(struct net_device *dev)
2144 {
2145 struct gem *gp = netdev_priv(dev);
2146 int rc;
2147
2148 /* Enable the cell */
2149 gem_get_cell(gp);
2150
2151 /* Make sure PCI access and bus master are enabled */
2152 rc = pci_enable_device(gp->pdev);
2153 if (rc) {
2154 netdev_err(dev, "Failed to enable chip on PCI bus !\n");
2155
2156 /* Put cell and forget it for now, it will be considered as
2157 * still asleep, a new sleep cycle may bring it back
2158 */
2159 gem_put_cell(gp);
2160 return -ENXIO;
2161 }
2162 pci_set_master(gp->pdev);
2163
2164 /* Init & setup chip hardware */
2165 gem_reinit_chip(gp);
2166
2167 /* An interrupt might come in handy */
2168 rc = request_irq(gp->pdev->irq, gem_interrupt,
2169 IRQF_SHARED, dev->name, (void *)dev);
2170 if (rc) {
2171 netdev_err(dev, "failed to request irq !\n");
2172
2173 gem_reset(gp);
2174 gem_clean_rings(gp);
2175 gem_put_cell(gp);
2176 return rc;
2177 }
2178
2179 /* Mark us as attached again if we come from resume(), this has
2180 * no effect if we weren't detatched and needs to be done now.
2181 */
2182 netif_device_attach(dev);
2183
2184 /* Restart NAPI & queues */
2185 gem_netif_start(gp);
2186
2187 /* Detect & init PHY, start autoneg etc... this will
2188 * eventually result in starting DMA operations when
2189 * the link is up
2190 */
2191 gem_init_phy(gp);
2192
2193 return 0;
2194 }
2195
2196 static void gem_do_stop(struct net_device *dev, int wol)
2197 {
2198 struct gem *gp = netdev_priv(dev);
2199
2200 /* Stop NAPI and stop tx queue */
2201 gem_netif_stop(gp);
2202
2203 /* Make sure ints are disabled. We don't care about
2204 * synchronizing as NAPI is disabled, thus a stray
2205 * interrupt will do nothing bad (our irq handler
2206 * just schedules NAPI)
2207 */
2208 gem_disable_ints(gp);
2209
2210 /* Stop the link timer */
2211 del_timer_sync(&gp->link_timer);
2212
2213 /* We cannot cancel the reset task while holding the
2214 * rtnl lock, we'd get an A->B / B->A deadlock stituation
2215 * if we did. This is not an issue however as the reset
2216 * task is synchronized vs. us (rtnl_lock) and will do
2217 * nothing if the device is down or suspended. We do
2218 * still clear reset_task_pending to avoid a spurrious
2219 * reset later on in case we do resume before it gets
2220 * scheduled.
2221 */
2222 gp->reset_task_pending = 0;
2223
2224 /* If we are going to sleep with WOL */
2225 gem_stop_dma(gp);
2226 msleep(10);
2227 if (!wol)
2228 gem_reset(gp);
2229 msleep(10);
2230
2231 /* Get rid of rings */
2232 gem_clean_rings(gp);
2233
2234 /* No irq needed anymore */
2235 free_irq(gp->pdev->irq, (void *) dev);
2236
2237 /* Shut the PHY down eventually and setup WOL */
2238 gem_stop_phy(gp, wol);
2239
2240 /* Make sure bus master is disabled */
2241 pci_disable_device(gp->pdev);
2242
2243 /* Cell not needed neither if no WOL */
2244 if (!wol)
2245 gem_put_cell(gp);
2246 }
2247
2248 static void gem_reset_task(struct work_struct *work)
2249 {
2250 struct gem *gp = container_of(work, struct gem, reset_task);
2251
2252 /* Lock out the network stack (essentially shield ourselves
2253 * against a racing open, close, control call, or suspend
2254 */
2255 rtnl_lock();
2256
2257 /* Skip the reset task if suspended or closed, or if it's
2258 * been cancelled by gem_do_stop (see comment there)
2259 */
2260 if (!netif_device_present(gp->dev) ||
2261 !netif_running(gp->dev) ||
2262 !gp->reset_task_pending) {
2263 rtnl_unlock();
2264 return;
2265 }
2266
2267 /* Stop the link timer */
2268 del_timer_sync(&gp->link_timer);
2269
2270 /* Stop NAPI and tx */
2271 gem_netif_stop(gp);
2272
2273 /* Reset the chip & rings */
2274 gem_reinit_chip(gp);
2275 if (gp->lstate == link_up)
2276 gem_set_link_modes(gp);
2277
2278 /* Restart NAPI and Tx */
2279 gem_netif_start(gp);
2280
2281 /* We are back ! */
2282 gp->reset_task_pending = 0;
2283
2284 /* If the link is not up, restart autoneg, else restart the
2285 * polling timer
2286 */
2287 if (gp->lstate != link_up)
2288 gem_begin_auto_negotiation(gp, NULL);
2289 else
2290 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
2291
2292 rtnl_unlock();
2293 }
2294
2295 static int gem_open(struct net_device *dev)
2296 {
2297 /* We allow open while suspended, we just do nothing,
2298 * the chip will be initialized in resume()
2299 */
2300 if (netif_device_present(dev))
2301 return gem_do_start(dev);
2302 return 0;
2303 }
2304
2305 static int gem_close(struct net_device *dev)
2306 {
2307 if (netif_device_present(dev))
2308 gem_do_stop(dev, 0);
2309
2310 return 0;
2311 }
2312
2313 #ifdef CONFIG_PM
2314 static int gem_suspend(struct pci_dev *pdev, pm_message_t state)
2315 {
2316 struct net_device *dev = pci_get_drvdata(pdev);
2317 struct gem *gp = netdev_priv(dev);
2318
2319 /* Lock the network stack first to avoid racing with open/close,
2320 * reset task and setting calls
2321 */
2322 rtnl_lock();
2323
2324 /* Not running, mark ourselves non-present, no need for
2325 * a lock here
2326 */
2327 if (!netif_running(dev)) {
2328 netif_device_detach(dev);
2329 rtnl_unlock();
2330 return 0;
2331 }
2332 netdev_info(dev, "suspending, WakeOnLan %s\n",
2333 (gp->wake_on_lan && netif_running(dev)) ?
2334 "enabled" : "disabled");
2335
2336 /* Tell the network stack we're gone. gem_do_stop() below will
2337 * synchronize with TX, stop NAPI etc...
2338 */
2339 netif_device_detach(dev);
2340
2341 /* Switch off chip, remember WOL setting */
2342 gp->asleep_wol = !!gp->wake_on_lan;
2343 gem_do_stop(dev, gp->asleep_wol);
2344
2345 /* Unlock the network stack */
2346 rtnl_unlock();
2347
2348 return 0;
2349 }
2350
2351 static int gem_resume(struct pci_dev *pdev)
2352 {
2353 struct net_device *dev = pci_get_drvdata(pdev);
2354 struct gem *gp = netdev_priv(dev);
2355
2356 /* See locking comment in gem_suspend */
2357 rtnl_lock();
2358
2359 /* Not running, mark ourselves present, no need for
2360 * a lock here
2361 */
2362 if (!netif_running(dev)) {
2363 netif_device_attach(dev);
2364 rtnl_unlock();
2365 return 0;
2366 }
2367
2368 /* Restart chip. If that fails there isn't much we can do, we
2369 * leave things stopped.
2370 */
2371 gem_do_start(dev);
2372
2373 /* If we had WOL enabled, the cell clock was never turned off during
2374 * sleep, so we end up beeing unbalanced. Fix that here
2375 */
2376 if (gp->asleep_wol)
2377 gem_put_cell(gp);
2378
2379 /* Unlock the network stack */
2380 rtnl_unlock();
2381
2382 return 0;
2383 }
2384 #endif /* CONFIG_PM */
2385
2386 static struct net_device_stats *gem_get_stats(struct net_device *dev)
2387 {
2388 struct gem *gp = netdev_priv(dev);
2389
2390 /* I have seen this being called while the PM was in progress,
2391 * so we shield against this. Let's also not poke at registers
2392 * while the reset task is going on.
2393 *
2394 * TODO: Move stats collection elsewhere (link timer ?) and
2395 * make this a nop to avoid all those synchro issues
2396 */
2397 if (!netif_device_present(dev) || !netif_running(dev))
2398 goto bail;
2399
2400 /* Better safe than sorry... */
2401 if (WARN_ON(!gp->cell_enabled))
2402 goto bail;
2403
2404 dev->stats.rx_crc_errors += readl(gp->regs + MAC_FCSERR);
2405 writel(0, gp->regs + MAC_FCSERR);
2406
2407 dev->stats.rx_frame_errors += readl(gp->regs + MAC_AERR);
2408 writel(0, gp->regs + MAC_AERR);
2409
2410 dev->stats.rx_length_errors += readl(gp->regs + MAC_LERR);
2411 writel(0, gp->regs + MAC_LERR);
2412
2413 dev->stats.tx_aborted_errors += readl(gp->regs + MAC_ECOLL);
2414 dev->stats.collisions +=
2415 (readl(gp->regs + MAC_ECOLL) + readl(gp->regs + MAC_LCOLL));
2416 writel(0, gp->regs + MAC_ECOLL);
2417 writel(0, gp->regs + MAC_LCOLL);
2418 bail:
2419 return &dev->stats;
2420 }
2421
2422 static int gem_set_mac_address(struct net_device *dev, void *addr)
2423 {
2424 struct sockaddr *macaddr = (struct sockaddr *) addr;
2425 struct gem *gp = netdev_priv(dev);
2426 unsigned char *e = &dev->dev_addr[0];
2427
2428 if (!is_valid_ether_addr(macaddr->sa_data))
2429 return -EADDRNOTAVAIL;
2430
2431 memcpy(dev->dev_addr, macaddr->sa_data, dev->addr_len);
2432
2433 /* We'll just catch it later when the device is up'd or resumed */
2434 if (!netif_running(dev) || !netif_device_present(dev))
2435 return 0;
2436
2437 /* Better safe than sorry... */
2438 if (WARN_ON(!gp->cell_enabled))
2439 return 0;
2440
2441 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
2442 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
2443 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
2444
2445 return 0;
2446 }
2447
2448 static void gem_set_multicast(struct net_device *dev)
2449 {
2450 struct gem *gp = netdev_priv(dev);
2451 u32 rxcfg, rxcfg_new;
2452 int limit = 10000;
2453
2454 if (!netif_running(dev) || !netif_device_present(dev))
2455 return;
2456
2457 /* Better safe than sorry... */
2458 if (gp->reset_task_pending || WARN_ON(!gp->cell_enabled))
2459 return;
2460
2461 rxcfg = readl(gp->regs + MAC_RXCFG);
2462 rxcfg_new = gem_setup_multicast(gp);
2463 #ifdef STRIP_FCS
2464 rxcfg_new |= MAC_RXCFG_SFCS;
2465 #endif
2466 gp->mac_rx_cfg = rxcfg_new;
2467
2468 writel(rxcfg & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
2469 while (readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB) {
2470 if (!limit--)
2471 break;
2472 udelay(10);
2473 }
2474
2475 rxcfg &= ~(MAC_RXCFG_PROM | MAC_RXCFG_HFE);
2476 rxcfg |= rxcfg_new;
2477
2478 writel(rxcfg, gp->regs + MAC_RXCFG);
2479 }
2480
2481 /* Jumbo-grams don't seem to work :-( */
2482 #define GEM_MIN_MTU 68
2483 #if 1
2484 #define GEM_MAX_MTU 1500
2485 #else
2486 #define GEM_MAX_MTU 9000
2487 #endif
2488
2489 static int gem_change_mtu(struct net_device *dev, int new_mtu)
2490 {
2491 struct gem *gp = netdev_priv(dev);
2492
2493 if (new_mtu < GEM_MIN_MTU || new_mtu > GEM_MAX_MTU)
2494 return -EINVAL;
2495
2496 dev->mtu = new_mtu;
2497
2498 /* We'll just catch it later when the device is up'd or resumed */
2499 if (!netif_running(dev) || !netif_device_present(dev))
2500 return 0;
2501
2502 /* Better safe than sorry... */
2503 if (WARN_ON(!gp->cell_enabled))
2504 return 0;
2505
2506 gem_netif_stop(gp);
2507 gem_reinit_chip(gp);
2508 if (gp->lstate == link_up)
2509 gem_set_link_modes(gp);
2510 gem_netif_start(gp);
2511
2512 return 0;
2513 }
2514
2515 static void gem_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2516 {
2517 struct gem *gp = netdev_priv(dev);
2518
2519 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2520 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
2521 strlcpy(info->bus_info, pci_name(gp->pdev), sizeof(info->bus_info));
2522 }
2523
2524 static int gem_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2525 {
2526 struct gem *gp = netdev_priv(dev);
2527
2528 if (gp->phy_type == phy_mii_mdio0 ||
2529 gp->phy_type == phy_mii_mdio1) {
2530 if (gp->phy_mii.def)
2531 cmd->supported = gp->phy_mii.def->features;
2532 else
2533 cmd->supported = (SUPPORTED_10baseT_Half |
2534 SUPPORTED_10baseT_Full);
2535
2536 /* XXX hardcoded stuff for now */
2537 cmd->port = PORT_MII;
2538 cmd->transceiver = XCVR_EXTERNAL;
2539 cmd->phy_address = 0; /* XXX fixed PHYAD */
2540
2541 /* Return current PHY settings */
2542 cmd->autoneg = gp->want_autoneg;
2543 ethtool_cmd_speed_set(cmd, gp->phy_mii.speed);
2544 cmd->duplex = gp->phy_mii.duplex;
2545 cmd->advertising = gp->phy_mii.advertising;
2546
2547 /* If we started with a forced mode, we don't have a default
2548 * advertise set, we need to return something sensible so
2549 * userland can re-enable autoneg properly.
2550 */
2551 if (cmd->advertising == 0)
2552 cmd->advertising = cmd->supported;
2553 } else { // XXX PCS ?
2554 cmd->supported =
2555 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2556 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2557 SUPPORTED_Autoneg);
2558 cmd->advertising = cmd->supported;
2559 ethtool_cmd_speed_set(cmd, 0);
2560 cmd->duplex = cmd->port = cmd->phy_address =
2561 cmd->transceiver = cmd->autoneg = 0;
2562
2563 /* serdes means usually a Fibre connector, with most fixed */
2564 if (gp->phy_type == phy_serdes) {
2565 cmd->port = PORT_FIBRE;
2566 cmd->supported = (SUPPORTED_1000baseT_Half |
2567 SUPPORTED_1000baseT_Full |
2568 SUPPORTED_FIBRE | SUPPORTED_Autoneg |
2569 SUPPORTED_Pause | SUPPORTED_Asym_Pause);
2570 cmd->advertising = cmd->supported;
2571 cmd->transceiver = XCVR_INTERNAL;
2572 if (gp->lstate == link_up)
2573 ethtool_cmd_speed_set(cmd, SPEED_1000);
2574 cmd->duplex = DUPLEX_FULL;
2575 cmd->autoneg = 1;
2576 }
2577 }
2578 cmd->maxtxpkt = cmd->maxrxpkt = 0;
2579
2580 return 0;
2581 }
2582
2583 static int gem_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2584 {
2585 struct gem *gp = netdev_priv(dev);
2586 u32 speed = ethtool_cmd_speed(cmd);
2587
2588 /* Verify the settings we care about. */
2589 if (cmd->autoneg != AUTONEG_ENABLE &&
2590 cmd->autoneg != AUTONEG_DISABLE)
2591 return -EINVAL;
2592
2593 if (cmd->autoneg == AUTONEG_ENABLE &&
2594 cmd->advertising == 0)
2595 return -EINVAL;
2596
2597 if (cmd->autoneg == AUTONEG_DISABLE &&
2598 ((speed != SPEED_1000 &&
2599 speed != SPEED_100 &&
2600 speed != SPEED_10) ||
2601 (cmd->duplex != DUPLEX_HALF &&
2602 cmd->duplex != DUPLEX_FULL)))
2603 return -EINVAL;
2604
2605 /* Apply settings and restart link process. */
2606 if (netif_device_present(gp->dev)) {
2607 del_timer_sync(&gp->link_timer);
2608 gem_begin_auto_negotiation(gp, cmd);
2609 }
2610
2611 return 0;
2612 }
2613
2614 static int gem_nway_reset(struct net_device *dev)
2615 {
2616 struct gem *gp = netdev_priv(dev);
2617
2618 if (!gp->want_autoneg)
2619 return -EINVAL;
2620
2621 /* Restart link process */
2622 if (netif_device_present(gp->dev)) {
2623 del_timer_sync(&gp->link_timer);
2624 gem_begin_auto_negotiation(gp, NULL);
2625 }
2626
2627 return 0;
2628 }
2629
2630 static u32 gem_get_msglevel(struct net_device *dev)
2631 {
2632 struct gem *gp = netdev_priv(dev);
2633 return gp->msg_enable;
2634 }
2635
2636 static void gem_set_msglevel(struct net_device *dev, u32 value)
2637 {
2638 struct gem *gp = netdev_priv(dev);
2639 gp->msg_enable = value;
2640 }
2641
2642
2643 /* Add more when I understand how to program the chip */
2644 /* like WAKE_UCAST | WAKE_MCAST | WAKE_BCAST */
2645
2646 #define WOL_SUPPORTED_MASK (WAKE_MAGIC)
2647
2648 static void gem_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2649 {
2650 struct gem *gp = netdev_priv(dev);
2651
2652 /* Add more when I understand how to program the chip */
2653 if (gp->has_wol) {
2654 wol->supported = WOL_SUPPORTED_MASK;
2655 wol->wolopts = gp->wake_on_lan;
2656 } else {
2657 wol->supported = 0;
2658 wol->wolopts = 0;
2659 }
2660 }
2661
2662 static int gem_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2663 {
2664 struct gem *gp = netdev_priv(dev);
2665
2666 if (!gp->has_wol)
2667 return -EOPNOTSUPP;
2668 gp->wake_on_lan = wol->wolopts & WOL_SUPPORTED_MASK;
2669 return 0;
2670 }
2671
2672 static const struct ethtool_ops gem_ethtool_ops = {
2673 .get_drvinfo = gem_get_drvinfo,
2674 .get_link = ethtool_op_get_link,
2675 .get_settings = gem_get_settings,
2676 .set_settings = gem_set_settings,
2677 .nway_reset = gem_nway_reset,
2678 .get_msglevel = gem_get_msglevel,
2679 .set_msglevel = gem_set_msglevel,
2680 .get_wol = gem_get_wol,
2681 .set_wol = gem_set_wol,
2682 };
2683
2684 static int gem_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2685 {
2686 struct gem *gp = netdev_priv(dev);
2687 struct mii_ioctl_data *data = if_mii(ifr);
2688 int rc = -EOPNOTSUPP;
2689
2690 /* For SIOCGMIIREG and SIOCSMIIREG the core checks for us that
2691 * netif_device_present() is true and holds rtnl_lock for us
2692 * so we have nothing to worry about
2693 */
2694
2695 switch (cmd) {
2696 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
2697 data->phy_id = gp->mii_phy_addr;
2698 /* Fallthrough... */
2699
2700 case SIOCGMIIREG: /* Read MII PHY register. */
2701 data->val_out = __phy_read(gp, data->phy_id & 0x1f,
2702 data->reg_num & 0x1f);
2703 rc = 0;
2704 break;
2705
2706 case SIOCSMIIREG: /* Write MII PHY register. */
2707 __phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f,
2708 data->val_in);
2709 rc = 0;
2710 break;
2711 }
2712 return rc;
2713 }
2714
2715 #if (!defined(CONFIG_SPARC) && !defined(CONFIG_PPC_PMAC))
2716 /* Fetch MAC address from vital product data of PCI ROM. */
2717 static int find_eth_addr_in_vpd(void __iomem *rom_base, int len, unsigned char *dev_addr)
2718 {
2719 int this_offset;
2720
2721 for (this_offset = 0x20; this_offset < len; this_offset++) {
2722 void __iomem *p = rom_base + this_offset;
2723 int i;
2724
2725 if (readb(p + 0) != 0x90 ||
2726 readb(p + 1) != 0x00 ||
2727 readb(p + 2) != 0x09 ||
2728 readb(p + 3) != 0x4e ||
2729 readb(p + 4) != 0x41 ||
2730 readb(p + 5) != 0x06)
2731 continue;
2732
2733 this_offset += 6;
2734 p += 6;
2735
2736 for (i = 0; i < 6; i++)
2737 dev_addr[i] = readb(p + i);
2738 return 1;
2739 }
2740 return 0;
2741 }
2742
2743 static void get_gem_mac_nonobp(struct pci_dev *pdev, unsigned char *dev_addr)
2744 {
2745 size_t size;
2746 void __iomem *p = pci_map_rom(pdev, &size);
2747
2748 if (p) {
2749 int found;
2750
2751 found = readb(p) == 0x55 &&
2752 readb(p + 1) == 0xaa &&
2753 find_eth_addr_in_vpd(p, (64 * 1024), dev_addr);
2754 pci_unmap_rom(pdev, p);
2755 if (found)
2756 return;
2757 }
2758
2759 /* Sun MAC prefix then 3 random bytes. */
2760 dev_addr[0] = 0x08;
2761 dev_addr[1] = 0x00;
2762 dev_addr[2] = 0x20;
2763 get_random_bytes(dev_addr + 3, 3);
2764 }
2765 #endif /* not Sparc and not PPC */
2766
2767 static int __devinit gem_get_device_address(struct gem *gp)
2768 {
2769 #if defined(CONFIG_SPARC) || defined(CONFIG_PPC_PMAC)
2770 struct net_device *dev = gp->dev;
2771 const unsigned char *addr;
2772
2773 addr = of_get_property(gp->of_node, "local-mac-address", NULL);
2774 if (addr == NULL) {
2775 #ifdef CONFIG_SPARC
2776 addr = idprom->id_ethaddr;
2777 #else
2778 printk("\n");
2779 pr_err("%s: can't get mac-address\n", dev->name);
2780 return -1;
2781 #endif
2782 }
2783 memcpy(dev->dev_addr, addr, 6);
2784 #else
2785 get_gem_mac_nonobp(gp->pdev, gp->dev->dev_addr);
2786 #endif
2787 return 0;
2788 }
2789
2790 static void gem_remove_one(struct pci_dev *pdev)
2791 {
2792 struct net_device *dev = pci_get_drvdata(pdev);
2793
2794 if (dev) {
2795 struct gem *gp = netdev_priv(dev);
2796
2797 unregister_netdev(dev);
2798
2799 /* Ensure reset task is truely gone */
2800 cancel_work_sync(&gp->reset_task);
2801
2802 /* Free resources */
2803 pci_free_consistent(pdev,
2804 sizeof(struct gem_init_block),
2805 gp->init_block,
2806 gp->gblock_dvma);
2807 iounmap(gp->regs);
2808 pci_release_regions(pdev);
2809 free_netdev(dev);
2810
2811 pci_set_drvdata(pdev, NULL);
2812 }
2813 }
2814
2815 static const struct net_device_ops gem_netdev_ops = {
2816 .ndo_open = gem_open,
2817 .ndo_stop = gem_close,
2818 .ndo_start_xmit = gem_start_xmit,
2819 .ndo_get_stats = gem_get_stats,
2820 .ndo_set_rx_mode = gem_set_multicast,
2821 .ndo_do_ioctl = gem_ioctl,
2822 .ndo_tx_timeout = gem_tx_timeout,
2823 .ndo_change_mtu = gem_change_mtu,
2824 .ndo_validate_addr = eth_validate_addr,
2825 .ndo_set_mac_address = gem_set_mac_address,
2826 #ifdef CONFIG_NET_POLL_CONTROLLER
2827 .ndo_poll_controller = gem_poll_controller,
2828 #endif
2829 };
2830
2831 static int __devinit gem_init_one(struct pci_dev *pdev,
2832 const struct pci_device_id *ent)
2833 {
2834 unsigned long gemreg_base, gemreg_len;
2835 struct net_device *dev;
2836 struct gem *gp;
2837 int err, pci_using_dac;
2838
2839 printk_once(KERN_INFO "%s", version);
2840
2841 /* Apple gmac note: during probe, the chip is powered up by
2842 * the arch code to allow the code below to work (and to let
2843 * the chip be probed on the config space. It won't stay powered
2844 * up until the interface is brought up however, so we can't rely
2845 * on register configuration done at this point.
2846 */
2847 err = pci_enable_device(pdev);
2848 if (err) {
2849 pr_err("Cannot enable MMIO operation, aborting\n");
2850 return err;
2851 }
2852 pci_set_master(pdev);
2853
2854 /* Configure DMA attributes. */
2855
2856 /* All of the GEM documentation states that 64-bit DMA addressing
2857 * is fully supported and should work just fine. However the
2858 * front end for RIO based GEMs is different and only supports
2859 * 32-bit addressing.
2860 *
2861 * For now we assume the various PPC GEMs are 32-bit only as well.
2862 */
2863 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
2864 pdev->device == PCI_DEVICE_ID_SUN_GEM &&
2865 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
2866 pci_using_dac = 1;
2867 } else {
2868 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2869 if (err) {
2870 pr_err("No usable DMA configuration, aborting\n");
2871 goto err_disable_device;
2872 }
2873 pci_using_dac = 0;
2874 }
2875
2876 gemreg_base = pci_resource_start(pdev, 0);
2877 gemreg_len = pci_resource_len(pdev, 0);
2878
2879 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
2880 pr_err("Cannot find proper PCI device base address, aborting\n");
2881 err = -ENODEV;
2882 goto err_disable_device;
2883 }
2884
2885 dev = alloc_etherdev(sizeof(*gp));
2886 if (!dev) {
2887 err = -ENOMEM;
2888 goto err_disable_device;
2889 }
2890 SET_NETDEV_DEV(dev, &pdev->dev);
2891
2892 gp = netdev_priv(dev);
2893
2894 err = pci_request_regions(pdev, DRV_NAME);
2895 if (err) {
2896 pr_err("Cannot obtain PCI resources, aborting\n");
2897 goto err_out_free_netdev;
2898 }
2899
2900 gp->pdev = pdev;
2901 dev->base_addr = (long) pdev;
2902 gp->dev = dev;
2903
2904 gp->msg_enable = DEFAULT_MSG;
2905
2906 init_timer(&gp->link_timer);
2907 gp->link_timer.function = gem_link_timer;
2908 gp->link_timer.data = (unsigned long) gp;
2909
2910 INIT_WORK(&gp->reset_task, gem_reset_task);
2911
2912 gp->lstate = link_down;
2913 gp->timer_ticks = 0;
2914 netif_carrier_off(dev);
2915
2916 gp->regs = ioremap(gemreg_base, gemreg_len);
2917 if (!gp->regs) {
2918 pr_err("Cannot map device registers, aborting\n");
2919 err = -EIO;
2920 goto err_out_free_res;
2921 }
2922
2923 /* On Apple, we want a reference to the Open Firmware device-tree
2924 * node. We use it for clock control.
2925 */
2926 #if defined(CONFIG_PPC_PMAC) || defined(CONFIG_SPARC)
2927 gp->of_node = pci_device_to_OF_node(pdev);
2928 #endif
2929
2930 /* Only Apple version supports WOL afaik */
2931 if (pdev->vendor == PCI_VENDOR_ID_APPLE)
2932 gp->has_wol = 1;
2933
2934 /* Make sure cell is enabled */
2935 gem_get_cell(gp);
2936
2937 /* Make sure everything is stopped and in init state */
2938 gem_reset(gp);
2939
2940 /* Fill up the mii_phy structure (even if we won't use it) */
2941 gp->phy_mii.dev = dev;
2942 gp->phy_mii.mdio_read = _phy_read;
2943 gp->phy_mii.mdio_write = _phy_write;
2944 #ifdef CONFIG_PPC_PMAC
2945 gp->phy_mii.platform_data = gp->of_node;
2946 #endif
2947 /* By default, we start with autoneg */
2948 gp->want_autoneg = 1;
2949
2950 /* Check fifo sizes, PHY type, etc... */
2951 if (gem_check_invariants(gp)) {
2952 err = -ENODEV;
2953 goto err_out_iounmap;
2954 }
2955
2956 /* It is guaranteed that the returned buffer will be at least
2957 * PAGE_SIZE aligned.
2958 */
2959 gp->init_block = (struct gem_init_block *)
2960 pci_alloc_consistent(pdev, sizeof(struct gem_init_block),
2961 &gp->gblock_dvma);
2962 if (!gp->init_block) {
2963 pr_err("Cannot allocate init block, aborting\n");
2964 err = -ENOMEM;
2965 goto err_out_iounmap;
2966 }
2967
2968 if (gem_get_device_address(gp))
2969 goto err_out_free_consistent;
2970
2971 dev->netdev_ops = &gem_netdev_ops;
2972 netif_napi_add(dev, &gp->napi, gem_poll, 64);
2973 dev->ethtool_ops = &gem_ethtool_ops;
2974 dev->watchdog_timeo = 5 * HZ;
2975 dev->irq = pdev->irq;
2976 dev->dma = 0;
2977
2978 /* Set that now, in case PM kicks in now */
2979 pci_set_drvdata(pdev, dev);
2980
2981 /* We can do scatter/gather and HW checksum */
2982 dev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM;
2983 dev->features |= dev->hw_features | NETIF_F_RXCSUM;
2984 if (pci_using_dac)
2985 dev->features |= NETIF_F_HIGHDMA;
2986
2987 /* Register with kernel */
2988 if (register_netdev(dev)) {
2989 pr_err("Cannot register net device, aborting\n");
2990 err = -ENOMEM;
2991 goto err_out_free_consistent;
2992 }
2993
2994 /* Undo the get_cell with appropriate locking (we could use
2995 * ndo_init/uninit but that would be even more clumsy imho)
2996 */
2997 rtnl_lock();
2998 gem_put_cell(gp);
2999 rtnl_unlock();
3000
3001 netdev_info(dev, "Sun GEM (PCI) 10/100/1000BaseT Ethernet %pM\n",
3002 dev->dev_addr);
3003 return 0;
3004
3005 err_out_free_consistent:
3006 gem_remove_one(pdev);
3007 err_out_iounmap:
3008 gem_put_cell(gp);
3009 iounmap(gp->regs);
3010
3011 err_out_free_res:
3012 pci_release_regions(pdev);
3013
3014 err_out_free_netdev:
3015 free_netdev(dev);
3016 err_disable_device:
3017 pci_disable_device(pdev);
3018 return err;
3019
3020 }
3021
3022
3023 static struct pci_driver gem_driver = {
3024 .name = GEM_MODULE_NAME,
3025 .id_table = gem_pci_tbl,
3026 .probe = gem_init_one,
3027 .remove = gem_remove_one,
3028 #ifdef CONFIG_PM
3029 .suspend = gem_suspend,
3030 .resume = gem_resume,
3031 #endif /* CONFIG_PM */
3032 };
3033
3034 static int __init gem_init(void)
3035 {
3036 return pci_register_driver(&gem_driver);
3037 }
3038
3039 static void __exit gem_cleanup(void)
3040 {
3041 pci_unregister_driver(&gem_driver);
3042 }
3043
3044 module_init(gem_init);
3045 module_exit(gem_cleanup);
Linux with added FPC-III support