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Linux 3.4.102
[linux/fpc-iii.git] / drivers / net / ethernet / xilinx / ll_temac_main.c
blobd240c0624d460c517892f1ca0d054cc2fa6f43bf
1 /*
2 * Driver for Xilinx TEMAC Ethernet device
3 *
4 * Copyright (c) 2008 Nissin Systems Co., Ltd., Yoshio Kashiwagi
5 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net>
6 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
7 *
8 * This is a driver for the Xilinx ll_temac ipcore which is often used
9 * in the Virtex and Spartan series of chips.
10 *
11 * Notes:
12 * - The ll_temac hardware uses indirect access for many of the TEMAC
13 * registers, include the MDIO bus. However, indirect access to MDIO
14 * registers take considerably more clock cycles than to TEMAC registers.
15 * MDIO accesses are long, so threads doing them should probably sleep
16 * rather than busywait. However, since only one indirect access can be
17 * in progress at any given time, that means that *all* indirect accesses
18 * could end up sleeping (to wait for an MDIO access to complete).
19 * Fortunately none of the indirect accesses are on the 'hot' path for tx
20 * or rx, so this should be okay.
21 *
22 * TODO:
23 * - Factor out locallink DMA code into separate driver
24 * - Fix multicast assignment.
25 * - Fix support for hardware checksumming.
26 * - Testing. Lots and lots of testing.
27 *
28 */
29
30 #include <linux/delay.h>
31 #include <linux/etherdevice.h>
32 #include <linux/init.h>
33 #include <linux/mii.h>
34 #include <linux/module.h>
35 #include <linux/mutex.h>
36 #include <linux/netdevice.h>
37 #include <linux/of.h>
38 #include <linux/of_device.h>
39 #include <linux/of_mdio.h>
40 #include <linux/of_platform.h>
41 #include <linux/of_address.h>
42 #include <linux/skbuff.h>
43 #include <linux/spinlock.h>
44 #include <linux/tcp.h> /* needed for sizeof(tcphdr) */
45 #include <linux/udp.h> /* needed for sizeof(udphdr) */
46 #include <linux/phy.h>
47 #include <linux/in.h>
48 #include <linux/io.h>
49 #include <linux/ip.h>
50 #include <linux/slab.h>
51 #include <linux/interrupt.h>
52 #include <linux/dma-mapping.h>
53
54 #include "ll_temac.h"
55
56 #define TX_BD_NUM 64
57 #define RX_BD_NUM 128
58
59 /* ---------------------------------------------------------------------
60 * Low level register access functions
61 */
62
63 u32 temac_ior(struct temac_local *lp, int offset)
64 {
65 return in_be32((u32 *)(lp->regs + offset));
66 }
67
68 void temac_iow(struct temac_local *lp, int offset, u32 value)
69 {
70 out_be32((u32 *) (lp->regs + offset), value);
71 }
72
73 int temac_indirect_busywait(struct temac_local *lp)
74 {
75 long end = jiffies + 2;
76
77 while (!(temac_ior(lp, XTE_RDY0_OFFSET) & XTE_RDY0_HARD_ACS_RDY_MASK)) {
78 if (end - jiffies <= 0) {
79 WARN_ON(1);
80 return -ETIMEDOUT;
81 }
82 msleep(1);
83 }
84 return 0;
85 }
86
87 /**
88 * temac_indirect_in32
89 *
90 * lp->indirect_mutex must be held when calling this function
91 */
92 u32 temac_indirect_in32(struct temac_local *lp, int reg)
93 {
94 u32 val;
95
96 if (temac_indirect_busywait(lp))
97 return -ETIMEDOUT;
98 temac_iow(lp, XTE_CTL0_OFFSET, reg);
99 if (temac_indirect_busywait(lp))
100 return -ETIMEDOUT;
101 val = temac_ior(lp, XTE_LSW0_OFFSET);
102
103 return val;
104 }
105
106 /**
107 * temac_indirect_out32
108 *
109 * lp->indirect_mutex must be held when calling this function
110 */
111 void temac_indirect_out32(struct temac_local *lp, int reg, u32 value)
112 {
113 if (temac_indirect_busywait(lp))
114 return;
115 temac_iow(lp, XTE_LSW0_OFFSET, value);
116 temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg);
117 temac_indirect_busywait(lp);
118 }
119
120 /**
121 * temac_dma_in32 - Memory mapped DMA read, this function expects a
122 * register input that is based on DCR word addresses which
123 * are then converted to memory mapped byte addresses
124 */
125 static u32 temac_dma_in32(struct temac_local *lp, int reg)
126 {
127 return in_be32((u32 *)(lp->sdma_regs + (reg << 2)));
128 }
129
130 /**
131 * temac_dma_out32 - Memory mapped DMA read, this function expects a
132 * register input that is based on DCR word addresses which
133 * are then converted to memory mapped byte addresses
134 */
135 static void temac_dma_out32(struct temac_local *lp, int reg, u32 value)
136 {
137 out_be32((u32 *)(lp->sdma_regs + (reg << 2)), value);
138 }
139
140 /* DMA register access functions can be DCR based or memory mapped.
141 * The PowerPC 440 is DCR based, the PowerPC 405 and MicroBlaze are both
142 * memory mapped.
143 */
144 #ifdef CONFIG_PPC_DCR
145
146 /**
147 * temac_dma_dcr_in32 - DCR based DMA read
148 */
149 static u32 temac_dma_dcr_in(struct temac_local *lp, int reg)
150 {
151 return dcr_read(lp->sdma_dcrs, reg);
152 }
153
154 /**
155 * temac_dma_dcr_out32 - DCR based DMA write
156 */
157 static void temac_dma_dcr_out(struct temac_local *lp, int reg, u32 value)
158 {
159 dcr_write(lp->sdma_dcrs, reg, value);
160 }
161
162 /**
163 * temac_dcr_setup - If the DMA is DCR based, then setup the address and
164 * I/O functions
165 */
166 static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
167 struct device_node *np)
168 {
169 unsigned int dcrs;
170
171 /* setup the dcr address mapping if it's in the device tree */
172
173 dcrs = dcr_resource_start(np, 0);
174 if (dcrs != 0) {
175 lp->sdma_dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
176 lp->dma_in = temac_dma_dcr_in;
177 lp->dma_out = temac_dma_dcr_out;
178 dev_dbg(&op->dev, "DCR base: %x\n", dcrs);
179 return 0;
180 }
181 /* no DCR in the device tree, indicate a failure */
182 return -1;
183 }
184
185 #else
186
187 /*
188 * temac_dcr_setup - This is a stub for when DCR is not supported,
189 * such as with MicroBlaze
190 */
191 static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
192 struct device_node *np)
193 {
194 return -1;
195 }
196
197 #endif
198
199 /**
200 * * temac_dma_bd_release - Release buffer descriptor rings
201 */
202 static void temac_dma_bd_release(struct net_device *ndev)
203 {
204 struct temac_local *lp = netdev_priv(ndev);
205 int i;
206
207 /* Reset Local Link (DMA) */
208 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
209
210 for (i = 0; i < RX_BD_NUM; i++) {
211 if (!lp->rx_skb[i])
212 break;
213 else {
214 dma_unmap_single(ndev->dev.parent, lp->rx_bd_v[i].phys,
215 XTE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE);
216 dev_kfree_skb(lp->rx_skb[i]);
217 }
218 }
219 if (lp->rx_bd_v)
220 dma_free_coherent(ndev->dev.parent,
221 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
222 lp->rx_bd_v, lp->rx_bd_p);
223 if (lp->tx_bd_v)
224 dma_free_coherent(ndev->dev.parent,
225 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
226 lp->tx_bd_v, lp->tx_bd_p);
227 if (lp->rx_skb)
228 kfree(lp->rx_skb);
229 }
230
231 /**
232 * temac_dma_bd_init - Setup buffer descriptor rings
233 */
234 static int temac_dma_bd_init(struct net_device *ndev)
235 {
236 struct temac_local *lp = netdev_priv(ndev);
237 struct sk_buff *skb;
238 int i;
239
240 lp->rx_skb = kcalloc(RX_BD_NUM, sizeof(*lp->rx_skb), GFP_KERNEL);
241 if (!lp->rx_skb) {
242 dev_err(&ndev->dev,
243 "can't allocate memory for DMA RX buffer\n");
244 goto out;
245 }
246 /* allocate the tx and rx ring buffer descriptors. */
247 /* returns a virtual address and a physical address. */
248 lp->tx_bd_v = dma_alloc_coherent(ndev->dev.parent,
249 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
250 &lp->tx_bd_p, GFP_KERNEL);
251 if (!lp->tx_bd_v) {
252 dev_err(&ndev->dev,
253 "unable to allocate DMA TX buffer descriptors");
254 goto out;
255 }
256 lp->rx_bd_v = dma_alloc_coherent(ndev->dev.parent,
257 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
258 &lp->rx_bd_p, GFP_KERNEL);
259 if (!lp->rx_bd_v) {
260 dev_err(&ndev->dev,
261 "unable to allocate DMA RX buffer descriptors");
262 goto out;
263 }
264
265 memset(lp->tx_bd_v, 0, sizeof(*lp->tx_bd_v) * TX_BD_NUM);
266 for (i = 0; i < TX_BD_NUM; i++) {
267 lp->tx_bd_v[i].next = lp->tx_bd_p +
268 sizeof(*lp->tx_bd_v) * ((i + 1) % TX_BD_NUM);
269 }
270
271 memset(lp->rx_bd_v, 0, sizeof(*lp->rx_bd_v) * RX_BD_NUM);
272 for (i = 0; i < RX_BD_NUM; i++) {
273 lp->rx_bd_v[i].next = lp->rx_bd_p +
274 sizeof(*lp->rx_bd_v) * ((i + 1) % RX_BD_NUM);
275
276 skb = netdev_alloc_skb_ip_align(ndev,
277 XTE_MAX_JUMBO_FRAME_SIZE);
278
279 if (skb == 0) {
280 dev_err(&ndev->dev, "alloc_skb error %d\n", i);
281 goto out;
282 }
283 lp->rx_skb[i] = skb;
284 /* returns physical address of skb->data */
285 lp->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent,
286 skb->data,
287 XTE_MAX_JUMBO_FRAME_SIZE,
288 DMA_FROM_DEVICE);
289 lp->rx_bd_v[i].len = XTE_MAX_JUMBO_FRAME_SIZE;
290 lp->rx_bd_v[i].app0 = STS_CTRL_APP0_IRQONEND;
291 }
292
293 lp->dma_out(lp, TX_CHNL_CTRL, 0x10220400 |
294 CHNL_CTRL_IRQ_EN |
295 CHNL_CTRL_IRQ_DLY_EN |
296 CHNL_CTRL_IRQ_COAL_EN);
297 /* 0x10220483 */
298 /* 0x00100483 */
299 lp->dma_out(lp, RX_CHNL_CTRL, 0xff070000 |
300 CHNL_CTRL_IRQ_EN |
301 CHNL_CTRL_IRQ_DLY_EN |
302 CHNL_CTRL_IRQ_COAL_EN |
303 CHNL_CTRL_IRQ_IOE);
304 /* 0xff010283 */
305
306 lp->dma_out(lp, RX_CURDESC_PTR, lp->rx_bd_p);
307 lp->dma_out(lp, RX_TAILDESC_PTR,
308 lp->rx_bd_p + (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
309 lp->dma_out(lp, TX_CURDESC_PTR, lp->tx_bd_p);
310
311 /* Init descriptor indexes */
312 lp->tx_bd_ci = 0;
313 lp->tx_bd_next = 0;
314 lp->tx_bd_tail = 0;
315 lp->rx_bd_ci = 0;
316
317 return 0;
318
319 out:
320 temac_dma_bd_release(ndev);
321 return -ENOMEM;
322 }
323
324 /* ---------------------------------------------------------------------
325 * net_device_ops
326 */
327
328 static int temac_set_mac_address(struct net_device *ndev, void *address)
329 {
330 struct temac_local *lp = netdev_priv(ndev);
331
332 if (address)
333 memcpy(ndev->dev_addr, address, ETH_ALEN);
334
335 if (!is_valid_ether_addr(ndev->dev_addr))
336 eth_hw_addr_random(ndev);
337 else
338 ndev->addr_assign_type &= ~NET_ADDR_RANDOM;
339
340 /* set up unicast MAC address filter set its mac address */
341 mutex_lock(&lp->indirect_mutex);
342 temac_indirect_out32(lp, XTE_UAW0_OFFSET,
343 (ndev->dev_addr[0]) |
344 (ndev->dev_addr[1] << 8) |
345 (ndev->dev_addr[2] << 16) |
346 (ndev->dev_addr[3] << 24));
347 /* There are reserved bits in EUAW1
348 * so don't affect them Set MAC bits [47:32] in EUAW1 */
349 temac_indirect_out32(lp, XTE_UAW1_OFFSET,
350 (ndev->dev_addr[4] & 0x000000ff) |
351 (ndev->dev_addr[5] << 8));
352 mutex_unlock(&lp->indirect_mutex);
353
354 return 0;
355 }
356
357 static int netdev_set_mac_address(struct net_device *ndev, void *p)
358 {
359 struct sockaddr *addr = p;
360
361 return temac_set_mac_address(ndev, addr->sa_data);
362 }
363
364 static void temac_set_multicast_list(struct net_device *ndev)
365 {
366 struct temac_local *lp = netdev_priv(ndev);
367 u32 multi_addr_msw, multi_addr_lsw, val;
368 int i;
369
370 mutex_lock(&lp->indirect_mutex);
371 if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) ||
372 netdev_mc_count(ndev) > MULTICAST_CAM_TABLE_NUM) {
373 /*
374 * We must make the kernel realise we had to move
375 * into promisc mode or we start all out war on
376 * the cable. If it was a promisc request the
377 * flag is already set. If not we assert it.
378 */
379 ndev->flags |= IFF_PROMISC;
380 temac_indirect_out32(lp, XTE_AFM_OFFSET, XTE_AFM_EPPRM_MASK);
381 dev_info(&ndev->dev, "Promiscuous mode enabled.\n");
382 } else if (!netdev_mc_empty(ndev)) {
383 struct netdev_hw_addr *ha;
384
385 i = 0;
386 netdev_for_each_mc_addr(ha, ndev) {
387 if (i >= MULTICAST_CAM_TABLE_NUM)
388 break;
389 multi_addr_msw = ((ha->addr[3] << 24) |
390 (ha->addr[2] << 16) |
391 (ha->addr[1] << 8) |
392 (ha->addr[0]));
393 temac_indirect_out32(lp, XTE_MAW0_OFFSET,
394 multi_addr_msw);
395 multi_addr_lsw = ((ha->addr[5] << 8) |
396 (ha->addr[4]) | (i << 16));
397 temac_indirect_out32(lp, XTE_MAW1_OFFSET,
398 multi_addr_lsw);
399 i++;
400 }
401 } else {
402 val = temac_indirect_in32(lp, XTE_AFM_OFFSET);
403 temac_indirect_out32(lp, XTE_AFM_OFFSET,
404 val & ~XTE_AFM_EPPRM_MASK);
405 temac_indirect_out32(lp, XTE_MAW0_OFFSET, 0);
406 temac_indirect_out32(lp, XTE_MAW1_OFFSET, 0);
407 dev_info(&ndev->dev, "Promiscuous mode disabled.\n");
408 }
409 mutex_unlock(&lp->indirect_mutex);
410 }
411
412 struct temac_option {
413 int flg;
414 u32 opt;
415 u32 reg;
416 u32 m_or;
417 u32 m_and;
418 } temac_options[] = {
419 /* Turn on jumbo packet support for both Rx and Tx */
420 {
421 .opt = XTE_OPTION_JUMBO,
422 .reg = XTE_TXC_OFFSET,
423 .m_or = XTE_TXC_TXJMBO_MASK,
424 },
425 {
426 .opt = XTE_OPTION_JUMBO,
427 .reg = XTE_RXC1_OFFSET,
428 .m_or =XTE_RXC1_RXJMBO_MASK,
429 },
430 /* Turn on VLAN packet support for both Rx and Tx */
431 {
432 .opt = XTE_OPTION_VLAN,
433 .reg = XTE_TXC_OFFSET,
434 .m_or =XTE_TXC_TXVLAN_MASK,
435 },
436 {
437 .opt = XTE_OPTION_VLAN,
438 .reg = XTE_RXC1_OFFSET,
439 .m_or =XTE_RXC1_RXVLAN_MASK,
440 },
441 /* Turn on FCS stripping on receive packets */
442 {
443 .opt = XTE_OPTION_FCS_STRIP,
444 .reg = XTE_RXC1_OFFSET,
445 .m_or =XTE_RXC1_RXFCS_MASK,
446 },
447 /* Turn on FCS insertion on transmit packets */
448 {
449 .opt = XTE_OPTION_FCS_INSERT,
450 .reg = XTE_TXC_OFFSET,
451 .m_or =XTE_TXC_TXFCS_MASK,
452 },
453 /* Turn on length/type field checking on receive packets */
454 {
455 .opt = XTE_OPTION_LENTYPE_ERR,
456 .reg = XTE_RXC1_OFFSET,
457 .m_or =XTE_RXC1_RXLT_MASK,
458 },
459 /* Turn on flow control */
460 {
461 .opt = XTE_OPTION_FLOW_CONTROL,
462 .reg = XTE_FCC_OFFSET,
463 .m_or =XTE_FCC_RXFLO_MASK,
464 },
465 /* Turn on flow control */
466 {
467 .opt = XTE_OPTION_FLOW_CONTROL,
468 .reg = XTE_FCC_OFFSET,
469 .m_or =XTE_FCC_TXFLO_MASK,
470 },
471 /* Turn on promiscuous frame filtering (all frames are received ) */
472 {
473 .opt = XTE_OPTION_PROMISC,
474 .reg = XTE_AFM_OFFSET,
475 .m_or =XTE_AFM_EPPRM_MASK,
476 },
477 /* Enable transmitter if not already enabled */
478 {
479 .opt = XTE_OPTION_TXEN,
480 .reg = XTE_TXC_OFFSET,
481 .m_or =XTE_TXC_TXEN_MASK,
482 },
483 /* Enable receiver? */
484 {
485 .opt = XTE_OPTION_RXEN,
486 .reg = XTE_RXC1_OFFSET,
487 .m_or =XTE_RXC1_RXEN_MASK,
488 },
489 {}
490 };
491
492 /**
493 * temac_setoptions
494 */
495 static u32 temac_setoptions(struct net_device *ndev, u32 options)
496 {
497 struct temac_local *lp = netdev_priv(ndev);
498 struct temac_option *tp = &temac_options[0];
499 int reg;
500
501 mutex_lock(&lp->indirect_mutex);
502 while (tp->opt) {
503 reg = temac_indirect_in32(lp, tp->reg) & ~tp->m_or;
504 if (options & tp->opt)
505 reg |= tp->m_or;
506 temac_indirect_out32(lp, tp->reg, reg);
507 tp++;
508 }
509 lp->options |= options;
510 mutex_unlock(&lp->indirect_mutex);
511
512 return 0;
513 }
514
515 /* Initialize temac */
516 static void temac_device_reset(struct net_device *ndev)
517 {
518 struct temac_local *lp = netdev_priv(ndev);
519 u32 timeout;
520 u32 val;
521
522 /* Perform a software reset */
523
524 /* 0x300 host enable bit ? */
525 /* reset PHY through control register ?:1 */
526
527 dev_dbg(&ndev->dev, "%s()\n", __func__);
528
529 mutex_lock(&lp->indirect_mutex);
530 /* Reset the receiver and wait for it to finish reset */
531 temac_indirect_out32(lp, XTE_RXC1_OFFSET, XTE_RXC1_RXRST_MASK);
532 timeout = 1000;
533 while (temac_indirect_in32(lp, XTE_RXC1_OFFSET) & XTE_RXC1_RXRST_MASK) {
534 udelay(1);
535 if (--timeout == 0) {
536 dev_err(&ndev->dev,
537 "temac_device_reset RX reset timeout!!\n");
538 break;
539 }
540 }
541
542 /* Reset the transmitter and wait for it to finish reset */
543 temac_indirect_out32(lp, XTE_TXC_OFFSET, XTE_TXC_TXRST_MASK);
544 timeout = 1000;
545 while (temac_indirect_in32(lp, XTE_TXC_OFFSET) & XTE_TXC_TXRST_MASK) {
546 udelay(1);
547 if (--timeout == 0) {
548 dev_err(&ndev->dev,
549 "temac_device_reset TX reset timeout!!\n");
550 break;
551 }
552 }
553
554 /* Disable the receiver */
555 val = temac_indirect_in32(lp, XTE_RXC1_OFFSET);
556 temac_indirect_out32(lp, XTE_RXC1_OFFSET, val & ~XTE_RXC1_RXEN_MASK);
557
558 /* Reset Local Link (DMA) */
559 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
560 timeout = 1000;
561 while (lp->dma_in(lp, DMA_CONTROL_REG) & DMA_CONTROL_RST) {
562 udelay(1);
563 if (--timeout == 0) {
564 dev_err(&ndev->dev,
565 "temac_device_reset DMA reset timeout!!\n");
566 break;
567 }
568 }
569 lp->dma_out(lp, DMA_CONTROL_REG, DMA_TAIL_ENABLE);
570
571 if (temac_dma_bd_init(ndev)) {
572 dev_err(&ndev->dev,
573 "temac_device_reset descriptor allocation failed\n");
574 }
575
576 temac_indirect_out32(lp, XTE_RXC0_OFFSET, 0);
577 temac_indirect_out32(lp, XTE_RXC1_OFFSET, 0);
578 temac_indirect_out32(lp, XTE_TXC_OFFSET, 0);
579 temac_indirect_out32(lp, XTE_FCC_OFFSET, XTE_FCC_RXFLO_MASK);
580
581 mutex_unlock(&lp->indirect_mutex);
582
583 /* Sync default options with HW
584 * but leave receiver and transmitter disabled. */
585 temac_setoptions(ndev,
586 lp->options & ~(XTE_OPTION_TXEN | XTE_OPTION_RXEN));
587
588 temac_set_mac_address(ndev, NULL);
589
590 /* Set address filter table */
591 temac_set_multicast_list(ndev);
592 if (temac_setoptions(ndev, lp->options))
593 dev_err(&ndev->dev, "Error setting TEMAC options\n");
594
595 /* Init Driver variable */
596 ndev->trans_start = jiffies; /* prevent tx timeout */
597 }
598
599 void temac_adjust_link(struct net_device *ndev)
600 {
601 struct temac_local *lp = netdev_priv(ndev);
602 struct phy_device *phy = lp->phy_dev;
603 u32 mii_speed;
604 int link_state;
605
606 /* hash together the state values to decide if something has changed */
607 link_state = phy->speed | (phy->duplex << 1) | phy->link;
608
609 mutex_lock(&lp->indirect_mutex);
610 if (lp->last_link != link_state) {
611 mii_speed = temac_indirect_in32(lp, XTE_EMCFG_OFFSET);
612 mii_speed &= ~XTE_EMCFG_LINKSPD_MASK;
613
614 switch (phy->speed) {
615 case SPEED_1000: mii_speed |= XTE_EMCFG_LINKSPD_1000; break;
616 case SPEED_100: mii_speed |= XTE_EMCFG_LINKSPD_100; break;
617 case SPEED_10: mii_speed |= XTE_EMCFG_LINKSPD_10; break;
618 }
619
620 /* Write new speed setting out to TEMAC */
621 temac_indirect_out32(lp, XTE_EMCFG_OFFSET, mii_speed);
622 lp->last_link = link_state;
623 phy_print_status(phy);
624 }
625 mutex_unlock(&lp->indirect_mutex);
626 }
627
628 static void temac_start_xmit_done(struct net_device *ndev)
629 {
630 struct temac_local *lp = netdev_priv(ndev);
631 struct cdmac_bd *cur_p;
632 unsigned int stat = 0;
633
634 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
635 stat = cur_p->app0;
636
637 while (stat & STS_CTRL_APP0_CMPLT) {
638 dma_unmap_single(ndev->dev.parent, cur_p->phys, cur_p->len,
639 DMA_TO_DEVICE);
640 if (cur_p->app4)
641 dev_kfree_skb_irq((struct sk_buff *)cur_p->app4);
642 cur_p->app0 = 0;
643 cur_p->app1 = 0;
644 cur_p->app2 = 0;
645 cur_p->app3 = 0;
646 cur_p->app4 = 0;
647
648 ndev->stats.tx_packets++;
649 ndev->stats.tx_bytes += cur_p->len;
650
651 lp->tx_bd_ci++;
652 if (lp->tx_bd_ci >= TX_BD_NUM)
653 lp->tx_bd_ci = 0;
654
655 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
656 stat = cur_p->app0;
657 }
658
659 netif_wake_queue(ndev);
660 }
661
662 static inline int temac_check_tx_bd_space(struct temac_local *lp, int num_frag)
663 {
664 struct cdmac_bd *cur_p;
665 int tail;
666
667 tail = lp->tx_bd_tail;
668 cur_p = &lp->tx_bd_v[tail];
669
670 do {
671 if (cur_p->app0)
672 return NETDEV_TX_BUSY;
673
674 tail++;
675 if (tail >= TX_BD_NUM)
676 tail = 0;
677
678 cur_p = &lp->tx_bd_v[tail];
679 num_frag--;
680 } while (num_frag >= 0);
681
682 return 0;
683 }
684
685 static int temac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
686 {
687 struct temac_local *lp = netdev_priv(ndev);
688 struct cdmac_bd *cur_p;
689 dma_addr_t start_p, tail_p;
690 int ii;
691 unsigned long num_frag;
692 skb_frag_t *frag;
693
694 num_frag = skb_shinfo(skb)->nr_frags;
695 frag = &skb_shinfo(skb)->frags[0];
696 start_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
697 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
698
699 if (temac_check_tx_bd_space(lp, num_frag)) {
700 if (!netif_queue_stopped(ndev)) {
701 netif_stop_queue(ndev);
702 return NETDEV_TX_BUSY;
703 }
704 return NETDEV_TX_BUSY;
705 }
706
707 cur_p->app0 = 0;
708 if (skb->ip_summed == CHECKSUM_PARTIAL) {
709 unsigned int csum_start_off = skb_checksum_start_offset(skb);
710 unsigned int csum_index_off = csum_start_off + skb->csum_offset;
711
712 cur_p->app0 |= 1; /* TX Checksum Enabled */
713 cur_p->app1 = (csum_start_off << 16) | csum_index_off;
714 cur_p->app2 = 0; /* initial checksum seed */
715 }
716
717 cur_p->app0 |= STS_CTRL_APP0_SOP;
718 cur_p->len = skb_headlen(skb);
719 cur_p->phys = dma_map_single(ndev->dev.parent, skb->data, skb->len,
720 DMA_TO_DEVICE);
721 cur_p->app4 = (unsigned long)skb;
722
723 for (ii = 0; ii < num_frag; ii++) {
724 lp->tx_bd_tail++;
725 if (lp->tx_bd_tail >= TX_BD_NUM)
726 lp->tx_bd_tail = 0;
727
728 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
729 cur_p->phys = dma_map_single(ndev->dev.parent,
730 skb_frag_address(frag),
731 skb_frag_size(frag), DMA_TO_DEVICE);
732 cur_p->len = skb_frag_size(frag);
733 cur_p->app0 = 0;
734 frag++;
735 }
736 cur_p->app0 |= STS_CTRL_APP0_EOP;
737
738 tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
739 lp->tx_bd_tail++;
740 if (lp->tx_bd_tail >= TX_BD_NUM)
741 lp->tx_bd_tail = 0;
742
743 skb_tx_timestamp(skb);
744
745 /* Kick off the transfer */
746 lp->dma_out(lp, TX_TAILDESC_PTR, tail_p); /* DMA start */
747
748 return NETDEV_TX_OK;
749 }
750
751
752 static void ll_temac_recv(struct net_device *ndev)
753 {
754 struct temac_local *lp = netdev_priv(ndev);
755 struct sk_buff *skb, *new_skb;
756 unsigned int bdstat;
757 struct cdmac_bd *cur_p;
758 dma_addr_t tail_p;
759 int length;
760 unsigned long flags;
761
762 spin_lock_irqsave(&lp->rx_lock, flags);
763
764 tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci;
765 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
766
767 bdstat = cur_p->app0;
768 while ((bdstat & STS_CTRL_APP0_CMPLT)) {
769
770 skb = lp->rx_skb[lp->rx_bd_ci];
771 length = cur_p->app4 & 0x3FFF;
772
773 dma_unmap_single(ndev->dev.parent, cur_p->phys, length,
774 DMA_FROM_DEVICE);
775
776 skb_put(skb, length);
777 skb->dev = ndev;
778 skb->protocol = eth_type_trans(skb, ndev);
779 skb_checksum_none_assert(skb);
780
781 /* if we're doing rx csum offload, set it up */
782 if (((lp->temac_features & TEMAC_FEATURE_RX_CSUM) != 0) &&
783 (skb->protocol == __constant_htons(ETH_P_IP)) &&
784 (skb->len > 64)) {
785
786 skb->csum = cur_p->app3 & 0xFFFF;
787 skb->ip_summed = CHECKSUM_COMPLETE;
788 }
789
790 if (!skb_defer_rx_timestamp(skb))
791 netif_rx(skb);
792
793 ndev->stats.rx_packets++;
794 ndev->stats.rx_bytes += length;
795
796 new_skb = netdev_alloc_skb_ip_align(ndev,
797 XTE_MAX_JUMBO_FRAME_SIZE);
798
799 if (new_skb == 0) {
800 dev_err(&ndev->dev, "no memory for new sk_buff\n");
801 spin_unlock_irqrestore(&lp->rx_lock, flags);
802 return;
803 }
804
805 cur_p->app0 = STS_CTRL_APP0_IRQONEND;
806 cur_p->phys = dma_map_single(ndev->dev.parent, new_skb->data,
807 XTE_MAX_JUMBO_FRAME_SIZE,
808 DMA_FROM_DEVICE);
809 cur_p->len = XTE_MAX_JUMBO_FRAME_SIZE;
810 lp->rx_skb[lp->rx_bd_ci] = new_skb;
811
812 lp->rx_bd_ci++;
813 if (lp->rx_bd_ci >= RX_BD_NUM)
814 lp->rx_bd_ci = 0;
815
816 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
817 bdstat = cur_p->app0;
818 }
819 lp->dma_out(lp, RX_TAILDESC_PTR, tail_p);
820
821 spin_unlock_irqrestore(&lp->rx_lock, flags);
822 }
823
824 static irqreturn_t ll_temac_tx_irq(int irq, void *_ndev)
825 {
826 struct net_device *ndev = _ndev;
827 struct temac_local *lp = netdev_priv(ndev);
828 unsigned int status;
829
830 status = lp->dma_in(lp, TX_IRQ_REG);
831 lp->dma_out(lp, TX_IRQ_REG, status);
832
833 if (status & (IRQ_COAL | IRQ_DLY))
834 temac_start_xmit_done(lp->ndev);
835 if (status & 0x080)
836 dev_err(&ndev->dev, "DMA error 0x%x\n", status);
837
838 return IRQ_HANDLED;
839 }
840
841 static irqreturn_t ll_temac_rx_irq(int irq, void *_ndev)
842 {
843 struct net_device *ndev = _ndev;
844 struct temac_local *lp = netdev_priv(ndev);
845 unsigned int status;
846
847 /* Read and clear the status registers */
848 status = lp->dma_in(lp, RX_IRQ_REG);
849 lp->dma_out(lp, RX_IRQ_REG, status);
850
851 if (status & (IRQ_COAL | IRQ_DLY))
852 ll_temac_recv(lp->ndev);
853
854 return IRQ_HANDLED;
855 }
856
857 static int temac_open(struct net_device *ndev)
858 {
859 struct temac_local *lp = netdev_priv(ndev);
860 int rc;
861
862 dev_dbg(&ndev->dev, "temac_open()\n");
863
864 if (lp->phy_node) {
865 lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node,
866 temac_adjust_link, 0, 0);
867 if (!lp->phy_dev) {
868 dev_err(lp->dev, "of_phy_connect() failed\n");
869 return -ENODEV;
870 }
871
872 phy_start(lp->phy_dev);
873 }
874
875 temac_device_reset(ndev);
876
877 rc = request_irq(lp->tx_irq, ll_temac_tx_irq, 0, ndev->name, ndev);
878 if (rc)
879 goto err_tx_irq;
880 rc = request_irq(lp->rx_irq, ll_temac_rx_irq, 0, ndev->name, ndev);
881 if (rc)
882 goto err_rx_irq;
883
884 return 0;
885
886 err_rx_irq:
887 free_irq(lp->tx_irq, ndev);
888 err_tx_irq:
889 if (lp->phy_dev)
890 phy_disconnect(lp->phy_dev);
891 lp->phy_dev = NULL;
892 dev_err(lp->dev, "request_irq() failed\n");
893 return rc;
894 }
895
896 static int temac_stop(struct net_device *ndev)
897 {
898 struct temac_local *lp = netdev_priv(ndev);
899
900 dev_dbg(&ndev->dev, "temac_close()\n");
901
902 free_irq(lp->tx_irq, ndev);
903 free_irq(lp->rx_irq, ndev);
904
905 if (lp->phy_dev)
906 phy_disconnect(lp->phy_dev);
907 lp->phy_dev = NULL;
908
909 temac_dma_bd_release(ndev);
910
911 return 0;
912 }
913
914 #ifdef CONFIG_NET_POLL_CONTROLLER
915 static void
916 temac_poll_controller(struct net_device *ndev)
917 {
918 struct temac_local *lp = netdev_priv(ndev);
919
920 disable_irq(lp->tx_irq);
921 disable_irq(lp->rx_irq);
922
923 ll_temac_rx_irq(lp->tx_irq, ndev);
924 ll_temac_tx_irq(lp->rx_irq, ndev);
925
926 enable_irq(lp->tx_irq);
927 enable_irq(lp->rx_irq);
928 }
929 #endif
930
931 static int temac_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
932 {
933 struct temac_local *lp = netdev_priv(ndev);
934
935 if (!netif_running(ndev))
936 return -EINVAL;
937
938 if (!lp->phy_dev)
939 return -EINVAL;
940
941 return phy_mii_ioctl(lp->phy_dev, rq, cmd);
942 }
943
944 static const struct net_device_ops temac_netdev_ops = {
945 .ndo_open = temac_open,
946 .ndo_stop = temac_stop,
947 .ndo_start_xmit = temac_start_xmit,
948 .ndo_set_mac_address = netdev_set_mac_address,
949 .ndo_validate_addr = eth_validate_addr,
950 .ndo_do_ioctl = temac_ioctl,
951 #ifdef CONFIG_NET_POLL_CONTROLLER
952 .ndo_poll_controller = temac_poll_controller,
953 #endif
954 };
955
956 /* ---------------------------------------------------------------------
957 * SYSFS device attributes
958 */
959 static ssize_t temac_show_llink_regs(struct device *dev,
960 struct device_attribute *attr, char *buf)
961 {
962 struct net_device *ndev = dev_get_drvdata(dev);
963 struct temac_local *lp = netdev_priv(ndev);
964 int i, len = 0;
965
966 for (i = 0; i < 0x11; i++)
967 len += sprintf(buf + len, "%.8x%s", lp->dma_in(lp, i),
968 (i % 8) == 7 ? "\n" : " ");
969 len += sprintf(buf + len, "\n");
970
971 return len;
972 }
973
974 static DEVICE_ATTR(llink_regs, 0440, temac_show_llink_regs, NULL);
975
976 static struct attribute *temac_device_attrs[] = {
977 &dev_attr_llink_regs.attr,
978 NULL,
979 };
980
981 static const struct attribute_group temac_attr_group = {
982 .attrs = temac_device_attrs,
983 };
984
985 /* ethtool support */
986 static int temac_get_settings(struct net_device *ndev, struct ethtool_cmd *cmd)
987 {
988 struct temac_local *lp = netdev_priv(ndev);
989 return phy_ethtool_gset(lp->phy_dev, cmd);
990 }
991
992 static int temac_set_settings(struct net_device *ndev, struct ethtool_cmd *cmd)
993 {
994 struct temac_local *lp = netdev_priv(ndev);
995 return phy_ethtool_sset(lp->phy_dev, cmd);
996 }
997
998 static int temac_nway_reset(struct net_device *ndev)
999 {
1000 struct temac_local *lp = netdev_priv(ndev);
1001 return phy_start_aneg(lp->phy_dev);
1002 }
1003
1004 static const struct ethtool_ops temac_ethtool_ops = {
1005 .get_settings = temac_get_settings,
1006 .set_settings = temac_set_settings,
1007 .nway_reset = temac_nway_reset,
1008 .get_link = ethtool_op_get_link,
1009 };
1010
1011 static int __devinit temac_of_probe(struct platform_device *op)
1012 {
1013 struct device_node *np;
1014 struct temac_local *lp;
1015 struct net_device *ndev;
1016 const void *addr;
1017 __be32 *p;
1018 int size, rc = 0;
1019
1020 /* Init network device structure */
1021 ndev = alloc_etherdev(sizeof(*lp));
1022 if (!ndev)
1023 return -ENOMEM;
1024
1025 ether_setup(ndev);
1026 dev_set_drvdata(&op->dev, ndev);
1027 SET_NETDEV_DEV(ndev, &op->dev);
1028 ndev->flags &= ~IFF_MULTICAST; /* clear multicast */
1029 ndev->features = NETIF_F_SG;
1030 ndev->netdev_ops = &temac_netdev_ops;
1031 ndev->ethtool_ops = &temac_ethtool_ops;
1032 #if 0
1033 ndev->features |= NETIF_F_IP_CSUM; /* Can checksum TCP/UDP over IPv4. */
1034 ndev->features |= NETIF_F_HW_CSUM; /* Can checksum all the packets. */
1035 ndev->features |= NETIF_F_IPV6_CSUM; /* Can checksum IPV6 TCP/UDP */
1036 ndev->features |= NETIF_F_HIGHDMA; /* Can DMA to high memory. */
1037 ndev->features |= NETIF_F_HW_VLAN_TX; /* Transmit VLAN hw accel */
1038 ndev->features |= NETIF_F_HW_VLAN_RX; /* Receive VLAN hw acceleration */
1039 ndev->features |= NETIF_F_HW_VLAN_FILTER; /* Receive VLAN filtering */
1040 ndev->features |= NETIF_F_VLAN_CHALLENGED; /* cannot handle VLAN pkts */
1041 ndev->features |= NETIF_F_GSO; /* Enable software GSO. */
1042 ndev->features |= NETIF_F_MULTI_QUEUE; /* Has multiple TX/RX queues */
1043 ndev->features |= NETIF_F_LRO; /* large receive offload */
1044 #endif
1045
1046 /* setup temac private info structure */
1047 lp = netdev_priv(ndev);
1048 lp->ndev = ndev;
1049 lp->dev = &op->dev;
1050 lp->options = XTE_OPTION_DEFAULTS;
1051 spin_lock_init(&lp->rx_lock);
1052 mutex_init(&lp->indirect_mutex);
1053
1054 /* map device registers */
1055 lp->regs = of_iomap(op->dev.of_node, 0);
1056 if (!lp->regs) {
1057 dev_err(&op->dev, "could not map temac regs.\n");
1058 goto nodev;
1059 }
1060
1061 /* Setup checksum offload, but default to off if not specified */
1062 lp->temac_features = 0;
1063 p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,txcsum", NULL);
1064 if (p && be32_to_cpu(*p)) {
1065 lp->temac_features |= TEMAC_FEATURE_TX_CSUM;
1066 /* Can checksum TCP/UDP over IPv4. */
1067 ndev->features |= NETIF_F_IP_CSUM;
1068 }
1069 p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,rxcsum", NULL);
1070 if (p && be32_to_cpu(*p))
1071 lp->temac_features |= TEMAC_FEATURE_RX_CSUM;
1072
1073 /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */
1074 np = of_parse_phandle(op->dev.of_node, "llink-connected", 0);
1075 if (!np) {
1076 dev_err(&op->dev, "could not find DMA node\n");
1077 goto err_iounmap;
1078 }
1079
1080 /* Setup the DMA register accesses, could be DCR or memory mapped */
1081 if (temac_dcr_setup(lp, op, np)) {
1082
1083 /* no DCR in the device tree, try non-DCR */
1084 lp->sdma_regs = of_iomap(np, 0);
1085 if (lp->sdma_regs) {
1086 lp->dma_in = temac_dma_in32;
1087 lp->dma_out = temac_dma_out32;
1088 dev_dbg(&op->dev, "MEM base: %p\n", lp->sdma_regs);
1089 } else {
1090 dev_err(&op->dev, "unable to map DMA registers\n");
1091 of_node_put(np);
1092 goto err_iounmap;
1093 }
1094 }
1095
1096 lp->rx_irq = irq_of_parse_and_map(np, 0);
1097 lp->tx_irq = irq_of_parse_and_map(np, 1);
1098
1099 of_node_put(np); /* Finished with the DMA node; drop the reference */
1100
1101 if (!lp->rx_irq || !lp->tx_irq) {
1102 dev_err(&op->dev, "could not determine irqs\n");
1103 rc = -ENOMEM;
1104 goto err_iounmap_2;
1105 }
1106
1107
1108 /* Retrieve the MAC address */
1109 addr = of_get_property(op->dev.of_node, "local-mac-address", &size);
1110 if ((!addr) || (size != 6)) {
1111 dev_err(&op->dev, "could not find MAC address\n");
1112 rc = -ENODEV;
1113 goto err_iounmap_2;
1114 }
1115 temac_set_mac_address(ndev, (void *)addr);
1116
1117 rc = temac_mdio_setup(lp, op->dev.of_node);
1118 if (rc)
1119 dev_warn(&op->dev, "error registering MDIO bus\n");
1120
1121 lp->phy_node = of_parse_phandle(op->dev.of_node, "phy-handle", 0);
1122 if (lp->phy_node)
1123 dev_dbg(lp->dev, "using PHY node %s (%p)\n", np->full_name, np);
1124
1125 /* Add the device attributes */
1126 rc = sysfs_create_group(&lp->dev->kobj, &temac_attr_group);
1127 if (rc) {
1128 dev_err(lp->dev, "Error creating sysfs files\n");
1129 goto err_iounmap_2;
1130 }
1131
1132 rc = register_netdev(lp->ndev);
1133 if (rc) {
1134 dev_err(lp->dev, "register_netdev() error (%i)\n", rc);
1135 goto err_register_ndev;
1136 }
1137
1138 return 0;
1139
1140 err_register_ndev:
1141 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1142 err_iounmap_2:
1143 if (lp->sdma_regs)
1144 iounmap(lp->sdma_regs);
1145 err_iounmap:
1146 iounmap(lp->regs);
1147 nodev:
1148 free_netdev(ndev);
1149 ndev = NULL;
1150 return rc;
1151 }
1152
1153 static int __devexit temac_of_remove(struct platform_device *op)
1154 {
1155 struct net_device *ndev = dev_get_drvdata(&op->dev);
1156 struct temac_local *lp = netdev_priv(ndev);
1157
1158 temac_mdio_teardown(lp);
1159 unregister_netdev(ndev);
1160 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1161 if (lp->phy_node)
1162 of_node_put(lp->phy_node);
1163 lp->phy_node = NULL;
1164 dev_set_drvdata(&op->dev, NULL);
1165 iounmap(lp->regs);
1166 if (lp->sdma_regs)
1167 iounmap(lp->sdma_regs);
1168 free_netdev(ndev);
1169 return 0;
1170 }
1171
1172 static struct of_device_id temac_of_match[] __devinitdata = {
1173 { .compatible = "xlnx,xps-ll-temac-1.01.b", },
1174 { .compatible = "xlnx,xps-ll-temac-2.00.a", },
1175 { .compatible = "xlnx,xps-ll-temac-2.02.a", },
1176 { .compatible = "xlnx,xps-ll-temac-2.03.a", },
1177 {},
1178 };
1179 MODULE_DEVICE_TABLE(of, temac_of_match);
1180
1181 static struct platform_driver temac_of_driver = {
1182 .probe = temac_of_probe,
1183 .remove = __devexit_p(temac_of_remove),
1184 .driver = {
1185 .owner = THIS_MODULE,
1186 .name = "xilinx_temac",
1187 .of_match_table = temac_of_match,
1188 },
1189 };
1190
1191 module_platform_driver(temac_of_driver);
1192
1193 MODULE_DESCRIPTION("Xilinx LL_TEMAC Ethernet driver");
1194 MODULE_AUTHOR("Yoshio Kashiwagi");
1195 MODULE_LICENSE("GPL");
Linux with added FPC-III support