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Linux 3.4.102
[linux/fpc-iii.git] / drivers / tty / serial / 8250 / 8250.c
blob5fe219142d41e1f50123f214b5db22d3d1fccc6b
1 /*
2 * Driver for 8250/16550-type serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * A note about mapbase / membase
14 *
15 * mapbase is the physical address of the IO port.
16 * membase is an 'ioremapped' cookie.
17 */
18
19 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
20 #define SUPPORT_SYSRQ
21 #endif
22
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/ioport.h>
26 #include <linux/init.h>
27 #include <linux/console.h>
28 #include <linux/sysrq.h>
29 #include <linux/delay.h>
30 #include <linux/platform_device.h>
31 #include <linux/tty.h>
32 #include <linux/ratelimit.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial_reg.h>
35 #include <linux/serial_core.h>
36 #include <linux/serial.h>
37 #include <linux/serial_8250.h>
38 #include <linux/nmi.h>
39 #include <linux/mutex.h>
40 #include <linux/slab.h>
41 #ifdef CONFIG_SPARC
42 #include <linux/sunserialcore.h>
43 #endif
44
45 #include <asm/io.h>
46 #include <asm/irq.h>
47
48 #include "8250.h"
49
50 /*
51 * Configuration:
52 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
53 * is unsafe when used on edge-triggered interrupts.
54 */
55 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
56
57 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
58
59 static struct uart_driver serial8250_reg;
60
61 static int serial_index(struct uart_port *port)
62 {
63 return (serial8250_reg.minor - 64) + port->line;
64 }
65
66 static unsigned int skip_txen_test; /* force skip of txen test at init time */
67
68 /*
69 * Debugging.
70 */
71 #if 0
72 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
73 #else
74 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
75 #endif
76
77 #if 0
78 #define DEBUG_INTR(fmt...) printk(fmt)
79 #else
80 #define DEBUG_INTR(fmt...) do { } while (0)
81 #endif
82
83 #define PASS_LIMIT 512
84
85 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
86
87
88 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
89 #define CONFIG_SERIAL_DETECT_IRQ 1
90 #endif
91 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
92 #define CONFIG_SERIAL_MANY_PORTS 1
93 #endif
94
95 /*
96 * HUB6 is always on. This will be removed once the header
97 * files have been cleaned.
98 */
99 #define CONFIG_HUB6 1
100
101 #include <asm/serial.h>
102 /*
103 * SERIAL_PORT_DFNS tells us about built-in ports that have no
104 * standard enumeration mechanism. Platforms that can find all
105 * serial ports via mechanisms like ACPI or PCI need not supply it.
106 */
107 #ifndef SERIAL_PORT_DFNS
108 #define SERIAL_PORT_DFNS
109 #endif
110
111 static const struct old_serial_port old_serial_port[] = {
112 SERIAL_PORT_DFNS /* defined in asm/serial.h */
113 };
114
115 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
116
117 #ifdef CONFIG_SERIAL_8250_RSA
118
119 #define PORT_RSA_MAX 4
120 static unsigned long probe_rsa[PORT_RSA_MAX];
121 static unsigned int probe_rsa_count;
122 #endif /* CONFIG_SERIAL_8250_RSA */
123
124 struct irq_info {
125 struct hlist_node node;
126 int irq;
127 spinlock_t lock; /* Protects list not the hash */
128 struct list_head *head;
129 };
130
131 #define NR_IRQ_HASH 32 /* Can be adjusted later */
132 static struct hlist_head irq_lists[NR_IRQ_HASH];
133 static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
134
135 /*
136 * Here we define the default xmit fifo size used for each type of UART.
137 */
138 static const struct serial8250_config uart_config[] = {
139 [PORT_UNKNOWN] = {
140 .name = "unknown",
141 .fifo_size = 1,
142 .tx_loadsz = 1,
143 },
144 [PORT_8250] = {
145 .name = "8250",
146 .fifo_size = 1,
147 .tx_loadsz = 1,
148 },
149 [PORT_16450] = {
150 .name = "16450",
151 .fifo_size = 1,
152 .tx_loadsz = 1,
153 },
154 [PORT_16550] = {
155 .name = "16550",
156 .fifo_size = 1,
157 .tx_loadsz = 1,
158 },
159 [PORT_16550A] = {
160 .name = "16550A",
161 .fifo_size = 16,
162 .tx_loadsz = 16,
163 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
164 .flags = UART_CAP_FIFO,
165 },
166 [PORT_CIRRUS] = {
167 .name = "Cirrus",
168 .fifo_size = 1,
169 .tx_loadsz = 1,
170 },
171 [PORT_16650] = {
172 .name = "ST16650",
173 .fifo_size = 1,
174 .tx_loadsz = 1,
175 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
176 },
177 [PORT_16650V2] = {
178 .name = "ST16650V2",
179 .fifo_size = 32,
180 .tx_loadsz = 16,
181 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
182 UART_FCR_T_TRIG_00,
183 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
184 },
185 [PORT_16750] = {
186 .name = "TI16750",
187 .fifo_size = 64,
188 .tx_loadsz = 64,
189 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
190 UART_FCR7_64BYTE,
191 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
192 },
193 [PORT_STARTECH] = {
194 .name = "Startech",
195 .fifo_size = 1,
196 .tx_loadsz = 1,
197 },
198 [PORT_16C950] = {
199 .name = "16C950/954",
200 .fifo_size = 128,
201 .tx_loadsz = 128,
202 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
203 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
204 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
205 },
206 [PORT_16654] = {
207 .name = "ST16654",
208 .fifo_size = 64,
209 .tx_loadsz = 32,
210 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
211 UART_FCR_T_TRIG_10,
212 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
213 },
214 [PORT_16850] = {
215 .name = "XR16850",
216 .fifo_size = 128,
217 .tx_loadsz = 128,
218 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
219 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
220 },
221 [PORT_RSA] = {
222 .name = "RSA",
223 .fifo_size = 2048,
224 .tx_loadsz = 2048,
225 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
226 .flags = UART_CAP_FIFO,
227 },
228 [PORT_NS16550A] = {
229 .name = "NS16550A",
230 .fifo_size = 16,
231 .tx_loadsz = 16,
232 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
233 .flags = UART_CAP_FIFO | UART_NATSEMI,
234 },
235 [PORT_XSCALE] = {
236 .name = "XScale",
237 .fifo_size = 32,
238 .tx_loadsz = 32,
239 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
240 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
241 },
242 [PORT_RM9000] = {
243 .name = "RM9000",
244 .fifo_size = 16,
245 .tx_loadsz = 16,
246 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
247 .flags = UART_CAP_FIFO,
248 },
249 [PORT_OCTEON] = {
250 .name = "OCTEON",
251 .fifo_size = 64,
252 .tx_loadsz = 64,
253 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
254 .flags = UART_CAP_FIFO,
255 },
256 [PORT_AR7] = {
257 .name = "AR7",
258 .fifo_size = 16,
259 .tx_loadsz = 16,
260 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
261 .flags = UART_CAP_FIFO | UART_CAP_AFE,
262 },
263 [PORT_U6_16550A] = {
264 .name = "U6_16550A",
265 .fifo_size = 64,
266 .tx_loadsz = 64,
267 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
268 .flags = UART_CAP_FIFO | UART_CAP_AFE,
269 },
270 [PORT_TEGRA] = {
271 .name = "Tegra",
272 .fifo_size = 32,
273 .tx_loadsz = 8,
274 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
275 UART_FCR_T_TRIG_01,
276 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
277 },
278 [PORT_XR17D15X] = {
279 .name = "XR17D15X",
280 .fifo_size = 64,
281 .tx_loadsz = 64,
282 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
283 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR,
284 },
285 [PORT_BRCM_TRUMANAGE] = {
286 .name = "TruManage",
287 .fifo_size = 1,
288 .tx_loadsz = 1024,
289 .flags = UART_CAP_HFIFO,
290 },
291 [PORT_ALTR_16550_F32] = {
292 .name = "Altera 16550 FIFO32",
293 .fifo_size = 32,
294 .tx_loadsz = 32,
295 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
296 .flags = UART_CAP_FIFO | UART_CAP_AFE,
297 },
298 [PORT_ALTR_16550_F64] = {
299 .name = "Altera 16550 FIFO64",
300 .fifo_size = 64,
301 .tx_loadsz = 64,
302 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
303 .flags = UART_CAP_FIFO | UART_CAP_AFE,
304 },
305 [PORT_ALTR_16550_F128] = {
306 .name = "Altera 16550 FIFO128",
307 .fifo_size = 128,
308 .tx_loadsz = 128,
309 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
310 .flags = UART_CAP_FIFO | UART_CAP_AFE,
311 },
312 };
313
314 #if defined(CONFIG_MIPS_ALCHEMY)
315
316 /* Au1x00 UART hardware has a weird register layout */
317 static const u8 au_io_in_map[] = {
318 [UART_RX] = 0,
319 [UART_IER] = 2,
320 [UART_IIR] = 3,
321 [UART_LCR] = 5,
322 [UART_MCR] = 6,
323 [UART_LSR] = 7,
324 [UART_MSR] = 8,
325 };
326
327 static const u8 au_io_out_map[] = {
328 [UART_TX] = 1,
329 [UART_IER] = 2,
330 [UART_FCR] = 4,
331 [UART_LCR] = 5,
332 [UART_MCR] = 6,
333 };
334
335 /* sane hardware needs no mapping */
336 static inline int map_8250_in_reg(struct uart_port *p, int offset)
337 {
338 if (p->iotype != UPIO_AU)
339 return offset;
340 return au_io_in_map[offset];
341 }
342
343 static inline int map_8250_out_reg(struct uart_port *p, int offset)
344 {
345 if (p->iotype != UPIO_AU)
346 return offset;
347 return au_io_out_map[offset];
348 }
349
350 #elif defined(CONFIG_SERIAL_8250_RM9K)
351
352 static const u8
353 regmap_in[8] = {
354 [UART_RX] = 0x00,
355 [UART_IER] = 0x0c,
356 [UART_IIR] = 0x14,
357 [UART_LCR] = 0x1c,
358 [UART_MCR] = 0x20,
359 [UART_LSR] = 0x24,
360 [UART_MSR] = 0x28,
361 [UART_SCR] = 0x2c
362 },
363 regmap_out[8] = {
364 [UART_TX] = 0x04,
365 [UART_IER] = 0x0c,
366 [UART_FCR] = 0x18,
367 [UART_LCR] = 0x1c,
368 [UART_MCR] = 0x20,
369 [UART_LSR] = 0x24,
370 [UART_MSR] = 0x28,
371 [UART_SCR] = 0x2c
372 };
373
374 static inline int map_8250_in_reg(struct uart_port *p, int offset)
375 {
376 if (p->iotype != UPIO_RM9000)
377 return offset;
378 return regmap_in[offset];
379 }
380
381 static inline int map_8250_out_reg(struct uart_port *p, int offset)
382 {
383 if (p->iotype != UPIO_RM9000)
384 return offset;
385 return regmap_out[offset];
386 }
387
388 #else
389
390 /* sane hardware needs no mapping */
391 #define map_8250_in_reg(up, offset) (offset)
392 #define map_8250_out_reg(up, offset) (offset)
393
394 #endif
395
396 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
397 {
398 offset = map_8250_in_reg(p, offset) << p->regshift;
399 outb(p->hub6 - 1 + offset, p->iobase);
400 return inb(p->iobase + 1);
401 }
402
403 static void hub6_serial_out(struct uart_port *p, int offset, int value)
404 {
405 offset = map_8250_out_reg(p, offset) << p->regshift;
406 outb(p->hub6 - 1 + offset, p->iobase);
407 outb(value, p->iobase + 1);
408 }
409
410 static unsigned int mem_serial_in(struct uart_port *p, int offset)
411 {
412 offset = map_8250_in_reg(p, offset) << p->regshift;
413 return readb(p->membase + offset);
414 }
415
416 static void mem_serial_out(struct uart_port *p, int offset, int value)
417 {
418 offset = map_8250_out_reg(p, offset) << p->regshift;
419 writeb(value, p->membase + offset);
420 }
421
422 static void mem32_serial_out(struct uart_port *p, int offset, int value)
423 {
424 offset = map_8250_out_reg(p, offset) << p->regshift;
425 writel(value, p->membase + offset);
426 }
427
428 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
429 {
430 offset = map_8250_in_reg(p, offset) << p->regshift;
431 return readl(p->membase + offset);
432 }
433
434 static unsigned int au_serial_in(struct uart_port *p, int offset)
435 {
436 offset = map_8250_in_reg(p, offset) << p->regshift;
437 return __raw_readl(p->membase + offset);
438 }
439
440 static void au_serial_out(struct uart_port *p, int offset, int value)
441 {
442 offset = map_8250_out_reg(p, offset) << p->regshift;
443 __raw_writel(value, p->membase + offset);
444 }
445
446 static unsigned int io_serial_in(struct uart_port *p, int offset)
447 {
448 offset = map_8250_in_reg(p, offset) << p->regshift;
449 return inb(p->iobase + offset);
450 }
451
452 static void io_serial_out(struct uart_port *p, int offset, int value)
453 {
454 offset = map_8250_out_reg(p, offset) << p->regshift;
455 outb(value, p->iobase + offset);
456 }
457
458 static int serial8250_default_handle_irq(struct uart_port *port);
459
460 static void set_io_from_upio(struct uart_port *p)
461 {
462 struct uart_8250_port *up =
463 container_of(p, struct uart_8250_port, port);
464 switch (p->iotype) {
465 case UPIO_HUB6:
466 p->serial_in = hub6_serial_in;
467 p->serial_out = hub6_serial_out;
468 break;
469
470 case UPIO_MEM:
471 p->serial_in = mem_serial_in;
472 p->serial_out = mem_serial_out;
473 break;
474
475 case UPIO_RM9000:
476 case UPIO_MEM32:
477 p->serial_in = mem32_serial_in;
478 p->serial_out = mem32_serial_out;
479 break;
480
481 case UPIO_AU:
482 p->serial_in = au_serial_in;
483 p->serial_out = au_serial_out;
484 break;
485
486 default:
487 p->serial_in = io_serial_in;
488 p->serial_out = io_serial_out;
489 break;
490 }
491 /* Remember loaded iotype */
492 up->cur_iotype = p->iotype;
493 p->handle_irq = serial8250_default_handle_irq;
494 }
495
496 static void
497 serial_port_out_sync(struct uart_port *p, int offset, int value)
498 {
499 switch (p->iotype) {
500 case UPIO_MEM:
501 case UPIO_MEM32:
502 case UPIO_AU:
503 p->serial_out(p, offset, value);
504 p->serial_in(p, UART_LCR); /* safe, no side-effects */
505 break;
506 default:
507 p->serial_out(p, offset, value);
508 }
509 }
510
511 /* Uart divisor latch read */
512 static inline int _serial_dl_read(struct uart_8250_port *up)
513 {
514 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
515 }
516
517 /* Uart divisor latch write */
518 static inline void _serial_dl_write(struct uart_8250_port *up, int value)
519 {
520 serial_out(up, UART_DLL, value & 0xff);
521 serial_out(up, UART_DLM, value >> 8 & 0xff);
522 }
523
524 #if defined(CONFIG_MIPS_ALCHEMY)
525 /* Au1x00 haven't got a standard divisor latch */
526 static int serial_dl_read(struct uart_8250_port *up)
527 {
528 if (up->port.iotype == UPIO_AU)
529 return __raw_readl(up->port.membase + 0x28);
530 else
531 return _serial_dl_read(up);
532 }
533
534 static void serial_dl_write(struct uart_8250_port *up, int value)
535 {
536 if (up->port.iotype == UPIO_AU)
537 __raw_writel(value, up->port.membase + 0x28);
538 else
539 _serial_dl_write(up, value);
540 }
541 #elif defined(CONFIG_SERIAL_8250_RM9K)
542 static int serial_dl_read(struct uart_8250_port *up)
543 {
544 return (up->port.iotype == UPIO_RM9000) ?
545 (((__raw_readl(up->port.membase + 0x10) << 8) |
546 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
547 _serial_dl_read(up);
548 }
549
550 static void serial_dl_write(struct uart_8250_port *up, int value)
551 {
552 if (up->port.iotype == UPIO_RM9000) {
553 __raw_writel(value, up->port.membase + 0x08);
554 __raw_writel(value >> 8, up->port.membase + 0x10);
555 } else {
556 _serial_dl_write(up, value);
557 }
558 }
559 #else
560 #define serial_dl_read(up) _serial_dl_read(up)
561 #define serial_dl_write(up, value) _serial_dl_write(up, value)
562 #endif
563
564 /*
565 * For the 16C950
566 */
567 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
568 {
569 serial_out(up, UART_SCR, offset);
570 serial_out(up, UART_ICR, value);
571 }
572
573 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
574 {
575 unsigned int value;
576
577 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
578 serial_out(up, UART_SCR, offset);
579 value = serial_in(up, UART_ICR);
580 serial_icr_write(up, UART_ACR, up->acr);
581
582 return value;
583 }
584
585 /*
586 * FIFO support.
587 */
588 static void serial8250_clear_fifos(struct uart_8250_port *p)
589 {
590 if (p->capabilities & UART_CAP_FIFO) {
591 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
592 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
593 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
594 serial_out(p, UART_FCR, 0);
595 }
596 }
597
598 /*
599 * IER sleep support. UARTs which have EFRs need the "extended
600 * capability" bit enabled. Note that on XR16C850s, we need to
601 * reset LCR to write to IER.
602 */
603 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
604 {
605 if (p->capabilities & UART_CAP_SLEEP) {
606 if (p->capabilities & UART_CAP_EFR) {
607 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
608 serial_out(p, UART_EFR, UART_EFR_ECB);
609 serial_out(p, UART_LCR, 0);
610 }
611 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
612 if (p->capabilities & UART_CAP_EFR) {
613 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
614 serial_out(p, UART_EFR, 0);
615 serial_out(p, UART_LCR, 0);
616 }
617 }
618 }
619
620 #ifdef CONFIG_SERIAL_8250_RSA
621 /*
622 * Attempts to turn on the RSA FIFO. Returns zero on failure.
623 * We set the port uart clock rate if we succeed.
624 */
625 static int __enable_rsa(struct uart_8250_port *up)
626 {
627 unsigned char mode;
628 int result;
629
630 mode = serial_in(up, UART_RSA_MSR);
631 result = mode & UART_RSA_MSR_FIFO;
632
633 if (!result) {
634 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
635 mode = serial_in(up, UART_RSA_MSR);
636 result = mode & UART_RSA_MSR_FIFO;
637 }
638
639 if (result)
640 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
641
642 return result;
643 }
644
645 static void enable_rsa(struct uart_8250_port *up)
646 {
647 if (up->port.type == PORT_RSA) {
648 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
649 spin_lock_irq(&up->port.lock);
650 __enable_rsa(up);
651 spin_unlock_irq(&up->port.lock);
652 }
653 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
654 serial_out(up, UART_RSA_FRR, 0);
655 }
656 }
657
658 /*
659 * Attempts to turn off the RSA FIFO. Returns zero on failure.
660 * It is unknown why interrupts were disabled in here. However,
661 * the caller is expected to preserve this behaviour by grabbing
662 * the spinlock before calling this function.
663 */
664 static void disable_rsa(struct uart_8250_port *up)
665 {
666 unsigned char mode;
667 int result;
668
669 if (up->port.type == PORT_RSA &&
670 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
671 spin_lock_irq(&up->port.lock);
672
673 mode = serial_in(up, UART_RSA_MSR);
674 result = !(mode & UART_RSA_MSR_FIFO);
675
676 if (!result) {
677 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
678 mode = serial_in(up, UART_RSA_MSR);
679 result = !(mode & UART_RSA_MSR_FIFO);
680 }
681
682 if (result)
683 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
684 spin_unlock_irq(&up->port.lock);
685 }
686 }
687 #endif /* CONFIG_SERIAL_8250_RSA */
688
689 /*
690 * This is a quickie test to see how big the FIFO is.
691 * It doesn't work at all the time, more's the pity.
692 */
693 static int size_fifo(struct uart_8250_port *up)
694 {
695 unsigned char old_fcr, old_mcr, old_lcr;
696 unsigned short old_dl;
697 int count;
698
699 old_lcr = serial_in(up, UART_LCR);
700 serial_out(up, UART_LCR, 0);
701 old_fcr = serial_in(up, UART_FCR);
702 old_mcr = serial_in(up, UART_MCR);
703 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
704 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
705 serial_out(up, UART_MCR, UART_MCR_LOOP);
706 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
707 old_dl = serial_dl_read(up);
708 serial_dl_write(up, 0x0001);
709 serial_out(up, UART_LCR, 0x03);
710 for (count = 0; count < 256; count++)
711 serial_out(up, UART_TX, count);
712 mdelay(20);/* FIXME - schedule_timeout */
713 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
714 (count < 256); count++)
715 serial_in(up, UART_RX);
716 serial_out(up, UART_FCR, old_fcr);
717 serial_out(up, UART_MCR, old_mcr);
718 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
719 serial_dl_write(up, old_dl);
720 serial_out(up, UART_LCR, old_lcr);
721
722 return count;
723 }
724
725 /*
726 * Read UART ID using the divisor method - set DLL and DLM to zero
727 * and the revision will be in DLL and device type in DLM. We
728 * preserve the device state across this.
729 */
730 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
731 {
732 unsigned char old_dll, old_dlm, old_lcr;
733 unsigned int id;
734
735 old_lcr = serial_in(p, UART_LCR);
736 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
737
738 old_dll = serial_in(p, UART_DLL);
739 old_dlm = serial_in(p, UART_DLM);
740
741 serial_out(p, UART_DLL, 0);
742 serial_out(p, UART_DLM, 0);
743
744 id = serial_in(p, UART_DLL) | serial_in(p, UART_DLM) << 8;
745
746 serial_out(p, UART_DLL, old_dll);
747 serial_out(p, UART_DLM, old_dlm);
748 serial_out(p, UART_LCR, old_lcr);
749
750 return id;
751 }
752
753 /*
754 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
755 * When this function is called we know it is at least a StarTech
756 * 16650 V2, but it might be one of several StarTech UARTs, or one of
757 * its clones. (We treat the broken original StarTech 16650 V1 as a
758 * 16550, and why not? Startech doesn't seem to even acknowledge its
759 * existence.)
760 *
761 * What evil have men's minds wrought...
762 */
763 static void autoconfig_has_efr(struct uart_8250_port *up)
764 {
765 unsigned int id1, id2, id3, rev;
766
767 /*
768 * Everything with an EFR has SLEEP
769 */
770 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
771
772 /*
773 * First we check to see if it's an Oxford Semiconductor UART.
774 *
775 * If we have to do this here because some non-National
776 * Semiconductor clone chips lock up if you try writing to the
777 * LSR register (which serial_icr_read does)
778 */
779
780 /*
781 * Check for Oxford Semiconductor 16C950.
782 *
783 * EFR [4] must be set else this test fails.
784 *
785 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
786 * claims that it's needed for 952 dual UART's (which are not
787 * recommended for new designs).
788 */
789 up->acr = 0;
790 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
791 serial_out(up, UART_EFR, UART_EFR_ECB);
792 serial_out(up, UART_LCR, 0x00);
793 id1 = serial_icr_read(up, UART_ID1);
794 id2 = serial_icr_read(up, UART_ID2);
795 id3 = serial_icr_read(up, UART_ID3);
796 rev = serial_icr_read(up, UART_REV);
797
798 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
799
800 if (id1 == 0x16 && id2 == 0xC9 &&
801 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
802 up->port.type = PORT_16C950;
803
804 /*
805 * Enable work around for the Oxford Semiconductor 952 rev B
806 * chip which causes it to seriously miscalculate baud rates
807 * when DLL is 0.
808 */
809 if (id3 == 0x52 && rev == 0x01)
810 up->bugs |= UART_BUG_QUOT;
811 return;
812 }
813
814 /*
815 * We check for a XR16C850 by setting DLL and DLM to 0, and then
816 * reading back DLL and DLM. The chip type depends on the DLM
817 * value read back:
818 * 0x10 - XR16C850 and the DLL contains the chip revision.
819 * 0x12 - XR16C2850.
820 * 0x14 - XR16C854.
821 */
822 id1 = autoconfig_read_divisor_id(up);
823 DEBUG_AUTOCONF("850id=%04x ", id1);
824
825 id2 = id1 >> 8;
826 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
827 up->port.type = PORT_16850;
828 return;
829 }
830
831 /*
832 * It wasn't an XR16C850.
833 *
834 * We distinguish between the '654 and the '650 by counting
835 * how many bytes are in the FIFO. I'm using this for now,
836 * since that's the technique that was sent to me in the
837 * serial driver update, but I'm not convinced this works.
838 * I've had problems doing this in the past. -TYT
839 */
840 if (size_fifo(up) == 64)
841 up->port.type = PORT_16654;
842 else
843 up->port.type = PORT_16650V2;
844 }
845
846 /*
847 * We detected a chip without a FIFO. Only two fall into
848 * this category - the original 8250 and the 16450. The
849 * 16450 has a scratch register (accessible with LCR=0)
850 */
851 static void autoconfig_8250(struct uart_8250_port *up)
852 {
853 unsigned char scratch, status1, status2;
854
855 up->port.type = PORT_8250;
856
857 scratch = serial_in(up, UART_SCR);
858 serial_out(up, UART_SCR, 0xa5);
859 status1 = serial_in(up, UART_SCR);
860 serial_out(up, UART_SCR, 0x5a);
861 status2 = serial_in(up, UART_SCR);
862 serial_out(up, UART_SCR, scratch);
863
864 if (status1 == 0xa5 && status2 == 0x5a)
865 up->port.type = PORT_16450;
866 }
867
868 static int broken_efr(struct uart_8250_port *up)
869 {
870 /*
871 * Exar ST16C2550 "A2" devices incorrectly detect as
872 * having an EFR, and report an ID of 0x0201. See
873 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
874 */
875 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
876 return 1;
877
878 return 0;
879 }
880
881 static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
882 {
883 unsigned char status;
884
885 status = serial_in(up, 0x04); /* EXCR2 */
886 #define PRESL(x) ((x) & 0x30)
887 if (PRESL(status) == 0x10) {
888 /* already in high speed mode */
889 return 0;
890 } else {
891 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
892 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
893 serial_out(up, 0x04, status);
894 }
895 return 1;
896 }
897
898 /*
899 * We know that the chip has FIFOs. Does it have an EFR? The
900 * EFR is located in the same register position as the IIR and
901 * we know the top two bits of the IIR are currently set. The
902 * EFR should contain zero. Try to read the EFR.
903 */
904 static void autoconfig_16550a(struct uart_8250_port *up)
905 {
906 unsigned char status1, status2;
907 unsigned int iersave;
908
909 up->port.type = PORT_16550A;
910 up->capabilities |= UART_CAP_FIFO;
911
912 /*
913 * Check for presence of the EFR when DLAB is set.
914 * Only ST16C650V1 UARTs pass this test.
915 */
916 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
917 if (serial_in(up, UART_EFR) == 0) {
918 serial_out(up, UART_EFR, 0xA8);
919 if (serial_in(up, UART_EFR) != 0) {
920 DEBUG_AUTOCONF("EFRv1 ");
921 up->port.type = PORT_16650;
922 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
923 } else {
924 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
925 }
926 serial_out(up, UART_EFR, 0);
927 return;
928 }
929
930 /*
931 * Maybe it requires 0xbf to be written to the LCR.
932 * (other ST16C650V2 UARTs, TI16C752A, etc)
933 */
934 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
935 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
936 DEBUG_AUTOCONF("EFRv2 ");
937 autoconfig_has_efr(up);
938 return;
939 }
940
941 /*
942 * Check for a National Semiconductor SuperIO chip.
943 * Attempt to switch to bank 2, read the value of the LOOP bit
944 * from EXCR1. Switch back to bank 0, change it in MCR. Then
945 * switch back to bank 2, read it from EXCR1 again and check
946 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
947 */
948 serial_out(up, UART_LCR, 0);
949 status1 = serial_in(up, UART_MCR);
950 serial_out(up, UART_LCR, 0xE0);
951 status2 = serial_in(up, 0x02); /* EXCR1 */
952
953 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
954 serial_out(up, UART_LCR, 0);
955 serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP);
956 serial_out(up, UART_LCR, 0xE0);
957 status2 = serial_in(up, 0x02); /* EXCR1 */
958 serial_out(up, UART_LCR, 0);
959 serial_out(up, UART_MCR, status1);
960
961 if ((status2 ^ status1) & UART_MCR_LOOP) {
962 unsigned short quot;
963
964 serial_out(up, UART_LCR, 0xE0);
965
966 quot = serial_dl_read(up);
967 quot <<= 3;
968
969 if (ns16550a_goto_highspeed(up))
970 serial_dl_write(up, quot);
971
972 serial_out(up, UART_LCR, 0);
973
974 up->port.uartclk = 921600*16;
975 up->port.type = PORT_NS16550A;
976 up->capabilities |= UART_NATSEMI;
977 return;
978 }
979 }
980
981 /*
982 * No EFR. Try to detect a TI16750, which only sets bit 5 of
983 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
984 * Try setting it with and without DLAB set. Cheap clones
985 * set bit 5 without DLAB set.
986 */
987 serial_out(up, UART_LCR, 0);
988 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
989 status1 = serial_in(up, UART_IIR) >> 5;
990 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
991 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
992 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
993 status2 = serial_in(up, UART_IIR) >> 5;
994 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
995 serial_out(up, UART_LCR, 0);
996
997 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
998
999 if (status1 == 6 && status2 == 7) {
1000 up->port.type = PORT_16750;
1001 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1002 return;
1003 }
1004
1005 /*
1006 * Try writing and reading the UART_IER_UUE bit (b6).
1007 * If it works, this is probably one of the Xscale platform's
1008 * internal UARTs.
1009 * We're going to explicitly set the UUE bit to 0 before
1010 * trying to write and read a 1 just to make sure it's not
1011 * already a 1 and maybe locked there before we even start start.
1012 */
1013 iersave = serial_in(up, UART_IER);
1014 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1015 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1016 /*
1017 * OK it's in a known zero state, try writing and reading
1018 * without disturbing the current state of the other bits.
1019 */
1020 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1021 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1022 /*
1023 * It's an Xscale.
1024 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1025 */
1026 DEBUG_AUTOCONF("Xscale ");
1027 up->port.type = PORT_XSCALE;
1028 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1029 return;
1030 }
1031 } else {
1032 /*
1033 * If we got here we couldn't force the IER_UUE bit to 0.
1034 * Log it and continue.
1035 */
1036 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1037 }
1038 serial_out(up, UART_IER, iersave);
1039
1040 /*
1041 * Exar uarts have EFR in a weird location
1042 */
1043 if (up->port.flags & UPF_EXAR_EFR) {
1044 up->port.type = PORT_XR17D15X;
1045 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR;
1046 }
1047
1048 /*
1049 * We distinguish between 16550A and U6 16550A by counting
1050 * how many bytes are in the FIFO.
1051 */
1052 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1053 up->port.type = PORT_U6_16550A;
1054 up->capabilities |= UART_CAP_AFE;
1055 }
1056 }
1057
1058 /*
1059 * This routine is called by rs_init() to initialize a specific serial
1060 * port. It determines what type of UART chip this serial port is
1061 * using: 8250, 16450, 16550, 16550A. The important question is
1062 * whether or not this UART is a 16550A or not, since this will
1063 * determine whether or not we can use its FIFO features or not.
1064 */
1065 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1066 {
1067 unsigned char status1, scratch, scratch2, scratch3;
1068 unsigned char save_lcr, save_mcr;
1069 struct uart_port *port = &up->port;
1070 unsigned long flags;
1071
1072 if (!port->iobase && !port->mapbase && !port->membase)
1073 return;
1074
1075 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1076 serial_index(port), port->iobase, port->membase);
1077
1078 /*
1079 * We really do need global IRQs disabled here - we're going to
1080 * be frobbing the chips IRQ enable register to see if it exists.
1081 */
1082 spin_lock_irqsave(&port->lock, flags);
1083
1084 up->capabilities = 0;
1085 up->bugs = 0;
1086
1087 if (!(port->flags & UPF_BUGGY_UART)) {
1088 /*
1089 * Do a simple existence test first; if we fail this,
1090 * there's no point trying anything else.
1091 *
1092 * 0x80 is used as a nonsense port to prevent against
1093 * false positives due to ISA bus float. The
1094 * assumption is that 0x80 is a non-existent port;
1095 * which should be safe since include/asm/io.h also
1096 * makes this assumption.
1097 *
1098 * Note: this is safe as long as MCR bit 4 is clear
1099 * and the device is in "PC" mode.
1100 */
1101 scratch = serial_in(up, UART_IER);
1102 serial_out(up, UART_IER, 0);
1103 #ifdef __i386__
1104 outb(0xff, 0x080);
1105 #endif
1106 /*
1107 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1108 * 16C754B) allow only to modify them if an EFR bit is set.
1109 */
1110 scratch2 = serial_in(up, UART_IER) & 0x0f;
1111 serial_out(up, UART_IER, 0x0F);
1112 #ifdef __i386__
1113 outb(0, 0x080);
1114 #endif
1115 scratch3 = serial_in(up, UART_IER) & 0x0f;
1116 serial_out(up, UART_IER, scratch);
1117 if (scratch2 != 0 || scratch3 != 0x0F) {
1118 /*
1119 * We failed; there's nothing here
1120 */
1121 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1122 scratch2, scratch3);
1123 goto out;
1124 }
1125 }
1126
1127 save_mcr = serial_in(up, UART_MCR);
1128 save_lcr = serial_in(up, UART_LCR);
1129
1130 /*
1131 * Check to see if a UART is really there. Certain broken
1132 * internal modems based on the Rockwell chipset fail this
1133 * test, because they apparently don't implement the loopback
1134 * test mode. So this test is skipped on the COM 1 through
1135 * COM 4 ports. This *should* be safe, since no board
1136 * manufacturer would be stupid enough to design a board
1137 * that conflicts with COM 1-4 --- we hope!
1138 */
1139 if (!(port->flags & UPF_SKIP_TEST)) {
1140 serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1141 status1 = serial_in(up, UART_MSR) & 0xF0;
1142 serial_out(up, UART_MCR, save_mcr);
1143 if (status1 != 0x90) {
1144 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1145 status1);
1146 goto out;
1147 }
1148 }
1149
1150 /*
1151 * We're pretty sure there's a port here. Lets find out what
1152 * type of port it is. The IIR top two bits allows us to find
1153 * out if it's 8250 or 16450, 16550, 16550A or later. This
1154 * determines what we test for next.
1155 *
1156 * We also initialise the EFR (if any) to zero for later. The
1157 * EFR occupies the same register location as the FCR and IIR.
1158 */
1159 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1160 serial_out(up, UART_EFR, 0);
1161 serial_out(up, UART_LCR, 0);
1162
1163 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1164 scratch = serial_in(up, UART_IIR) >> 6;
1165
1166 DEBUG_AUTOCONF("iir=%d ", scratch);
1167
1168 switch (scratch) {
1169 case 0:
1170 autoconfig_8250(up);
1171 break;
1172 case 1:
1173 port->type = PORT_UNKNOWN;
1174 break;
1175 case 2:
1176 port->type = PORT_16550;
1177 break;
1178 case 3:
1179 autoconfig_16550a(up);
1180 break;
1181 }
1182
1183 #ifdef CONFIG_SERIAL_8250_RSA
1184 /*
1185 * Only probe for RSA ports if we got the region.
1186 */
1187 if (port->type == PORT_16550A && probeflags & PROBE_RSA) {
1188 int i;
1189
1190 for (i = 0 ; i < probe_rsa_count; ++i) {
1191 if (probe_rsa[i] == port->iobase && __enable_rsa(up)) {
1192 port->type = PORT_RSA;
1193 break;
1194 }
1195 }
1196 }
1197 #endif
1198
1199 serial_out(up, UART_LCR, save_lcr);
1200
1201 if (up->capabilities != uart_config[port->type].flags) {
1202 printk(KERN_WARNING
1203 "ttyS%d: detected caps %08x should be %08x\n",
1204 serial_index(port), up->capabilities,
1205 uart_config[port->type].flags);
1206 }
1207
1208 port->fifosize = uart_config[up->port.type].fifo_size;
1209 up->capabilities = uart_config[port->type].flags;
1210 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1211
1212 if (port->type == PORT_UNKNOWN)
1213 goto out;
1214
1215 /*
1216 * Reset the UART.
1217 */
1218 #ifdef CONFIG_SERIAL_8250_RSA
1219 if (port->type == PORT_RSA)
1220 serial_out(up, UART_RSA_FRR, 0);
1221 #endif
1222 serial_out(up, UART_MCR, save_mcr);
1223 serial8250_clear_fifos(up);
1224 serial_in(up, UART_RX);
1225 if (up->capabilities & UART_CAP_UUE)
1226 serial_out(up, UART_IER, UART_IER_UUE);
1227 else
1228 serial_out(up, UART_IER, 0);
1229
1230 out:
1231 spin_unlock_irqrestore(&port->lock, flags);
1232 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1233 }
1234
1235 static void autoconfig_irq(struct uart_8250_port *up)
1236 {
1237 struct uart_port *port = &up->port;
1238 unsigned char save_mcr, save_ier;
1239 unsigned char save_ICP = 0;
1240 unsigned int ICP = 0;
1241 unsigned long irqs;
1242 int irq;
1243
1244 if (port->flags & UPF_FOURPORT) {
1245 ICP = (port->iobase & 0xfe0) | 0x1f;
1246 save_ICP = inb_p(ICP);
1247 outb_p(0x80, ICP);
1248 inb_p(ICP);
1249 }
1250
1251 /* forget possible initially masked and pending IRQ */
1252 probe_irq_off(probe_irq_on());
1253 save_mcr = serial_in(up, UART_MCR);
1254 save_ier = serial_in(up, UART_IER);
1255 serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1256
1257 irqs = probe_irq_on();
1258 serial_out(up, UART_MCR, 0);
1259 udelay(10);
1260 if (port->flags & UPF_FOURPORT) {
1261 serial_out(up, UART_MCR,
1262 UART_MCR_DTR | UART_MCR_RTS);
1263 } else {
1264 serial_out(up, UART_MCR,
1265 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1266 }
1267 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1268 serial_in(up, UART_LSR);
1269 serial_in(up, UART_RX);
1270 serial_in(up, UART_IIR);
1271 serial_in(up, UART_MSR);
1272 serial_out(up, UART_TX, 0xFF);
1273 udelay(20);
1274 irq = probe_irq_off(irqs);
1275
1276 serial_out(up, UART_MCR, save_mcr);
1277 serial_out(up, UART_IER, save_ier);
1278
1279 if (port->flags & UPF_FOURPORT)
1280 outb_p(save_ICP, ICP);
1281
1282 port->irq = (irq > 0) ? irq : 0;
1283 }
1284
1285 static inline void __stop_tx(struct uart_8250_port *p)
1286 {
1287 if (p->ier & UART_IER_THRI) {
1288 p->ier &= ~UART_IER_THRI;
1289 serial_out(p, UART_IER, p->ier);
1290 }
1291 }
1292
1293 static void serial8250_stop_tx(struct uart_port *port)
1294 {
1295 struct uart_8250_port *up =
1296 container_of(port, struct uart_8250_port, port);
1297
1298 __stop_tx(up);
1299
1300 /*
1301 * We really want to stop the transmitter from sending.
1302 */
1303 if (port->type == PORT_16C950) {
1304 up->acr |= UART_ACR_TXDIS;
1305 serial_icr_write(up, UART_ACR, up->acr);
1306 }
1307 }
1308
1309 static void serial8250_start_tx(struct uart_port *port)
1310 {
1311 struct uart_8250_port *up =
1312 container_of(port, struct uart_8250_port, port);
1313
1314 if (!(up->ier & UART_IER_THRI)) {
1315 up->ier |= UART_IER_THRI;
1316 serial_port_out(port, UART_IER, up->ier);
1317
1318 if (up->bugs & UART_BUG_TXEN) {
1319 unsigned char lsr;
1320 lsr = serial_in(up, UART_LSR);
1321 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1322 if ((port->type == PORT_RM9000) ?
1323 (lsr & UART_LSR_THRE) :
1324 (lsr & UART_LSR_TEMT))
1325 serial8250_tx_chars(up);
1326 }
1327 }
1328
1329 /*
1330 * Re-enable the transmitter if we disabled it.
1331 */
1332 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1333 up->acr &= ~UART_ACR_TXDIS;
1334 serial_icr_write(up, UART_ACR, up->acr);
1335 }
1336 }
1337
1338 static void serial8250_stop_rx(struct uart_port *port)
1339 {
1340 struct uart_8250_port *up =
1341 container_of(port, struct uart_8250_port, port);
1342
1343 up->ier &= ~UART_IER_RLSI;
1344 up->port.read_status_mask &= ~UART_LSR_DR;
1345 serial_port_out(port, UART_IER, up->ier);
1346 }
1347
1348 static void serial8250_enable_ms(struct uart_port *port)
1349 {
1350 struct uart_8250_port *up =
1351 container_of(port, struct uart_8250_port, port);
1352
1353 /* no MSR capabilities */
1354 if (up->bugs & UART_BUG_NOMSR)
1355 return;
1356
1357 up->ier |= UART_IER_MSI;
1358 serial_port_out(port, UART_IER, up->ier);
1359 }
1360
1361 /*
1362 * Clear the Tegra rx fifo after a break
1363 *
1364 * FIXME: This needs to become a port specific callback once we have a
1365 * framework for this
1366 */
1367 static void clear_rx_fifo(struct uart_8250_port *up)
1368 {
1369 unsigned int status, tmout = 10000;
1370 do {
1371 status = serial_in(up, UART_LSR);
1372 if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))
1373 status = serial_in(up, UART_RX);
1374 else
1375 break;
1376 if (--tmout == 0)
1377 break;
1378 udelay(1);
1379 } while (1);
1380 }
1381
1382 /*
1383 * serial8250_rx_chars: processes according to the passed in LSR
1384 * value, and returns the remaining LSR bits not handled
1385 * by this Rx routine.
1386 */
1387 unsigned char
1388 serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1389 {
1390 struct uart_port *port = &up->port;
1391 struct tty_struct *tty = port->state->port.tty;
1392 unsigned char ch;
1393 int max_count = 256;
1394 char flag;
1395
1396 do {
1397 if (likely(lsr & UART_LSR_DR))
1398 ch = serial_in(up, UART_RX);
1399 else
1400 /*
1401 * Intel 82571 has a Serial Over Lan device that will
1402 * set UART_LSR_BI without setting UART_LSR_DR when
1403 * it receives a break. To avoid reading from the
1404 * receive buffer without UART_LSR_DR bit set, we
1405 * just force the read character to be 0
1406 */
1407 ch = 0;
1408
1409 flag = TTY_NORMAL;
1410 port->icount.rx++;
1411
1412 lsr |= up->lsr_saved_flags;
1413 up->lsr_saved_flags = 0;
1414
1415 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1416 /*
1417 * For statistics only
1418 */
1419 if (lsr & UART_LSR_BI) {
1420 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1421 port->icount.brk++;
1422 /*
1423 * If tegra port then clear the rx fifo to
1424 * accept another break/character.
1425 */
1426 if (port->type == PORT_TEGRA)
1427 clear_rx_fifo(up);
1428
1429 /*
1430 * We do the SysRQ and SAK checking
1431 * here because otherwise the break
1432 * may get masked by ignore_status_mask
1433 * or read_status_mask.
1434 */
1435 if (uart_handle_break(port))
1436 goto ignore_char;
1437 } else if (lsr & UART_LSR_PE)
1438 port->icount.parity++;
1439 else if (lsr & UART_LSR_FE)
1440 port->icount.frame++;
1441 if (lsr & UART_LSR_OE)
1442 port->icount.overrun++;
1443
1444 /*
1445 * Mask off conditions which should be ignored.
1446 */
1447 lsr &= port->read_status_mask;
1448
1449 if (lsr & UART_LSR_BI) {
1450 DEBUG_INTR("handling break....");
1451 flag = TTY_BREAK;
1452 } else if (lsr & UART_LSR_PE)
1453 flag = TTY_PARITY;
1454 else if (lsr & UART_LSR_FE)
1455 flag = TTY_FRAME;
1456 }
1457 if (uart_handle_sysrq_char(port, ch))
1458 goto ignore_char;
1459
1460 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1461
1462 ignore_char:
1463 lsr = serial_in(up, UART_LSR);
1464 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1465 spin_unlock(&port->lock);
1466 tty_flip_buffer_push(tty);
1467 spin_lock(&port->lock);
1468 return lsr;
1469 }
1470 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1471
1472 void serial8250_tx_chars(struct uart_8250_port *up)
1473 {
1474 struct uart_port *port = &up->port;
1475 struct circ_buf *xmit = &port->state->xmit;
1476 int count;
1477
1478 if (port->x_char) {
1479 serial_out(up, UART_TX, port->x_char);
1480 port->icount.tx++;
1481 port->x_char = 0;
1482 return;
1483 }
1484 if (uart_tx_stopped(port)) {
1485 serial8250_stop_tx(port);
1486 return;
1487 }
1488 if (uart_circ_empty(xmit)) {
1489 __stop_tx(up);
1490 return;
1491 }
1492
1493 count = up->tx_loadsz;
1494 do {
1495 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1496 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1497 port->icount.tx++;
1498 if (uart_circ_empty(xmit))
1499 break;
1500 if (up->capabilities & UART_CAP_HFIFO) {
1501 if ((serial_port_in(port, UART_LSR) & BOTH_EMPTY) !=
1502 BOTH_EMPTY)
1503 break;
1504 }
1505 } while (--count > 0);
1506
1507 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1508 uart_write_wakeup(port);
1509
1510 DEBUG_INTR("THRE...");
1511
1512 if (uart_circ_empty(xmit))
1513 __stop_tx(up);
1514 }
1515 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1516
1517 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1518 {
1519 struct uart_port *port = &up->port;
1520 unsigned int status = serial_in(up, UART_MSR);
1521
1522 status |= up->msr_saved_flags;
1523 up->msr_saved_flags = 0;
1524 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1525 port->state != NULL) {
1526 if (status & UART_MSR_TERI)
1527 port->icount.rng++;
1528 if (status & UART_MSR_DDSR)
1529 port->icount.dsr++;
1530 if (status & UART_MSR_DDCD)
1531 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1532 if (status & UART_MSR_DCTS)
1533 uart_handle_cts_change(port, status & UART_MSR_CTS);
1534
1535 wake_up_interruptible(&port->state->port.delta_msr_wait);
1536 }
1537
1538 return status;
1539 }
1540 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1541
1542 /*
1543 * This handles the interrupt from one port.
1544 */
1545 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1546 {
1547 unsigned char status;
1548 unsigned long flags;
1549 struct uart_8250_port *up =
1550 container_of(port, struct uart_8250_port, port);
1551
1552 if (iir & UART_IIR_NO_INT)
1553 return 0;
1554
1555 spin_lock_irqsave(&port->lock, flags);
1556
1557 status = serial_port_in(port, UART_LSR);
1558
1559 DEBUG_INTR("status = %x...", status);
1560
1561 if (status & (UART_LSR_DR | UART_LSR_BI))
1562 status = serial8250_rx_chars(up, status);
1563 serial8250_modem_status(up);
1564 if (status & UART_LSR_THRE)
1565 serial8250_tx_chars(up);
1566
1567 spin_unlock_irqrestore(&port->lock, flags);
1568 return 1;
1569 }
1570 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1571
1572 static int serial8250_default_handle_irq(struct uart_port *port)
1573 {
1574 unsigned int iir = serial_port_in(port, UART_IIR);
1575
1576 return serial8250_handle_irq(port, iir);
1577 }
1578
1579 /*
1580 * This is the serial driver's interrupt routine.
1581 *
1582 * Arjan thinks the old way was overly complex, so it got simplified.
1583 * Alan disagrees, saying that need the complexity to handle the weird
1584 * nature of ISA shared interrupts. (This is a special exception.)
1585 *
1586 * In order to handle ISA shared interrupts properly, we need to check
1587 * that all ports have been serviced, and therefore the ISA interrupt
1588 * line has been de-asserted.
1589 *
1590 * This means we need to loop through all ports. checking that they
1591 * don't have an interrupt pending.
1592 */
1593 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1594 {
1595 struct irq_info *i = dev_id;
1596 struct list_head *l, *end = NULL;
1597 int pass_counter = 0, handled = 0;
1598
1599 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1600
1601 spin_lock(&i->lock);
1602
1603 l = i->head;
1604 do {
1605 struct uart_8250_port *up;
1606 struct uart_port *port;
1607
1608 up = list_entry(l, struct uart_8250_port, list);
1609 port = &up->port;
1610
1611 if (port->handle_irq(port)) {
1612 handled = 1;
1613 end = NULL;
1614 } else if (end == NULL)
1615 end = l;
1616
1617 l = l->next;
1618
1619 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1620 /* If we hit this, we're dead. */
1621 printk_ratelimited(KERN_ERR
1622 "serial8250: too much work for irq%d\n", irq);
1623 break;
1624 }
1625 } while (l != end);
1626
1627 spin_unlock(&i->lock);
1628
1629 DEBUG_INTR("end.\n");
1630
1631 return IRQ_RETVAL(handled);
1632 }
1633
1634 /*
1635 * To support ISA shared interrupts, we need to have one interrupt
1636 * handler that ensures that the IRQ line has been deasserted
1637 * before returning. Failing to do this will result in the IRQ
1638 * line being stuck active, and, since ISA irqs are edge triggered,
1639 * no more IRQs will be seen.
1640 */
1641 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1642 {
1643 spin_lock_irq(&i->lock);
1644
1645 if (!list_empty(i->head)) {
1646 if (i->head == &up->list)
1647 i->head = i->head->next;
1648 list_del(&up->list);
1649 } else {
1650 BUG_ON(i->head != &up->list);
1651 i->head = NULL;
1652 }
1653 spin_unlock_irq(&i->lock);
1654 /* List empty so throw away the hash node */
1655 if (i->head == NULL) {
1656 hlist_del(&i->node);
1657 kfree(i);
1658 }
1659 }
1660
1661 static int serial_link_irq_chain(struct uart_8250_port *up)
1662 {
1663 struct hlist_head *h;
1664 struct hlist_node *n;
1665 struct irq_info *i;
1666 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1667
1668 mutex_lock(&hash_mutex);
1669
1670 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1671
1672 hlist_for_each(n, h) {
1673 i = hlist_entry(n, struct irq_info, node);
1674 if (i->irq == up->port.irq)
1675 break;
1676 }
1677
1678 if (n == NULL) {
1679 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1680 if (i == NULL) {
1681 mutex_unlock(&hash_mutex);
1682 return -ENOMEM;
1683 }
1684 spin_lock_init(&i->lock);
1685 i->irq = up->port.irq;
1686 hlist_add_head(&i->node, h);
1687 }
1688 mutex_unlock(&hash_mutex);
1689
1690 spin_lock_irq(&i->lock);
1691
1692 if (i->head) {
1693 list_add(&up->list, i->head);
1694 spin_unlock_irq(&i->lock);
1695
1696 ret = 0;
1697 } else {
1698 INIT_LIST_HEAD(&up->list);
1699 i->head = &up->list;
1700 spin_unlock_irq(&i->lock);
1701 irq_flags |= up->port.irqflags;
1702 ret = request_irq(up->port.irq, serial8250_interrupt,
1703 irq_flags, "serial", i);
1704 if (ret < 0)
1705 serial_do_unlink(i, up);
1706 }
1707
1708 return ret;
1709 }
1710
1711 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1712 {
1713 struct irq_info *i;
1714 struct hlist_node *n;
1715 struct hlist_head *h;
1716
1717 mutex_lock(&hash_mutex);
1718
1719 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1720
1721 hlist_for_each(n, h) {
1722 i = hlist_entry(n, struct irq_info, node);
1723 if (i->irq == up->port.irq)
1724 break;
1725 }
1726
1727 BUG_ON(n == NULL);
1728 BUG_ON(i->head == NULL);
1729
1730 if (list_empty(i->head))
1731 free_irq(up->port.irq, i);
1732
1733 serial_do_unlink(i, up);
1734 mutex_unlock(&hash_mutex);
1735 }
1736
1737 /*
1738 * This function is used to handle ports that do not have an
1739 * interrupt. This doesn't work very well for 16450's, but gives
1740 * barely passable results for a 16550A. (Although at the expense
1741 * of much CPU overhead).
1742 */
1743 static void serial8250_timeout(unsigned long data)
1744 {
1745 struct uart_8250_port *up = (struct uart_8250_port *)data;
1746
1747 up->port.handle_irq(&up->port);
1748 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
1749 }
1750
1751 static void serial8250_backup_timeout(unsigned long data)
1752 {
1753 struct uart_8250_port *up = (struct uart_8250_port *)data;
1754 unsigned int iir, ier = 0, lsr;
1755 unsigned long flags;
1756
1757 spin_lock_irqsave(&up->port.lock, flags);
1758
1759 /*
1760 * Must disable interrupts or else we risk racing with the interrupt
1761 * based handler.
1762 */
1763 if (up->port.irq) {
1764 ier = serial_in(up, UART_IER);
1765 serial_out(up, UART_IER, 0);
1766 }
1767
1768 iir = serial_in(up, UART_IIR);
1769
1770 /*
1771 * This should be a safe test for anyone who doesn't trust the
1772 * IIR bits on their UART, but it's specifically designed for
1773 * the "Diva" UART used on the management processor on many HP
1774 * ia64 and parisc boxes.
1775 */
1776 lsr = serial_in(up, UART_LSR);
1777 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1778 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1779 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
1780 (lsr & UART_LSR_THRE)) {
1781 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1782 iir |= UART_IIR_THRI;
1783 }
1784
1785 if (!(iir & UART_IIR_NO_INT))
1786 serial8250_tx_chars(up);
1787
1788 if (up->port.irq)
1789 serial_out(up, UART_IER, ier);
1790
1791 spin_unlock_irqrestore(&up->port.lock, flags);
1792
1793 /* Standard timer interval plus 0.2s to keep the port running */
1794 mod_timer(&up->timer,
1795 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1796 }
1797
1798 static unsigned int serial8250_tx_empty(struct uart_port *port)
1799 {
1800 struct uart_8250_port *up =
1801 container_of(port, struct uart_8250_port, port);
1802 unsigned long flags;
1803 unsigned int lsr;
1804
1805 spin_lock_irqsave(&port->lock, flags);
1806 lsr = serial_port_in(port, UART_LSR);
1807 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1808 spin_unlock_irqrestore(&port->lock, flags);
1809
1810 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1811 }
1812
1813 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1814 {
1815 struct uart_8250_port *up =
1816 container_of(port, struct uart_8250_port, port);
1817 unsigned int status;
1818 unsigned int ret;
1819
1820 status = serial8250_modem_status(up);
1821
1822 ret = 0;
1823 if (status & UART_MSR_DCD)
1824 ret |= TIOCM_CAR;
1825 if (status & UART_MSR_RI)
1826 ret |= TIOCM_RNG;
1827 if (status & UART_MSR_DSR)
1828 ret |= TIOCM_DSR;
1829 if (status & UART_MSR_CTS)
1830 ret |= TIOCM_CTS;
1831 return ret;
1832 }
1833
1834 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1835 {
1836 struct uart_8250_port *up =
1837 container_of(port, struct uart_8250_port, port);
1838 unsigned char mcr = 0;
1839
1840 if (mctrl & TIOCM_RTS)
1841 mcr |= UART_MCR_RTS;
1842 if (mctrl & TIOCM_DTR)
1843 mcr |= UART_MCR_DTR;
1844 if (mctrl & TIOCM_OUT1)
1845 mcr |= UART_MCR_OUT1;
1846 if (mctrl & TIOCM_OUT2)
1847 mcr |= UART_MCR_OUT2;
1848 if (mctrl & TIOCM_LOOP)
1849 mcr |= UART_MCR_LOOP;
1850
1851 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1852
1853 serial_port_out(port, UART_MCR, mcr);
1854 }
1855
1856 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1857 {
1858 struct uart_8250_port *up =
1859 container_of(port, struct uart_8250_port, port);
1860 unsigned long flags;
1861
1862 spin_lock_irqsave(&port->lock, flags);
1863 if (break_state == -1)
1864 up->lcr |= UART_LCR_SBC;
1865 else
1866 up->lcr &= ~UART_LCR_SBC;
1867 serial_port_out(port, UART_LCR, up->lcr);
1868 spin_unlock_irqrestore(&port->lock, flags);
1869 }
1870
1871 /*
1872 * Wait for transmitter & holding register to empty
1873 */
1874 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1875 {
1876 unsigned int status, tmout = 10000;
1877
1878 /* Wait up to 10ms for the character(s) to be sent. */
1879 for (;;) {
1880 status = serial_in(up, UART_LSR);
1881
1882 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1883
1884 if ((status & bits) == bits)
1885 break;
1886 if (--tmout == 0)
1887 break;
1888 udelay(1);
1889 }
1890
1891 /* Wait up to 1s for flow control if necessary */
1892 if (up->port.flags & UPF_CONS_FLOW) {
1893 unsigned int tmout;
1894 for (tmout = 1000000; tmout; tmout--) {
1895 unsigned int msr = serial_in(up, UART_MSR);
1896 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1897 if (msr & UART_MSR_CTS)
1898 break;
1899 udelay(1);
1900 touch_nmi_watchdog();
1901 }
1902 }
1903 }
1904
1905 #ifdef CONFIG_CONSOLE_POLL
1906 /*
1907 * Console polling routines for writing and reading from the uart while
1908 * in an interrupt or debug context.
1909 */
1910
1911 static int serial8250_get_poll_char(struct uart_port *port)
1912 {
1913 unsigned char lsr = serial_port_in(port, UART_LSR);
1914
1915 if (!(lsr & UART_LSR_DR))
1916 return NO_POLL_CHAR;
1917
1918 return serial_port_in(port, UART_RX);
1919 }
1920
1921
1922 static void serial8250_put_poll_char(struct uart_port *port,
1923 unsigned char c)
1924 {
1925 unsigned int ier;
1926 struct uart_8250_port *up =
1927 container_of(port, struct uart_8250_port, port);
1928
1929 /*
1930 * First save the IER then disable the interrupts
1931 */
1932 ier = serial_port_in(port, UART_IER);
1933 if (up->capabilities & UART_CAP_UUE)
1934 serial_port_out(port, UART_IER, UART_IER_UUE);
1935 else
1936 serial_port_out(port, UART_IER, 0);
1937
1938 wait_for_xmitr(up, BOTH_EMPTY);
1939 /*
1940 * Send the character out.
1941 * If a LF, also do CR...
1942 */
1943 serial_port_out(port, UART_TX, c);
1944 if (c == 10) {
1945 wait_for_xmitr(up, BOTH_EMPTY);
1946 serial_port_out(port, UART_TX, 13);
1947 }
1948
1949 /*
1950 * Finally, wait for transmitter to become empty
1951 * and restore the IER
1952 */
1953 wait_for_xmitr(up, BOTH_EMPTY);
1954 serial_port_out(port, UART_IER, ier);
1955 }
1956
1957 #endif /* CONFIG_CONSOLE_POLL */
1958
1959 static int serial8250_startup(struct uart_port *port)
1960 {
1961 struct uart_8250_port *up =
1962 container_of(port, struct uart_8250_port, port);
1963 unsigned long flags;
1964 unsigned char lsr, iir;
1965 int retval;
1966
1967 port->fifosize = uart_config[up->port.type].fifo_size;
1968 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1969 up->capabilities = uart_config[up->port.type].flags;
1970 up->mcr = 0;
1971
1972 if (port->iotype != up->cur_iotype)
1973 set_io_from_upio(port);
1974
1975 if (port->type == PORT_16C950) {
1976 /* Wake up and initialize UART */
1977 up->acr = 0;
1978 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1979 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1980 serial_port_out(port, UART_IER, 0);
1981 serial_port_out(port, UART_LCR, 0);
1982 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1983 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1984 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1985 serial_port_out(port, UART_LCR, 0);
1986 }
1987
1988 #ifdef CONFIG_SERIAL_8250_RSA
1989 /*
1990 * If this is an RSA port, see if we can kick it up to the
1991 * higher speed clock.
1992 */
1993 enable_rsa(up);
1994 #endif
1995
1996 /*
1997 * Clear the FIFO buffers and disable them.
1998 * (they will be reenabled in set_termios())
1999 */
2000 serial8250_clear_fifos(up);
2001
2002 /*
2003 * Clear the interrupt registers.
2004 */
2005 serial_port_in(port, UART_LSR);
2006 serial_port_in(port, UART_RX);
2007 serial_port_in(port, UART_IIR);
2008 serial_port_in(port, UART_MSR);
2009
2010 /*
2011 * At this point, there's no way the LSR could still be 0xff;
2012 * if it is, then bail out, because there's likely no UART
2013 * here.
2014 */
2015 if (!(port->flags & UPF_BUGGY_UART) &&
2016 (serial_port_in(port, UART_LSR) == 0xff)) {
2017 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2018 serial_index(port));
2019 return -ENODEV;
2020 }
2021
2022 /*
2023 * For a XR16C850, we need to set the trigger levels
2024 */
2025 if (port->type == PORT_16850) {
2026 unsigned char fctr;
2027
2028 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2029
2030 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2031 serial_port_out(port, UART_FCTR,
2032 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2033 serial_port_out(port, UART_TRG, UART_TRG_96);
2034 serial_port_out(port, UART_FCTR,
2035 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2036 serial_port_out(port, UART_TRG, UART_TRG_96);
2037
2038 serial_port_out(port, UART_LCR, 0);
2039 }
2040
2041 if (port->irq) {
2042 unsigned char iir1;
2043 /*
2044 * Test for UARTs that do not reassert THRE when the
2045 * transmitter is idle and the interrupt has already
2046 * been cleared. Real 16550s should always reassert
2047 * this interrupt whenever the transmitter is idle and
2048 * the interrupt is enabled. Delays are necessary to
2049 * allow register changes to become visible.
2050 */
2051 spin_lock_irqsave(&port->lock, flags);
2052 if (up->port.irqflags & IRQF_SHARED)
2053 disable_irq_nosync(port->irq);
2054
2055 wait_for_xmitr(up, UART_LSR_THRE);
2056 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2057 udelay(1); /* allow THRE to set */
2058 iir1 = serial_port_in(port, UART_IIR);
2059 serial_port_out(port, UART_IER, 0);
2060 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2061 udelay(1); /* allow a working UART time to re-assert THRE */
2062 iir = serial_port_in(port, UART_IIR);
2063 serial_port_out(port, UART_IER, 0);
2064
2065 if (port->irqflags & IRQF_SHARED)
2066 enable_irq(port->irq);
2067 spin_unlock_irqrestore(&port->lock, flags);
2068
2069 /*
2070 * If the interrupt is not reasserted, or we otherwise
2071 * don't trust the iir, setup a timer to kick the UART
2072 * on a regular basis.
2073 */
2074 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2075 up->port.flags & UPF_BUG_THRE) {
2076 up->bugs |= UART_BUG_THRE;
2077 pr_debug("ttyS%d - using backup timer\n",
2078 serial_index(port));
2079 }
2080 }
2081
2082 /*
2083 * The above check will only give an accurate result the first time
2084 * the port is opened so this value needs to be preserved.
2085 */
2086 if (up->bugs & UART_BUG_THRE) {
2087 up->timer.function = serial8250_backup_timeout;
2088 up->timer.data = (unsigned long)up;
2089 mod_timer(&up->timer, jiffies +
2090 uart_poll_timeout(port) + HZ / 5);
2091 }
2092
2093 /*
2094 * If the "interrupt" for this port doesn't correspond with any
2095 * hardware interrupt, we use a timer-based system. The original
2096 * driver used to do this with IRQ0.
2097 */
2098 if (!port->irq) {
2099 up->timer.data = (unsigned long)up;
2100 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
2101 } else {
2102 retval = serial_link_irq_chain(up);
2103 if (retval)
2104 return retval;
2105 }
2106
2107 /*
2108 * Now, initialize the UART
2109 */
2110 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2111
2112 spin_lock_irqsave(&port->lock, flags);
2113 if (up->port.flags & UPF_FOURPORT) {
2114 if (!up->port.irq)
2115 up->port.mctrl |= TIOCM_OUT1;
2116 } else
2117 /*
2118 * Most PC uarts need OUT2 raised to enable interrupts.
2119 */
2120 if (port->irq)
2121 up->port.mctrl |= TIOCM_OUT2;
2122
2123 serial8250_set_mctrl(port, port->mctrl);
2124
2125 /* Serial over Lan (SoL) hack:
2126 Intel 8257x Gigabit ethernet chips have a
2127 16550 emulation, to be used for Serial Over Lan.
2128 Those chips take a longer time than a normal
2129 serial device to signalize that a transmission
2130 data was queued. Due to that, the above test generally
2131 fails. One solution would be to delay the reading of
2132 iir. However, this is not reliable, since the timeout
2133 is variable. So, let's just don't test if we receive
2134 TX irq. This way, we'll never enable UART_BUG_TXEN.
2135 */
2136 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
2137 goto dont_test_tx_en;
2138
2139 /*
2140 * Do a quick test to see if we receive an
2141 * interrupt when we enable the TX irq.
2142 */
2143 serial_port_out(port, UART_IER, UART_IER_THRI);
2144 lsr = serial_port_in(port, UART_LSR);
2145 iir = serial_port_in(port, UART_IIR);
2146 serial_port_out(port, UART_IER, 0);
2147
2148 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2149 if (!(up->bugs & UART_BUG_TXEN)) {
2150 up->bugs |= UART_BUG_TXEN;
2151 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2152 serial_index(port));
2153 }
2154 } else {
2155 up->bugs &= ~UART_BUG_TXEN;
2156 }
2157
2158 dont_test_tx_en:
2159 spin_unlock_irqrestore(&port->lock, flags);
2160
2161 /*
2162 * Clear the interrupt registers again for luck, and clear the
2163 * saved flags to avoid getting false values from polling
2164 * routines or the previous session.
2165 */
2166 serial_port_in(port, UART_LSR);
2167 serial_port_in(port, UART_RX);
2168 serial_port_in(port, UART_IIR);
2169 serial_port_in(port, UART_MSR);
2170 up->lsr_saved_flags = 0;
2171 up->msr_saved_flags = 0;
2172
2173 /*
2174 * Finally, enable interrupts. Note: Modem status interrupts
2175 * are set via set_termios(), which will be occurring imminently
2176 * anyway, so we don't enable them here.
2177 */
2178 up->ier = UART_IER_RLSI | UART_IER_RDI;
2179 serial_port_out(port, UART_IER, up->ier);
2180
2181 if (port->flags & UPF_FOURPORT) {
2182 unsigned int icp;
2183 /*
2184 * Enable interrupts on the AST Fourport board
2185 */
2186 icp = (port->iobase & 0xfe0) | 0x01f;
2187 outb_p(0x80, icp);
2188 inb_p(icp);
2189 }
2190
2191 return 0;
2192 }
2193
2194 static void serial8250_shutdown(struct uart_port *port)
2195 {
2196 struct uart_8250_port *up =
2197 container_of(port, struct uart_8250_port, port);
2198 unsigned long flags;
2199
2200 /*
2201 * Disable interrupts from this port
2202 */
2203 up->ier = 0;
2204 serial_port_out(port, UART_IER, 0);
2205
2206 spin_lock_irqsave(&port->lock, flags);
2207 if (port->flags & UPF_FOURPORT) {
2208 /* reset interrupts on the AST Fourport board */
2209 inb((port->iobase & 0xfe0) | 0x1f);
2210 port->mctrl |= TIOCM_OUT1;
2211 } else
2212 port->mctrl &= ~TIOCM_OUT2;
2213
2214 serial8250_set_mctrl(port, port->mctrl);
2215 spin_unlock_irqrestore(&port->lock, flags);
2216
2217 /*
2218 * Disable break condition and FIFOs
2219 */
2220 serial_port_out(port, UART_LCR,
2221 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2222 serial8250_clear_fifos(up);
2223
2224 #ifdef CONFIG_SERIAL_8250_RSA
2225 /*
2226 * Reset the RSA board back to 115kbps compat mode.
2227 */
2228 disable_rsa(up);
2229 #endif
2230
2231 /*
2232 * Read data port to reset things, and then unlink from
2233 * the IRQ chain.
2234 */
2235 serial_port_in(port, UART_RX);
2236
2237 del_timer_sync(&up->timer);
2238 up->timer.function = serial8250_timeout;
2239 if (port->irq)
2240 serial_unlink_irq_chain(up);
2241 }
2242
2243 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2244 {
2245 unsigned int quot;
2246
2247 /*
2248 * Handle magic divisors for baud rates above baud_base on
2249 * SMSC SuperIO chips.
2250 */
2251 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2252 baud == (port->uartclk/4))
2253 quot = 0x8001;
2254 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2255 baud == (port->uartclk/8))
2256 quot = 0x8002;
2257 else
2258 quot = uart_get_divisor(port, baud);
2259
2260 return quot;
2261 }
2262
2263 void
2264 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2265 struct ktermios *old)
2266 {
2267 struct uart_8250_port *up =
2268 container_of(port, struct uart_8250_port, port);
2269 unsigned char cval, fcr = 0;
2270 unsigned long flags;
2271 unsigned int baud, quot;
2272
2273 switch (termios->c_cflag & CSIZE) {
2274 case CS5:
2275 cval = UART_LCR_WLEN5;
2276 break;
2277 case CS6:
2278 cval = UART_LCR_WLEN6;
2279 break;
2280 case CS7:
2281 cval = UART_LCR_WLEN7;
2282 break;
2283 default:
2284 case CS8:
2285 cval = UART_LCR_WLEN8;
2286 break;
2287 }
2288
2289 if (termios->c_cflag & CSTOPB)
2290 cval |= UART_LCR_STOP;
2291 if (termios->c_cflag & PARENB)
2292 cval |= UART_LCR_PARITY;
2293 if (!(termios->c_cflag & PARODD))
2294 cval |= UART_LCR_EPAR;
2295 #ifdef CMSPAR
2296 if (termios->c_cflag & CMSPAR)
2297 cval |= UART_LCR_SPAR;
2298 #endif
2299
2300 /*
2301 * Ask the core to calculate the divisor for us.
2302 */
2303 baud = uart_get_baud_rate(port, termios, old,
2304 port->uartclk / 16 / 0xffff,
2305 port->uartclk / 16);
2306 quot = serial8250_get_divisor(port, baud);
2307
2308 /*
2309 * Oxford Semi 952 rev B workaround
2310 */
2311 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2312 quot++;
2313
2314 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2315 fcr = uart_config[port->type].fcr;
2316 if (baud < 2400) {
2317 fcr &= ~UART_FCR_TRIGGER_MASK;
2318 fcr |= UART_FCR_TRIGGER_1;
2319 }
2320 }
2321
2322 /*
2323 * MCR-based auto flow control. When AFE is enabled, RTS will be
2324 * deasserted when the receive FIFO contains more characters than
2325 * the trigger, or the MCR RTS bit is cleared. In the case where
2326 * the remote UART is not using CTS auto flow control, we must
2327 * have sufficient FIFO entries for the latency of the remote
2328 * UART to respond. IOW, at least 32 bytes of FIFO.
2329 */
2330 if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) {
2331 up->mcr &= ~UART_MCR_AFE;
2332 if (termios->c_cflag & CRTSCTS)
2333 up->mcr |= UART_MCR_AFE;
2334 }
2335
2336 /*
2337 * Ok, we're now changing the port state. Do it with
2338 * interrupts disabled.
2339 */
2340 spin_lock_irqsave(&port->lock, flags);
2341
2342 /*
2343 * Update the per-port timeout.
2344 */
2345 uart_update_timeout(port, termios->c_cflag, baud);
2346
2347 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2348 if (termios->c_iflag & INPCK)
2349 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2350 if (termios->c_iflag & (BRKINT | PARMRK))
2351 port->read_status_mask |= UART_LSR_BI;
2352
2353 /*
2354 * Characteres to ignore
2355 */
2356 port->ignore_status_mask = 0;
2357 if (termios->c_iflag & IGNPAR)
2358 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2359 if (termios->c_iflag & IGNBRK) {
2360 port->ignore_status_mask |= UART_LSR_BI;
2361 /*
2362 * If we're ignoring parity and break indicators,
2363 * ignore overruns too (for real raw support).
2364 */
2365 if (termios->c_iflag & IGNPAR)
2366 port->ignore_status_mask |= UART_LSR_OE;
2367 }
2368
2369 /*
2370 * ignore all characters if CREAD is not set
2371 */
2372 if ((termios->c_cflag & CREAD) == 0)
2373 port->ignore_status_mask |= UART_LSR_DR;
2374
2375 /*
2376 * CTS flow control flag and modem status interrupts
2377 */
2378 up->ier &= ~UART_IER_MSI;
2379 if (!(up->bugs & UART_BUG_NOMSR) &&
2380 UART_ENABLE_MS(&up->port, termios->c_cflag))
2381 up->ier |= UART_IER_MSI;
2382 if (up->capabilities & UART_CAP_UUE)
2383 up->ier |= UART_IER_UUE;
2384 if (up->capabilities & UART_CAP_RTOIE)
2385 up->ier |= UART_IER_RTOIE;
2386
2387 serial_port_out(port, UART_IER, up->ier);
2388
2389 if (up->capabilities & UART_CAP_EFR) {
2390 unsigned char efr = 0;
2391 /*
2392 * TI16C752/Startech hardware flow control. FIXME:
2393 * - TI16C752 requires control thresholds to be set.
2394 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2395 */
2396 if (termios->c_cflag & CRTSCTS)
2397 efr |= UART_EFR_CTS;
2398
2399 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2400 if (port->flags & UPF_EXAR_EFR)
2401 serial_port_out(port, UART_XR_EFR, efr);
2402 else
2403 serial_port_out(port, UART_EFR, efr);
2404 }
2405
2406 #ifdef CONFIG_ARCH_OMAP
2407 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2408 if (cpu_is_omap1510() && is_omap_port(up)) {
2409 if (baud == 115200) {
2410 quot = 1;
2411 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2412 } else
2413 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2414 }
2415 #endif
2416
2417 /*
2418 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2419 * otherwise just set DLAB
2420 */
2421 if (up->capabilities & UART_NATSEMI)
2422 serial_port_out(port, UART_LCR, 0xe0);
2423 else
2424 serial_port_out(port, UART_LCR, cval | UART_LCR_DLAB);
2425
2426 serial_dl_write(up, quot);
2427
2428 /*
2429 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2430 * is written without DLAB set, this mode will be disabled.
2431 */
2432 if (port->type == PORT_16750)
2433 serial_port_out(port, UART_FCR, fcr);
2434
2435 serial_port_out(port, UART_LCR, cval); /* reset DLAB */
2436 up->lcr = cval; /* Save LCR */
2437 if (port->type != PORT_16750) {
2438 /* emulated UARTs (Lucent Venus 167x) need two steps */
2439 if (fcr & UART_FCR_ENABLE_FIFO)
2440 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2441 serial_port_out(port, UART_FCR, fcr); /* set fcr */
2442 }
2443 serial8250_set_mctrl(port, port->mctrl);
2444 spin_unlock_irqrestore(&port->lock, flags);
2445 /* Don't rewrite B0 */
2446 if (tty_termios_baud_rate(termios))
2447 tty_termios_encode_baud_rate(termios, baud, baud);
2448 }
2449 EXPORT_SYMBOL(serial8250_do_set_termios);
2450
2451 static void
2452 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2453 struct ktermios *old)
2454 {
2455 if (port->set_termios)
2456 port->set_termios(port, termios, old);
2457 else
2458 serial8250_do_set_termios(port, termios, old);
2459 }
2460
2461 static void
2462 serial8250_set_ldisc(struct uart_port *port, int new)
2463 {
2464 if (new == N_PPS) {
2465 port->flags |= UPF_HARDPPS_CD;
2466 serial8250_enable_ms(port);
2467 } else
2468 port->flags &= ~UPF_HARDPPS_CD;
2469 }
2470
2471
2472 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2473 unsigned int oldstate)
2474 {
2475 struct uart_8250_port *p =
2476 container_of(port, struct uart_8250_port, port);
2477
2478 serial8250_set_sleep(p, state != 0);
2479 }
2480 EXPORT_SYMBOL(serial8250_do_pm);
2481
2482 static void
2483 serial8250_pm(struct uart_port *port, unsigned int state,
2484 unsigned int oldstate)
2485 {
2486 if (port->pm)
2487 port->pm(port, state, oldstate);
2488 else
2489 serial8250_do_pm(port, state, oldstate);
2490 }
2491
2492 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2493 {
2494 if (pt->port.iotype == UPIO_AU)
2495 return 0x1000;
2496 #ifdef CONFIG_ARCH_OMAP
2497 if (is_omap_port(pt))
2498 return 0x16 << pt->port.regshift;
2499 #endif
2500 return 8 << pt->port.regshift;
2501 }
2502
2503 /*
2504 * Resource handling.
2505 */
2506 static int serial8250_request_std_resource(struct uart_8250_port *up)
2507 {
2508 unsigned int size = serial8250_port_size(up);
2509 struct uart_port *port = &up->port;
2510 int ret = 0;
2511
2512 switch (port->iotype) {
2513 case UPIO_AU:
2514 case UPIO_TSI:
2515 case UPIO_MEM32:
2516 case UPIO_MEM:
2517 if (!port->mapbase)
2518 break;
2519
2520 if (!request_mem_region(port->mapbase, size, "serial")) {
2521 ret = -EBUSY;
2522 break;
2523 }
2524
2525 if (port->flags & UPF_IOREMAP) {
2526 port->membase = ioremap_nocache(port->mapbase, size);
2527 if (!port->membase) {
2528 release_mem_region(port->mapbase, size);
2529 ret = -ENOMEM;
2530 }
2531 }
2532 break;
2533
2534 case UPIO_HUB6:
2535 case UPIO_PORT:
2536 if (!request_region(port->iobase, size, "serial"))
2537 ret = -EBUSY;
2538 break;
2539 }
2540 return ret;
2541 }
2542
2543 static void serial8250_release_std_resource(struct uart_8250_port *up)
2544 {
2545 unsigned int size = serial8250_port_size(up);
2546 struct uart_port *port = &up->port;
2547
2548 switch (port->iotype) {
2549 case UPIO_AU:
2550 case UPIO_TSI:
2551 case UPIO_MEM32:
2552 case UPIO_MEM:
2553 if (!port->mapbase)
2554 break;
2555
2556 if (port->flags & UPF_IOREMAP) {
2557 iounmap(port->membase);
2558 port->membase = NULL;
2559 }
2560
2561 release_mem_region(port->mapbase, size);
2562 break;
2563
2564 case UPIO_HUB6:
2565 case UPIO_PORT:
2566 release_region(port->iobase, size);
2567 break;
2568 }
2569 }
2570
2571 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2572 {
2573 unsigned long start = UART_RSA_BASE << up->port.regshift;
2574 unsigned int size = 8 << up->port.regshift;
2575 struct uart_port *port = &up->port;
2576 int ret = -EINVAL;
2577
2578 switch (port->iotype) {
2579 case UPIO_HUB6:
2580 case UPIO_PORT:
2581 start += port->iobase;
2582 if (request_region(start, size, "serial-rsa"))
2583 ret = 0;
2584 else
2585 ret = -EBUSY;
2586 break;
2587 }
2588
2589 return ret;
2590 }
2591
2592 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2593 {
2594 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2595 unsigned int size = 8 << up->port.regshift;
2596 struct uart_port *port = &up->port;
2597
2598 switch (port->iotype) {
2599 case UPIO_HUB6:
2600 case UPIO_PORT:
2601 release_region(port->iobase + offset, size);
2602 break;
2603 }
2604 }
2605
2606 static void serial8250_release_port(struct uart_port *port)
2607 {
2608 struct uart_8250_port *up =
2609 container_of(port, struct uart_8250_port, port);
2610
2611 serial8250_release_std_resource(up);
2612 if (port->type == PORT_RSA)
2613 serial8250_release_rsa_resource(up);
2614 }
2615
2616 static int serial8250_request_port(struct uart_port *port)
2617 {
2618 struct uart_8250_port *up =
2619 container_of(port, struct uart_8250_port, port);
2620 int ret = 0;
2621
2622 ret = serial8250_request_std_resource(up);
2623 if (ret == 0 && port->type == PORT_RSA) {
2624 ret = serial8250_request_rsa_resource(up);
2625 if (ret < 0)
2626 serial8250_release_std_resource(up);
2627 }
2628
2629 return ret;
2630 }
2631
2632 static void serial8250_config_port(struct uart_port *port, int flags)
2633 {
2634 struct uart_8250_port *up =
2635 container_of(port, struct uart_8250_port, port);
2636 int probeflags = PROBE_ANY;
2637 int ret;
2638
2639 /*
2640 * Find the region that we can probe for. This in turn
2641 * tells us whether we can probe for the type of port.
2642 */
2643 ret = serial8250_request_std_resource(up);
2644 if (ret < 0)
2645 return;
2646
2647 ret = serial8250_request_rsa_resource(up);
2648 if (ret < 0)
2649 probeflags &= ~PROBE_RSA;
2650
2651 if (port->iotype != up->cur_iotype)
2652 set_io_from_upio(port);
2653
2654 if (flags & UART_CONFIG_TYPE)
2655 autoconfig(up, probeflags);
2656
2657 /* if access method is AU, it is a 16550 with a quirk */
2658 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
2659 up->bugs |= UART_BUG_NOMSR;
2660
2661 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2662 autoconfig_irq(up);
2663
2664 if (port->type != PORT_RSA && probeflags & PROBE_RSA)
2665 serial8250_release_rsa_resource(up);
2666 if (port->type == PORT_UNKNOWN)
2667 serial8250_release_std_resource(up);
2668 }
2669
2670 static int
2671 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2672 {
2673 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2674 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2675 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2676 ser->type == PORT_STARTECH || uart_config[ser->type].name == NULL)
2677 return -EINVAL;
2678 return 0;
2679 }
2680
2681 static const char *
2682 serial8250_type(struct uart_port *port)
2683 {
2684 int type = port->type;
2685
2686 if (type >= ARRAY_SIZE(uart_config) || uart_config[type].name == NULL)
2687 type = 0;
2688 return uart_config[type].name;
2689 }
2690
2691 static struct uart_ops serial8250_pops = {
2692 .tx_empty = serial8250_tx_empty,
2693 .set_mctrl = serial8250_set_mctrl,
2694 .get_mctrl = serial8250_get_mctrl,
2695 .stop_tx = serial8250_stop_tx,
2696 .start_tx = serial8250_start_tx,
2697 .stop_rx = serial8250_stop_rx,
2698 .enable_ms = serial8250_enable_ms,
2699 .break_ctl = serial8250_break_ctl,
2700 .startup = serial8250_startup,
2701 .shutdown = serial8250_shutdown,
2702 .set_termios = serial8250_set_termios,
2703 .set_ldisc = serial8250_set_ldisc,
2704 .pm = serial8250_pm,
2705 .type = serial8250_type,
2706 .release_port = serial8250_release_port,
2707 .request_port = serial8250_request_port,
2708 .config_port = serial8250_config_port,
2709 .verify_port = serial8250_verify_port,
2710 #ifdef CONFIG_CONSOLE_POLL
2711 .poll_get_char = serial8250_get_poll_char,
2712 .poll_put_char = serial8250_put_poll_char,
2713 #endif
2714 };
2715
2716 static struct uart_8250_port serial8250_ports[UART_NR];
2717
2718 static void (*serial8250_isa_config)(int port, struct uart_port *up,
2719 unsigned short *capabilities);
2720
2721 void serial8250_set_isa_configurator(
2722 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2723 {
2724 serial8250_isa_config = v;
2725 }
2726 EXPORT_SYMBOL(serial8250_set_isa_configurator);
2727
2728 static void __init serial8250_isa_init_ports(void)
2729 {
2730 struct uart_8250_port *up;
2731 static int first = 1;
2732 int i, irqflag = 0;
2733
2734 if (!first)
2735 return;
2736 first = 0;
2737
2738 for (i = 0; i < nr_uarts; i++) {
2739 struct uart_8250_port *up = &serial8250_ports[i];
2740 struct uart_port *port = &up->port;
2741
2742 port->line = i;
2743 spin_lock_init(&port->lock);
2744
2745 init_timer(&up->timer);
2746 up->timer.function = serial8250_timeout;
2747
2748 /*
2749 * ALPHA_KLUDGE_MCR needs to be killed.
2750 */
2751 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2752 up->mcr_force = ALPHA_KLUDGE_MCR;
2753
2754 port->ops = &serial8250_pops;
2755 }
2756
2757 if (share_irqs)
2758 irqflag = IRQF_SHARED;
2759
2760 for (i = 0, up = serial8250_ports;
2761 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2762 i++, up++) {
2763 struct uart_port *port = &up->port;
2764
2765 port->iobase = old_serial_port[i].port;
2766 port->irq = irq_canonicalize(old_serial_port[i].irq);
2767 port->irqflags = old_serial_port[i].irqflags;
2768 port->uartclk = old_serial_port[i].baud_base * 16;
2769 port->flags = old_serial_port[i].flags;
2770 port->hub6 = old_serial_port[i].hub6;
2771 port->membase = old_serial_port[i].iomem_base;
2772 port->iotype = old_serial_port[i].io_type;
2773 port->regshift = old_serial_port[i].iomem_reg_shift;
2774 set_io_from_upio(port);
2775 port->irqflags |= irqflag;
2776 if (serial8250_isa_config != NULL)
2777 serial8250_isa_config(i, &up->port, &up->capabilities);
2778
2779 }
2780 }
2781
2782 static void
2783 serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2784 {
2785 up->port.type = type;
2786 up->port.fifosize = uart_config[type].fifo_size;
2787 up->capabilities = uart_config[type].flags;
2788 up->tx_loadsz = uart_config[type].tx_loadsz;
2789 }
2790
2791 static void __init
2792 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2793 {
2794 int i;
2795
2796 for (i = 0; i < nr_uarts; i++) {
2797 struct uart_8250_port *up = &serial8250_ports[i];
2798 up->cur_iotype = 0xFF;
2799 }
2800
2801 serial8250_isa_init_ports();
2802
2803 for (i = 0; i < nr_uarts; i++) {
2804 struct uart_8250_port *up = &serial8250_ports[i];
2805
2806 up->port.dev = dev;
2807
2808 if (up->port.flags & UPF_FIXED_TYPE)
2809 serial8250_init_fixed_type_port(up, up->port.type);
2810
2811 uart_add_one_port(drv, &up->port);
2812 }
2813 }
2814
2815 #ifdef CONFIG_SERIAL_8250_CONSOLE
2816
2817 static void serial8250_console_putchar(struct uart_port *port, int ch)
2818 {
2819 struct uart_8250_port *up =
2820 container_of(port, struct uart_8250_port, port);
2821
2822 wait_for_xmitr(up, UART_LSR_THRE);
2823 serial_port_out(port, UART_TX, ch);
2824 }
2825
2826 /*
2827 * Print a string to the serial port trying not to disturb
2828 * any possible real use of the port...
2829 *
2830 * The console_lock must be held when we get here.
2831 */
2832 static void
2833 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2834 {
2835 struct uart_8250_port *up = &serial8250_ports[co->index];
2836 struct uart_port *port = &up->port;
2837 unsigned long flags;
2838 unsigned int ier;
2839 int locked = 1;
2840
2841 touch_nmi_watchdog();
2842
2843 local_irq_save(flags);
2844 if (port->sysrq) {
2845 /* serial8250_handle_irq() already took the lock */
2846 locked = 0;
2847 } else if (oops_in_progress) {
2848 locked = spin_trylock(&port->lock);
2849 } else
2850 spin_lock(&port->lock);
2851
2852 /*
2853 * First save the IER then disable the interrupts
2854 */
2855 ier = serial_port_in(port, UART_IER);
2856
2857 if (up->capabilities & UART_CAP_UUE)
2858 serial_port_out(port, UART_IER, UART_IER_UUE);
2859 else
2860 serial_port_out(port, UART_IER, 0);
2861
2862 uart_console_write(port, s, count, serial8250_console_putchar);
2863
2864 /*
2865 * Finally, wait for transmitter to become empty
2866 * and restore the IER
2867 */
2868 wait_for_xmitr(up, BOTH_EMPTY);
2869 serial_port_out(port, UART_IER, ier);
2870
2871 /*
2872 * The receive handling will happen properly because the
2873 * receive ready bit will still be set; it is not cleared
2874 * on read. However, modem control will not, we must
2875 * call it if we have saved something in the saved flags
2876 * while processing with interrupts off.
2877 */
2878 if (up->msr_saved_flags)
2879 serial8250_modem_status(up);
2880
2881 if (locked)
2882 spin_unlock(&port->lock);
2883 local_irq_restore(flags);
2884 }
2885
2886 static int __init serial8250_console_setup(struct console *co, char *options)
2887 {
2888 struct uart_port *port;
2889 int baud = 9600;
2890 int bits = 8;
2891 int parity = 'n';
2892 int flow = 'n';
2893
2894 /*
2895 * Check whether an invalid uart number has been specified, and
2896 * if so, search for the first available port that does have
2897 * console support.
2898 */
2899 if (co->index >= nr_uarts)
2900 co->index = 0;
2901 port = &serial8250_ports[co->index].port;
2902 if (!port->iobase && !port->membase)
2903 return -ENODEV;
2904
2905 if (options)
2906 uart_parse_options(options, &baud, &parity, &bits, &flow);
2907
2908 return uart_set_options(port, co, baud, parity, bits, flow);
2909 }
2910
2911 static int serial8250_console_early_setup(void)
2912 {
2913 return serial8250_find_port_for_earlycon();
2914 }
2915
2916 static struct console serial8250_console = {
2917 .name = "ttyS",
2918 .write = serial8250_console_write,
2919 .device = uart_console_device,
2920 .setup = serial8250_console_setup,
2921 .early_setup = serial8250_console_early_setup,
2922 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2923 .index = -1,
2924 .data = &serial8250_reg,
2925 };
2926
2927 static int __init serial8250_console_init(void)
2928 {
2929 if (nr_uarts > UART_NR)
2930 nr_uarts = UART_NR;
2931
2932 serial8250_isa_init_ports();
2933 register_console(&serial8250_console);
2934 return 0;
2935 }
2936 console_initcall(serial8250_console_init);
2937
2938 int serial8250_find_port(struct uart_port *p)
2939 {
2940 int line;
2941 struct uart_port *port;
2942
2943 for (line = 0; line < nr_uarts; line++) {
2944 port = &serial8250_ports[line].port;
2945 if (uart_match_port(p, port))
2946 return line;
2947 }
2948 return -ENODEV;
2949 }
2950
2951 #define SERIAL8250_CONSOLE &serial8250_console
2952 #else
2953 #define SERIAL8250_CONSOLE NULL
2954 #endif
2955
2956 static struct uart_driver serial8250_reg = {
2957 .owner = THIS_MODULE,
2958 .driver_name = "serial",
2959 .dev_name = "ttyS",
2960 .major = TTY_MAJOR,
2961 .minor = 64,
2962 .cons = SERIAL8250_CONSOLE,
2963 };
2964
2965 /*
2966 * early_serial_setup - early registration for 8250 ports
2967 *
2968 * Setup an 8250 port structure prior to console initialisation. Use
2969 * after console initialisation will cause undefined behaviour.
2970 */
2971 int __init early_serial_setup(struct uart_port *port)
2972 {
2973 struct uart_port *p;
2974
2975 if (port->line >= ARRAY_SIZE(serial8250_ports))
2976 return -ENODEV;
2977
2978 serial8250_isa_init_ports();
2979 p = &serial8250_ports[port->line].port;
2980 p->iobase = port->iobase;
2981 p->membase = port->membase;
2982 p->irq = port->irq;
2983 p->irqflags = port->irqflags;
2984 p->uartclk = port->uartclk;
2985 p->fifosize = port->fifosize;
2986 p->regshift = port->regshift;
2987 p->iotype = port->iotype;
2988 p->flags = port->flags;
2989 p->mapbase = port->mapbase;
2990 p->private_data = port->private_data;
2991 p->type = port->type;
2992 p->line = port->line;
2993
2994 set_io_from_upio(p);
2995 if (port->serial_in)
2996 p->serial_in = port->serial_in;
2997 if (port->serial_out)
2998 p->serial_out = port->serial_out;
2999 if (port->handle_irq)
3000 p->handle_irq = port->handle_irq;
3001 else
3002 p->handle_irq = serial8250_default_handle_irq;
3003
3004 return 0;
3005 }
3006
3007 /**
3008 * serial8250_suspend_port - suspend one serial port
3009 * @line: serial line number
3010 *
3011 * Suspend one serial port.
3012 */
3013 void serial8250_suspend_port(int line)
3014 {
3015 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
3016 }
3017
3018 /**
3019 * serial8250_resume_port - resume one serial port
3020 * @line: serial line number
3021 *
3022 * Resume one serial port.
3023 */
3024 void serial8250_resume_port(int line)
3025 {
3026 struct uart_8250_port *up = &serial8250_ports[line];
3027 struct uart_port *port = &up->port;
3028
3029 if (up->capabilities & UART_NATSEMI) {
3030 /* Ensure it's still in high speed mode */
3031 serial_port_out(port, UART_LCR, 0xE0);
3032
3033 ns16550a_goto_highspeed(up);
3034
3035 serial_port_out(port, UART_LCR, 0);
3036 port->uartclk = 921600*16;
3037 }
3038 uart_resume_port(&serial8250_reg, port);
3039 }
3040
3041 /*
3042 * Register a set of serial devices attached to a platform device. The
3043 * list is terminated with a zero flags entry, which means we expect
3044 * all entries to have at least UPF_BOOT_AUTOCONF set.
3045 */
3046 static int __devinit serial8250_probe(struct platform_device *dev)
3047 {
3048 struct plat_serial8250_port *p = dev->dev.platform_data;
3049 struct uart_port port;
3050 int ret, i, irqflag = 0;
3051
3052 memset(&port, 0, sizeof(struct uart_port));
3053
3054 if (share_irqs)
3055 irqflag = IRQF_SHARED;
3056
3057 for (i = 0; p && p->flags != 0; p++, i++) {
3058 port.iobase = p->iobase;
3059 port.membase = p->membase;
3060 port.irq = p->irq;
3061 port.irqflags = p->irqflags;
3062 port.uartclk = p->uartclk;
3063 port.regshift = p->regshift;
3064 port.iotype = p->iotype;
3065 port.flags = p->flags;
3066 port.mapbase = p->mapbase;
3067 port.hub6 = p->hub6;
3068 port.private_data = p->private_data;
3069 port.type = p->type;
3070 port.serial_in = p->serial_in;
3071 port.serial_out = p->serial_out;
3072 port.handle_irq = p->handle_irq;
3073 port.set_termios = p->set_termios;
3074 port.pm = p->pm;
3075 port.dev = &dev->dev;
3076 port.irqflags |= irqflag;
3077 ret = serial8250_register_port(&port);
3078 if (ret < 0) {
3079 dev_err(&dev->dev, "unable to register port at index %d "
3080 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3081 p->iobase, (unsigned long long)p->mapbase,
3082 p->irq, ret);
3083 }
3084 }
3085 return 0;
3086 }
3087
3088 /*
3089 * Remove serial ports registered against a platform device.
3090 */
3091 static int __devexit serial8250_remove(struct platform_device *dev)
3092 {
3093 int i;
3094
3095 for (i = 0; i < nr_uarts; i++) {
3096 struct uart_8250_port *up = &serial8250_ports[i];
3097
3098 if (up->port.dev == &dev->dev)
3099 serial8250_unregister_port(i);
3100 }
3101 return 0;
3102 }
3103
3104 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
3105 {
3106 int i;
3107
3108 for (i = 0; i < UART_NR; i++) {
3109 struct uart_8250_port *up = &serial8250_ports[i];
3110
3111 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3112 uart_suspend_port(&serial8250_reg, &up->port);
3113 }
3114
3115 return 0;
3116 }
3117
3118 static int serial8250_resume(struct platform_device *dev)
3119 {
3120 int i;
3121
3122 for (i = 0; i < UART_NR; i++) {
3123 struct uart_8250_port *up = &serial8250_ports[i];
3124
3125 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3126 serial8250_resume_port(i);
3127 }
3128
3129 return 0;
3130 }
3131
3132 static struct platform_driver serial8250_isa_driver = {
3133 .probe = serial8250_probe,
3134 .remove = __devexit_p(serial8250_remove),
3135 .suspend = serial8250_suspend,
3136 .resume = serial8250_resume,
3137 .driver = {
3138 .name = "serial8250",
3139 .owner = THIS_MODULE,
3140 },
3141 };
3142
3143 /*
3144 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3145 * in the table in include/asm/serial.h
3146 */
3147 static struct platform_device *serial8250_isa_devs;
3148
3149 /*
3150 * serial8250_register_port and serial8250_unregister_port allows for
3151 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3152 * modems and PCI multiport cards.
3153 */
3154 static DEFINE_MUTEX(serial_mutex);
3155
3156 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3157 {
3158 int i;
3159
3160 /*
3161 * First, find a port entry which matches.
3162 */
3163 for (i = 0; i < nr_uarts; i++)
3164 if (uart_match_port(&serial8250_ports[i].port, port))
3165 return &serial8250_ports[i];
3166
3167 /*
3168 * We didn't find a matching entry, so look for the first
3169 * free entry. We look for one which hasn't been previously
3170 * used (indicated by zero iobase).
3171 */
3172 for (i = 0; i < nr_uarts; i++)
3173 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3174 serial8250_ports[i].port.iobase == 0)
3175 return &serial8250_ports[i];
3176
3177 /*
3178 * That also failed. Last resort is to find any entry which
3179 * doesn't have a real port associated with it.
3180 */
3181 for (i = 0; i < nr_uarts; i++)
3182 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3183 return &serial8250_ports[i];
3184
3185 return NULL;
3186 }
3187
3188 /**
3189 * serial8250_register_port - register a serial port
3190 * @port: serial port template
3191 *
3192 * Configure the serial port specified by the request. If the
3193 * port exists and is in use, it is hung up and unregistered
3194 * first.
3195 *
3196 * The port is then probed and if necessary the IRQ is autodetected
3197 * If this fails an error is returned.
3198 *
3199 * On success the port is ready to use and the line number is returned.
3200 */
3201 int serial8250_register_port(struct uart_port *port)
3202 {
3203 struct uart_8250_port *uart;
3204 int ret = -ENOSPC;
3205
3206 if (port->uartclk == 0)
3207 return -EINVAL;
3208
3209 mutex_lock(&serial_mutex);
3210
3211 uart = serial8250_find_match_or_unused(port);
3212 if (uart) {
3213 uart_remove_one_port(&serial8250_reg, &uart->port);
3214
3215 uart->port.iobase = port->iobase;
3216 uart->port.membase = port->membase;
3217 uart->port.irq = port->irq;
3218 uart->port.irqflags = port->irqflags;
3219 uart->port.uartclk = port->uartclk;
3220 uart->port.fifosize = port->fifosize;
3221 uart->port.regshift = port->regshift;
3222 uart->port.iotype = port->iotype;
3223 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3224 uart->port.mapbase = port->mapbase;
3225 uart->port.private_data = port->private_data;
3226 if (port->dev)
3227 uart->port.dev = port->dev;
3228
3229 if (port->flags & UPF_FIXED_TYPE)
3230 serial8250_init_fixed_type_port(uart, port->type);
3231
3232 set_io_from_upio(&uart->port);
3233 /* Possibly override default I/O functions. */
3234 if (port->serial_in)
3235 uart->port.serial_in = port->serial_in;
3236 if (port->serial_out)
3237 uart->port.serial_out = port->serial_out;
3238 if (port->handle_irq)
3239 uart->port.handle_irq = port->handle_irq;
3240 /* Possibly override set_termios call */
3241 if (port->set_termios)
3242 uart->port.set_termios = port->set_termios;
3243 if (port->pm)
3244 uart->port.pm = port->pm;
3245
3246 if (serial8250_isa_config != NULL)
3247 serial8250_isa_config(0, &uart->port,
3248 &uart->capabilities);
3249
3250 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3251 if (ret == 0)
3252 ret = uart->port.line;
3253 }
3254 mutex_unlock(&serial_mutex);
3255
3256 return ret;
3257 }
3258 EXPORT_SYMBOL(serial8250_register_port);
3259
3260 /**
3261 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3262 * @line: serial line number
3263 *
3264 * Remove one serial port. This may not be called from interrupt
3265 * context. We hand the port back to the our control.
3266 */
3267 void serial8250_unregister_port(int line)
3268 {
3269 struct uart_8250_port *uart = &serial8250_ports[line];
3270
3271 mutex_lock(&serial_mutex);
3272 uart_remove_one_port(&serial8250_reg, &uart->port);
3273 if (serial8250_isa_devs) {
3274 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3275 uart->port.type = PORT_UNKNOWN;
3276 uart->port.dev = &serial8250_isa_devs->dev;
3277 uart->capabilities = uart_config[uart->port.type].flags;
3278 uart_add_one_port(&serial8250_reg, &uart->port);
3279 } else {
3280 uart->port.dev = NULL;
3281 }
3282 mutex_unlock(&serial_mutex);
3283 }
3284 EXPORT_SYMBOL(serial8250_unregister_port);
3285
3286 static int __init serial8250_init(void)
3287 {
3288 int ret;
3289
3290 if (nr_uarts > UART_NR)
3291 nr_uarts = UART_NR;
3292
3293 printk(KERN_INFO "Serial: 8250/16550 driver, "
3294 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3295 share_irqs ? "en" : "dis");
3296
3297 #ifdef CONFIG_SPARC
3298 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3299 #else
3300 serial8250_reg.nr = UART_NR;
3301 ret = uart_register_driver(&serial8250_reg);
3302 #endif
3303 if (ret)
3304 goto out;
3305
3306 serial8250_isa_devs = platform_device_alloc("serial8250",
3307 PLAT8250_DEV_LEGACY);
3308 if (!serial8250_isa_devs) {
3309 ret = -ENOMEM;
3310 goto unreg_uart_drv;
3311 }
3312
3313 ret = platform_device_add(serial8250_isa_devs);
3314 if (ret)
3315 goto put_dev;
3316
3317 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3318
3319 ret = platform_driver_register(&serial8250_isa_driver);
3320 if (ret == 0)
3321 goto out;
3322
3323 platform_device_del(serial8250_isa_devs);
3324 put_dev:
3325 platform_device_put(serial8250_isa_devs);
3326 unreg_uart_drv:
3327 #ifdef CONFIG_SPARC
3328 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3329 #else
3330 uart_unregister_driver(&serial8250_reg);
3331 #endif
3332 out:
3333 return ret;
3334 }
3335
3336 static void __exit serial8250_exit(void)
3337 {
3338 struct platform_device *isa_dev = serial8250_isa_devs;
3339
3340 /*
3341 * This tells serial8250_unregister_port() not to re-register
3342 * the ports (thereby making serial8250_isa_driver permanently
3343 * in use.)
3344 */
3345 serial8250_isa_devs = NULL;
3346
3347 platform_driver_unregister(&serial8250_isa_driver);
3348 platform_device_unregister(isa_dev);
3349
3350 #ifdef CONFIG_SPARC
3351 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3352 #else
3353 uart_unregister_driver(&serial8250_reg);
3354 #endif
3355 }
3356
3357 module_init(serial8250_init);
3358 module_exit(serial8250_exit);
3359
3360 EXPORT_SYMBOL(serial8250_suspend_port);
3361 EXPORT_SYMBOL(serial8250_resume_port);
3362
3363 MODULE_LICENSE("GPL");
3364 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3365
3366 module_param(share_irqs, uint, 0644);
3367 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3368 " (unsafe)");
3369
3370 module_param(nr_uarts, uint, 0644);
3371 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3372
3373 module_param(skip_txen_test, uint, 0644);
3374 MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3375
3376 #ifdef CONFIG_SERIAL_8250_RSA
3377 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3378 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3379 #endif
3380 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
Linux with added FPC-III support