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Linux 3.4.102
[linux/fpc-iii.git] / drivers / tty / serial / 8250 / 8250_pci.c
blobc48cf891e6bc35341c7b93eafaa448d74800e258
1 /*
2 * Probe module for 8250/16550-type PCI serial ports.
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
11 */
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/pci.h>
15 #include <linux/string.h>
16 #include <linux/kernel.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/serial_core.h>
21 #include <linux/8250_pci.h>
22 #include <linux/bitops.h>
23
24 #include <asm/byteorder.h>
25 #include <asm/io.h>
26
27 #include "8250.h"
28
29 #undef SERIAL_DEBUG_PCI
30
31 /*
32 * init function returns:
33 * > 0 - number of ports
34 * = 0 - use board->num_ports
35 * < 0 - error
36 */
37 struct pci_serial_quirk {
38 u32 vendor;
39 u32 device;
40 u32 subvendor;
41 u32 subdevice;
42 int (*probe)(struct pci_dev *dev);
43 int (*init)(struct pci_dev *dev);
44 int (*setup)(struct serial_private *,
45 const struct pciserial_board *,
46 struct uart_port *, int);
47 void (*exit)(struct pci_dev *dev);
48 };
49
50 #define PCI_NUM_BAR_RESOURCES 6
51
52 struct serial_private {
53 struct pci_dev *dev;
54 unsigned int nr;
55 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
56 struct pci_serial_quirk *quirk;
57 int line[0];
58 };
59
60 static int pci_default_setup(struct serial_private*,
61 const struct pciserial_board*, struct uart_port*, int);
62
63 static void moan_device(const char *str, struct pci_dev *dev)
64 {
65 printk(KERN_WARNING
66 "%s: %s\n"
67 "Please send the output of lspci -vv, this\n"
68 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
69 "manufacturer and name of serial board or\n"
70 "modem board to rmk+serial@arm.linux.org.uk.\n",
71 pci_name(dev), str, dev->vendor, dev->device,
72 dev->subsystem_vendor, dev->subsystem_device);
73 }
74
75 static int
76 setup_port(struct serial_private *priv, struct uart_port *port,
77 int bar, int offset, int regshift)
78 {
79 struct pci_dev *dev = priv->dev;
80 unsigned long base, len;
81
82 if (bar >= PCI_NUM_BAR_RESOURCES)
83 return -EINVAL;
84
85 base = pci_resource_start(dev, bar);
86
87 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
88 len = pci_resource_len(dev, bar);
89
90 if (!priv->remapped_bar[bar])
91 priv->remapped_bar[bar] = ioremap_nocache(base, len);
92 if (!priv->remapped_bar[bar])
93 return -ENOMEM;
94
95 port->iotype = UPIO_MEM;
96 port->iobase = 0;
97 port->mapbase = base + offset;
98 port->membase = priv->remapped_bar[bar] + offset;
99 port->regshift = regshift;
100 } else {
101 port->iotype = UPIO_PORT;
102 port->iobase = base + offset;
103 port->mapbase = 0;
104 port->membase = NULL;
105 port->regshift = 0;
106 }
107 return 0;
108 }
109
110 /*
111 * ADDI-DATA GmbH communication cards <info@addi-data.com>
112 */
113 static int addidata_apci7800_setup(struct serial_private *priv,
114 const struct pciserial_board *board,
115 struct uart_port *port, int idx)
116 {
117 unsigned int bar = 0, offset = board->first_offset;
118 bar = FL_GET_BASE(board->flags);
119
120 if (idx < 2) {
121 offset += idx * board->uart_offset;
122 } else if ((idx >= 2) && (idx < 4)) {
123 bar += 1;
124 offset += ((idx - 2) * board->uart_offset);
125 } else if ((idx >= 4) && (idx < 6)) {
126 bar += 2;
127 offset += ((idx - 4) * board->uart_offset);
128 } else if (idx >= 6) {
129 bar += 3;
130 offset += ((idx - 6) * board->uart_offset);
131 }
132
133 return setup_port(priv, port, bar, offset, board->reg_shift);
134 }
135
136 /*
137 * AFAVLAB uses a different mixture of BARs and offsets
138 * Not that ugly ;) -- HW
139 */
140 static int
141 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
142 struct uart_port *port, int idx)
143 {
144 unsigned int bar, offset = board->first_offset;
145
146 bar = FL_GET_BASE(board->flags);
147 if (idx < 4)
148 bar += idx;
149 else {
150 bar = 4;
151 offset += (idx - 4) * board->uart_offset;
152 }
153
154 return setup_port(priv, port, bar, offset, board->reg_shift);
155 }
156
157 /*
158 * HP's Remote Management Console. The Diva chip came in several
159 * different versions. N-class, L2000 and A500 have two Diva chips, each
160 * with 3 UARTs (the third UART on the second chip is unused). Superdome
161 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
162 * one Diva chip, but it has been expanded to 5 UARTs.
163 */
164 static int pci_hp_diva_init(struct pci_dev *dev)
165 {
166 int rc = 0;
167
168 switch (dev->subsystem_device) {
169 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
170 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
171 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
172 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
173 rc = 3;
174 break;
175 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
176 rc = 2;
177 break;
178 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
179 rc = 4;
180 break;
181 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
182 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
183 rc = 1;
184 break;
185 }
186
187 return rc;
188 }
189
190 /*
191 * HP's Diva chip puts the 4th/5th serial port further out, and
192 * some serial ports are supposed to be hidden on certain models.
193 */
194 static int
195 pci_hp_diva_setup(struct serial_private *priv,
196 const struct pciserial_board *board,
197 struct uart_port *port, int idx)
198 {
199 unsigned int offset = board->first_offset;
200 unsigned int bar = FL_GET_BASE(board->flags);
201
202 switch (priv->dev->subsystem_device) {
203 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
204 if (idx == 3)
205 idx++;
206 break;
207 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
208 if (idx > 0)
209 idx++;
210 if (idx > 2)
211 idx++;
212 break;
213 }
214 if (idx > 2)
215 offset = 0x18;
216
217 offset += idx * board->uart_offset;
218
219 return setup_port(priv, port, bar, offset, board->reg_shift);
220 }
221
222 /*
223 * Added for EKF Intel i960 serial boards
224 */
225 static int pci_inteli960ni_init(struct pci_dev *dev)
226 {
227 unsigned long oldval;
228
229 if (!(dev->subsystem_device & 0x1000))
230 return -ENODEV;
231
232 /* is firmware started? */
233 pci_read_config_dword(dev, 0x44, (void *)&oldval);
234 if (oldval == 0x00001000L) { /* RESET value */
235 printk(KERN_DEBUG "Local i960 firmware missing");
236 return -ENODEV;
237 }
238 return 0;
239 }
240
241 /*
242 * Some PCI serial cards using the PLX 9050 PCI interface chip require
243 * that the card interrupt be explicitly enabled or disabled. This
244 * seems to be mainly needed on card using the PLX which also use I/O
245 * mapped memory.
246 */
247 static int pci_plx9050_init(struct pci_dev *dev)
248 {
249 u8 irq_config;
250 void __iomem *p;
251
252 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
253 moan_device("no memory in bar 0", dev);
254 return 0;
255 }
256
257 irq_config = 0x41;
258 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
259 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
260 irq_config = 0x43;
261
262 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
263 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
264 /*
265 * As the megawolf cards have the int pins active
266 * high, and have 2 UART chips, both ints must be
267 * enabled on the 9050. Also, the UARTS are set in
268 * 16450 mode by default, so we have to enable the
269 * 16C950 'enhanced' mode so that we can use the
270 * deep FIFOs
271 */
272 irq_config = 0x5b;
273 /*
274 * enable/disable interrupts
275 */
276 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
277 if (p == NULL)
278 return -ENOMEM;
279 writel(irq_config, p + 0x4c);
280
281 /*
282 * Read the register back to ensure that it took effect.
283 */
284 readl(p + 0x4c);
285 iounmap(p);
286
287 return 0;
288 }
289
290 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
291 {
292 u8 __iomem *p;
293
294 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
295 return;
296
297 /*
298 * disable interrupts
299 */
300 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
301 if (p != NULL) {
302 writel(0, p + 0x4c);
303
304 /*
305 * Read the register back to ensure that it took effect.
306 */
307 readl(p + 0x4c);
308 iounmap(p);
309 }
310 }
311
312 #define NI8420_INT_ENABLE_REG 0x38
313 #define NI8420_INT_ENABLE_BIT 0x2000
314
315 static void __devexit pci_ni8420_exit(struct pci_dev *dev)
316 {
317 void __iomem *p;
318 unsigned long base, len;
319 unsigned int bar = 0;
320
321 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
322 moan_device("no memory in bar", dev);
323 return;
324 }
325
326 base = pci_resource_start(dev, bar);
327 len = pci_resource_len(dev, bar);
328 p = ioremap_nocache(base, len);
329 if (p == NULL)
330 return;
331
332 /* Disable the CPU Interrupt */
333 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
334 p + NI8420_INT_ENABLE_REG);
335 iounmap(p);
336 }
337
338
339 /* MITE registers */
340 #define MITE_IOWBSR1 0xc4
341 #define MITE_IOWCR1 0xf4
342 #define MITE_LCIMR1 0x08
343 #define MITE_LCIMR2 0x10
344
345 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
346
347 static void __devexit pci_ni8430_exit(struct pci_dev *dev)
348 {
349 void __iomem *p;
350 unsigned long base, len;
351 unsigned int bar = 0;
352
353 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
354 moan_device("no memory in bar", dev);
355 return;
356 }
357
358 base = pci_resource_start(dev, bar);
359 len = pci_resource_len(dev, bar);
360 p = ioremap_nocache(base, len);
361 if (p == NULL)
362 return;
363
364 /* Disable the CPU Interrupt */
365 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
366 iounmap(p);
367 }
368
369 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
370 static int
371 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
372 struct uart_port *port, int idx)
373 {
374 unsigned int bar, offset = board->first_offset;
375
376 bar = 0;
377
378 if (idx < 4) {
379 /* first four channels map to 0, 0x100, 0x200, 0x300 */
380 offset += idx * board->uart_offset;
381 } else if (idx < 8) {
382 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
383 offset += idx * board->uart_offset + 0xC00;
384 } else /* we have only 8 ports on PMC-OCTALPRO */
385 return 1;
386
387 return setup_port(priv, port, bar, offset, board->reg_shift);
388 }
389
390 /*
391 * This does initialization for PMC OCTALPRO cards:
392 * maps the device memory, resets the UARTs (needed, bc
393 * if the module is removed and inserted again, the card
394 * is in the sleep mode) and enables global interrupt.
395 */
396
397 /* global control register offset for SBS PMC-OctalPro */
398 #define OCT_REG_CR_OFF 0x500
399
400 static int sbs_init(struct pci_dev *dev)
401 {
402 u8 __iomem *p;
403
404 p = pci_ioremap_bar(dev, 0);
405
406 if (p == NULL)
407 return -ENOMEM;
408 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
409 writeb(0x10, p + OCT_REG_CR_OFF);
410 udelay(50);
411 writeb(0x0, p + OCT_REG_CR_OFF);
412
413 /* Set bit-2 (INTENABLE) of Control Register */
414 writeb(0x4, p + OCT_REG_CR_OFF);
415 iounmap(p);
416
417 return 0;
418 }
419
420 /*
421 * Disables the global interrupt of PMC-OctalPro
422 */
423
424 static void __devexit sbs_exit(struct pci_dev *dev)
425 {
426 u8 __iomem *p;
427
428 p = pci_ioremap_bar(dev, 0);
429 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
430 if (p != NULL)
431 writeb(0, p + OCT_REG_CR_OFF);
432 iounmap(p);
433 }
434
435 /*
436 * SIIG serial cards have an PCI interface chip which also controls
437 * the UART clocking frequency. Each UART can be clocked independently
438 * (except cards equipped with 4 UARTs) and initial clocking settings
439 * are stored in the EEPROM chip. It can cause problems because this
440 * version of serial driver doesn't support differently clocked UART's
441 * on single PCI card. To prevent this, initialization functions set
442 * high frequency clocking for all UART's on given card. It is safe (I
443 * hope) because it doesn't touch EEPROM settings to prevent conflicts
444 * with other OSes (like M$ DOS).
445 *
446 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
447 *
448 * There is two family of SIIG serial cards with different PCI
449 * interface chip and different configuration methods:
450 * - 10x cards have control registers in IO and/or memory space;
451 * - 20x cards have control registers in standard PCI configuration space.
452 *
453 * Note: all 10x cards have PCI device ids 0x10..
454 * all 20x cards have PCI device ids 0x20..
455 *
456 * There are also Quartet Serial cards which use Oxford Semiconductor
457 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
458 *
459 * Note: some SIIG cards are probed by the parport_serial object.
460 */
461
462 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
463 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
464
465 static int pci_siig10x_init(struct pci_dev *dev)
466 {
467 u16 data;
468 void __iomem *p;
469
470 switch (dev->device & 0xfff8) {
471 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
472 data = 0xffdf;
473 break;
474 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
475 data = 0xf7ff;
476 break;
477 default: /* 1S1P, 4S */
478 data = 0xfffb;
479 break;
480 }
481
482 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
483 if (p == NULL)
484 return -ENOMEM;
485
486 writew(readw(p + 0x28) & data, p + 0x28);
487 readw(p + 0x28);
488 iounmap(p);
489 return 0;
490 }
491
492 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
493 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
494
495 static int pci_siig20x_init(struct pci_dev *dev)
496 {
497 u8 data;
498
499 /* Change clock frequency for the first UART. */
500 pci_read_config_byte(dev, 0x6f, &data);
501 pci_write_config_byte(dev, 0x6f, data & 0xef);
502
503 /* If this card has 2 UART, we have to do the same with second UART. */
504 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
505 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
506 pci_read_config_byte(dev, 0x73, &data);
507 pci_write_config_byte(dev, 0x73, data & 0xef);
508 }
509 return 0;
510 }
511
512 static int pci_siig_init(struct pci_dev *dev)
513 {
514 unsigned int type = dev->device & 0xff00;
515
516 if (type == 0x1000)
517 return pci_siig10x_init(dev);
518 else if (type == 0x2000)
519 return pci_siig20x_init(dev);
520
521 moan_device("Unknown SIIG card", dev);
522 return -ENODEV;
523 }
524
525 static int pci_siig_setup(struct serial_private *priv,
526 const struct pciserial_board *board,
527 struct uart_port *port, int idx)
528 {
529 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
530
531 if (idx > 3) {
532 bar = 4;
533 offset = (idx - 4) * 8;
534 }
535
536 return setup_port(priv, port, bar, offset, 0);
537 }
538
539 /*
540 * Timedia has an explosion of boards, and to avoid the PCI table from
541 * growing *huge*, we use this function to collapse some 70 entries
542 * in the PCI table into one, for sanity's and compactness's sake.
543 */
544 static const unsigned short timedia_single_port[] = {
545 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
546 };
547
548 static const unsigned short timedia_dual_port[] = {
549 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
550 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
551 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
552 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
553 0xD079, 0
554 };
555
556 static const unsigned short timedia_quad_port[] = {
557 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
558 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
559 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
560 0xB157, 0
561 };
562
563 static const unsigned short timedia_eight_port[] = {
564 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
565 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
566 };
567
568 static const struct timedia_struct {
569 int num;
570 const unsigned short *ids;
571 } timedia_data[] = {
572 { 1, timedia_single_port },
573 { 2, timedia_dual_port },
574 { 4, timedia_quad_port },
575 { 8, timedia_eight_port }
576 };
577
578 /*
579 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
580 * listing them individually, this driver merely grabs them all with
581 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
582 * and should be left free to be claimed by parport_serial instead.
583 */
584 static int pci_timedia_probe(struct pci_dev *dev)
585 {
586 /*
587 * Check the third digit of the subdevice ID
588 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
589 */
590 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
591 dev_info(&dev->dev,
592 "ignoring Timedia subdevice %04x for parport_serial\n",
593 dev->subsystem_device);
594 return -ENODEV;
595 }
596
597 return 0;
598 }
599
600 static int pci_timedia_init(struct pci_dev *dev)
601 {
602 const unsigned short *ids;
603 int i, j;
604
605 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
606 ids = timedia_data[i].ids;
607 for (j = 0; ids[j]; j++)
608 if (dev->subsystem_device == ids[j])
609 return timedia_data[i].num;
610 }
611 return 0;
612 }
613
614 /*
615 * Timedia/SUNIX uses a mixture of BARs and offsets
616 * Ugh, this is ugly as all hell --- TYT
617 */
618 static int
619 pci_timedia_setup(struct serial_private *priv,
620 const struct pciserial_board *board,
621 struct uart_port *port, int idx)
622 {
623 unsigned int bar = 0, offset = board->first_offset;
624
625 switch (idx) {
626 case 0:
627 bar = 0;
628 break;
629 case 1:
630 offset = board->uart_offset;
631 bar = 0;
632 break;
633 case 2:
634 bar = 1;
635 break;
636 case 3:
637 offset = board->uart_offset;
638 /* FALLTHROUGH */
639 case 4: /* BAR 2 */
640 case 5: /* BAR 3 */
641 case 6: /* BAR 4 */
642 case 7: /* BAR 5 */
643 bar = idx - 2;
644 }
645
646 return setup_port(priv, port, bar, offset, board->reg_shift);
647 }
648
649 /*
650 * Some Titan cards are also a little weird
651 */
652 static int
653 titan_400l_800l_setup(struct serial_private *priv,
654 const struct pciserial_board *board,
655 struct uart_port *port, int idx)
656 {
657 unsigned int bar, offset = board->first_offset;
658
659 switch (idx) {
660 case 0:
661 bar = 1;
662 break;
663 case 1:
664 bar = 2;
665 break;
666 default:
667 bar = 4;
668 offset = (idx - 2) * board->uart_offset;
669 }
670
671 return setup_port(priv, port, bar, offset, board->reg_shift);
672 }
673
674 static int pci_xircom_init(struct pci_dev *dev)
675 {
676 msleep(100);
677 return 0;
678 }
679
680 static int pci_ni8420_init(struct pci_dev *dev)
681 {
682 void __iomem *p;
683 unsigned long base, len;
684 unsigned int bar = 0;
685
686 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
687 moan_device("no memory in bar", dev);
688 return 0;
689 }
690
691 base = pci_resource_start(dev, bar);
692 len = pci_resource_len(dev, bar);
693 p = ioremap_nocache(base, len);
694 if (p == NULL)
695 return -ENOMEM;
696
697 /* Enable CPU Interrupt */
698 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
699 p + NI8420_INT_ENABLE_REG);
700
701 iounmap(p);
702 return 0;
703 }
704
705 #define MITE_IOWBSR1_WSIZE 0xa
706 #define MITE_IOWBSR1_WIN_OFFSET 0x800
707 #define MITE_IOWBSR1_WENAB (1 << 7)
708 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
709 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
710 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
711
712 static int pci_ni8430_init(struct pci_dev *dev)
713 {
714 void __iomem *p;
715 unsigned long base, len;
716 u32 device_window;
717 unsigned int bar = 0;
718
719 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
720 moan_device("no memory in bar", dev);
721 return 0;
722 }
723
724 base = pci_resource_start(dev, bar);
725 len = pci_resource_len(dev, bar);
726 p = ioremap_nocache(base, len);
727 if (p == NULL)
728 return -ENOMEM;
729
730 /* Set device window address and size in BAR0 */
731 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
732 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
733 writel(device_window, p + MITE_IOWBSR1);
734
735 /* Set window access to go to RAMSEL IO address space */
736 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
737 p + MITE_IOWCR1);
738
739 /* Enable IO Bus Interrupt 0 */
740 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
741
742 /* Enable CPU Interrupt */
743 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
744
745 iounmap(p);
746 return 0;
747 }
748
749 /* UART Port Control Register */
750 #define NI8430_PORTCON 0x0f
751 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
752
753 static int
754 pci_ni8430_setup(struct serial_private *priv,
755 const struct pciserial_board *board,
756 struct uart_port *port, int idx)
757 {
758 void __iomem *p;
759 unsigned long base, len;
760 unsigned int bar, offset = board->first_offset;
761
762 if (idx >= board->num_ports)
763 return 1;
764
765 bar = FL_GET_BASE(board->flags);
766 offset += idx * board->uart_offset;
767
768 base = pci_resource_start(priv->dev, bar);
769 len = pci_resource_len(priv->dev, bar);
770 p = ioremap_nocache(base, len);
771
772 /* enable the transceiver */
773 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
774 p + offset + NI8430_PORTCON);
775
776 iounmap(p);
777
778 return setup_port(priv, port, bar, offset, board->reg_shift);
779 }
780
781 static int pci_netmos_9900_setup(struct serial_private *priv,
782 const struct pciserial_board *board,
783 struct uart_port *port, int idx)
784 {
785 unsigned int bar;
786
787 if ((priv->dev->subsystem_device & 0xff00) == 0x3000) {
788 /* netmos apparently orders BARs by datasheet layout, so serial
789 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
790 */
791 bar = 3 * idx;
792
793 return setup_port(priv, port, bar, 0, board->reg_shift);
794 } else {
795 return pci_default_setup(priv, board, port, idx);
796 }
797 }
798
799 /* the 99xx series comes with a range of device IDs and a variety
800 * of capabilities:
801 *
802 * 9900 has varying capabilities and can cascade to sub-controllers
803 * (cascading should be purely internal)
804 * 9904 is hardwired with 4 serial ports
805 * 9912 and 9922 are hardwired with 2 serial ports
806 */
807 static int pci_netmos_9900_numports(struct pci_dev *dev)
808 {
809 unsigned int c = dev->class;
810 unsigned int pi;
811 unsigned short sub_serports;
812
813 pi = (c & 0xff);
814
815 if (pi == 2) {
816 return 1;
817 } else if ((pi == 0) &&
818 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
819 /* two possibilities: 0x30ps encodes number of parallel and
820 * serial ports, or 0x1000 indicates *something*. This is not
821 * immediately obvious, since the 2s1p+4s configuration seems
822 * to offer all functionality on functions 0..2, while still
823 * advertising the same function 3 as the 4s+2s1p config.
824 */
825 sub_serports = dev->subsystem_device & 0xf;
826 if (sub_serports > 0) {
827 return sub_serports;
828 } else {
829 printk(KERN_NOTICE "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
830 return 0;
831 }
832 }
833
834 moan_device("unknown NetMos/Mostech program interface", dev);
835 return 0;
836 }
837
838 static int pci_netmos_init(struct pci_dev *dev)
839 {
840 /* subdevice 0x00PS means <P> parallel, <S> serial */
841 unsigned int num_serial = dev->subsystem_device & 0xf;
842
843 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
844 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
845 return 0;
846
847 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
848 dev->subsystem_device == 0x0299)
849 return 0;
850
851 switch (dev->device) { /* FALLTHROUGH on all */
852 case PCI_DEVICE_ID_NETMOS_9904:
853 case PCI_DEVICE_ID_NETMOS_9912:
854 case PCI_DEVICE_ID_NETMOS_9922:
855 case PCI_DEVICE_ID_NETMOS_9900:
856 num_serial = pci_netmos_9900_numports(dev);
857 break;
858
859 default:
860 if (num_serial == 0 ) {
861 moan_device("unknown NetMos/Mostech device", dev);
862 }
863 }
864
865 if (num_serial == 0)
866 return -ENODEV;
867
868 return num_serial;
869 }
870
871 /*
872 * These chips are available with optionally one parallel port and up to
873 * two serial ports. Unfortunately they all have the same product id.
874 *
875 * Basic configuration is done over a region of 32 I/O ports. The base
876 * ioport is called INTA or INTC, depending on docs/other drivers.
877 *
878 * The region of the 32 I/O ports is configured in POSIO0R...
879 */
880
881 /* registers */
882 #define ITE_887x_MISCR 0x9c
883 #define ITE_887x_INTCBAR 0x78
884 #define ITE_887x_UARTBAR 0x7c
885 #define ITE_887x_PS0BAR 0x10
886 #define ITE_887x_POSIO0 0x60
887
888 /* I/O space size */
889 #define ITE_887x_IOSIZE 32
890 /* I/O space size (bits 26-24; 8 bytes = 011b) */
891 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
892 /* I/O space size (bits 26-24; 32 bytes = 101b) */
893 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
894 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
895 #define ITE_887x_POSIO_SPEED (3 << 29)
896 /* enable IO_Space bit */
897 #define ITE_887x_POSIO_ENABLE (1 << 31)
898
899 static int pci_ite887x_init(struct pci_dev *dev)
900 {
901 /* inta_addr are the configuration addresses of the ITE */
902 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
903 0x200, 0x280, 0 };
904 int ret, i, type;
905 struct resource *iobase = NULL;
906 u32 miscr, uartbar, ioport;
907
908 /* search for the base-ioport */
909 i = 0;
910 while (inta_addr[i] && iobase == NULL) {
911 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
912 "ite887x");
913 if (iobase != NULL) {
914 /* write POSIO0R - speed | size | ioport */
915 pci_write_config_dword(dev, ITE_887x_POSIO0,
916 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
917 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
918 /* write INTCBAR - ioport */
919 pci_write_config_dword(dev, ITE_887x_INTCBAR,
920 inta_addr[i]);
921 ret = inb(inta_addr[i]);
922 if (ret != 0xff) {
923 /* ioport connected */
924 break;
925 }
926 release_region(iobase->start, ITE_887x_IOSIZE);
927 iobase = NULL;
928 }
929 i++;
930 }
931
932 if (!inta_addr[i]) {
933 printk(KERN_ERR "ite887x: could not find iobase\n");
934 return -ENODEV;
935 }
936
937 /* start of undocumented type checking (see parport_pc.c) */
938 type = inb(iobase->start + 0x18) & 0x0f;
939
940 switch (type) {
941 case 0x2: /* ITE8871 (1P) */
942 case 0xa: /* ITE8875 (1P) */
943 ret = 0;
944 break;
945 case 0xe: /* ITE8872 (2S1P) */
946 ret = 2;
947 break;
948 case 0x6: /* ITE8873 (1S) */
949 ret = 1;
950 break;
951 case 0x8: /* ITE8874 (2S) */
952 ret = 2;
953 break;
954 default:
955 moan_device("Unknown ITE887x", dev);
956 ret = -ENODEV;
957 }
958
959 /* configure all serial ports */
960 for (i = 0; i < ret; i++) {
961 /* read the I/O port from the device */
962 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
963 &ioport);
964 ioport &= 0x0000FF00; /* the actual base address */
965 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
966 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
967 ITE_887x_POSIO_IOSIZE_8 | ioport);
968
969 /* write the ioport to the UARTBAR */
970 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
971 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
972 uartbar |= (ioport << (16 * i)); /* set the ioport */
973 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
974
975 /* get current config */
976 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
977 /* disable interrupts (UARTx_Routing[3:0]) */
978 miscr &= ~(0xf << (12 - 4 * i));
979 /* activate the UART (UARTx_En) */
980 miscr |= 1 << (23 - i);
981 /* write new config with activated UART */
982 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
983 }
984
985 if (ret <= 0) {
986 /* the device has no UARTs if we get here */
987 release_region(iobase->start, ITE_887x_IOSIZE);
988 }
989
990 return ret;
991 }
992
993 static void __devexit pci_ite887x_exit(struct pci_dev *dev)
994 {
995 u32 ioport;
996 /* the ioport is bit 0-15 in POSIO0R */
997 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
998 ioport &= 0xffff;
999 release_region(ioport, ITE_887x_IOSIZE);
1000 }
1001
1002 /*
1003 * Oxford Semiconductor Inc.
1004 * Check that device is part of the Tornado range of devices, then determine
1005 * the number of ports available on the device.
1006 */
1007 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1008 {
1009 u8 __iomem *p;
1010 unsigned long deviceID;
1011 unsigned int number_uarts = 0;
1012
1013 /* OxSemi Tornado devices are all 0xCxxx */
1014 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1015 (dev->device & 0xF000) != 0xC000)
1016 return 0;
1017
1018 p = pci_iomap(dev, 0, 5);
1019 if (p == NULL)
1020 return -ENOMEM;
1021
1022 deviceID = ioread32(p);
1023 /* Tornado device */
1024 if (deviceID == 0x07000200) {
1025 number_uarts = ioread8(p + 4);
1026 printk(KERN_DEBUG
1027 "%d ports detected on Oxford PCI Express device\n",
1028 number_uarts);
1029 }
1030 pci_iounmap(dev, p);
1031 return number_uarts;
1032 }
1033
1034 static int
1035 pci_default_setup(struct serial_private *priv,
1036 const struct pciserial_board *board,
1037 struct uart_port *port, int idx)
1038 {
1039 unsigned int bar, offset = board->first_offset, maxnr;
1040
1041 bar = FL_GET_BASE(board->flags);
1042 if (board->flags & FL_BASE_BARS)
1043 bar += idx;
1044 else
1045 offset += idx * board->uart_offset;
1046
1047 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1048 (board->reg_shift + 3);
1049
1050 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1051 return 1;
1052
1053 return setup_port(priv, port, bar, offset, board->reg_shift);
1054 }
1055
1056 static int
1057 ce4100_serial_setup(struct serial_private *priv,
1058 const struct pciserial_board *board,
1059 struct uart_port *port, int idx)
1060 {
1061 int ret;
1062
1063 ret = setup_port(priv, port, 0, 0, board->reg_shift);
1064 port->iotype = UPIO_MEM32;
1065 port->type = PORT_XSCALE;
1066 port->flags = (port->flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1067 port->regshift = 2;
1068
1069 return ret;
1070 }
1071
1072 static int
1073 pci_omegapci_setup(struct serial_private *priv,
1074 const struct pciserial_board *board,
1075 struct uart_port *port, int idx)
1076 {
1077 return setup_port(priv, port, 2, idx * 8, 0);
1078 }
1079
1080 static int
1081 pci_brcm_trumanage_setup(struct serial_private *priv,
1082 const struct pciserial_board *board,
1083 struct uart_8250_port *port, int idx)
1084 {
1085 int ret = pci_default_setup(priv, board, port, idx);
1086
1087 port->port.type = PORT_BRCM_TRUMANAGE;
1088 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1089 return ret;
1090 }
1091
1092 static int skip_tx_en_setup(struct serial_private *priv,
1093 const struct pciserial_board *board,
1094 struct uart_port *port, int idx)
1095 {
1096 port->flags |= UPF_NO_TXEN_TEST;
1097 printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
1098 "[%04x:%04x] subsystem [%04x:%04x]\n",
1099 priv->dev->vendor,
1100 priv->dev->device,
1101 priv->dev->subsystem_vendor,
1102 priv->dev->subsystem_device);
1103
1104 return pci_default_setup(priv, board, port, idx);
1105 }
1106
1107 static int kt_serial_setup(struct serial_private *priv,
1108 const struct pciserial_board *board,
1109 struct uart_port *port, int idx)
1110 {
1111 port->flags |= UPF_BUG_THRE;
1112 return skip_tx_en_setup(priv, board, port, idx);
1113 }
1114
1115 static int pci_eg20t_init(struct pci_dev *dev)
1116 {
1117 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1118 return -ENODEV;
1119 #else
1120 return 0;
1121 #endif
1122 }
1123
1124 static int
1125 pci_xr17c154_setup(struct serial_private *priv,
1126 const struct pciserial_board *board,
1127 struct uart_port *port, int idx)
1128 {
1129 port->flags |= UPF_EXAR_EFR;
1130 return pci_default_setup(priv, board, port, idx);
1131 }
1132
1133 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1134 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1135 #define PCI_DEVICE_ID_OCTPRO 0x0001
1136 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1137 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1138 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1139 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1140 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1141 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
1142 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1143 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1144 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1145 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1146 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1147 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1148 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1149 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1150 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1151 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1152 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1153 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1154 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1155 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1156 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1157 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
1158 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1159 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1160 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1161 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1162 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1163 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1164 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1165 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1166 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1167
1168 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1169 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1170 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1171
1172 /*
1173 * Master list of serial port init/setup/exit quirks.
1174 * This does not describe the general nature of the port.
1175 * (ie, baud base, number and location of ports, etc)
1176 *
1177 * This list is ordered alphabetically by vendor then device.
1178 * Specific entries must come before more generic entries.
1179 */
1180 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1181 /*
1182 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1183 */
1184 {
1185 .vendor = PCI_VENDOR_ID_ADDIDATA_OLD,
1186 .device = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1187 .subvendor = PCI_ANY_ID,
1188 .subdevice = PCI_ANY_ID,
1189 .setup = addidata_apci7800_setup,
1190 },
1191 /*
1192 * AFAVLAB cards - these may be called via parport_serial
1193 * It is not clear whether this applies to all products.
1194 */
1195 {
1196 .vendor = PCI_VENDOR_ID_AFAVLAB,
1197 .device = PCI_ANY_ID,
1198 .subvendor = PCI_ANY_ID,
1199 .subdevice = PCI_ANY_ID,
1200 .setup = afavlab_setup,
1201 },
1202 /*
1203 * HP Diva
1204 */
1205 {
1206 .vendor = PCI_VENDOR_ID_HP,
1207 .device = PCI_DEVICE_ID_HP_DIVA,
1208 .subvendor = PCI_ANY_ID,
1209 .subdevice = PCI_ANY_ID,
1210 .init = pci_hp_diva_init,
1211 .setup = pci_hp_diva_setup,
1212 },
1213 /*
1214 * Intel
1215 */
1216 {
1217 .vendor = PCI_VENDOR_ID_INTEL,
1218 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1219 .subvendor = 0xe4bf,
1220 .subdevice = PCI_ANY_ID,
1221 .init = pci_inteli960ni_init,
1222 .setup = pci_default_setup,
1223 },
1224 {
1225 .vendor = PCI_VENDOR_ID_INTEL,
1226 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1227 .subvendor = PCI_ANY_ID,
1228 .subdevice = PCI_ANY_ID,
1229 .setup = skip_tx_en_setup,
1230 },
1231 {
1232 .vendor = PCI_VENDOR_ID_INTEL,
1233 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1234 .subvendor = PCI_ANY_ID,
1235 .subdevice = PCI_ANY_ID,
1236 .setup = skip_tx_en_setup,
1237 },
1238 {
1239 .vendor = PCI_VENDOR_ID_INTEL,
1240 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1241 .subvendor = PCI_ANY_ID,
1242 .subdevice = PCI_ANY_ID,
1243 .setup = skip_tx_en_setup,
1244 },
1245 {
1246 .vendor = PCI_VENDOR_ID_INTEL,
1247 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1248 .subvendor = PCI_ANY_ID,
1249 .subdevice = PCI_ANY_ID,
1250 .setup = ce4100_serial_setup,
1251 },
1252 {
1253 .vendor = PCI_VENDOR_ID_INTEL,
1254 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1255 .subvendor = PCI_ANY_ID,
1256 .subdevice = PCI_ANY_ID,
1257 .setup = kt_serial_setup,
1258 },
1259 /*
1260 * ITE
1261 */
1262 {
1263 .vendor = PCI_VENDOR_ID_ITE,
1264 .device = PCI_DEVICE_ID_ITE_8872,
1265 .subvendor = PCI_ANY_ID,
1266 .subdevice = PCI_ANY_ID,
1267 .init = pci_ite887x_init,
1268 .setup = pci_default_setup,
1269 .exit = __devexit_p(pci_ite887x_exit),
1270 },
1271 /*
1272 * National Instruments
1273 */
1274 {
1275 .vendor = PCI_VENDOR_ID_NI,
1276 .device = PCI_DEVICE_ID_NI_PCI23216,
1277 .subvendor = PCI_ANY_ID,
1278 .subdevice = PCI_ANY_ID,
1279 .init = pci_ni8420_init,
1280 .setup = pci_default_setup,
1281 .exit = __devexit_p(pci_ni8420_exit),
1282 },
1283 {
1284 .vendor = PCI_VENDOR_ID_NI,
1285 .device = PCI_DEVICE_ID_NI_PCI2328,
1286 .subvendor = PCI_ANY_ID,
1287 .subdevice = PCI_ANY_ID,
1288 .init = pci_ni8420_init,
1289 .setup = pci_default_setup,
1290 .exit = __devexit_p(pci_ni8420_exit),
1291 },
1292 {
1293 .vendor = PCI_VENDOR_ID_NI,
1294 .device = PCI_DEVICE_ID_NI_PCI2324,
1295 .subvendor = PCI_ANY_ID,
1296 .subdevice = PCI_ANY_ID,
1297 .init = pci_ni8420_init,
1298 .setup = pci_default_setup,
1299 .exit = __devexit_p(pci_ni8420_exit),
1300 },
1301 {
1302 .vendor = PCI_VENDOR_ID_NI,
1303 .device = PCI_DEVICE_ID_NI_PCI2322,
1304 .subvendor = PCI_ANY_ID,
1305 .subdevice = PCI_ANY_ID,
1306 .init = pci_ni8420_init,
1307 .setup = pci_default_setup,
1308 .exit = __devexit_p(pci_ni8420_exit),
1309 },
1310 {
1311 .vendor = PCI_VENDOR_ID_NI,
1312 .device = PCI_DEVICE_ID_NI_PCI2324I,
1313 .subvendor = PCI_ANY_ID,
1314 .subdevice = PCI_ANY_ID,
1315 .init = pci_ni8420_init,
1316 .setup = pci_default_setup,
1317 .exit = __devexit_p(pci_ni8420_exit),
1318 },
1319 {
1320 .vendor = PCI_VENDOR_ID_NI,
1321 .device = PCI_DEVICE_ID_NI_PCI2322I,
1322 .subvendor = PCI_ANY_ID,
1323 .subdevice = PCI_ANY_ID,
1324 .init = pci_ni8420_init,
1325 .setup = pci_default_setup,
1326 .exit = __devexit_p(pci_ni8420_exit),
1327 },
1328 {
1329 .vendor = PCI_VENDOR_ID_NI,
1330 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1331 .subvendor = PCI_ANY_ID,
1332 .subdevice = PCI_ANY_ID,
1333 .init = pci_ni8420_init,
1334 .setup = pci_default_setup,
1335 .exit = __devexit_p(pci_ni8420_exit),
1336 },
1337 {
1338 .vendor = PCI_VENDOR_ID_NI,
1339 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1340 .subvendor = PCI_ANY_ID,
1341 .subdevice = PCI_ANY_ID,
1342 .init = pci_ni8420_init,
1343 .setup = pci_default_setup,
1344 .exit = __devexit_p(pci_ni8420_exit),
1345 },
1346 {
1347 .vendor = PCI_VENDOR_ID_NI,
1348 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1349 .subvendor = PCI_ANY_ID,
1350 .subdevice = PCI_ANY_ID,
1351 .init = pci_ni8420_init,
1352 .setup = pci_default_setup,
1353 .exit = __devexit_p(pci_ni8420_exit),
1354 },
1355 {
1356 .vendor = PCI_VENDOR_ID_NI,
1357 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1358 .subvendor = PCI_ANY_ID,
1359 .subdevice = PCI_ANY_ID,
1360 .init = pci_ni8420_init,
1361 .setup = pci_default_setup,
1362 .exit = __devexit_p(pci_ni8420_exit),
1363 },
1364 {
1365 .vendor = PCI_VENDOR_ID_NI,
1366 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1367 .subvendor = PCI_ANY_ID,
1368 .subdevice = PCI_ANY_ID,
1369 .init = pci_ni8420_init,
1370 .setup = pci_default_setup,
1371 .exit = __devexit_p(pci_ni8420_exit),
1372 },
1373 {
1374 .vendor = PCI_VENDOR_ID_NI,
1375 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1376 .subvendor = PCI_ANY_ID,
1377 .subdevice = PCI_ANY_ID,
1378 .init = pci_ni8420_init,
1379 .setup = pci_default_setup,
1380 .exit = __devexit_p(pci_ni8420_exit),
1381 },
1382 {
1383 .vendor = PCI_VENDOR_ID_NI,
1384 .device = PCI_ANY_ID,
1385 .subvendor = PCI_ANY_ID,
1386 .subdevice = PCI_ANY_ID,
1387 .init = pci_ni8430_init,
1388 .setup = pci_ni8430_setup,
1389 .exit = __devexit_p(pci_ni8430_exit),
1390 },
1391 /*
1392 * Panacom
1393 */
1394 {
1395 .vendor = PCI_VENDOR_ID_PANACOM,
1396 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1397 .subvendor = PCI_ANY_ID,
1398 .subdevice = PCI_ANY_ID,
1399 .init = pci_plx9050_init,
1400 .setup = pci_default_setup,
1401 .exit = __devexit_p(pci_plx9050_exit),
1402 },
1403 {
1404 .vendor = PCI_VENDOR_ID_PANACOM,
1405 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1406 .subvendor = PCI_ANY_ID,
1407 .subdevice = PCI_ANY_ID,
1408 .init = pci_plx9050_init,
1409 .setup = pci_default_setup,
1410 .exit = __devexit_p(pci_plx9050_exit),
1411 },
1412 /*
1413 * PLX
1414 */
1415 {
1416 .vendor = PCI_VENDOR_ID_PLX,
1417 .device = PCI_DEVICE_ID_PLX_9030,
1418 .subvendor = PCI_SUBVENDOR_ID_PERLE,
1419 .subdevice = PCI_ANY_ID,
1420 .setup = pci_default_setup,
1421 },
1422 {
1423 .vendor = PCI_VENDOR_ID_PLX,
1424 .device = PCI_DEVICE_ID_PLX_9050,
1425 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
1426 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
1427 .init = pci_plx9050_init,
1428 .setup = pci_default_setup,
1429 .exit = __devexit_p(pci_plx9050_exit),
1430 },
1431 {
1432 .vendor = PCI_VENDOR_ID_PLX,
1433 .device = PCI_DEVICE_ID_PLX_9050,
1434 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
1435 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1436 .init = pci_plx9050_init,
1437 .setup = pci_default_setup,
1438 .exit = __devexit_p(pci_plx9050_exit),
1439 },
1440 {
1441 .vendor = PCI_VENDOR_ID_PLX,
1442 .device = PCI_DEVICE_ID_PLX_ROMULUS,
1443 .subvendor = PCI_VENDOR_ID_PLX,
1444 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
1445 .init = pci_plx9050_init,
1446 .setup = pci_default_setup,
1447 .exit = __devexit_p(pci_plx9050_exit),
1448 },
1449 /*
1450 * SBS Technologies, Inc., PMC-OCTALPRO 232
1451 */
1452 {
1453 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1454 .device = PCI_DEVICE_ID_OCTPRO,
1455 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1456 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
1457 .init = sbs_init,
1458 .setup = sbs_setup,
1459 .exit = __devexit_p(sbs_exit),
1460 },
1461 /*
1462 * SBS Technologies, Inc., PMC-OCTALPRO 422
1463 */
1464 {
1465 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1466 .device = PCI_DEVICE_ID_OCTPRO,
1467 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1468 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
1469 .init = sbs_init,
1470 .setup = sbs_setup,
1471 .exit = __devexit_p(sbs_exit),
1472 },
1473 /*
1474 * SBS Technologies, Inc., P-Octal 232
1475 */
1476 {
1477 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1478 .device = PCI_DEVICE_ID_OCTPRO,
1479 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1480 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
1481 .init = sbs_init,
1482 .setup = sbs_setup,
1483 .exit = __devexit_p(sbs_exit),
1484 },
1485 /*
1486 * SBS Technologies, Inc., P-Octal 422
1487 */
1488 {
1489 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1490 .device = PCI_DEVICE_ID_OCTPRO,
1491 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1492 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
1493 .init = sbs_init,
1494 .setup = sbs_setup,
1495 .exit = __devexit_p(sbs_exit),
1496 },
1497 /*
1498 * SIIG cards - these may be called via parport_serial
1499 */
1500 {
1501 .vendor = PCI_VENDOR_ID_SIIG,
1502 .device = PCI_ANY_ID,
1503 .subvendor = PCI_ANY_ID,
1504 .subdevice = PCI_ANY_ID,
1505 .init = pci_siig_init,
1506 .setup = pci_siig_setup,
1507 },
1508 /*
1509 * Titan cards
1510 */
1511 {
1512 .vendor = PCI_VENDOR_ID_TITAN,
1513 .device = PCI_DEVICE_ID_TITAN_400L,
1514 .subvendor = PCI_ANY_ID,
1515 .subdevice = PCI_ANY_ID,
1516 .setup = titan_400l_800l_setup,
1517 },
1518 {
1519 .vendor = PCI_VENDOR_ID_TITAN,
1520 .device = PCI_DEVICE_ID_TITAN_800L,
1521 .subvendor = PCI_ANY_ID,
1522 .subdevice = PCI_ANY_ID,
1523 .setup = titan_400l_800l_setup,
1524 },
1525 /*
1526 * Timedia cards
1527 */
1528 {
1529 .vendor = PCI_VENDOR_ID_TIMEDIA,
1530 .device = PCI_DEVICE_ID_TIMEDIA_1889,
1531 .subvendor = PCI_VENDOR_ID_TIMEDIA,
1532 .subdevice = PCI_ANY_ID,
1533 .probe = pci_timedia_probe,
1534 .init = pci_timedia_init,
1535 .setup = pci_timedia_setup,
1536 },
1537 {
1538 .vendor = PCI_VENDOR_ID_TIMEDIA,
1539 .device = PCI_ANY_ID,
1540 .subvendor = PCI_ANY_ID,
1541 .subdevice = PCI_ANY_ID,
1542 .setup = pci_timedia_setup,
1543 },
1544 /*
1545 * Exar cards
1546 */
1547 {
1548 .vendor = PCI_VENDOR_ID_EXAR,
1549 .device = PCI_DEVICE_ID_EXAR_XR17C152,
1550 .subvendor = PCI_ANY_ID,
1551 .subdevice = PCI_ANY_ID,
1552 .setup = pci_xr17c154_setup,
1553 },
1554 {
1555 .vendor = PCI_VENDOR_ID_EXAR,
1556 .device = PCI_DEVICE_ID_EXAR_XR17C154,
1557 .subvendor = PCI_ANY_ID,
1558 .subdevice = PCI_ANY_ID,
1559 .setup = pci_xr17c154_setup,
1560 },
1561 {
1562 .vendor = PCI_VENDOR_ID_EXAR,
1563 .device = PCI_DEVICE_ID_EXAR_XR17C158,
1564 .subvendor = PCI_ANY_ID,
1565 .subdevice = PCI_ANY_ID,
1566 .setup = pci_xr17c154_setup,
1567 },
1568 /*
1569 * Xircom cards
1570 */
1571 {
1572 .vendor = PCI_VENDOR_ID_XIRCOM,
1573 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1574 .subvendor = PCI_ANY_ID,
1575 .subdevice = PCI_ANY_ID,
1576 .init = pci_xircom_init,
1577 .setup = pci_default_setup,
1578 },
1579 /*
1580 * Netmos cards - these may be called via parport_serial
1581 */
1582 {
1583 .vendor = PCI_VENDOR_ID_NETMOS,
1584 .device = PCI_ANY_ID,
1585 .subvendor = PCI_ANY_ID,
1586 .subdevice = PCI_ANY_ID,
1587 .init = pci_netmos_init,
1588 .setup = pci_netmos_9900_setup,
1589 },
1590 /*
1591 * For Oxford Semiconductor Tornado based devices
1592 */
1593 {
1594 .vendor = PCI_VENDOR_ID_OXSEMI,
1595 .device = PCI_ANY_ID,
1596 .subvendor = PCI_ANY_ID,
1597 .subdevice = PCI_ANY_ID,
1598 .init = pci_oxsemi_tornado_init,
1599 .setup = pci_default_setup,
1600 },
1601 {
1602 .vendor = PCI_VENDOR_ID_MAINPINE,
1603 .device = PCI_ANY_ID,
1604 .subvendor = PCI_ANY_ID,
1605 .subdevice = PCI_ANY_ID,
1606 .init = pci_oxsemi_tornado_init,
1607 .setup = pci_default_setup,
1608 },
1609 {
1610 .vendor = PCI_VENDOR_ID_DIGI,
1611 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
1612 .subvendor = PCI_SUBVENDOR_ID_IBM,
1613 .subdevice = PCI_ANY_ID,
1614 .init = pci_oxsemi_tornado_init,
1615 .setup = pci_default_setup,
1616 },
1617 {
1618 .vendor = PCI_VENDOR_ID_INTEL,
1619 .device = 0x8811,
1620 .subvendor = PCI_ANY_ID,
1621 .subdevice = PCI_ANY_ID,
1622 .init = pci_eg20t_init,
1623 .setup = pci_default_setup,
1624 },
1625 {
1626 .vendor = PCI_VENDOR_ID_INTEL,
1627 .device = 0x8812,
1628 .subvendor = PCI_ANY_ID,
1629 .subdevice = PCI_ANY_ID,
1630 .init = pci_eg20t_init,
1631 .setup = pci_default_setup,
1632 },
1633 {
1634 .vendor = PCI_VENDOR_ID_INTEL,
1635 .device = 0x8813,
1636 .subvendor = PCI_ANY_ID,
1637 .subdevice = PCI_ANY_ID,
1638 .init = pci_eg20t_init,
1639 .setup = pci_default_setup,
1640 },
1641 {
1642 .vendor = PCI_VENDOR_ID_INTEL,
1643 .device = 0x8814,
1644 .subvendor = PCI_ANY_ID,
1645 .subdevice = PCI_ANY_ID,
1646 .init = pci_eg20t_init,
1647 .setup = pci_default_setup,
1648 },
1649 {
1650 .vendor = 0x10DB,
1651 .device = 0x8027,
1652 .subvendor = PCI_ANY_ID,
1653 .subdevice = PCI_ANY_ID,
1654 .init = pci_eg20t_init,
1655 .setup = pci_default_setup,
1656 },
1657 {
1658 .vendor = 0x10DB,
1659 .device = 0x8028,
1660 .subvendor = PCI_ANY_ID,
1661 .subdevice = PCI_ANY_ID,
1662 .init = pci_eg20t_init,
1663 .setup = pci_default_setup,
1664 },
1665 {
1666 .vendor = 0x10DB,
1667 .device = 0x8029,
1668 .subvendor = PCI_ANY_ID,
1669 .subdevice = PCI_ANY_ID,
1670 .init = pci_eg20t_init,
1671 .setup = pci_default_setup,
1672 },
1673 {
1674 .vendor = 0x10DB,
1675 .device = 0x800C,
1676 .subvendor = PCI_ANY_ID,
1677 .subdevice = PCI_ANY_ID,
1678 .init = pci_eg20t_init,
1679 .setup = pci_default_setup,
1680 },
1681 {
1682 .vendor = 0x10DB,
1683 .device = 0x800D,
1684 .subvendor = PCI_ANY_ID,
1685 .subdevice = PCI_ANY_ID,
1686 .init = pci_eg20t_init,
1687 .setup = pci_default_setup,
1688 },
1689 /*
1690 * Cronyx Omega PCI (PLX-chip based)
1691 */
1692 {
1693 .vendor = PCI_VENDOR_ID_PLX,
1694 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
1695 .subvendor = PCI_ANY_ID,
1696 .subdevice = PCI_ANY_ID,
1697 .setup = pci_omegapci_setup,
1698 },
1699 /*
1700 * Broadcom TruManage (NetXtreme)
1701 */
1702 {
1703 .vendor = PCI_VENDOR_ID_BROADCOM,
1704 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
1705 .subvendor = PCI_ANY_ID,
1706 .subdevice = PCI_ANY_ID,
1707 .setup = pci_brcm_trumanage_setup,
1708 },
1709
1710 /*
1711 * Default "match everything" terminator entry
1712 */
1713 {
1714 .vendor = PCI_ANY_ID,
1715 .device = PCI_ANY_ID,
1716 .subvendor = PCI_ANY_ID,
1717 .subdevice = PCI_ANY_ID,
1718 .setup = pci_default_setup,
1719 }
1720 };
1721
1722 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1723 {
1724 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1725 }
1726
1727 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1728 {
1729 struct pci_serial_quirk *quirk;
1730
1731 for (quirk = pci_serial_quirks; ; quirk++)
1732 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1733 quirk_id_matches(quirk->device, dev->device) &&
1734 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1735 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
1736 break;
1737 return quirk;
1738 }
1739
1740 static inline int get_pci_irq(struct pci_dev *dev,
1741 const struct pciserial_board *board)
1742 {
1743 if (board->flags & FL_NOIRQ)
1744 return 0;
1745 else
1746 return dev->irq;
1747 }
1748
1749 /*
1750 * This is the configuration table for all of the PCI serial boards
1751 * which we support. It is directly indexed by the pci_board_num_t enum
1752 * value, which is encoded in the pci_device_id PCI probe table's
1753 * driver_data member.
1754 *
1755 * The makeup of these names are:
1756 * pbn_bn{_bt}_n_baud{_offsetinhex}
1757 *
1758 * bn = PCI BAR number
1759 * bt = Index using PCI BARs
1760 * n = number of serial ports
1761 * baud = baud rate
1762 * offsetinhex = offset for each sequential port (in hex)
1763 *
1764 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1765 *
1766 * Please note: in theory if n = 1, _bt infix should make no difference.
1767 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1768 */
1769 enum pci_board_num_t {
1770 pbn_default = 0,
1771
1772 pbn_b0_1_115200,
1773 pbn_b0_2_115200,
1774 pbn_b0_4_115200,
1775 pbn_b0_5_115200,
1776 pbn_b0_8_115200,
1777
1778 pbn_b0_1_921600,
1779 pbn_b0_2_921600,
1780 pbn_b0_4_921600,
1781
1782 pbn_b0_2_1130000,
1783
1784 pbn_b0_4_1152000,
1785
1786 pbn_b0_2_1843200,
1787 pbn_b0_4_1843200,
1788
1789 pbn_b0_2_1843200_200,
1790 pbn_b0_4_1843200_200,
1791 pbn_b0_8_1843200_200,
1792
1793 pbn_b0_1_4000000,
1794
1795 pbn_b0_bt_1_115200,
1796 pbn_b0_bt_2_115200,
1797 pbn_b0_bt_4_115200,
1798 pbn_b0_bt_8_115200,
1799
1800 pbn_b0_bt_1_460800,
1801 pbn_b0_bt_2_460800,
1802 pbn_b0_bt_4_460800,
1803
1804 pbn_b0_bt_1_921600,
1805 pbn_b0_bt_2_921600,
1806 pbn_b0_bt_4_921600,
1807 pbn_b0_bt_8_921600,
1808
1809 pbn_b1_1_115200,
1810 pbn_b1_2_115200,
1811 pbn_b1_4_115200,
1812 pbn_b1_8_115200,
1813 pbn_b1_16_115200,
1814
1815 pbn_b1_1_921600,
1816 pbn_b1_2_921600,
1817 pbn_b1_4_921600,
1818 pbn_b1_8_921600,
1819
1820 pbn_b1_2_1250000,
1821
1822 pbn_b1_bt_1_115200,
1823 pbn_b1_bt_2_115200,
1824 pbn_b1_bt_4_115200,
1825
1826 pbn_b1_bt_2_921600,
1827
1828 pbn_b1_1_1382400,
1829 pbn_b1_2_1382400,
1830 pbn_b1_4_1382400,
1831 pbn_b1_8_1382400,
1832
1833 pbn_b2_1_115200,
1834 pbn_b2_2_115200,
1835 pbn_b2_4_115200,
1836 pbn_b2_8_115200,
1837
1838 pbn_b2_1_460800,
1839 pbn_b2_4_460800,
1840 pbn_b2_8_460800,
1841 pbn_b2_16_460800,
1842
1843 pbn_b2_1_921600,
1844 pbn_b2_4_921600,
1845 pbn_b2_8_921600,
1846
1847 pbn_b2_8_1152000,
1848
1849 pbn_b2_bt_1_115200,
1850 pbn_b2_bt_2_115200,
1851 pbn_b2_bt_4_115200,
1852
1853 pbn_b2_bt_2_921600,
1854 pbn_b2_bt_4_921600,
1855
1856 pbn_b3_2_115200,
1857 pbn_b3_4_115200,
1858 pbn_b3_8_115200,
1859
1860 pbn_b4_bt_2_921600,
1861 pbn_b4_bt_4_921600,
1862 pbn_b4_bt_8_921600,
1863
1864 /*
1865 * Board-specific versions.
1866 */
1867 pbn_panacom,
1868 pbn_panacom2,
1869 pbn_panacom4,
1870 pbn_exsys_4055,
1871 pbn_plx_romulus,
1872 pbn_oxsemi,
1873 pbn_oxsemi_1_4000000,
1874 pbn_oxsemi_2_4000000,
1875 pbn_oxsemi_4_4000000,
1876 pbn_oxsemi_8_4000000,
1877 pbn_intel_i960,
1878 pbn_sgi_ioc3,
1879 pbn_computone_4,
1880 pbn_computone_6,
1881 pbn_computone_8,
1882 pbn_sbsxrsio,
1883 pbn_exar_XR17C152,
1884 pbn_exar_XR17C154,
1885 pbn_exar_XR17C158,
1886 pbn_exar_ibm_saturn,
1887 pbn_pasemi_1682M,
1888 pbn_ni8430_2,
1889 pbn_ni8430_4,
1890 pbn_ni8430_8,
1891 pbn_ni8430_16,
1892 pbn_ADDIDATA_PCIe_1_3906250,
1893 pbn_ADDIDATA_PCIe_2_3906250,
1894 pbn_ADDIDATA_PCIe_4_3906250,
1895 pbn_ADDIDATA_PCIe_8_3906250,
1896 pbn_ce4100_1_115200,
1897 pbn_omegapci,
1898 pbn_NETMOS9900_2s_115200,
1899 pbn_brcm_trumanage,
1900 };
1901
1902 /*
1903 * uart_offset - the space between channels
1904 * reg_shift - describes how the UART registers are mapped
1905 * to PCI memory by the card.
1906 * For example IER register on SBS, Inc. PMC-OctPro is located at
1907 * offset 0x10 from the UART base, while UART_IER is defined as 1
1908 * in include/linux/serial_reg.h,
1909 * see first lines of serial_in() and serial_out() in 8250.c
1910 */
1911
1912 static struct pciserial_board pci_boards[] __devinitdata = {
1913 [pbn_default] = {
1914 .flags = FL_BASE0,
1915 .num_ports = 1,
1916 .base_baud = 115200,
1917 .uart_offset = 8,
1918 },
1919 [pbn_b0_1_115200] = {
1920 .flags = FL_BASE0,
1921 .num_ports = 1,
1922 .base_baud = 115200,
1923 .uart_offset = 8,
1924 },
1925 [pbn_b0_2_115200] = {
1926 .flags = FL_BASE0,
1927 .num_ports = 2,
1928 .base_baud = 115200,
1929 .uart_offset = 8,
1930 },
1931 [pbn_b0_4_115200] = {
1932 .flags = FL_BASE0,
1933 .num_ports = 4,
1934 .base_baud = 115200,
1935 .uart_offset = 8,
1936 },
1937 [pbn_b0_5_115200] = {
1938 .flags = FL_BASE0,
1939 .num_ports = 5,
1940 .base_baud = 115200,
1941 .uart_offset = 8,
1942 },
1943 [pbn_b0_8_115200] = {
1944 .flags = FL_BASE0,
1945 .num_ports = 8,
1946 .base_baud = 115200,
1947 .uart_offset = 8,
1948 },
1949 [pbn_b0_1_921600] = {
1950 .flags = FL_BASE0,
1951 .num_ports = 1,
1952 .base_baud = 921600,
1953 .uart_offset = 8,
1954 },
1955 [pbn_b0_2_921600] = {
1956 .flags = FL_BASE0,
1957 .num_ports = 2,
1958 .base_baud = 921600,
1959 .uart_offset = 8,
1960 },
1961 [pbn_b0_4_921600] = {
1962 .flags = FL_BASE0,
1963 .num_ports = 4,
1964 .base_baud = 921600,
1965 .uart_offset = 8,
1966 },
1967
1968 [pbn_b0_2_1130000] = {
1969 .flags = FL_BASE0,
1970 .num_ports = 2,
1971 .base_baud = 1130000,
1972 .uart_offset = 8,
1973 },
1974
1975 [pbn_b0_4_1152000] = {
1976 .flags = FL_BASE0,
1977 .num_ports = 4,
1978 .base_baud = 1152000,
1979 .uart_offset = 8,
1980 },
1981
1982 [pbn_b0_2_1843200] = {
1983 .flags = FL_BASE0,
1984 .num_ports = 2,
1985 .base_baud = 1843200,
1986 .uart_offset = 8,
1987 },
1988 [pbn_b0_4_1843200] = {
1989 .flags = FL_BASE0,
1990 .num_ports = 4,
1991 .base_baud = 1843200,
1992 .uart_offset = 8,
1993 },
1994
1995 [pbn_b0_2_1843200_200] = {
1996 .flags = FL_BASE0,
1997 .num_ports = 2,
1998 .base_baud = 1843200,
1999 .uart_offset = 0x200,
2000 },
2001 [pbn_b0_4_1843200_200] = {
2002 .flags = FL_BASE0,
2003 .num_ports = 4,
2004 .base_baud = 1843200,
2005 .uart_offset = 0x200,
2006 },
2007 [pbn_b0_8_1843200_200] = {
2008 .flags = FL_BASE0,
2009 .num_ports = 8,
2010 .base_baud = 1843200,
2011 .uart_offset = 0x200,
2012 },
2013 [pbn_b0_1_4000000] = {
2014 .flags = FL_BASE0,
2015 .num_ports = 1,
2016 .base_baud = 4000000,
2017 .uart_offset = 8,
2018 },
2019
2020 [pbn_b0_bt_1_115200] = {
2021 .flags = FL_BASE0|FL_BASE_BARS,
2022 .num_ports = 1,
2023 .base_baud = 115200,
2024 .uart_offset = 8,
2025 },
2026 [pbn_b0_bt_2_115200] = {
2027 .flags = FL_BASE0|FL_BASE_BARS,
2028 .num_ports = 2,
2029 .base_baud = 115200,
2030 .uart_offset = 8,
2031 },
2032 [pbn_b0_bt_4_115200] = {
2033 .flags = FL_BASE0|FL_BASE_BARS,
2034 .num_ports = 4,
2035 .base_baud = 115200,
2036 .uart_offset = 8,
2037 },
2038 [pbn_b0_bt_8_115200] = {
2039 .flags = FL_BASE0|FL_BASE_BARS,
2040 .num_ports = 8,
2041 .base_baud = 115200,
2042 .uart_offset = 8,
2043 },
2044
2045 [pbn_b0_bt_1_460800] = {
2046 .flags = FL_BASE0|FL_BASE_BARS,
2047 .num_ports = 1,
2048 .base_baud = 460800,
2049 .uart_offset = 8,
2050 },
2051 [pbn_b0_bt_2_460800] = {
2052 .flags = FL_BASE0|FL_BASE_BARS,
2053 .num_ports = 2,
2054 .base_baud = 460800,
2055 .uart_offset = 8,
2056 },
2057 [pbn_b0_bt_4_460800] = {
2058 .flags = FL_BASE0|FL_BASE_BARS,
2059 .num_ports = 4,
2060 .base_baud = 460800,
2061 .uart_offset = 8,
2062 },
2063
2064 [pbn_b0_bt_1_921600] = {
2065 .flags = FL_BASE0|FL_BASE_BARS,
2066 .num_ports = 1,
2067 .base_baud = 921600,
2068 .uart_offset = 8,
2069 },
2070 [pbn_b0_bt_2_921600] = {
2071 .flags = FL_BASE0|FL_BASE_BARS,
2072 .num_ports = 2,
2073 .base_baud = 921600,
2074 .uart_offset = 8,
2075 },
2076 [pbn_b0_bt_4_921600] = {
2077 .flags = FL_BASE0|FL_BASE_BARS,
2078 .num_ports = 4,
2079 .base_baud = 921600,
2080 .uart_offset = 8,
2081 },
2082 [pbn_b0_bt_8_921600] = {
2083 .flags = FL_BASE0|FL_BASE_BARS,
2084 .num_ports = 8,
2085 .base_baud = 921600,
2086 .uart_offset = 8,
2087 },
2088
2089 [pbn_b1_1_115200] = {
2090 .flags = FL_BASE1,
2091 .num_ports = 1,
2092 .base_baud = 115200,
2093 .uart_offset = 8,
2094 },
2095 [pbn_b1_2_115200] = {
2096 .flags = FL_BASE1,
2097 .num_ports = 2,
2098 .base_baud = 115200,
2099 .uart_offset = 8,
2100 },
2101 [pbn_b1_4_115200] = {
2102 .flags = FL_BASE1,
2103 .num_ports = 4,
2104 .base_baud = 115200,
2105 .uart_offset = 8,
2106 },
2107 [pbn_b1_8_115200] = {
2108 .flags = FL_BASE1,
2109 .num_ports = 8,
2110 .base_baud = 115200,
2111 .uart_offset = 8,
2112 },
2113 [pbn_b1_16_115200] = {
2114 .flags = FL_BASE1,
2115 .num_ports = 16,
2116 .base_baud = 115200,
2117 .uart_offset = 8,
2118 },
2119
2120 [pbn_b1_1_921600] = {
2121 .flags = FL_BASE1,
2122 .num_ports = 1,
2123 .base_baud = 921600,
2124 .uart_offset = 8,
2125 },
2126 [pbn_b1_2_921600] = {
2127 .flags = FL_BASE1,
2128 .num_ports = 2,
2129 .base_baud = 921600,
2130 .uart_offset = 8,
2131 },
2132 [pbn_b1_4_921600] = {
2133 .flags = FL_BASE1,
2134 .num_ports = 4,
2135 .base_baud = 921600,
2136 .uart_offset = 8,
2137 },
2138 [pbn_b1_8_921600] = {
2139 .flags = FL_BASE1,
2140 .num_ports = 8,
2141 .base_baud = 921600,
2142 .uart_offset = 8,
2143 },
2144 [pbn_b1_2_1250000] = {
2145 .flags = FL_BASE1,
2146 .num_ports = 2,
2147 .base_baud = 1250000,
2148 .uart_offset = 8,
2149 },
2150
2151 [pbn_b1_bt_1_115200] = {
2152 .flags = FL_BASE1|FL_BASE_BARS,
2153 .num_ports = 1,
2154 .base_baud = 115200,
2155 .uart_offset = 8,
2156 },
2157 [pbn_b1_bt_2_115200] = {
2158 .flags = FL_BASE1|FL_BASE_BARS,
2159 .num_ports = 2,
2160 .base_baud = 115200,
2161 .uart_offset = 8,
2162 },
2163 [pbn_b1_bt_4_115200] = {
2164 .flags = FL_BASE1|FL_BASE_BARS,
2165 .num_ports = 4,
2166 .base_baud = 115200,
2167 .uart_offset = 8,
2168 },
2169
2170 [pbn_b1_bt_2_921600] = {
2171 .flags = FL_BASE1|FL_BASE_BARS,
2172 .num_ports = 2,
2173 .base_baud = 921600,
2174 .uart_offset = 8,
2175 },
2176
2177 [pbn_b1_1_1382400] = {
2178 .flags = FL_BASE1,
2179 .num_ports = 1,
2180 .base_baud = 1382400,
2181 .uart_offset = 8,
2182 },
2183 [pbn_b1_2_1382400] = {
2184 .flags = FL_BASE1,
2185 .num_ports = 2,
2186 .base_baud = 1382400,
2187 .uart_offset = 8,
2188 },
2189 [pbn_b1_4_1382400] = {
2190 .flags = FL_BASE1,
2191 .num_ports = 4,
2192 .base_baud = 1382400,
2193 .uart_offset = 8,
2194 },
2195 [pbn_b1_8_1382400] = {
2196 .flags = FL_BASE1,
2197 .num_ports = 8,
2198 .base_baud = 1382400,
2199 .uart_offset = 8,
2200 },
2201
2202 [pbn_b2_1_115200] = {
2203 .flags = FL_BASE2,
2204 .num_ports = 1,
2205 .base_baud = 115200,
2206 .uart_offset = 8,
2207 },
2208 [pbn_b2_2_115200] = {
2209 .flags = FL_BASE2,
2210 .num_ports = 2,
2211 .base_baud = 115200,
2212 .uart_offset = 8,
2213 },
2214 [pbn_b2_4_115200] = {
2215 .flags = FL_BASE2,
2216 .num_ports = 4,
2217 .base_baud = 115200,
2218 .uart_offset = 8,
2219 },
2220 [pbn_b2_8_115200] = {
2221 .flags = FL_BASE2,
2222 .num_ports = 8,
2223 .base_baud = 115200,
2224 .uart_offset = 8,
2225 },
2226
2227 [pbn_b2_1_460800] = {
2228 .flags = FL_BASE2,
2229 .num_ports = 1,
2230 .base_baud = 460800,
2231 .uart_offset = 8,
2232 },
2233 [pbn_b2_4_460800] = {
2234 .flags = FL_BASE2,
2235 .num_ports = 4,
2236 .base_baud = 460800,
2237 .uart_offset = 8,
2238 },
2239 [pbn_b2_8_460800] = {
2240 .flags = FL_BASE2,
2241 .num_ports = 8,
2242 .base_baud = 460800,
2243 .uart_offset = 8,
2244 },
2245 [pbn_b2_16_460800] = {
2246 .flags = FL_BASE2,
2247 .num_ports = 16,
2248 .base_baud = 460800,
2249 .uart_offset = 8,
2250 },
2251
2252 [pbn_b2_1_921600] = {
2253 .flags = FL_BASE2,
2254 .num_ports = 1,
2255 .base_baud = 921600,
2256 .uart_offset = 8,
2257 },
2258 [pbn_b2_4_921600] = {
2259 .flags = FL_BASE2,
2260 .num_ports = 4,
2261 .base_baud = 921600,
2262 .uart_offset = 8,
2263 },
2264 [pbn_b2_8_921600] = {
2265 .flags = FL_BASE2,
2266 .num_ports = 8,
2267 .base_baud = 921600,
2268 .uart_offset = 8,
2269 },
2270
2271 [pbn_b2_8_1152000] = {
2272 .flags = FL_BASE2,
2273 .num_ports = 8,
2274 .base_baud = 1152000,
2275 .uart_offset = 8,
2276 },
2277
2278 [pbn_b2_bt_1_115200] = {
2279 .flags = FL_BASE2|FL_BASE_BARS,
2280 .num_ports = 1,
2281 .base_baud = 115200,
2282 .uart_offset = 8,
2283 },
2284 [pbn_b2_bt_2_115200] = {
2285 .flags = FL_BASE2|FL_BASE_BARS,
2286 .num_ports = 2,
2287 .base_baud = 115200,
2288 .uart_offset = 8,
2289 },
2290 [pbn_b2_bt_4_115200] = {
2291 .flags = FL_BASE2|FL_BASE_BARS,
2292 .num_ports = 4,
2293 .base_baud = 115200,
2294 .uart_offset = 8,
2295 },
2296
2297 [pbn_b2_bt_2_921600] = {
2298 .flags = FL_BASE2|FL_BASE_BARS,
2299 .num_ports = 2,
2300 .base_baud = 921600,
2301 .uart_offset = 8,
2302 },
2303 [pbn_b2_bt_4_921600] = {
2304 .flags = FL_BASE2|FL_BASE_BARS,
2305 .num_ports = 4,
2306 .base_baud = 921600,
2307 .uart_offset = 8,
2308 },
2309
2310 [pbn_b3_2_115200] = {
2311 .flags = FL_BASE3,
2312 .num_ports = 2,
2313 .base_baud = 115200,
2314 .uart_offset = 8,
2315 },
2316 [pbn_b3_4_115200] = {
2317 .flags = FL_BASE3,
2318 .num_ports = 4,
2319 .base_baud = 115200,
2320 .uart_offset = 8,
2321 },
2322 [pbn_b3_8_115200] = {
2323 .flags = FL_BASE3,
2324 .num_ports = 8,
2325 .base_baud = 115200,
2326 .uart_offset = 8,
2327 },
2328
2329 [pbn_b4_bt_2_921600] = {
2330 .flags = FL_BASE4,
2331 .num_ports = 2,
2332 .base_baud = 921600,
2333 .uart_offset = 8,
2334 },
2335 [pbn_b4_bt_4_921600] = {
2336 .flags = FL_BASE4,
2337 .num_ports = 4,
2338 .base_baud = 921600,
2339 .uart_offset = 8,
2340 },
2341 [pbn_b4_bt_8_921600] = {
2342 .flags = FL_BASE4,
2343 .num_ports = 8,
2344 .base_baud = 921600,
2345 .uart_offset = 8,
2346 },
2347
2348 /*
2349 * Entries following this are board-specific.
2350 */
2351
2352 /*
2353 * Panacom - IOMEM
2354 */
2355 [pbn_panacom] = {
2356 .flags = FL_BASE2,
2357 .num_ports = 2,
2358 .base_baud = 921600,
2359 .uart_offset = 0x400,
2360 .reg_shift = 7,
2361 },
2362 [pbn_panacom2] = {
2363 .flags = FL_BASE2|FL_BASE_BARS,
2364 .num_ports = 2,
2365 .base_baud = 921600,
2366 .uart_offset = 0x400,
2367 .reg_shift = 7,
2368 },
2369 [pbn_panacom4] = {
2370 .flags = FL_BASE2|FL_BASE_BARS,
2371 .num_ports = 4,
2372 .base_baud = 921600,
2373 .uart_offset = 0x400,
2374 .reg_shift = 7,
2375 },
2376
2377 [pbn_exsys_4055] = {
2378 .flags = FL_BASE2,
2379 .num_ports = 4,
2380 .base_baud = 115200,
2381 .uart_offset = 8,
2382 },
2383
2384 /* I think this entry is broken - the first_offset looks wrong --rmk */
2385 [pbn_plx_romulus] = {
2386 .flags = FL_BASE2,
2387 .num_ports = 4,
2388 .base_baud = 921600,
2389 .uart_offset = 8 << 2,
2390 .reg_shift = 2,
2391 .first_offset = 0x03,
2392 },
2393
2394 /*
2395 * This board uses the size of PCI Base region 0 to
2396 * signal now many ports are available
2397 */
2398 [pbn_oxsemi] = {
2399 .flags = FL_BASE0|FL_REGION_SZ_CAP,
2400 .num_ports = 32,
2401 .base_baud = 115200,
2402 .uart_offset = 8,
2403 },
2404 [pbn_oxsemi_1_4000000] = {
2405 .flags = FL_BASE0,
2406 .num_ports = 1,
2407 .base_baud = 4000000,
2408 .uart_offset = 0x200,
2409 .first_offset = 0x1000,
2410 },
2411 [pbn_oxsemi_2_4000000] = {
2412 .flags = FL_BASE0,
2413 .num_ports = 2,
2414 .base_baud = 4000000,
2415 .uart_offset = 0x200,
2416 .first_offset = 0x1000,
2417 },
2418 [pbn_oxsemi_4_4000000] = {
2419 .flags = FL_BASE0,
2420 .num_ports = 4,
2421 .base_baud = 4000000,
2422 .uart_offset = 0x200,
2423 .first_offset = 0x1000,
2424 },
2425 [pbn_oxsemi_8_4000000] = {
2426 .flags = FL_BASE0,
2427 .num_ports = 8,
2428 .base_baud = 4000000,
2429 .uart_offset = 0x200,
2430 .first_offset = 0x1000,
2431 },
2432
2433
2434 /*
2435 * EKF addition for i960 Boards form EKF with serial port.
2436 * Max 256 ports.
2437 */
2438 [pbn_intel_i960] = {
2439 .flags = FL_BASE0,
2440 .num_ports = 32,
2441 .base_baud = 921600,
2442 .uart_offset = 8 << 2,
2443 .reg_shift = 2,
2444 .first_offset = 0x10000,
2445 },
2446 [pbn_sgi_ioc3] = {
2447 .flags = FL_BASE0|FL_NOIRQ,
2448 .num_ports = 1,
2449 .base_baud = 458333,
2450 .uart_offset = 8,
2451 .reg_shift = 0,
2452 .first_offset = 0x20178,
2453 },
2454
2455 /*
2456 * Computone - uses IOMEM.
2457 */
2458 [pbn_computone_4] = {
2459 .flags = FL_BASE0,
2460 .num_ports = 4,
2461 .base_baud = 921600,
2462 .uart_offset = 0x40,
2463 .reg_shift = 2,
2464 .first_offset = 0x200,
2465 },
2466 [pbn_computone_6] = {
2467 .flags = FL_BASE0,
2468 .num_ports = 6,
2469 .base_baud = 921600,
2470 .uart_offset = 0x40,
2471 .reg_shift = 2,
2472 .first_offset = 0x200,
2473 },
2474 [pbn_computone_8] = {
2475 .flags = FL_BASE0,
2476 .num_ports = 8,
2477 .base_baud = 921600,
2478 .uart_offset = 0x40,
2479 .reg_shift = 2,
2480 .first_offset = 0x200,
2481 },
2482 [pbn_sbsxrsio] = {
2483 .flags = FL_BASE0,
2484 .num_ports = 8,
2485 .base_baud = 460800,
2486 .uart_offset = 256,
2487 .reg_shift = 4,
2488 },
2489 /*
2490 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2491 * Only basic 16550A support.
2492 * XR17C15[24] are not tested, but they should work.
2493 */
2494 [pbn_exar_XR17C152] = {
2495 .flags = FL_BASE0,
2496 .num_ports = 2,
2497 .base_baud = 921600,
2498 .uart_offset = 0x200,
2499 },
2500 [pbn_exar_XR17C154] = {
2501 .flags = FL_BASE0,
2502 .num_ports = 4,
2503 .base_baud = 921600,
2504 .uart_offset = 0x200,
2505 },
2506 [pbn_exar_XR17C158] = {
2507 .flags = FL_BASE0,
2508 .num_ports = 8,
2509 .base_baud = 921600,
2510 .uart_offset = 0x200,
2511 },
2512 [pbn_exar_ibm_saturn] = {
2513 .flags = FL_BASE0,
2514 .num_ports = 1,
2515 .base_baud = 921600,
2516 .uart_offset = 0x200,
2517 },
2518
2519 /*
2520 * PA Semi PWRficient PA6T-1682M on-chip UART
2521 */
2522 [pbn_pasemi_1682M] = {
2523 .flags = FL_BASE0,
2524 .num_ports = 1,
2525 .base_baud = 8333333,
2526 },
2527 /*
2528 * National Instruments 843x
2529 */
2530 [pbn_ni8430_16] = {
2531 .flags = FL_BASE0,
2532 .num_ports = 16,
2533 .base_baud = 3686400,
2534 .uart_offset = 0x10,
2535 .first_offset = 0x800,
2536 },
2537 [pbn_ni8430_8] = {
2538 .flags = FL_BASE0,
2539 .num_ports = 8,
2540 .base_baud = 3686400,
2541 .uart_offset = 0x10,
2542 .first_offset = 0x800,
2543 },
2544 [pbn_ni8430_4] = {
2545 .flags = FL_BASE0,
2546 .num_ports = 4,
2547 .base_baud = 3686400,
2548 .uart_offset = 0x10,
2549 .first_offset = 0x800,
2550 },
2551 [pbn_ni8430_2] = {
2552 .flags = FL_BASE0,
2553 .num_ports = 2,
2554 .base_baud = 3686400,
2555 .uart_offset = 0x10,
2556 .first_offset = 0x800,
2557 },
2558 /*
2559 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
2560 */
2561 [pbn_ADDIDATA_PCIe_1_3906250] = {
2562 .flags = FL_BASE0,
2563 .num_ports = 1,
2564 .base_baud = 3906250,
2565 .uart_offset = 0x200,
2566 .first_offset = 0x1000,
2567 },
2568 [pbn_ADDIDATA_PCIe_2_3906250] = {
2569 .flags = FL_BASE0,
2570 .num_ports = 2,
2571 .base_baud = 3906250,
2572 .uart_offset = 0x200,
2573 .first_offset = 0x1000,
2574 },
2575 [pbn_ADDIDATA_PCIe_4_3906250] = {
2576 .flags = FL_BASE0,
2577 .num_ports = 4,
2578 .base_baud = 3906250,
2579 .uart_offset = 0x200,
2580 .first_offset = 0x1000,
2581 },
2582 [pbn_ADDIDATA_PCIe_8_3906250] = {
2583 .flags = FL_BASE0,
2584 .num_ports = 8,
2585 .base_baud = 3906250,
2586 .uart_offset = 0x200,
2587 .first_offset = 0x1000,
2588 },
2589 [pbn_ce4100_1_115200] = {
2590 .flags = FL_BASE0,
2591 .num_ports = 1,
2592 .base_baud = 921600,
2593 .reg_shift = 2,
2594 },
2595 [pbn_omegapci] = {
2596 .flags = FL_BASE0,
2597 .num_ports = 8,
2598 .base_baud = 115200,
2599 .uart_offset = 0x200,
2600 },
2601 [pbn_NETMOS9900_2s_115200] = {
2602 .flags = FL_BASE0,
2603 .num_ports = 2,
2604 .base_baud = 115200,
2605 },
2606 [pbn_brcm_trumanage] = {
2607 .flags = FL_BASE0,
2608 .num_ports = 1,
2609 .reg_shift = 2,
2610 .base_baud = 115200,
2611 },
2612 };
2613
2614 static const struct pci_device_id softmodem_blacklist[] = {
2615 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
2616 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
2617 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
2618 };
2619
2620 /*
2621 * Given a complete unknown PCI device, try to use some heuristics to
2622 * guess what the configuration might be, based on the pitiful PCI
2623 * serial specs. Returns 0 on success, 1 on failure.
2624 */
2625 static int __devinit
2626 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
2627 {
2628 const struct pci_device_id *blacklist;
2629 int num_iomem, num_port, first_port = -1, i;
2630
2631 /*
2632 * If it is not a communications device or the programming
2633 * interface is greater than 6, give up.
2634 *
2635 * (Should we try to make guesses for multiport serial devices
2636 * later?)
2637 */
2638 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2639 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2640 (dev->class & 0xff) > 6)
2641 return -ENODEV;
2642
2643 /*
2644 * Do not access blacklisted devices that are known not to
2645 * feature serial ports.
2646 */
2647 for (blacklist = softmodem_blacklist;
2648 blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
2649 blacklist++) {
2650 if (dev->vendor == blacklist->vendor &&
2651 dev->device == blacklist->device)
2652 return -ENODEV;
2653 }
2654
2655 num_iomem = num_port = 0;
2656 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2657 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2658 num_port++;
2659 if (first_port == -1)
2660 first_port = i;
2661 }
2662 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2663 num_iomem++;
2664 }
2665
2666 /*
2667 * If there is 1 or 0 iomem regions, and exactly one port,
2668 * use it. We guess the number of ports based on the IO
2669 * region size.
2670 */
2671 if (num_iomem <= 1 && num_port == 1) {
2672 board->flags = first_port;
2673 board->num_ports = pci_resource_len(dev, first_port) / 8;
2674 return 0;
2675 }
2676
2677 /*
2678 * Now guess if we've got a board which indexes by BARs.
2679 * Each IO BAR should be 8 bytes, and they should follow
2680 * consecutively.
2681 */
2682 first_port = -1;
2683 num_port = 0;
2684 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2685 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2686 pci_resource_len(dev, i) == 8 &&
2687 (first_port == -1 || (first_port + num_port) == i)) {
2688 num_port++;
2689 if (first_port == -1)
2690 first_port = i;
2691 }
2692 }
2693
2694 if (num_port > 1) {
2695 board->flags = first_port | FL_BASE_BARS;
2696 board->num_ports = num_port;
2697 return 0;
2698 }
2699
2700 return -ENODEV;
2701 }
2702
2703 static inline int
2704 serial_pci_matches(const struct pciserial_board *board,
2705 const struct pciserial_board *guessed)
2706 {
2707 return
2708 board->num_ports == guessed->num_ports &&
2709 board->base_baud == guessed->base_baud &&
2710 board->uart_offset == guessed->uart_offset &&
2711 board->reg_shift == guessed->reg_shift &&
2712 board->first_offset == guessed->first_offset;
2713 }
2714
2715 struct serial_private *
2716 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
2717 {
2718 struct uart_port serial_port;
2719 struct serial_private *priv;
2720 struct pci_serial_quirk *quirk;
2721 int rc, nr_ports, i;
2722
2723 nr_ports = board->num_ports;
2724
2725 /*
2726 * Find an init and setup quirks.
2727 */
2728 quirk = find_quirk(dev);
2729
2730 /*
2731 * Run the new-style initialization function.
2732 * The initialization function returns:
2733 * <0 - error
2734 * 0 - use board->num_ports
2735 * >0 - number of ports
2736 */
2737 if (quirk->init) {
2738 rc = quirk->init(dev);
2739 if (rc < 0) {
2740 priv = ERR_PTR(rc);
2741 goto err_out;
2742 }
2743 if (rc)
2744 nr_ports = rc;
2745 }
2746
2747 priv = kzalloc(sizeof(struct serial_private) +
2748 sizeof(unsigned int) * nr_ports,
2749 GFP_KERNEL);
2750 if (!priv) {
2751 priv = ERR_PTR(-ENOMEM);
2752 goto err_deinit;
2753 }
2754
2755 priv->dev = dev;
2756 priv->quirk = quirk;
2757
2758 memset(&serial_port, 0, sizeof(struct uart_port));
2759 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2760 serial_port.uartclk = board->base_baud * 16;
2761 serial_port.irq = get_pci_irq(dev, board);
2762 serial_port.dev = &dev->dev;
2763
2764 for (i = 0; i < nr_ports; i++) {
2765 if (quirk->setup(priv, board, &serial_port, i))
2766 break;
2767
2768 #ifdef SERIAL_DEBUG_PCI
2769 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
2770 serial_port.iobase, serial_port.irq, serial_port.iotype);
2771 #endif
2772
2773 priv->line[i] = serial8250_register_port(&serial_port);
2774 if (priv->line[i] < 0) {
2775 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2776 break;
2777 }
2778 }
2779 priv->nr = i;
2780 return priv;
2781
2782 err_deinit:
2783 if (quirk->exit)
2784 quirk->exit(dev);
2785 err_out:
2786 return priv;
2787 }
2788 EXPORT_SYMBOL_GPL(pciserial_init_ports);
2789
2790 void pciserial_remove_ports(struct serial_private *priv)
2791 {
2792 struct pci_serial_quirk *quirk;
2793 int i;
2794
2795 for (i = 0; i < priv->nr; i++)
2796 serial8250_unregister_port(priv->line[i]);
2797
2798 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2799 if (priv->remapped_bar[i])
2800 iounmap(priv->remapped_bar[i]);
2801 priv->remapped_bar[i] = NULL;
2802 }
2803
2804 /*
2805 * Find the exit quirks.
2806 */
2807 quirk = find_quirk(priv->dev);
2808 if (quirk->exit)
2809 quirk->exit(priv->dev);
2810
2811 kfree(priv);
2812 }
2813 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2814
2815 void pciserial_suspend_ports(struct serial_private *priv)
2816 {
2817 int i;
2818
2819 for (i = 0; i < priv->nr; i++)
2820 if (priv->line[i] >= 0)
2821 serial8250_suspend_port(priv->line[i]);
2822 }
2823 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2824
2825 void pciserial_resume_ports(struct serial_private *priv)
2826 {
2827 int i;
2828
2829 /*
2830 * Ensure that the board is correctly configured.
2831 */
2832 if (priv->quirk->init)
2833 priv->quirk->init(priv->dev);
2834
2835 for (i = 0; i < priv->nr; i++)
2836 if (priv->line[i] >= 0)
2837 serial8250_resume_port(priv->line[i]);
2838 }
2839 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2840
2841 /*
2842 * Probe one serial board. Unfortunately, there is no rhyme nor reason
2843 * to the arrangement of serial ports on a PCI card.
2844 */
2845 static int __devinit
2846 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2847 {
2848 struct pci_serial_quirk *quirk;
2849 struct serial_private *priv;
2850 const struct pciserial_board *board;
2851 struct pciserial_board tmp;
2852 int rc;
2853
2854 quirk = find_quirk(dev);
2855 if (quirk->probe) {
2856 rc = quirk->probe(dev);
2857 if (rc)
2858 return rc;
2859 }
2860
2861 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2862 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2863 ent->driver_data);
2864 return -EINVAL;
2865 }
2866
2867 board = &pci_boards[ent->driver_data];
2868
2869 rc = pci_enable_device(dev);
2870 pci_save_state(dev);
2871 if (rc)
2872 return rc;
2873
2874 if (ent->driver_data == pbn_default) {
2875 /*
2876 * Use a copy of the pci_board entry for this;
2877 * avoid changing entries in the table.
2878 */
2879 memcpy(&tmp, board, sizeof(struct pciserial_board));
2880 board = &tmp;
2881
2882 /*
2883 * We matched one of our class entries. Try to
2884 * determine the parameters of this board.
2885 */
2886 rc = serial_pci_guess_board(dev, &tmp);
2887 if (rc)
2888 goto disable;
2889 } else {
2890 /*
2891 * We matched an explicit entry. If we are able to
2892 * detect this boards settings with our heuristic,
2893 * then we no longer need this entry.
2894 */
2895 memcpy(&tmp, &pci_boards[pbn_default],
2896 sizeof(struct pciserial_board));
2897 rc = serial_pci_guess_board(dev, &tmp);
2898 if (rc == 0 && serial_pci_matches(board, &tmp))
2899 moan_device("Redundant entry in serial pci_table.",
2900 dev);
2901 }
2902
2903 priv = pciserial_init_ports(dev, board);
2904 if (!IS_ERR(priv)) {
2905 pci_set_drvdata(dev, priv);
2906 return 0;
2907 }
2908
2909 rc = PTR_ERR(priv);
2910
2911 disable:
2912 pci_disable_device(dev);
2913 return rc;
2914 }
2915
2916 static void __devexit pciserial_remove_one(struct pci_dev *dev)
2917 {
2918 struct serial_private *priv = pci_get_drvdata(dev);
2919
2920 pci_set_drvdata(dev, NULL);
2921
2922 pciserial_remove_ports(priv);
2923
2924 pci_disable_device(dev);
2925 }
2926
2927 #ifdef CONFIG_PM
2928 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2929 {
2930 struct serial_private *priv = pci_get_drvdata(dev);
2931
2932 if (priv)
2933 pciserial_suspend_ports(priv);
2934
2935 pci_save_state(dev);
2936 pci_set_power_state(dev, pci_choose_state(dev, state));
2937 return 0;
2938 }
2939
2940 static int pciserial_resume_one(struct pci_dev *dev)
2941 {
2942 int err;
2943 struct serial_private *priv = pci_get_drvdata(dev);
2944
2945 pci_set_power_state(dev, PCI_D0);
2946 pci_restore_state(dev);
2947
2948 if (priv) {
2949 /*
2950 * The device may have been disabled. Re-enable it.
2951 */
2952 err = pci_enable_device(dev);
2953 /* FIXME: We cannot simply error out here */
2954 if (err)
2955 printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
2956 pciserial_resume_ports(priv);
2957 }
2958 return 0;
2959 }
2960 #endif
2961
2962 static struct pci_device_id serial_pci_tbl[] = {
2963 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2964 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2965 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2966 pbn_b2_8_921600 },
2967 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2968 PCI_SUBVENDOR_ID_CONNECT_TECH,
2969 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2970 pbn_b1_8_1382400 },
2971 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2972 PCI_SUBVENDOR_ID_CONNECT_TECH,
2973 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2974 pbn_b1_4_1382400 },
2975 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2976 PCI_SUBVENDOR_ID_CONNECT_TECH,
2977 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2978 pbn_b1_2_1382400 },
2979 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2980 PCI_SUBVENDOR_ID_CONNECT_TECH,
2981 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2982 pbn_b1_8_1382400 },
2983 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2984 PCI_SUBVENDOR_ID_CONNECT_TECH,
2985 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2986 pbn_b1_4_1382400 },
2987 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2988 PCI_SUBVENDOR_ID_CONNECT_TECH,
2989 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2990 pbn_b1_2_1382400 },
2991 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2992 PCI_SUBVENDOR_ID_CONNECT_TECH,
2993 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2994 pbn_b1_8_921600 },
2995 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2996 PCI_SUBVENDOR_ID_CONNECT_TECH,
2997 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2998 pbn_b1_8_921600 },
2999 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3000 PCI_SUBVENDOR_ID_CONNECT_TECH,
3001 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
3002 pbn_b1_4_921600 },
3003 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3004 PCI_SUBVENDOR_ID_CONNECT_TECH,
3005 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
3006 pbn_b1_4_921600 },
3007 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3008 PCI_SUBVENDOR_ID_CONNECT_TECH,
3009 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
3010 pbn_b1_2_921600 },
3011 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3012 PCI_SUBVENDOR_ID_CONNECT_TECH,
3013 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
3014 pbn_b1_8_921600 },
3015 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3016 PCI_SUBVENDOR_ID_CONNECT_TECH,
3017 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
3018 pbn_b1_8_921600 },
3019 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3020 PCI_SUBVENDOR_ID_CONNECT_TECH,
3021 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
3022 pbn_b1_4_921600 },
3023 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3024 PCI_SUBVENDOR_ID_CONNECT_TECH,
3025 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
3026 pbn_b1_2_1250000 },
3027 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3028 PCI_SUBVENDOR_ID_CONNECT_TECH,
3029 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3030 pbn_b0_2_1843200 },
3031 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3032 PCI_SUBVENDOR_ID_CONNECT_TECH,
3033 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3034 pbn_b0_4_1843200 },
3035 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3036 PCI_VENDOR_ID_AFAVLAB,
3037 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3038 pbn_b0_4_1152000 },
3039 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3040 PCI_SUBVENDOR_ID_CONNECT_TECH,
3041 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
3042 pbn_b0_2_1843200_200 },
3043 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3044 PCI_SUBVENDOR_ID_CONNECT_TECH,
3045 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
3046 pbn_b0_4_1843200_200 },
3047 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3048 PCI_SUBVENDOR_ID_CONNECT_TECH,
3049 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
3050 pbn_b0_8_1843200_200 },
3051 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3052 PCI_SUBVENDOR_ID_CONNECT_TECH,
3053 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
3054 pbn_b0_2_1843200_200 },
3055 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3056 PCI_SUBVENDOR_ID_CONNECT_TECH,
3057 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
3058 pbn_b0_4_1843200_200 },
3059 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3060 PCI_SUBVENDOR_ID_CONNECT_TECH,
3061 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
3062 pbn_b0_8_1843200_200 },
3063 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3064 PCI_SUBVENDOR_ID_CONNECT_TECH,
3065 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
3066 pbn_b0_2_1843200_200 },
3067 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3068 PCI_SUBVENDOR_ID_CONNECT_TECH,
3069 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
3070 pbn_b0_4_1843200_200 },
3071 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3072 PCI_SUBVENDOR_ID_CONNECT_TECH,
3073 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
3074 pbn_b0_8_1843200_200 },
3075 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3076 PCI_SUBVENDOR_ID_CONNECT_TECH,
3077 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
3078 pbn_b0_2_1843200_200 },
3079 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3080 PCI_SUBVENDOR_ID_CONNECT_TECH,
3081 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
3082 pbn_b0_4_1843200_200 },
3083 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3084 PCI_SUBVENDOR_ID_CONNECT_TECH,
3085 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
3086 pbn_b0_8_1843200_200 },
3087 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3088 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
3089 0, 0, pbn_exar_ibm_saturn },
3090
3091 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
3092 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3093 pbn_b2_bt_1_115200 },
3094 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
3095 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3096 pbn_b2_bt_2_115200 },
3097 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
3098 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3099 pbn_b2_bt_4_115200 },
3100 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
3101 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3102 pbn_b2_bt_2_115200 },
3103 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
3104 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3105 pbn_b2_bt_4_115200 },
3106 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
3107 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3108 pbn_b2_8_115200 },
3109 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
3110 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3111 pbn_b2_8_460800 },
3112 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
3113 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3114 pbn_b2_8_115200 },
3115
3116 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
3117 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3118 pbn_b2_bt_2_115200 },
3119 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
3120 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3121 pbn_b2_bt_2_921600 },
3122 /*
3123 * VScom SPCOM800, from sl@s.pl
3124 */
3125 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
3126 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3127 pbn_b2_8_921600 },
3128 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
3129 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3130 pbn_b2_4_921600 },
3131 /* Unknown card - subdevice 0x1584 */
3132 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3133 PCI_VENDOR_ID_PLX,
3134 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
3135 pbn_b2_4_115200 },
3136 /* Unknown card - subdevice 0x1588 */
3137 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3138 PCI_VENDOR_ID_PLX,
3139 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
3140 pbn_b2_8_115200 },
3141 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3142 PCI_SUBVENDOR_ID_KEYSPAN,
3143 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
3144 pbn_panacom },
3145 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
3146 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3147 pbn_panacom4 },
3148 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
3149 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3150 pbn_panacom2 },
3151 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3152 PCI_VENDOR_ID_ESDGMBH,
3153 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
3154 pbn_b2_4_115200 },
3155 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3156 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3157 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
3158 pbn_b2_4_460800 },
3159 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3160 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3161 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
3162 pbn_b2_8_460800 },
3163 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3164 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3165 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
3166 pbn_b2_16_460800 },
3167 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3168 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3169 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
3170 pbn_b2_16_460800 },
3171 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3172 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3173 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
3174 pbn_b2_4_460800 },
3175 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3176 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3177 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
3178 pbn_b2_8_460800 },
3179 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3180 PCI_SUBVENDOR_ID_EXSYS,
3181 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
3182 pbn_exsys_4055 },
3183 /*
3184 * Megawolf Romulus PCI Serial Card, from Mike Hudson
3185 * (Exoray@isys.ca)
3186 */
3187 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
3188 0x10b5, 0x106a, 0, 0,
3189 pbn_plx_romulus },
3190 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
3191 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3192 pbn_b1_4_115200 },
3193 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
3194 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3195 pbn_b1_2_115200 },
3196 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
3197 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3198 pbn_b1_8_115200 },
3199 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
3200 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3201 pbn_b1_8_115200 },
3202 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
3203 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
3204 0, 0,
3205 pbn_b0_4_921600 },
3206 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3207 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
3208 0, 0,
3209 pbn_b0_4_1152000 },
3210 { PCI_VENDOR_ID_OXSEMI, 0x9505,
3211 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3212 pbn_b0_bt_2_921600 },
3213
3214 /*
3215 * The below card is a little controversial since it is the
3216 * subject of a PCI vendor/device ID clash. (See
3217 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
3218 * For now just used the hex ID 0x950a.
3219 */
3220 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3221 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
3222 0, 0, pbn_b0_2_115200 },
3223 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3224 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
3225 0, 0, pbn_b0_2_115200 },
3226 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3227 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3228 pbn_b0_2_1130000 },
3229 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
3230 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
3231 pbn_b0_1_921600 },
3232 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3233 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3234 pbn_b0_4_115200 },
3235 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
3236 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3237 pbn_b0_bt_2_921600 },
3238 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
3239 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
3240 pbn_b2_8_1152000 },
3241
3242 /*
3243 * Oxford Semiconductor Inc. Tornado PCI express device range.
3244 */
3245 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
3246 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3247 pbn_b0_1_4000000 },
3248 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
3249 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3250 pbn_b0_1_4000000 },
3251 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
3252 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3253 pbn_oxsemi_1_4000000 },
3254 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
3255 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3256 pbn_oxsemi_1_4000000 },
3257 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
3258 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3259 pbn_b0_1_4000000 },
3260 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
3261 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3262 pbn_b0_1_4000000 },
3263 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
3264 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3265 pbn_oxsemi_1_4000000 },
3266 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
3267 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3268 pbn_oxsemi_1_4000000 },
3269 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
3270 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3271 pbn_b0_1_4000000 },
3272 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
3273 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3274 pbn_b0_1_4000000 },
3275 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
3276 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3277 pbn_b0_1_4000000 },
3278 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
3279 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3280 pbn_b0_1_4000000 },
3281 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
3282 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3283 pbn_oxsemi_2_4000000 },
3284 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
3285 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3286 pbn_oxsemi_2_4000000 },
3287 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
3288 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3289 pbn_oxsemi_4_4000000 },
3290 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
3291 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3292 pbn_oxsemi_4_4000000 },
3293 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
3294 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3295 pbn_oxsemi_8_4000000 },
3296 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
3297 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3298 pbn_oxsemi_8_4000000 },
3299 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
3300 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3301 pbn_oxsemi_1_4000000 },
3302 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
3303 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3304 pbn_oxsemi_1_4000000 },
3305 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
3306 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3307 pbn_oxsemi_1_4000000 },
3308 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
3309 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3310 pbn_oxsemi_1_4000000 },
3311 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
3312 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3313 pbn_oxsemi_1_4000000 },
3314 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
3315 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3316 pbn_oxsemi_1_4000000 },
3317 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
3318 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3319 pbn_oxsemi_1_4000000 },
3320 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
3321 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3322 pbn_oxsemi_1_4000000 },
3323 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
3324 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3325 pbn_oxsemi_1_4000000 },
3326 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
3327 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3328 pbn_oxsemi_1_4000000 },
3329 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
3330 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3331 pbn_oxsemi_1_4000000 },
3332 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
3333 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3334 pbn_oxsemi_1_4000000 },
3335 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
3336 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3337 pbn_oxsemi_1_4000000 },
3338 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
3339 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3340 pbn_oxsemi_1_4000000 },
3341 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
3342 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3343 pbn_oxsemi_1_4000000 },
3344 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
3345 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3346 pbn_oxsemi_1_4000000 },
3347 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
3348 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3349 pbn_oxsemi_1_4000000 },
3350 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
3351 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3352 pbn_oxsemi_1_4000000 },
3353 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
3354 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3355 pbn_oxsemi_1_4000000 },
3356 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
3357 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3358 pbn_oxsemi_1_4000000 },
3359 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
3360 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3361 pbn_oxsemi_1_4000000 },
3362 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
3363 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3364 pbn_oxsemi_1_4000000 },
3365 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
3366 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3367 pbn_oxsemi_1_4000000 },
3368 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
3369 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3370 pbn_oxsemi_1_4000000 },
3371 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
3372 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3373 pbn_oxsemi_1_4000000 },
3374 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
3375 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3376 pbn_oxsemi_1_4000000 },
3377 /*
3378 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
3379 */
3380 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
3381 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
3382 pbn_oxsemi_1_4000000 },
3383 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
3384 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
3385 pbn_oxsemi_2_4000000 },
3386 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
3387 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
3388 pbn_oxsemi_4_4000000 },
3389 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
3390 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
3391 pbn_oxsemi_8_4000000 },
3392
3393 /*
3394 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
3395 */
3396 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
3397 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
3398 pbn_oxsemi_2_4000000 },
3399
3400 /*
3401 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
3402 * from skokodyn@yahoo.com
3403 */
3404 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3405 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
3406 pbn_sbsxrsio },
3407 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3408 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
3409 pbn_sbsxrsio },
3410 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3411 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
3412 pbn_sbsxrsio },
3413 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3414 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
3415 pbn_sbsxrsio },
3416
3417 /*
3418 * Digitan DS560-558, from jimd@esoft.com
3419 */
3420 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
3421 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3422 pbn_b1_1_115200 },
3423
3424 /*
3425 * Titan Electronic cards
3426 * The 400L and 800L have a custom setup quirk.
3427 */
3428 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
3429 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3430 pbn_b0_1_921600 },
3431 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
3432 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3433 pbn_b0_2_921600 },
3434 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
3435 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3436 pbn_b0_4_921600 },
3437 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
3438 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3439 pbn_b0_4_921600 },
3440 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
3441 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3442 pbn_b1_1_921600 },
3443 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
3444 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3445 pbn_b1_bt_2_921600 },
3446 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
3447 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3448 pbn_b0_bt_4_921600 },
3449 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
3450 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3451 pbn_b0_bt_8_921600 },
3452 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
3453 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3454 pbn_b4_bt_2_921600 },
3455 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
3456 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3457 pbn_b4_bt_4_921600 },
3458 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
3459 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3460 pbn_b4_bt_8_921600 },
3461 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
3462 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3463 pbn_b0_4_921600 },
3464 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
3465 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3466 pbn_b0_4_921600 },
3467 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
3468 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3469 pbn_b0_4_921600 },
3470 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
3471 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3472 pbn_oxsemi_1_4000000 },
3473 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
3474 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3475 pbn_oxsemi_2_4000000 },
3476 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
3477 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3478 pbn_oxsemi_4_4000000 },
3479 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
3480 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3481 pbn_oxsemi_8_4000000 },
3482 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
3483 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3484 pbn_oxsemi_2_4000000 },
3485 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
3486 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3487 pbn_oxsemi_2_4000000 },
3488 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
3489 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3490 pbn_b0_bt_2_921600 },
3491 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
3492 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3493 pbn_b0_4_921600 },
3494 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
3495 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3496 pbn_b0_4_921600 },
3497 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
3498 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3499 pbn_b0_4_921600 },
3500 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
3501 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3502 pbn_b0_4_921600 },
3503
3504 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
3505 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3506 pbn_b2_1_460800 },
3507 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
3508 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3509 pbn_b2_1_460800 },
3510 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
3511 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3512 pbn_b2_1_460800 },
3513 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3514 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3515 pbn_b2_bt_2_921600 },
3516 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3517 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3518 pbn_b2_bt_2_921600 },
3519 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3520 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3521 pbn_b2_bt_2_921600 },
3522 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3523 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3524 pbn_b2_bt_4_921600 },
3525 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3526 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3527 pbn_b2_bt_4_921600 },
3528 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3529 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3530 pbn_b2_bt_4_921600 },
3531 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3532 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3533 pbn_b0_1_921600 },
3534 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3535 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3536 pbn_b0_1_921600 },
3537 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3538 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3539 pbn_b0_1_921600 },
3540 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3541 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3542 pbn_b0_bt_2_921600 },
3543 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3544 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3545 pbn_b0_bt_2_921600 },
3546 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3547 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3548 pbn_b0_bt_2_921600 },
3549 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3550 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3551 pbn_b0_bt_4_921600 },
3552 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3553 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3554 pbn_b0_bt_4_921600 },
3555 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3556 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3557 pbn_b0_bt_4_921600 },
3558 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3559 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3560 pbn_b0_bt_8_921600 },
3561 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3562 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3563 pbn_b0_bt_8_921600 },
3564 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3565 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3566 pbn_b0_bt_8_921600 },
3567
3568 /*
3569 * Computone devices submitted by Doug McNash dmcnash@computone.com
3570 */
3571 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3572 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3573 0, 0, pbn_computone_4 },
3574 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3575 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3576 0, 0, pbn_computone_8 },
3577 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3578 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3579 0, 0, pbn_computone_6 },
3580
3581 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3582 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3583 pbn_oxsemi },
3584 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3585 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3586 pbn_b0_bt_1_921600 },
3587
3588 /*
3589 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3590 */
3591 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3592 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3593 pbn_b0_bt_8_115200 },
3594 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3595 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3596 pbn_b0_bt_8_115200 },
3597
3598 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3599 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3600 pbn_b0_bt_2_115200 },
3601 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3602 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3603 pbn_b0_bt_2_115200 },
3604 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3605 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3606 pbn_b0_bt_2_115200 },
3607 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
3608 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3609 pbn_b0_bt_2_115200 },
3610 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
3611 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3612 pbn_b0_bt_2_115200 },
3613 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3614 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3615 pbn_b0_bt_4_460800 },
3616 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3617 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3618 pbn_b0_bt_4_460800 },
3619 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3620 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3621 pbn_b0_bt_2_460800 },
3622 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3623 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3624 pbn_b0_bt_2_460800 },
3625 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3626 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3627 pbn_b0_bt_2_460800 },
3628 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3629 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3630 pbn_b0_bt_1_115200 },
3631 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3632 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3633 pbn_b0_bt_1_460800 },
3634
3635 /*
3636 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3637 * Cards are identified by their subsystem vendor IDs, which
3638 * (in hex) match the model number.
3639 *
3640 * Note that JC140x are RS422/485 cards which require ox950
3641 * ACR = 0x10, and as such are not currently fully supported.
3642 */
3643 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3644 0x1204, 0x0004, 0, 0,
3645 pbn_b0_4_921600 },
3646 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3647 0x1208, 0x0004, 0, 0,
3648 pbn_b0_4_921600 },
3649 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3650 0x1402, 0x0002, 0, 0,
3651 pbn_b0_2_921600 }, */
3652 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3653 0x1404, 0x0004, 0, 0,
3654 pbn_b0_4_921600 }, */
3655 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3656 0x1208, 0x0004, 0, 0,
3657 pbn_b0_4_921600 },
3658
3659 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3660 0x1204, 0x0004, 0, 0,
3661 pbn_b0_4_921600 },
3662 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3663 0x1208, 0x0004, 0, 0,
3664 pbn_b0_4_921600 },
3665 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
3666 0x1208, 0x0004, 0, 0,
3667 pbn_b0_4_921600 },
3668 /*
3669 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3670 */
3671 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3672 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3673 pbn_b1_1_1382400 },
3674
3675 /*
3676 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3677 */
3678 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3679 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3680 pbn_b1_1_1382400 },
3681
3682 /*
3683 * RAStel 2 port modem, gerg@moreton.com.au
3684 */
3685 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3686 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3687 pbn_b2_bt_2_115200 },
3688
3689 /*
3690 * EKF addition for i960 Boards form EKF with serial port
3691 */
3692 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3693 0xE4BF, PCI_ANY_ID, 0, 0,
3694 pbn_intel_i960 },
3695
3696 /*
3697 * Xircom Cardbus/Ethernet combos
3698 */
3699 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3700 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3701 pbn_b0_1_115200 },
3702 /*
3703 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3704 */
3705 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3706 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3707 pbn_b0_1_115200 },
3708
3709 /*
3710 * Untested PCI modems, sent in from various folks...
3711 */
3712
3713 /*
3714 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3715 */
3716 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
3717 0x1048, 0x1500, 0, 0,
3718 pbn_b1_1_115200 },
3719
3720 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3721 0xFF00, 0, 0, 0,
3722 pbn_sgi_ioc3 },
3723
3724 /*
3725 * HP Diva card
3726 */
3727 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3728 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3729 pbn_b1_1_115200 },
3730 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3731 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3732 pbn_b0_5_115200 },
3733 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3734 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3735 pbn_b2_1_115200 },
3736
3737 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3738 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3739 pbn_b3_2_115200 },
3740 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3741 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3742 pbn_b3_4_115200 },
3743 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3744 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3745 pbn_b3_8_115200 },
3746
3747 /*
3748 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3749 */
3750 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3751 PCI_ANY_ID, PCI_ANY_ID,
3752 0,
3753 0, pbn_exar_XR17C152 },
3754 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3755 PCI_ANY_ID, PCI_ANY_ID,
3756 0,
3757 0, pbn_exar_XR17C154 },
3758 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3759 PCI_ANY_ID, PCI_ANY_ID,
3760 0,
3761 0, pbn_exar_XR17C158 },
3762
3763 /*
3764 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3765 */
3766 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3767 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3768 pbn_b0_1_115200 },
3769 /*
3770 * ITE
3771 */
3772 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3773 PCI_ANY_ID, PCI_ANY_ID,
3774 0, 0,
3775 pbn_b1_bt_1_115200 },
3776
3777 /*
3778 * IntaShield IS-200
3779 */
3780 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3781 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
3782 pbn_b2_2_115200 },
3783 /*
3784 * IntaShield IS-400
3785 */
3786 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3787 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
3788 pbn_b2_4_115200 },
3789 /*
3790 * Perle PCI-RAS cards
3791 */
3792 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3793 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3794 0, 0, pbn_b2_4_921600 },
3795 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3796 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3797 0, 0, pbn_b2_8_921600 },
3798
3799 /*
3800 * Mainpine series cards: Fairly standard layout but fools
3801 * parts of the autodetect in some cases and uses otherwise
3802 * unmatched communications subclasses in the PCI Express case
3803 */
3804
3805 { /* RockForceDUO */
3806 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3807 PCI_VENDOR_ID_MAINPINE, 0x0200,
3808 0, 0, pbn_b0_2_115200 },
3809 { /* RockForceQUATRO */
3810 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3811 PCI_VENDOR_ID_MAINPINE, 0x0300,
3812 0, 0, pbn_b0_4_115200 },
3813 { /* RockForceDUO+ */
3814 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3815 PCI_VENDOR_ID_MAINPINE, 0x0400,
3816 0, 0, pbn_b0_2_115200 },
3817 { /* RockForceQUATRO+ */
3818 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3819 PCI_VENDOR_ID_MAINPINE, 0x0500,
3820 0, 0, pbn_b0_4_115200 },
3821 { /* RockForce+ */
3822 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3823 PCI_VENDOR_ID_MAINPINE, 0x0600,
3824 0, 0, pbn_b0_2_115200 },
3825 { /* RockForce+ */
3826 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3827 PCI_VENDOR_ID_MAINPINE, 0x0700,
3828 0, 0, pbn_b0_4_115200 },
3829 { /* RockForceOCTO+ */
3830 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3831 PCI_VENDOR_ID_MAINPINE, 0x0800,
3832 0, 0, pbn_b0_8_115200 },
3833 { /* RockForceDUO+ */
3834 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3835 PCI_VENDOR_ID_MAINPINE, 0x0C00,
3836 0, 0, pbn_b0_2_115200 },
3837 { /* RockForceQUARTRO+ */
3838 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3839 PCI_VENDOR_ID_MAINPINE, 0x0D00,
3840 0, 0, pbn_b0_4_115200 },
3841 { /* RockForceOCTO+ */
3842 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3843 PCI_VENDOR_ID_MAINPINE, 0x1D00,
3844 0, 0, pbn_b0_8_115200 },
3845 { /* RockForceD1 */
3846 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3847 PCI_VENDOR_ID_MAINPINE, 0x2000,
3848 0, 0, pbn_b0_1_115200 },
3849 { /* RockForceF1 */
3850 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3851 PCI_VENDOR_ID_MAINPINE, 0x2100,
3852 0, 0, pbn_b0_1_115200 },
3853 { /* RockForceD2 */
3854 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3855 PCI_VENDOR_ID_MAINPINE, 0x2200,
3856 0, 0, pbn_b0_2_115200 },
3857 { /* RockForceF2 */
3858 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3859 PCI_VENDOR_ID_MAINPINE, 0x2300,
3860 0, 0, pbn_b0_2_115200 },
3861 { /* RockForceD4 */
3862 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3863 PCI_VENDOR_ID_MAINPINE, 0x2400,
3864 0, 0, pbn_b0_4_115200 },
3865 { /* RockForceF4 */
3866 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3867 PCI_VENDOR_ID_MAINPINE, 0x2500,
3868 0, 0, pbn_b0_4_115200 },
3869 { /* RockForceD8 */
3870 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3871 PCI_VENDOR_ID_MAINPINE, 0x2600,
3872 0, 0, pbn_b0_8_115200 },
3873 { /* RockForceF8 */
3874 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3875 PCI_VENDOR_ID_MAINPINE, 0x2700,
3876 0, 0, pbn_b0_8_115200 },
3877 { /* IQ Express D1 */
3878 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3879 PCI_VENDOR_ID_MAINPINE, 0x3000,
3880 0, 0, pbn_b0_1_115200 },
3881 { /* IQ Express F1 */
3882 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3883 PCI_VENDOR_ID_MAINPINE, 0x3100,
3884 0, 0, pbn_b0_1_115200 },
3885 { /* IQ Express D2 */
3886 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3887 PCI_VENDOR_ID_MAINPINE, 0x3200,
3888 0, 0, pbn_b0_2_115200 },
3889 { /* IQ Express F2 */
3890 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3891 PCI_VENDOR_ID_MAINPINE, 0x3300,
3892 0, 0, pbn_b0_2_115200 },
3893 { /* IQ Express D4 */
3894 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3895 PCI_VENDOR_ID_MAINPINE, 0x3400,
3896 0, 0, pbn_b0_4_115200 },
3897 { /* IQ Express F4 */
3898 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3899 PCI_VENDOR_ID_MAINPINE, 0x3500,
3900 0, 0, pbn_b0_4_115200 },
3901 { /* IQ Express D8 */
3902 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3903 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3904 0, 0, pbn_b0_8_115200 },
3905 { /* IQ Express F8 */
3906 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3907 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3908 0, 0, pbn_b0_8_115200 },
3909
3910
3911 /*
3912 * PA Semi PA6T-1682M on-chip UART
3913 */
3914 { PCI_VENDOR_ID_PASEMI, 0xa004,
3915 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3916 pbn_pasemi_1682M },
3917
3918 /*
3919 * National Instruments
3920 */
3921 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3922 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3923 pbn_b1_16_115200 },
3924 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3925 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3926 pbn_b1_8_115200 },
3927 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3928 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3929 pbn_b1_bt_4_115200 },
3930 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3931 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3932 pbn_b1_bt_2_115200 },
3933 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
3934 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3935 pbn_b1_bt_4_115200 },
3936 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
3937 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3938 pbn_b1_bt_2_115200 },
3939 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
3940 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3941 pbn_b1_16_115200 },
3942 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
3943 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3944 pbn_b1_8_115200 },
3945 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
3946 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3947 pbn_b1_bt_4_115200 },
3948 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
3949 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3950 pbn_b1_bt_2_115200 },
3951 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
3952 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3953 pbn_b1_bt_4_115200 },
3954 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
3955 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3956 pbn_b1_bt_2_115200 },
3957 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3958 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3959 pbn_ni8430_2 },
3960 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
3961 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3962 pbn_ni8430_2 },
3963 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
3964 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3965 pbn_ni8430_4 },
3966 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
3967 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3968 pbn_ni8430_4 },
3969 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
3970 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3971 pbn_ni8430_8 },
3972 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
3973 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3974 pbn_ni8430_8 },
3975 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
3976 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3977 pbn_ni8430_16 },
3978 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
3979 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3980 pbn_ni8430_16 },
3981 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
3982 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3983 pbn_ni8430_2 },
3984 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
3985 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3986 pbn_ni8430_2 },
3987 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
3988 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3989 pbn_ni8430_4 },
3990 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
3991 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3992 pbn_ni8430_4 },
3993
3994 /*
3995 * ADDI-DATA GmbH communication cards <info@addi-data.com>
3996 */
3997 { PCI_VENDOR_ID_ADDIDATA,
3998 PCI_DEVICE_ID_ADDIDATA_APCI7500,
3999 PCI_ANY_ID,
4000 PCI_ANY_ID,
4001 0,
4002 0,
4003 pbn_b0_4_115200 },
4004
4005 { PCI_VENDOR_ID_ADDIDATA,
4006 PCI_DEVICE_ID_ADDIDATA_APCI7420,
4007 PCI_ANY_ID,
4008 PCI_ANY_ID,
4009 0,
4010 0,
4011 pbn_b0_2_115200 },
4012
4013 { PCI_VENDOR_ID_ADDIDATA,
4014 PCI_DEVICE_ID_ADDIDATA_APCI7300,
4015 PCI_ANY_ID,
4016 PCI_ANY_ID,
4017 0,
4018 0,
4019 pbn_b0_1_115200 },
4020
4021 { PCI_VENDOR_ID_ADDIDATA_OLD,
4022 PCI_DEVICE_ID_ADDIDATA_APCI7800,
4023 PCI_ANY_ID,
4024 PCI_ANY_ID,
4025 0,
4026 0,
4027 pbn_b1_8_115200 },
4028
4029 { PCI_VENDOR_ID_ADDIDATA,
4030 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
4031 PCI_ANY_ID,
4032 PCI_ANY_ID,
4033 0,
4034 0,
4035 pbn_b0_4_115200 },
4036
4037 { PCI_VENDOR_ID_ADDIDATA,
4038 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
4039 PCI_ANY_ID,
4040 PCI_ANY_ID,
4041 0,
4042 0,
4043 pbn_b0_2_115200 },
4044
4045 { PCI_VENDOR_ID_ADDIDATA,
4046 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
4047 PCI_ANY_ID,
4048 PCI_ANY_ID,
4049 0,
4050 0,
4051 pbn_b0_1_115200 },
4052
4053 { PCI_VENDOR_ID_ADDIDATA,
4054 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
4055 PCI_ANY_ID,
4056 PCI_ANY_ID,
4057 0,
4058 0,
4059 pbn_b0_4_115200 },
4060
4061 { PCI_VENDOR_ID_ADDIDATA,
4062 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
4063 PCI_ANY_ID,
4064 PCI_ANY_ID,
4065 0,
4066 0,
4067 pbn_b0_2_115200 },
4068
4069 { PCI_VENDOR_ID_ADDIDATA,
4070 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
4071 PCI_ANY_ID,
4072 PCI_ANY_ID,
4073 0,
4074 0,
4075 pbn_b0_1_115200 },
4076
4077 { PCI_VENDOR_ID_ADDIDATA,
4078 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
4079 PCI_ANY_ID,
4080 PCI_ANY_ID,
4081 0,
4082 0,
4083 pbn_b0_8_115200 },
4084
4085 { PCI_VENDOR_ID_ADDIDATA,
4086 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
4087 PCI_ANY_ID,
4088 PCI_ANY_ID,
4089 0,
4090 0,
4091 pbn_ADDIDATA_PCIe_4_3906250 },
4092
4093 { PCI_VENDOR_ID_ADDIDATA,
4094 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
4095 PCI_ANY_ID,
4096 PCI_ANY_ID,
4097 0,
4098 0,
4099 pbn_ADDIDATA_PCIe_2_3906250 },
4100
4101 { PCI_VENDOR_ID_ADDIDATA,
4102 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
4103 PCI_ANY_ID,
4104 PCI_ANY_ID,
4105 0,
4106 0,
4107 pbn_ADDIDATA_PCIe_1_3906250 },
4108
4109 { PCI_VENDOR_ID_ADDIDATA,
4110 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
4111 PCI_ANY_ID,
4112 PCI_ANY_ID,
4113 0,
4114 0,
4115 pbn_ADDIDATA_PCIe_8_3906250 },
4116
4117 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
4118 PCI_VENDOR_ID_IBM, 0x0299,
4119 0, 0, pbn_b0_bt_2_115200 },
4120
4121 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
4122 0xA000, 0x1000,
4123 0, 0, pbn_b0_1_115200 },
4124
4125 /* the 9901 is a rebranded 9912 */
4126 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
4127 0xA000, 0x1000,
4128 0, 0, pbn_b0_1_115200 },
4129
4130 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
4131 0xA000, 0x1000,
4132 0, 0, pbn_b0_1_115200 },
4133
4134 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
4135 0xA000, 0x1000,
4136 0, 0, pbn_b0_1_115200 },
4137
4138 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4139 0xA000, 0x1000,
4140 0, 0, pbn_b0_1_115200 },
4141
4142 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4143 0xA000, 0x3002,
4144 0, 0, pbn_NETMOS9900_2s_115200 },
4145
4146 /*
4147 * Best Connectivity and Rosewill PCI Multi I/O cards
4148 */
4149
4150 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4151 0xA000, 0x1000,
4152 0, 0, pbn_b0_1_115200 },
4153
4154 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4155 0xA000, 0x3002,
4156 0, 0, pbn_b0_bt_2_115200 },
4157
4158 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4159 0xA000, 0x3004,
4160 0, 0, pbn_b0_bt_4_115200 },
4161 /* Intel CE4100 */
4162 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
4163 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4164 pbn_ce4100_1_115200 },
4165
4166 /*
4167 * Cronyx Omega PCI
4168 */
4169 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
4170 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4171 pbn_omegapci },
4172
4173 /*
4174 * Broadcom TruManage
4175 */
4176 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
4177 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4178 pbn_brcm_trumanage },
4179
4180 /*
4181 * These entries match devices with class COMMUNICATION_SERIAL,
4182 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
4183 */
4184 { PCI_ANY_ID, PCI_ANY_ID,
4185 PCI_ANY_ID, PCI_ANY_ID,
4186 PCI_CLASS_COMMUNICATION_SERIAL << 8,
4187 0xffff00, pbn_default },
4188 { PCI_ANY_ID, PCI_ANY_ID,
4189 PCI_ANY_ID, PCI_ANY_ID,
4190 PCI_CLASS_COMMUNICATION_MODEM << 8,
4191 0xffff00, pbn_default },
4192 { PCI_ANY_ID, PCI_ANY_ID,
4193 PCI_ANY_ID, PCI_ANY_ID,
4194 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
4195 0xffff00, pbn_default },
4196 { 0, }
4197 };
4198
4199 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
4200 pci_channel_state_t state)
4201 {
4202 struct serial_private *priv = pci_get_drvdata(dev);
4203
4204 if (state == pci_channel_io_perm_failure)
4205 return PCI_ERS_RESULT_DISCONNECT;
4206
4207 if (priv)
4208 pciserial_suspend_ports(priv);
4209
4210 pci_disable_device(dev);
4211
4212 return PCI_ERS_RESULT_NEED_RESET;
4213 }
4214
4215 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
4216 {
4217 int rc;
4218
4219 rc = pci_enable_device(dev);
4220
4221 if (rc)
4222 return PCI_ERS_RESULT_DISCONNECT;
4223
4224 pci_restore_state(dev);
4225 pci_save_state(dev);
4226
4227 return PCI_ERS_RESULT_RECOVERED;
4228 }
4229
4230 static void serial8250_io_resume(struct pci_dev *dev)
4231 {
4232 struct serial_private *priv = pci_get_drvdata(dev);
4233
4234 if (priv)
4235 pciserial_resume_ports(priv);
4236 }
4237
4238 static struct pci_error_handlers serial8250_err_handler = {
4239 .error_detected = serial8250_io_error_detected,
4240 .slot_reset = serial8250_io_slot_reset,
4241 .resume = serial8250_io_resume,
4242 };
4243
4244 static struct pci_driver serial_pci_driver = {
4245 .name = "serial",
4246 .probe = pciserial_init_one,
4247 .remove = __devexit_p(pciserial_remove_one),
4248 #ifdef CONFIG_PM
4249 .suspend = pciserial_suspend_one,
4250 .resume = pciserial_resume_one,
4251 #endif
4252 .id_table = serial_pci_tbl,
4253 .err_handler = &serial8250_err_handler,
4254 };
4255
4256 static int __init serial8250_pci_init(void)
4257 {
4258 return pci_register_driver(&serial_pci_driver);
4259 }
4260
4261 static void __exit serial8250_pci_exit(void)
4262 {
4263 pci_unregister_driver(&serial_pci_driver);
4264 }
4265
4266 module_init(serial8250_pci_init);
4267 module_exit(serial8250_pci_exit);
4268
4269 MODULE_LICENSE("GPL");
4270 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
4271 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
Linux with added FPC-III support