drivers/tty/serial/mxs-auart.c

   1 /*
   2  * Freescale STMP37XX/STMP378X Application UART driver
   3  *
   4  * Author: dmitry pervushin <dimka@embeddedalley.com>
   5  *
   6  * Copyright 2008-2010 Freescale Semiconductor, Inc.
   7  * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
   8  *
   9  * The code contained herein is licensed under the GNU General Public
  10  * License. You may obtain a copy of the GNU General Public License
  11  * Version 2 or later at the following locations:
  12  *
  13  * http://www.opensource.org/licenses/gpl-license.html
  14  * http://www.gnu.org/copyleft/gpl.html
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/errno.h>
  19 #include <linux/init.h>
  20 #include <linux/console.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/module.h>
  23 #include <linux/slab.h>
  24 #include <linux/wait.h>
  25 #include <linux/tty.h>
  26 #include <linux/tty_driver.h>
  27 #include <linux/tty_flip.h>
  28 #include <linux/serial.h>
  29 #include <linux/serial_core.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/device.h>
  32 #include <linux/clk.h>
  33 #include <linux/delay.h>
  34 #include <linux/io.h>
  35
  36 #include <asm/cacheflush.h>
  37
  38 #define MXS_AUART_PORTS 5
  39
  40 #define AUART_CTRL0                     0x00000000
  41 #define AUART_CTRL0_SET                 0x00000004
  42 #define AUART_CTRL0_CLR                 0x00000008
  43 #define AUART_CTRL0_TOG                 0x0000000c
  44 #define AUART_CTRL1                     0x00000010
  45 #define AUART_CTRL1_SET                 0x00000014
  46 #define AUART_CTRL1_CLR                 0x00000018
  47 #define AUART_CTRL1_TOG                 0x0000001c
  48 #define AUART_CTRL2                     0x00000020
  49 #define AUART_CTRL2_SET                 0x00000024
  50 #define AUART_CTRL2_CLR                 0x00000028
  51 #define AUART_CTRL2_TOG                 0x0000002c
  52 #define AUART_LINECTRL                  0x00000030
  53 #define AUART_LINECTRL_SET              0x00000034
  54 #define AUART_LINECTRL_CLR              0x00000038
  55 #define AUART_LINECTRL_TOG              0x0000003c
  56 #define AUART_LINECTRL2                 0x00000040
  57 #define AUART_LINECTRL2_SET             0x00000044
  58 #define AUART_LINECTRL2_CLR             0x00000048
  59 #define AUART_LINECTRL2_TOG             0x0000004c
  60 #define AUART_INTR                      0x00000050
  61 #define AUART_INTR_SET                  0x00000054
  62 #define AUART_INTR_CLR                  0x00000058
  63 #define AUART_INTR_TOG                  0x0000005c
  64 #define AUART_DATA                      0x00000060
  65 #define AUART_STAT                      0x00000070
  66 #define AUART_DEBUG                     0x00000080
  67 #define AUART_VERSION                   0x00000090
  68 #define AUART_AUTOBAUD                  0x000000a0
  69
  70 #define AUART_CTRL0_SFTRST                      (1 << 31)
  71 #define AUART_CTRL0_CLKGATE                     (1 << 30)
  72
  73 #define AUART_CTRL2_CTSEN                       (1 << 15)
  74 #define AUART_CTRL2_RTS                         (1 << 11)
  75 #define AUART_CTRL2_RXE                         (1 << 9)
  76 #define AUART_CTRL2_TXE                         (1 << 8)
  77 #define AUART_CTRL2_UARTEN                      (1 << 0)
  78
  79 #define AUART_LINECTRL_BAUD_DIVINT_SHIFT        16
  80 #define AUART_LINECTRL_BAUD_DIVINT_MASK         0xffff0000
  81 #define AUART_LINECTRL_BAUD_DIVINT(v)           (((v) & 0xffff) << 16)
  82 #define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT       8
  83 #define AUART_LINECTRL_BAUD_DIVFRAC_MASK        0x00003f00
  84 #define AUART_LINECTRL_BAUD_DIVFRAC(v)          (((v) & 0x3f) << 8)
  85 #define AUART_LINECTRL_WLEN_MASK                0x00000060
  86 #define AUART_LINECTRL_WLEN(v)                  (((v) & 0x3) << 5)
  87 #define AUART_LINECTRL_FEN                      (1 << 4)
  88 #define AUART_LINECTRL_STP2                     (1 << 3)
  89 #define AUART_LINECTRL_EPS                      (1 << 2)
  90 #define AUART_LINECTRL_PEN                      (1 << 1)
  91 #define AUART_LINECTRL_BRK                      (1 << 0)
  92
  93 #define AUART_INTR_RTIEN                        (1 << 22)
  94 #define AUART_INTR_TXIEN                        (1 << 21)
  95 #define AUART_INTR_RXIEN                        (1 << 20)
  96 #define AUART_INTR_CTSMIEN                      (1 << 17)
  97 #define AUART_INTR_RTIS                         (1 << 6)
  98 #define AUART_INTR_TXIS                         (1 << 5)
  99 #define AUART_INTR_RXIS                         (1 << 4)
 100 #define AUART_INTR_CTSMIS                       (1 << 1)
 101
 102 #define AUART_STAT_BUSY                         (1 << 29)
 103 #define AUART_STAT_CTS                          (1 << 28)
 104 #define AUART_STAT_TXFE                         (1 << 27)
 105 #define AUART_STAT_TXFF                         (1 << 25)
 106 #define AUART_STAT_RXFE                         (1 << 24)
 107 #define AUART_STAT_OERR                         (1 << 19)
 108 #define AUART_STAT_BERR                         (1 << 18)
 109 #define AUART_STAT_PERR                         (1 << 17)
 110 #define AUART_STAT_FERR                         (1 << 16)
 111
 112 static struct uart_driver auart_driver;
 113
 114 struct mxs_auart_port {
 115         struct uart_port port;
 116
 117         unsigned int flags;
 118         unsigned int ctrl;
 119
 120         unsigned int irq;
 121
 122         struct clk *clk;
 123         struct device *dev;
 124 };
 125
 126 static void mxs_auart_stop_tx(struct uart_port *u);
 127
 128 #define to_auart_port(u) container_of(u, struct mxs_auart_port, port)
 129
 130 static inline void mxs_auart_tx_chars(struct mxs_auart_port *s)
 131 {
 132         struct circ_buf *xmit = &s->port.state->xmit;
 133
 134         while (!(readl(s->port.membase + AUART_STAT) &
 135                  AUART_STAT_TXFF)) {
 136                 if (s->port.x_char) {
 137                         s->port.icount.tx++;
 138                         writel(s->port.x_char,
 139                                      s->port.membase + AUART_DATA);
 140                         s->port.x_char = 0;
 141                         continue;
 142                 }
 143                 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
 144                         s->port.icount.tx++;
 145                         writel(xmit->buf[xmit->tail],
 146                                      s->port.membase + AUART_DATA);
 147                         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 148                 } else
 149                         break;
 150         }
 151         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 152                 uart_write_wakeup(&s->port);
 153
 154         if (uart_circ_empty(&(s->port.state->xmit)))
 155                 writel(AUART_INTR_TXIEN,
 156                              s->port.membase + AUART_INTR_CLR);
 157         else
 158                 writel(AUART_INTR_TXIEN,
 159                              s->port.membase + AUART_INTR_SET);
 160
 161         if (uart_tx_stopped(&s->port))
 162                 mxs_auart_stop_tx(&s->port);
 163 }
 164
 165 static void mxs_auart_rx_char(struct mxs_auart_port *s)
 166 {
 167         int flag;
 168         u32 stat;
 169         u8 c;
 170
 171         c = readl(s->port.membase + AUART_DATA);
 172         stat = readl(s->port.membase + AUART_STAT);
 173
 174         flag = TTY_NORMAL;
 175         s->port.icount.rx++;
 176
 177         if (stat & AUART_STAT_BERR) {
 178                 s->port.icount.brk++;
 179                 if (uart_handle_break(&s->port))
 180                         goto out;
 181         } else if (stat & AUART_STAT_PERR) {
 182                 s->port.icount.parity++;
 183         } else if (stat & AUART_STAT_FERR) {
 184                 s->port.icount.frame++;
 185         }
 186
 187         /*
 188          * Mask off conditions which should be ingored.
 189          */
 190         stat &= s->port.read_status_mask;
 191
 192         if (stat & AUART_STAT_BERR) {
 193                 flag = TTY_BREAK;
 194         } else if (stat & AUART_STAT_PERR)
 195                 flag = TTY_PARITY;
 196         else if (stat & AUART_STAT_FERR)
 197                 flag = TTY_FRAME;
 198
 199         if (stat & AUART_STAT_OERR)
 200                 s->port.icount.overrun++;
 201
 202         if (uart_handle_sysrq_char(&s->port, c))
 203                 goto out;
 204
 205         uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag);
 206 out:
 207         writel(stat, s->port.membase + AUART_STAT);
 208 }
 209
 210 static void mxs_auart_rx_chars(struct mxs_auart_port *s)
 211 {
 212         struct tty_struct *tty = s->port.state->port.tty;
 213         u32 stat = 0;
 214
 215         for (;;) {
 216                 stat = readl(s->port.membase + AUART_STAT);
 217                 if (stat & AUART_STAT_RXFE)
 218                         break;
 219                 mxs_auart_rx_char(s);
 220         }
 221
 222         writel(stat, s->port.membase + AUART_STAT);
 223         tty_flip_buffer_push(tty);
 224 }
 225
 226 static int mxs_auart_request_port(struct uart_port *u)
 227 {
 228         return 0;
 229 }
 230
 231 static int mxs_auart_verify_port(struct uart_port *u,
 232                                     struct serial_struct *ser)
 233 {
 234         if (u->type != PORT_UNKNOWN && u->type != PORT_IMX)
 235                 return -EINVAL;
 236         return 0;
 237 }
 238
 239 static void mxs_auart_config_port(struct uart_port *u, int flags)
 240 {
 241 }
 242
 243 static const char *mxs_auart_type(struct uart_port *u)
 244 {
 245         struct mxs_auart_port *s = to_auart_port(u);
 246
 247         return dev_name(s->dev);
 248 }
 249
 250 static void mxs_auart_release_port(struct uart_port *u)
 251 {
 252 }
 253
 254 static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl)
 255 {
 256         struct mxs_auart_port *s = to_auart_port(u);
 257
 258         u32 ctrl = readl(u->membase + AUART_CTRL2);
 259
 260         ctrl &= ~AUART_CTRL2_RTS;
 261         if (mctrl & TIOCM_RTS)
 262                 ctrl |= AUART_CTRL2_RTS;
 263         s->ctrl = mctrl;
 264         writel(ctrl, u->membase + AUART_CTRL2);
 265 }
 266
 267 static u32 mxs_auart_get_mctrl(struct uart_port *u)
 268 {
 269         struct mxs_auart_port *s = to_auart_port(u);
 270         u32 stat = readl(u->membase + AUART_STAT);
 271         int ctrl2 = readl(u->membase + AUART_CTRL2);
 272         u32 mctrl = s->ctrl;
 273
 274         mctrl &= ~TIOCM_CTS;
 275         if (stat & AUART_STAT_CTS)
 276                 mctrl |= TIOCM_CTS;
 277
 278         if (ctrl2 & AUART_CTRL2_RTS)
 279                 mctrl |= TIOCM_RTS;
 280
 281         return mctrl;
 282 }
 283
 284 static void mxs_auart_settermios(struct uart_port *u,
 285                                  struct ktermios *termios,
 286                                  struct ktermios *old)
 287 {
 288         u32 bm, ctrl, ctrl2, div;
 289         unsigned int cflag, baud;
 290
 291         cflag = termios->c_cflag;
 292
 293         ctrl = AUART_LINECTRL_FEN;
 294         ctrl2 = readl(u->membase + AUART_CTRL2);
 295
 296         /* byte size */
 297         switch (cflag & CSIZE) {
 298         case CS5:
 299                 bm = 0;
 300                 break;
 301         case CS6:
 302                 bm = 1;
 303                 break;
 304         case CS7:
 305                 bm = 2;
 306                 break;
 307         case CS8:
 308                 bm = 3;
 309                 break;
 310         default:
 311                 return;
 312         }
 313
 314         ctrl |= AUART_LINECTRL_WLEN(bm);
 315
 316         /* parity */
 317         if (cflag & PARENB) {
 318                 ctrl |= AUART_LINECTRL_PEN;
 319                 if ((cflag & PARODD) == 0)
 320                         ctrl |= AUART_LINECTRL_EPS;
 321         }
 322
 323         u->read_status_mask = 0;
 324
 325         if (termios->c_iflag & INPCK)
 326                 u->read_status_mask |= AUART_STAT_PERR;
 327         if (termios->c_iflag & (BRKINT | PARMRK))
 328                 u->read_status_mask |= AUART_STAT_BERR;
 329
 330         /*
 331          * Characters to ignore
 332          */
 333         u->ignore_status_mask = 0;
 334         if (termios->c_iflag & IGNPAR)
 335                 u->ignore_status_mask |= AUART_STAT_PERR;
 336         if (termios->c_iflag & IGNBRK) {
 337                 u->ignore_status_mask |= AUART_STAT_BERR;
 338                 /*
 339                  * If we're ignoring parity and break indicators,
 340                  * ignore overruns too (for real raw support).
 341                  */
 342                 if (termios->c_iflag & IGNPAR)
 343                         u->ignore_status_mask |= AUART_STAT_OERR;
 344         }
 345
 346         /*
 347          * ignore all characters if CREAD is not set
 348          */
 349         if (cflag & CREAD)
 350                 ctrl2 |= AUART_CTRL2_RXE;
 351         else
 352                 ctrl2 &= ~AUART_CTRL2_RXE;
 353
 354         /* figure out the stop bits requested */
 355         if (cflag & CSTOPB)
 356                 ctrl |= AUART_LINECTRL_STP2;
 357
 358         /* figure out the hardware flow control settings */
 359         if (cflag & CRTSCTS)
 360                 ctrl2 |= AUART_CTRL2_CTSEN;
 361         else
 362                 ctrl2 &= ~AUART_CTRL2_CTSEN;
 363
 364         /* set baud rate */
 365         baud = uart_get_baud_rate(u, termios, old, 0, u->uartclk);
 366         div = u->uartclk * 32 / baud;
 367         ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F);
 368         ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6);
 369
 370         writel(ctrl, u->membase + AUART_LINECTRL);
 371         writel(ctrl2, u->membase + AUART_CTRL2);
 372
 373         uart_update_timeout(u, termios->c_cflag, baud);
 374 }
 375
 376 static irqreturn_t mxs_auart_irq_handle(int irq, void *context)
 377 {
 378         u32 istat;
 379         struct mxs_auart_port *s = context;
 380         u32 stat = readl(s->port.membase + AUART_STAT);
 381
 382         istat = readl(s->port.membase + AUART_INTR);
 383
 384         /* ack irq */
 385         writel(istat & (AUART_INTR_RTIS
 386                 | AUART_INTR_TXIS
 387                 | AUART_INTR_RXIS
 388                 | AUART_INTR_CTSMIS),
 389                         s->port.membase + AUART_INTR_CLR);
 390
 391         if (istat & AUART_INTR_CTSMIS) {
 392                 uart_handle_cts_change(&s->port, stat & AUART_STAT_CTS);
 393                 writel(AUART_INTR_CTSMIS,
 394                                 s->port.membase + AUART_INTR_CLR);
 395                 istat &= ~AUART_INTR_CTSMIS;
 396         }
 397
 398         if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) {
 399                 mxs_auart_rx_chars(s);
 400                 istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS);
 401         }
 402
 403         if (istat & AUART_INTR_TXIS) {
 404                 mxs_auart_tx_chars(s);
 405                 istat &= ~AUART_INTR_TXIS;
 406         }
 407
 408         return IRQ_HANDLED;
 409 }
 410
 411 static void mxs_auart_reset(struct uart_port *u)
 412 {
 413         int i;
 414         unsigned int reg;
 415
 416         writel(AUART_CTRL0_SFTRST, u->membase + AUART_CTRL0_CLR);
 417
 418         for (i = 0; i < 10000; i++) {
 419                 reg = readl(u->membase + AUART_CTRL0);
 420                 if (!(reg & AUART_CTRL0_SFTRST))
 421                         break;
 422                 udelay(3);
 423         }
 424         writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
 425 }
 426
 427 static int mxs_auart_startup(struct uart_port *u)
 428 {
 429         struct mxs_auart_port *s = to_auart_port(u);
 430
 431         clk_prepare_enable(s->clk);
 432
 433         writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
 434
 435         writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_SET);
 436
 437         writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
 438                         u->membase + AUART_INTR);
 439
 440         /*
 441          * Enable fifo so all four bytes of a DMA word are written to
 442          * output (otherwise, only the LSB is written, ie. 1 in 4 bytes)
 443          */
 444         writel(AUART_LINECTRL_FEN, u->membase + AUART_LINECTRL_SET);
 445
 446         return 0;
 447 }
 448
 449 static void mxs_auart_shutdown(struct uart_port *u)
 450 {
 451         struct mxs_auart_port *s = to_auart_port(u);
 452
 453         writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_CLR);
 454
 455         writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_SET);
 456
 457         writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
 458                         u->membase + AUART_INTR_CLR);
 459
 460         clk_disable_unprepare(s->clk);
 461 }
 462
 463 static unsigned int mxs_auart_tx_empty(struct uart_port *u)
 464 {
 465         if (readl(u->membase + AUART_STAT) & AUART_STAT_TXFE)
 466                 return TIOCSER_TEMT;
 467         else
 468                 return 0;
 469 }
 470
 471 static void mxs_auart_start_tx(struct uart_port *u)
 472 {
 473         struct mxs_auart_port *s = to_auart_port(u);
 474
 475         /* enable transmitter */
 476         writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_SET);
 477
 478         mxs_auart_tx_chars(s);
 479 }
 480
 481 static void mxs_auart_stop_tx(struct uart_port *u)
 482 {
 483         writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_CLR);
 484 }
 485
 486 static void mxs_auart_stop_rx(struct uart_port *u)
 487 {
 488         writel(AUART_CTRL2_RXE, u->membase + AUART_CTRL2_CLR);
 489 }
 490
 491 static void mxs_auart_break_ctl(struct uart_port *u, int ctl)
 492 {
 493         if (ctl)
 494                 writel(AUART_LINECTRL_BRK,
 495                              u->membase + AUART_LINECTRL_SET);
 496         else
 497                 writel(AUART_LINECTRL_BRK,
 498                              u->membase + AUART_LINECTRL_CLR);
 499 }
 500
 501 static void mxs_auart_enable_ms(struct uart_port *port)
 502 {
 503         /* just empty */
 504 }
 505
 506 static struct uart_ops mxs_auart_ops = {
 507         .tx_empty       = mxs_auart_tx_empty,
 508         .start_tx       = mxs_auart_start_tx,
 509         .stop_tx        = mxs_auart_stop_tx,
 510         .stop_rx        = mxs_auart_stop_rx,
 511         .enable_ms      = mxs_auart_enable_ms,
 512         .break_ctl      = mxs_auart_break_ctl,
 513         .set_mctrl      = mxs_auart_set_mctrl,
 514         .get_mctrl      = mxs_auart_get_mctrl,
 515         .startup        = mxs_auart_startup,
 516         .shutdown       = mxs_auart_shutdown,
 517         .set_termios    = mxs_auart_settermios,
 518         .type           = mxs_auart_type,
 519         .release_port   = mxs_auart_release_port,
 520         .request_port   = mxs_auart_request_port,
 521         .config_port    = mxs_auart_config_port,
 522         .verify_port    = mxs_auart_verify_port,
 523 };
 524
 525 static struct mxs_auart_port *auart_port[MXS_AUART_PORTS];
 526
 527 #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
 528 static void mxs_auart_console_putchar(struct uart_port *port, int ch)
 529 {
 530         unsigned int to = 1000;
 531
 532         while (readl(port->membase + AUART_STAT) & AUART_STAT_TXFF) {
 533                 if (!to--)
 534                         break;
 535                 udelay(1);
 536         }
 537
 538         writel(ch, port->membase + AUART_DATA);
 539 }
 540
 541 static void
 542 auart_console_write(struct console *co, const char *str, unsigned int count)
 543 {
 544         struct mxs_auart_port *s;
 545         struct uart_port *port;
 546         unsigned int old_ctrl0, old_ctrl2;
 547         unsigned int to = 20000;
 548
 549         if (co->index > MXS_AUART_PORTS || co->index < 0)
 550                 return;
 551
 552         s = auart_port[co->index];
 553         port = &s->port;
 554
 555         clk_enable(s->clk);
 556
 557         /* First save the CR then disable the interrupts */
 558         old_ctrl2 = readl(port->membase + AUART_CTRL2);
 559         old_ctrl0 = readl(port->membase + AUART_CTRL0);
 560
 561         writel(AUART_CTRL0_CLKGATE,
 562                      port->membase + AUART_CTRL0_CLR);
 563         writel(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE,
 564                      port->membase + AUART_CTRL2_SET);
 565
 566         uart_console_write(port, str, count, mxs_auart_console_putchar);
 567
 568         /* Finally, wait for transmitter to become empty ... */
 569         while (readl(port->membase + AUART_STAT) & AUART_STAT_BUSY) {
 570                 udelay(1);
 571                 if (!to--)
 572                         break;
 573         }
 574
 575         /*
 576          * ... and restore the TCR if we waited long enough for the transmitter
 577          * to be idle. This might keep the transmitter enabled although it is
 578          * unused, but that is better than to disable it while it is still
 579          * transmitting.
 580          */
 581         if (!(readl(port->membase + AUART_STAT) & AUART_STAT_BUSY)) {
 582                 writel(old_ctrl0, port->membase + AUART_CTRL0);
 583                 writel(old_ctrl2, port->membase + AUART_CTRL2);
 584         }
 585
 586         clk_disable(s->clk);
 587 }
 588
 589 static void __init
 590 auart_console_get_options(struct uart_port *port, int *baud,
 591                           int *parity, int *bits)
 592 {
 593         unsigned int lcr_h, quot;
 594
 595         if (!(readl(port->membase + AUART_CTRL2) & AUART_CTRL2_UARTEN))
 596                 return;
 597
 598         lcr_h = readl(port->membase + AUART_LINECTRL);
 599
 600         *parity = 'n';
 601         if (lcr_h & AUART_LINECTRL_PEN) {
 602                 if (lcr_h & AUART_LINECTRL_EPS)
 603                         *parity = 'e';
 604                 else
 605                         *parity = 'o';
 606         }
 607
 608         if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(2))
 609                 *bits = 7;
 610         else
 611                 *bits = 8;
 612
 613         quot = ((readl(port->membase + AUART_LINECTRL)
 614                         & AUART_LINECTRL_BAUD_DIVINT_MASK))
 615                             >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6);
 616         quot |= ((readl(port->membase + AUART_LINECTRL)
 617                         & AUART_LINECTRL_BAUD_DIVFRAC_MASK))
 618                                 >> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT;
 619         if (quot == 0)
 620                 quot = 1;
 621
 622         *baud = (port->uartclk << 2) / quot;
 623 }
 624
 625 static int __init
 626 auart_console_setup(struct console *co, char *options)
 627 {
 628         struct mxs_auart_port *s;
 629         int baud = 9600;
 630         int bits = 8;
 631         int parity = 'n';
 632         int flow = 'n';
 633         int ret;
 634
 635         /*
 636          * Check whether an invalid uart number has been specified, and
 637          * if so, search for the first available port that does have
 638          * console support.
 639          */
 640         if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port))
 641                 co->index = 0;
 642         s = auart_port[co->index];
 643         if (!s)
 644                 return -ENODEV;
 645
 646         clk_prepare_enable(s->clk);
 647
 648         if (options)
 649                 uart_parse_options(options, &baud, &parity, &bits, &flow);
 650         else
 651                 auart_console_get_options(&s->port, &baud, &parity, &bits);
 652
 653         ret = uart_set_options(&s->port, co, baud, parity, bits, flow);
 654
 655         clk_disable_unprepare(s->clk);
 656
 657         return ret;
 658 }
 659
 660 static struct console auart_console = {
 661         .name           = "ttyAPP",
 662         .write          = auart_console_write,
 663         .device         = uart_console_device,
 664         .setup          = auart_console_setup,
 665         .flags          = CON_PRINTBUFFER,
 666         .index          = -1,
 667         .data           = &auart_driver,
 668 };
 669 #endif
 670
 671 static struct uart_driver auart_driver = {
 672         .owner          = THIS_MODULE,
 673         .driver_name    = "ttyAPP",
 674         .dev_name       = "ttyAPP",
 675         .major          = 0,
 676         .minor          = 0,
 677         .nr             = MXS_AUART_PORTS,
 678 #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
 679         .cons =         &auart_console,
 680 #endif
 681 };
 682
 683 static int __devinit mxs_auart_probe(struct platform_device *pdev)
 684 {
 685         struct mxs_auart_port *s;
 686         u32 version;
 687         int ret = 0;
 688         struct resource *r;
 689
 690         s = kzalloc(sizeof(struct mxs_auart_port), GFP_KERNEL);
 691         if (!s) {
 692                 ret = -ENOMEM;
 693                 goto out;
 694         }
 695
 696         s->clk = clk_get(&pdev->dev, NULL);
 697         if (IS_ERR(s->clk)) {
 698                 ret = PTR_ERR(s->clk);
 699                 goto out_free;
 700         }
 701
 702         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 703         if (!r) {
 704                 ret = -ENXIO;
 705                 goto out_free_clk;
 706         }
 707
 708         s->port.mapbase = r->start;
 709         s->port.membase = ioremap(r->start, resource_size(r));
 710         s->port.ops = &mxs_auart_ops;
 711         s->port.iotype = UPIO_MEM;
 712         s->port.line = pdev->id < 0 ? 0 : pdev->id;
 713         s->port.fifosize = 16;
 714         s->port.uartclk = clk_get_rate(s->clk);
 715         s->port.type = PORT_IMX;
 716         s->port.dev = s->dev = get_device(&pdev->dev);
 717
 718         s->flags = 0;
 719         s->ctrl = 0;
 720
 721         s->irq = platform_get_irq(pdev, 0);
 722         s->port.irq = s->irq;
 723         ret = request_irq(s->irq, mxs_auart_irq_handle, 0, dev_name(&pdev->dev), s);
 724         if (ret)
 725                 goto out_free_clk;
 726
 727         platform_set_drvdata(pdev, s);
 728
 729         auart_port[pdev->id] = s;
 730
 731         mxs_auart_reset(&s->port);
 732
 733         ret = uart_add_one_port(&auart_driver, &s->port);
 734         if (ret)
 735                 goto out_free_irq;
 736
 737         version = readl(s->port.membase + AUART_VERSION);
 738         dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n",
 739                (version >> 24) & 0xff,
 740                (version >> 16) & 0xff, version & 0xffff);
 741
 742         return 0;
 743
 744 out_free_irq:
 745         auart_port[pdev->id] = NULL;
 746         free_irq(s->irq, s);
 747 out_free_clk:
 748         clk_put(s->clk);
 749 out_free:
 750         kfree(s);
 751 out:
 752         return ret;
 753 }
 754
 755 static int __devexit mxs_auart_remove(struct platform_device *pdev)
 756 {
 757         struct mxs_auart_port *s = platform_get_drvdata(pdev);
 758
 759         uart_remove_one_port(&auart_driver, &s->port);
 760
 761         auart_port[pdev->id] = NULL;
 762
 763         clk_put(s->clk);
 764         free_irq(s->irq, s);
 765         kfree(s);
 766
 767         return 0;
 768 }
 769
 770 static struct platform_driver mxs_auart_driver = {
 771         .probe = mxs_auart_probe,
 772         .remove = __devexit_p(mxs_auart_remove),
 773         .driver = {
 774                 .name = "mxs-auart",
 775                 .owner = THIS_MODULE,
 776         },
 777 };
 778
 779 static int __init mxs_auart_init(void)
 780 {
 781         int r;
 782
 783         r = uart_register_driver(&auart_driver);
 784         if (r)
 785                 goto out;
 786
 787         r = platform_driver_register(&mxs_auart_driver);
 788         if (r)
 789                 goto out_err;
 790
 791         return 0;
 792 out_err:
 793         uart_unregister_driver(&auart_driver);
 794 out:
 795         return r;
 796 }
 797
 798 static void __exit mxs_auart_exit(void)
 799 {
 800         platform_driver_unregister(&mxs_auart_driver);
 801         uart_unregister_driver(&auart_driver);
 802 }
 803
 804 module_init(mxs_auart_init);
 805 module_exit(mxs_auart_exit);
 806 MODULE_LICENSE("GPL");
 807 MODULE_DESCRIPTION("Freescale MXS application uart driver");