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Linux 3.4.102
[linux/fpc-iii.git] / drivers / tty / serial / pch_uart.c
blobe78d2a6b408332d1e63592b3f7655c0e593b9e42
1 /*
2 *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
3 *
4 *This program is free software; you can redistribute it and/or modify
5 *it under the terms of the GNU General Public License as published by
6 *the Free Software Foundation; version 2 of the License.
7 *
8 *This program is distributed in the hope that it will be useful,
9 *but WITHOUT ANY WARRANTY; without even the implied warranty of
10 *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 *GNU General Public License for more details.
12 *
13 *You should have received a copy of the GNU General Public License
14 *along with this program; if not, write to the Free Software
15 *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
16 */
17 #include <linux/kernel.h>
18 #include <linux/serial_reg.h>
19 #include <linux/slab.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/serial_core.h>
23 #include <linux/tty.h>
24 #include <linux/tty_flip.h>
25 #include <linux/interrupt.h>
26 #include <linux/io.h>
27 #include <linux/dmi.h>
28 #include <linux/console.h>
29 #include <linux/nmi.h>
30 #include <linux/delay.h>
31
32 #include <linux/debugfs.h>
33 #include <linux/dmaengine.h>
34 #include <linux/pch_dma.h>
35
36 enum {
37 PCH_UART_HANDLED_RX_INT_SHIFT,
38 PCH_UART_HANDLED_TX_INT_SHIFT,
39 PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
40 PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
41 PCH_UART_HANDLED_MS_INT_SHIFT,
42 };
43
44 enum {
45 PCH_UART_8LINE,
46 PCH_UART_2LINE,
47 };
48
49 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
50
51 /* Set the max number of UART port
52 * Intel EG20T PCH: 4 port
53 * LAPIS Semiconductor ML7213 IOH: 3 port
54 * LAPIS Semiconductor ML7223 IOH: 2 port
55 */
56 #define PCH_UART_NR 4
57
58 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
59 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
60 #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\
61 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
62 #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\
63 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
64 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
65
66 #define PCH_UART_RBR 0x00
67 #define PCH_UART_THR 0x00
68
69 #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
70 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
71 #define PCH_UART_IER_ERBFI 0x00000001
72 #define PCH_UART_IER_ETBEI 0x00000002
73 #define PCH_UART_IER_ELSI 0x00000004
74 #define PCH_UART_IER_EDSSI 0x00000008
75
76 #define PCH_UART_IIR_IP 0x00000001
77 #define PCH_UART_IIR_IID 0x00000006
78 #define PCH_UART_IIR_MSI 0x00000000
79 #define PCH_UART_IIR_TRI 0x00000002
80 #define PCH_UART_IIR_RRI 0x00000004
81 #define PCH_UART_IIR_REI 0x00000006
82 #define PCH_UART_IIR_TOI 0x00000008
83 #define PCH_UART_IIR_FIFO256 0x00000020
84 #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256
85 #define PCH_UART_IIR_FE 0x000000C0
86
87 #define PCH_UART_FCR_FIFOE 0x00000001
88 #define PCH_UART_FCR_RFR 0x00000002
89 #define PCH_UART_FCR_TFR 0x00000004
90 #define PCH_UART_FCR_DMS 0x00000008
91 #define PCH_UART_FCR_FIFO256 0x00000020
92 #define PCH_UART_FCR_RFTL 0x000000C0
93
94 #define PCH_UART_FCR_RFTL1 0x00000000
95 #define PCH_UART_FCR_RFTL64 0x00000040
96 #define PCH_UART_FCR_RFTL128 0x00000080
97 #define PCH_UART_FCR_RFTL224 0x000000C0
98 #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64
99 #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128
100 #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224
101 #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64
102 #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128
103 #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224
104 #define PCH_UART_FCR_RFTL_SHIFT 6
105
106 #define PCH_UART_LCR_WLS 0x00000003
107 #define PCH_UART_LCR_STB 0x00000004
108 #define PCH_UART_LCR_PEN 0x00000008
109 #define PCH_UART_LCR_EPS 0x00000010
110 #define PCH_UART_LCR_SP 0x00000020
111 #define PCH_UART_LCR_SB 0x00000040
112 #define PCH_UART_LCR_DLAB 0x00000080
113 #define PCH_UART_LCR_NP 0x00000000
114 #define PCH_UART_LCR_OP PCH_UART_LCR_PEN
115 #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
116 #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
117 #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
118 PCH_UART_LCR_SP)
119
120 #define PCH_UART_LCR_5BIT 0x00000000
121 #define PCH_UART_LCR_6BIT 0x00000001
122 #define PCH_UART_LCR_7BIT 0x00000002
123 #define PCH_UART_LCR_8BIT 0x00000003
124
125 #define PCH_UART_MCR_DTR 0x00000001
126 #define PCH_UART_MCR_RTS 0x00000002
127 #define PCH_UART_MCR_OUT 0x0000000C
128 #define PCH_UART_MCR_LOOP 0x00000010
129 #define PCH_UART_MCR_AFE 0x00000020
130
131 #define PCH_UART_LSR_DR 0x00000001
132 #define PCH_UART_LSR_ERR (1<<7)
133
134 #define PCH_UART_MSR_DCTS 0x00000001
135 #define PCH_UART_MSR_DDSR 0x00000002
136 #define PCH_UART_MSR_TERI 0x00000004
137 #define PCH_UART_MSR_DDCD 0x00000008
138 #define PCH_UART_MSR_CTS 0x00000010
139 #define PCH_UART_MSR_DSR 0x00000020
140 #define PCH_UART_MSR_RI 0x00000040
141 #define PCH_UART_MSR_DCD 0x00000080
142 #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
143 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
144
145 #define PCH_UART_DLL 0x00
146 #define PCH_UART_DLM 0x01
147
148 #define PCH_UART_BRCSR 0x0E
149
150 #define PCH_UART_IID_RLS (PCH_UART_IIR_REI)
151 #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI)
152 #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
153 #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI)
154 #define PCH_UART_IID_MS (PCH_UART_IIR_MSI)
155
156 #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP)
157 #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP)
158 #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP)
159 #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P)
160 #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P)
161 #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT)
162 #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT)
163 #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT)
164 #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT)
165 #define PCH_UART_HAL_STB1 0
166 #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB)
167
168 #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR)
169 #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR)
170 #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \
171 PCH_UART_HAL_CLR_RX_FIFO)
172
173 #define PCH_UART_HAL_DMA_MODE0 0
174 #define PCH_UART_HAL_FIFO_DIS 0
175 #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE)
176 #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \
177 PCH_UART_FCR_FIFO256)
178 #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256)
179 #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1)
180 #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64)
181 #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128)
182 #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224)
183 #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16)
184 #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32)
185 #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56)
186 #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4)
187 #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8)
188 #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14)
189 #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64)
190 #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128)
191 #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224)
192
193 #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI)
194 #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI)
195 #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI)
196 #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI)
197 #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK)
198
199 #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR)
200 #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS)
201 #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT)
202 #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP)
203 #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE)
204
205 #define PCI_VENDOR_ID_ROHM 0x10DB
206
207 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
208
209 #define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */
210 #define CMITC_UARTCLK 192000000 /* 192.0000 MHz */
211 #define FRI2_64_UARTCLK 64000000 /* 64.0000 MHz */
212 #define FRI2_48_UARTCLK 48000000 /* 48.0000 MHz */
213 #define NTC1_UARTCLK 64000000 /* 64.0000 MHz */
214
215 struct pch_uart_buffer {
216 unsigned char *buf;
217 int size;
218 };
219
220 struct eg20t_port {
221 struct uart_port port;
222 int port_type;
223 void __iomem *membase;
224 resource_size_t mapbase;
225 unsigned int iobase;
226 struct pci_dev *pdev;
227 int fifo_size;
228 int uartclk;
229 int start_tx;
230 int start_rx;
231 int tx_empty;
232 int int_dis_flag;
233 int trigger;
234 int trigger_level;
235 struct pch_uart_buffer rxbuf;
236 unsigned int dmsr;
237 unsigned int fcr;
238 unsigned int mcr;
239 unsigned int use_dma;
240 unsigned int use_dma_flag;
241 struct dma_async_tx_descriptor *desc_tx;
242 struct dma_async_tx_descriptor *desc_rx;
243 struct pch_dma_slave param_tx;
244 struct pch_dma_slave param_rx;
245 struct dma_chan *chan_tx;
246 struct dma_chan *chan_rx;
247 struct scatterlist *sg_tx_p;
248 int nent;
249 struct scatterlist sg_rx;
250 int tx_dma_use;
251 void *rx_buf_virt;
252 dma_addr_t rx_buf_dma;
253
254 struct dentry *debugfs;
255
256 /* protect the eg20t_port private structure and io access to membase */
257 spinlock_t lock;
258 };
259
260 /**
261 * struct pch_uart_driver_data - private data structure for UART-DMA
262 * @port_type: The number of DMA channel
263 * @line_no: UART port line number (0, 1, 2...)
264 */
265 struct pch_uart_driver_data {
266 int port_type;
267 int line_no;
268 };
269
270 enum pch_uart_num_t {
271 pch_et20t_uart0 = 0,
272 pch_et20t_uart1,
273 pch_et20t_uart2,
274 pch_et20t_uart3,
275 pch_ml7213_uart0,
276 pch_ml7213_uart1,
277 pch_ml7213_uart2,
278 pch_ml7223_uart0,
279 pch_ml7223_uart1,
280 pch_ml7831_uart0,
281 pch_ml7831_uart1,
282 };
283
284 static struct pch_uart_driver_data drv_dat[] = {
285 [pch_et20t_uart0] = {PCH_UART_8LINE, 0},
286 [pch_et20t_uart1] = {PCH_UART_2LINE, 1},
287 [pch_et20t_uart2] = {PCH_UART_2LINE, 2},
288 [pch_et20t_uart3] = {PCH_UART_2LINE, 3},
289 [pch_ml7213_uart0] = {PCH_UART_8LINE, 0},
290 [pch_ml7213_uart1] = {PCH_UART_2LINE, 1},
291 [pch_ml7213_uart2] = {PCH_UART_2LINE, 2},
292 [pch_ml7223_uart0] = {PCH_UART_8LINE, 0},
293 [pch_ml7223_uart1] = {PCH_UART_2LINE, 1},
294 [pch_ml7831_uart0] = {PCH_UART_8LINE, 0},
295 [pch_ml7831_uart1] = {PCH_UART_2LINE, 1},
296 };
297
298 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
299 static struct eg20t_port *pch_uart_ports[PCH_UART_NR];
300 #endif
301 static unsigned int default_baud = 9600;
302 static unsigned int user_uartclk = 0;
303 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
304 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
305 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
306 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
307
308 #ifdef CONFIG_DEBUG_FS
309
310 #define PCH_REGS_BUFSIZE 1024
311
312
313 static ssize_t port_show_regs(struct file *file, char __user *user_buf,
314 size_t count, loff_t *ppos)
315 {
316 struct eg20t_port *priv = file->private_data;
317 char *buf;
318 u32 len = 0;
319 ssize_t ret;
320 unsigned char lcr;
321
322 buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL);
323 if (!buf)
324 return 0;
325
326 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
327 "PCH EG20T port[%d] regs:\n", priv->port.line);
328
329 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
330 "=================================\n");
331 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
332 "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER));
333 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
334 "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR));
335 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
336 "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR));
337 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
338 "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));
339 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
340 "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR));
341 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
342 "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR));
343 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
344 "BRCSR: \t0x%02x\n",
345 ioread8(priv->membase + PCH_UART_BRCSR));
346
347 lcr = ioread8(priv->membase + UART_LCR);
348 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
349 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
350 "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL));
351 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
352 "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM));
353 iowrite8(lcr, priv->membase + UART_LCR);
354
355 if (len > PCH_REGS_BUFSIZE)
356 len = PCH_REGS_BUFSIZE;
357
358 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
359 kfree(buf);
360 return ret;
361 }
362
363 static const struct file_operations port_regs_ops = {
364 .owner = THIS_MODULE,
365 .open = simple_open,
366 .read = port_show_regs,
367 .llseek = default_llseek,
368 };
369 #endif /* CONFIG_DEBUG_FS */
370
371 /* Return UART clock, checking for board specific clocks. */
372 static int pch_uart_get_uartclk(void)
373 {
374 const char *cmp;
375
376 if (user_uartclk)
377 return user_uartclk;
378
379 cmp = dmi_get_system_info(DMI_BOARD_NAME);
380 if (cmp && strstr(cmp, "CM-iTC"))
381 return CMITC_UARTCLK;
382
383 cmp = dmi_get_system_info(DMI_BIOS_VERSION);
384 if (cmp && strnstr(cmp, "FRI2", 4))
385 return FRI2_64_UARTCLK;
386
387 cmp = dmi_get_system_info(DMI_PRODUCT_NAME);
388 if (cmp && strstr(cmp, "Fish River Island II"))
389 return FRI2_48_UARTCLK;
390
391 /* Kontron COMe-mTT10 (nanoETXexpress-TT) */
392 cmp = dmi_get_system_info(DMI_BOARD_NAME);
393 if (cmp && (strstr(cmp, "COMe-mTT") ||
394 strstr(cmp, "nanoETXexpress-TT")))
395 return NTC1_UARTCLK;
396
397 return DEFAULT_UARTCLK;
398 }
399
400 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
401 unsigned int flag)
402 {
403 u8 ier = ioread8(priv->membase + UART_IER);
404 ier |= flag & PCH_UART_IER_MASK;
405 iowrite8(ier, priv->membase + UART_IER);
406 }
407
408 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
409 unsigned int flag)
410 {
411 u8 ier = ioread8(priv->membase + UART_IER);
412 ier &= ~(flag & PCH_UART_IER_MASK);
413 iowrite8(ier, priv->membase + UART_IER);
414 }
415
416 static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud,
417 unsigned int parity, unsigned int bits,
418 unsigned int stb)
419 {
420 unsigned int dll, dlm, lcr;
421 int div;
422
423 div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud);
424 if (div < 0 || USHRT_MAX <= div) {
425 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
426 return -EINVAL;
427 }
428
429 dll = (unsigned int)div & 0x00FFU;
430 dlm = ((unsigned int)div >> 8) & 0x00FFU;
431
432 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
433 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
434 return -EINVAL;
435 }
436
437 if (bits & ~PCH_UART_LCR_WLS) {
438 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
439 return -EINVAL;
440 }
441
442 if (stb & ~PCH_UART_LCR_STB) {
443 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
444 return -EINVAL;
445 }
446
447 lcr = parity;
448 lcr |= bits;
449 lcr |= stb;
450
451 dev_dbg(priv->port.dev, "%s:baud = %d, div = %04x, lcr = %02x (%lu)\n",
452 __func__, baud, div, lcr, jiffies);
453 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
454 iowrite8(dll, priv->membase + PCH_UART_DLL);
455 iowrite8(dlm, priv->membase + PCH_UART_DLM);
456 iowrite8(lcr, priv->membase + UART_LCR);
457
458 return 0;
459 }
460
461 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
462 unsigned int flag)
463 {
464 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
465 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
466 __func__, flag);
467 return -EINVAL;
468 }
469
470 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
471 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
472 priv->membase + UART_FCR);
473 iowrite8(priv->fcr, priv->membase + UART_FCR);
474
475 return 0;
476 }
477
478 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
479 unsigned int dmamode,
480 unsigned int fifo_size, unsigned int trigger)
481 {
482 u8 fcr;
483
484 if (dmamode & ~PCH_UART_FCR_DMS) {
485 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
486 __func__, dmamode);
487 return -EINVAL;
488 }
489
490 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
491 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
492 __func__, fifo_size);
493 return -EINVAL;
494 }
495
496 if (trigger & ~PCH_UART_FCR_RFTL) {
497 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
498 __func__, trigger);
499 return -EINVAL;
500 }
501
502 switch (priv->fifo_size) {
503 case 256:
504 priv->trigger_level =
505 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
506 break;
507 case 64:
508 priv->trigger_level =
509 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
510 break;
511 case 16:
512 priv->trigger_level =
513 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
514 break;
515 default:
516 priv->trigger_level =
517 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
518 break;
519 }
520 fcr =
521 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
522 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
523 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
524 priv->membase + UART_FCR);
525 iowrite8(fcr, priv->membase + UART_FCR);
526 priv->fcr = fcr;
527
528 return 0;
529 }
530
531 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
532 {
533 unsigned int msr = ioread8(priv->membase + UART_MSR);
534 priv->dmsr = msr & PCH_UART_MSR_DELTA;
535 return (u8)msr;
536 }
537
538 static void pch_uart_hal_write(struct eg20t_port *priv,
539 const unsigned char *buf, int tx_size)
540 {
541 int i;
542 unsigned int thr;
543
544 for (i = 0; i < tx_size;) {
545 thr = buf[i++];
546 iowrite8(thr, priv->membase + PCH_UART_THR);
547 }
548 }
549
550 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
551 int rx_size)
552 {
553 int i;
554 u8 rbr, lsr;
555
556 lsr = ioread8(priv->membase + UART_LSR);
557 for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
558 i < rx_size && lsr & UART_LSR_DR;
559 lsr = ioread8(priv->membase + UART_LSR)) {
560 rbr = ioread8(priv->membase + PCH_UART_RBR);
561 buf[i++] = rbr;
562 }
563 return i;
564 }
565
566 static unsigned int pch_uart_hal_get_iid(struct eg20t_port *priv)
567 {
568 unsigned int iir;
569 int ret;
570
571 iir = ioread8(priv->membase + UART_IIR);
572 ret = (iir & (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP));
573 return ret;
574 }
575
576 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
577 {
578 return ioread8(priv->membase + UART_LSR);
579 }
580
581 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
582 {
583 unsigned int lcr;
584
585 lcr = ioread8(priv->membase + UART_LCR);
586 if (on)
587 lcr |= PCH_UART_LCR_SB;
588 else
589 lcr &= ~PCH_UART_LCR_SB;
590
591 iowrite8(lcr, priv->membase + UART_LCR);
592 }
593
594 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
595 int size)
596 {
597 struct uart_port *port;
598 struct tty_struct *tty;
599
600 port = &priv->port;
601 tty = tty_port_tty_get(&port->state->port);
602 if (!tty) {
603 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
604 return -EBUSY;
605 }
606
607 tty_insert_flip_string(tty, buf, size);
608 tty_flip_buffer_push(tty);
609 tty_kref_put(tty);
610
611 return 0;
612 }
613
614 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
615 {
616 int ret = 0;
617 struct uart_port *port = &priv->port;
618
619 if (port->x_char) {
620 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
621 __func__, port->x_char, jiffies);
622 buf[0] = port->x_char;
623 port->x_char = 0;
624 ret = 1;
625 }
626
627 return ret;
628 }
629
630 static int dma_push_rx(struct eg20t_port *priv, int size)
631 {
632 struct tty_struct *tty;
633 int room;
634 struct uart_port *port = &priv->port;
635
636 port = &priv->port;
637 tty = tty_port_tty_get(&port->state->port);
638 if (!tty) {
639 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
640 return 0;
641 }
642
643 room = tty_buffer_request_room(tty, size);
644
645 if (room < size)
646 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
647 size - room);
648 if (!room)
649 goto out;
650
651 tty_insert_flip_string(tty, sg_virt(&priv->sg_rx), size);
652
653 port->icount.rx += room;
654 out:
655 tty_kref_put(tty);
656
657 return room;
658 }
659
660 static void pch_free_dma(struct uart_port *port)
661 {
662 struct eg20t_port *priv;
663 priv = container_of(port, struct eg20t_port, port);
664
665 if (priv->chan_tx) {
666 dma_release_channel(priv->chan_tx);
667 priv->chan_tx = NULL;
668 }
669 if (priv->chan_rx) {
670 dma_release_channel(priv->chan_rx);
671 priv->chan_rx = NULL;
672 }
673 if (sg_dma_address(&priv->sg_rx))
674 dma_free_coherent(port->dev, port->fifosize,
675 sg_virt(&priv->sg_rx),
676 sg_dma_address(&priv->sg_rx));
677
678 return;
679 }
680
681 static bool filter(struct dma_chan *chan, void *slave)
682 {
683 struct pch_dma_slave *param = slave;
684
685 if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
686 chan->device->dev)) {
687 chan->private = param;
688 return true;
689 } else {
690 return false;
691 }
692 }
693
694 static void pch_request_dma(struct uart_port *port)
695 {
696 dma_cap_mask_t mask;
697 struct dma_chan *chan;
698 struct pci_dev *dma_dev;
699 struct pch_dma_slave *param;
700 struct eg20t_port *priv =
701 container_of(port, struct eg20t_port, port);
702 dma_cap_zero(mask);
703 dma_cap_set(DMA_SLAVE, mask);
704
705 dma_dev = pci_get_bus_and_slot(priv->pdev->bus->number,
706 PCI_DEVFN(0xa, 0)); /* Get DMA's dev
707 information */
708 /* Set Tx DMA */
709 param = &priv->param_tx;
710 param->dma_dev = &dma_dev->dev;
711 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
712
713 param->tx_reg = port->mapbase + UART_TX;
714 chan = dma_request_channel(mask, filter, param);
715 if (!chan) {
716 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
717 __func__);
718 return;
719 }
720 priv->chan_tx = chan;
721
722 /* Set Rx DMA */
723 param = &priv->param_rx;
724 param->dma_dev = &dma_dev->dev;
725 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
726
727 param->rx_reg = port->mapbase + UART_RX;
728 chan = dma_request_channel(mask, filter, param);
729 if (!chan) {
730 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
731 __func__);
732 dma_release_channel(priv->chan_tx);
733 priv->chan_tx = NULL;
734 return;
735 }
736
737 /* Get Consistent memory for DMA */
738 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
739 &priv->rx_buf_dma, GFP_KERNEL);
740 priv->chan_rx = chan;
741 }
742
743 static void pch_dma_rx_complete(void *arg)
744 {
745 struct eg20t_port *priv = arg;
746 struct uart_port *port = &priv->port;
747 struct tty_struct *tty = tty_port_tty_get(&port->state->port);
748 int count;
749
750 if (!tty) {
751 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
752 return;
753 }
754
755 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
756 count = dma_push_rx(priv, priv->trigger_level);
757 if (count)
758 tty_flip_buffer_push(tty);
759 tty_kref_put(tty);
760 async_tx_ack(priv->desc_rx);
761 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
762 PCH_UART_HAL_RX_ERR_INT);
763 }
764
765 static void pch_dma_tx_complete(void *arg)
766 {
767 struct eg20t_port *priv = arg;
768 struct uart_port *port = &priv->port;
769 struct circ_buf *xmit = &port->state->xmit;
770 struct scatterlist *sg = priv->sg_tx_p;
771 int i;
772
773 for (i = 0; i < priv->nent; i++, sg++) {
774 xmit->tail += sg_dma_len(sg);
775 port->icount.tx += sg_dma_len(sg);
776 }
777 xmit->tail &= UART_XMIT_SIZE - 1;
778 async_tx_ack(priv->desc_tx);
779 dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE);
780 priv->tx_dma_use = 0;
781 priv->nent = 0;
782 kfree(priv->sg_tx_p);
783 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
784 }
785
786 static int pop_tx(struct eg20t_port *priv, int size)
787 {
788 int count = 0;
789 struct uart_port *port = &priv->port;
790 struct circ_buf *xmit = &port->state->xmit;
791
792 if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
793 goto pop_tx_end;
794
795 do {
796 int cnt_to_end =
797 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
798 int sz = min(size - count, cnt_to_end);
799 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
800 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
801 count += sz;
802 } while (!uart_circ_empty(xmit) && count < size);
803
804 pop_tx_end:
805 dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
806 count, size - count, jiffies);
807
808 return count;
809 }
810
811 static int handle_rx_to(struct eg20t_port *priv)
812 {
813 struct pch_uart_buffer *buf;
814 int rx_size;
815 int ret;
816 if (!priv->start_rx) {
817 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
818 PCH_UART_HAL_RX_ERR_INT);
819 return 0;
820 }
821 buf = &priv->rxbuf;
822 do {
823 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
824 ret = push_rx(priv, buf->buf, rx_size);
825 if (ret)
826 return 0;
827 } while (rx_size == buf->size);
828
829 return PCH_UART_HANDLED_RX_INT;
830 }
831
832 static int handle_rx(struct eg20t_port *priv)
833 {
834 return handle_rx_to(priv);
835 }
836
837 static int dma_handle_rx(struct eg20t_port *priv)
838 {
839 struct uart_port *port = &priv->port;
840 struct dma_async_tx_descriptor *desc;
841 struct scatterlist *sg;
842
843 priv = container_of(port, struct eg20t_port, port);
844 sg = &priv->sg_rx;
845
846 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
847
848 sg_dma_len(sg) = priv->trigger_level;
849
850 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
851 sg_dma_len(sg), (unsigned long)priv->rx_buf_virt &
852 ~PAGE_MASK);
853
854 sg_dma_address(sg) = priv->rx_buf_dma;
855
856 desc = dmaengine_prep_slave_sg(priv->chan_rx,
857 sg, 1, DMA_DEV_TO_MEM,
858 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
859
860 if (!desc)
861 return 0;
862
863 priv->desc_rx = desc;
864 desc->callback = pch_dma_rx_complete;
865 desc->callback_param = priv;
866 desc->tx_submit(desc);
867 dma_async_issue_pending(priv->chan_rx);
868
869 return PCH_UART_HANDLED_RX_INT;
870 }
871
872 static unsigned int handle_tx(struct eg20t_port *priv)
873 {
874 struct uart_port *port = &priv->port;
875 struct circ_buf *xmit = &port->state->xmit;
876 int fifo_size;
877 int tx_size;
878 int size;
879 int tx_empty;
880
881 if (!priv->start_tx) {
882 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
883 __func__, jiffies);
884 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
885 priv->tx_empty = 1;
886 return 0;
887 }
888
889 fifo_size = max(priv->fifo_size, 1);
890 tx_empty = 1;
891 if (pop_tx_x(priv, xmit->buf)) {
892 pch_uart_hal_write(priv, xmit->buf, 1);
893 port->icount.tx++;
894 tx_empty = 0;
895 fifo_size--;
896 }
897 size = min(xmit->head - xmit->tail, fifo_size);
898 if (size < 0)
899 size = fifo_size;
900
901 tx_size = pop_tx(priv, size);
902 if (tx_size > 0) {
903 port->icount.tx += tx_size;
904 tx_empty = 0;
905 }
906
907 priv->tx_empty = tx_empty;
908
909 if (tx_empty) {
910 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
911 uart_write_wakeup(port);
912 }
913
914 return PCH_UART_HANDLED_TX_INT;
915 }
916
917 static unsigned int dma_handle_tx(struct eg20t_port *priv)
918 {
919 struct uart_port *port = &priv->port;
920 struct circ_buf *xmit = &port->state->xmit;
921 struct scatterlist *sg;
922 int nent;
923 int fifo_size;
924 int tx_empty;
925 struct dma_async_tx_descriptor *desc;
926 int num;
927 int i;
928 int bytes;
929 int size;
930 int rem;
931
932 if (!priv->start_tx) {
933 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
934 __func__, jiffies);
935 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
936 priv->tx_empty = 1;
937 return 0;
938 }
939
940 if (priv->tx_dma_use) {
941 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
942 __func__, jiffies);
943 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
944 priv->tx_empty = 1;
945 return 0;
946 }
947
948 fifo_size = max(priv->fifo_size, 1);
949 tx_empty = 1;
950 if (pop_tx_x(priv, xmit->buf)) {
951 pch_uart_hal_write(priv, xmit->buf, 1);
952 port->icount.tx++;
953 tx_empty = 0;
954 fifo_size--;
955 }
956
957 bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
958 UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
959 xmit->tail, UART_XMIT_SIZE));
960 if (!bytes) {
961 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
962 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
963 uart_write_wakeup(port);
964 return 0;
965 }
966
967 if (bytes > fifo_size) {
968 num = bytes / fifo_size + 1;
969 size = fifo_size;
970 rem = bytes % fifo_size;
971 } else {
972 num = 1;
973 size = bytes;
974 rem = bytes;
975 }
976
977 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
978 __func__, num, size, rem);
979
980 priv->tx_dma_use = 1;
981
982 priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
983
984 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
985 sg = priv->sg_tx_p;
986
987 for (i = 0; i < num; i++, sg++) {
988 if (i == (num - 1))
989 sg_set_page(sg, virt_to_page(xmit->buf),
990 rem, fifo_size * i);
991 else
992 sg_set_page(sg, virt_to_page(xmit->buf),
993 size, fifo_size * i);
994 }
995
996 sg = priv->sg_tx_p;
997 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
998 if (!nent) {
999 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
1000 return 0;
1001 }
1002 priv->nent = nent;
1003
1004 for (i = 0; i < nent; i++, sg++) {
1005 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
1006 fifo_size * i;
1007 sg_dma_address(sg) = (sg_dma_address(sg) &
1008 ~(UART_XMIT_SIZE - 1)) + sg->offset;
1009 if (i == (nent - 1))
1010 sg_dma_len(sg) = rem;
1011 else
1012 sg_dma_len(sg) = size;
1013 }
1014
1015 desc = dmaengine_prep_slave_sg(priv->chan_tx,
1016 priv->sg_tx_p, nent, DMA_MEM_TO_DEV,
1017 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1018 if (!desc) {
1019 dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n",
1020 __func__);
1021 return 0;
1022 }
1023 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
1024 priv->desc_tx = desc;
1025 desc->callback = pch_dma_tx_complete;
1026 desc->callback_param = priv;
1027
1028 desc->tx_submit(desc);
1029
1030 dma_async_issue_pending(priv->chan_tx);
1031
1032 return PCH_UART_HANDLED_TX_INT;
1033 }
1034
1035 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
1036 {
1037 u8 fcr = ioread8(priv->membase + UART_FCR);
1038 struct uart_port *port = &priv->port;
1039 struct tty_struct *tty = tty_port_tty_get(&port->state->port);
1040 char *error_msg[5] = {};
1041 int i = 0;
1042
1043 /* Reset FIFO */
1044 fcr |= UART_FCR_CLEAR_RCVR;
1045 iowrite8(fcr, priv->membase + UART_FCR);
1046
1047 if (lsr & PCH_UART_LSR_ERR)
1048 error_msg[i++] = "Error data in FIFO\n";
1049
1050 if (lsr & UART_LSR_FE) {
1051 port->icount.frame++;
1052 error_msg[i++] = " Framing Error\n";
1053 }
1054
1055 if (lsr & UART_LSR_PE) {
1056 port->icount.parity++;
1057 error_msg[i++] = " Parity Error\n";
1058 }
1059
1060 if (lsr & UART_LSR_OE) {
1061 port->icount.overrun++;
1062 error_msg[i++] = " Overrun Error\n";
1063 }
1064
1065 if (tty == NULL) {
1066 for (i = 0; error_msg[i] != NULL; i++)
1067 dev_err(&priv->pdev->dev, error_msg[i]);
1068 } else {
1069 tty_kref_put(tty);
1070 }
1071 }
1072
1073 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
1074 {
1075 struct eg20t_port *priv = dev_id;
1076 unsigned int handled;
1077 u8 lsr;
1078 int ret = 0;
1079 unsigned int iid;
1080 unsigned long flags;
1081
1082 spin_lock_irqsave(&priv->lock, flags);
1083 handled = 0;
1084 while ((iid = pch_uart_hal_get_iid(priv)) > 1) {
1085 switch (iid) {
1086 case PCH_UART_IID_RLS: /* Receiver Line Status */
1087 lsr = pch_uart_hal_get_line_status(priv);
1088 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
1089 UART_LSR_PE | UART_LSR_OE)) {
1090 pch_uart_err_ir(priv, lsr);
1091 ret = PCH_UART_HANDLED_RX_ERR_INT;
1092 }
1093 break;
1094 case PCH_UART_IID_RDR: /* Received Data Ready */
1095 if (priv->use_dma) {
1096 pch_uart_hal_disable_interrupt(priv,
1097 PCH_UART_HAL_RX_INT |
1098 PCH_UART_HAL_RX_ERR_INT);
1099 ret = dma_handle_rx(priv);
1100 if (!ret)
1101 pch_uart_hal_enable_interrupt(priv,
1102 PCH_UART_HAL_RX_INT |
1103 PCH_UART_HAL_RX_ERR_INT);
1104 } else {
1105 ret = handle_rx(priv);
1106 }
1107 break;
1108 case PCH_UART_IID_RDR_TO: /* Received Data Ready
1109 (FIFO Timeout) */
1110 ret = handle_rx_to(priv);
1111 break;
1112 case PCH_UART_IID_THRE: /* Transmitter Holding Register
1113 Empty */
1114 if (priv->use_dma)
1115 ret = dma_handle_tx(priv);
1116 else
1117 ret = handle_tx(priv);
1118 break;
1119 case PCH_UART_IID_MS: /* Modem Status */
1120 ret = PCH_UART_HANDLED_MS_INT;
1121 break;
1122 default: /* Never junp to this label */
1123 dev_err(priv->port.dev, "%s:iid=%d (%lu)\n", __func__,
1124 iid, jiffies);
1125 ret = -1;
1126 break;
1127 }
1128 handled |= (unsigned int)ret;
1129 }
1130 if (handled == 0 && iid <= 1) {
1131 if (priv->int_dis_flag)
1132 priv->int_dis_flag = 0;
1133 }
1134
1135 spin_unlock_irqrestore(&priv->lock, flags);
1136 return IRQ_RETVAL(handled);
1137 }
1138
1139 /* This function tests whether the transmitter fifo and shifter for the port
1140 described by 'port' is empty. */
1141 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1142 {
1143 struct eg20t_port *priv;
1144
1145 priv = container_of(port, struct eg20t_port, port);
1146 if (priv->tx_empty)
1147 return TIOCSER_TEMT;
1148 else
1149 return 0;
1150 }
1151
1152 /* Returns the current state of modem control inputs. */
1153 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1154 {
1155 struct eg20t_port *priv;
1156 u8 modem;
1157 unsigned int ret = 0;
1158
1159 priv = container_of(port, struct eg20t_port, port);
1160 modem = pch_uart_hal_get_modem(priv);
1161
1162 if (modem & UART_MSR_DCD)
1163 ret |= TIOCM_CAR;
1164
1165 if (modem & UART_MSR_RI)
1166 ret |= TIOCM_RNG;
1167
1168 if (modem & UART_MSR_DSR)
1169 ret |= TIOCM_DSR;
1170
1171 if (modem & UART_MSR_CTS)
1172 ret |= TIOCM_CTS;
1173
1174 return ret;
1175 }
1176
1177 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1178 {
1179 u32 mcr = 0;
1180 struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1181
1182 if (mctrl & TIOCM_DTR)
1183 mcr |= UART_MCR_DTR;
1184 if (mctrl & TIOCM_RTS)
1185 mcr |= UART_MCR_RTS;
1186 if (mctrl & TIOCM_LOOP)
1187 mcr |= UART_MCR_LOOP;
1188
1189 if (priv->mcr & UART_MCR_AFE)
1190 mcr |= UART_MCR_AFE;
1191
1192 if (mctrl)
1193 iowrite8(mcr, priv->membase + UART_MCR);
1194 }
1195
1196 static void pch_uart_stop_tx(struct uart_port *port)
1197 {
1198 struct eg20t_port *priv;
1199 priv = container_of(port, struct eg20t_port, port);
1200 priv->start_tx = 0;
1201 priv->tx_dma_use = 0;
1202 }
1203
1204 static void pch_uart_start_tx(struct uart_port *port)
1205 {
1206 struct eg20t_port *priv;
1207
1208 priv = container_of(port, struct eg20t_port, port);
1209
1210 if (priv->use_dma) {
1211 if (priv->tx_dma_use) {
1212 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1213 __func__);
1214 return;
1215 }
1216 }
1217
1218 priv->start_tx = 1;
1219 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1220 }
1221
1222 static void pch_uart_stop_rx(struct uart_port *port)
1223 {
1224 struct eg20t_port *priv;
1225 priv = container_of(port, struct eg20t_port, port);
1226 priv->start_rx = 0;
1227 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
1228 PCH_UART_HAL_RX_ERR_INT);
1229 priv->int_dis_flag = 1;
1230 }
1231
1232 /* Enable the modem status interrupts. */
1233 static void pch_uart_enable_ms(struct uart_port *port)
1234 {
1235 struct eg20t_port *priv;
1236 priv = container_of(port, struct eg20t_port, port);
1237 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1238 }
1239
1240 /* Control the transmission of a break signal. */
1241 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1242 {
1243 struct eg20t_port *priv;
1244 unsigned long flags;
1245
1246 priv = container_of(port, struct eg20t_port, port);
1247 spin_lock_irqsave(&priv->lock, flags);
1248 pch_uart_hal_set_break(priv, ctl);
1249 spin_unlock_irqrestore(&priv->lock, flags);
1250 }
1251
1252 /* Grab any interrupt resources and initialise any low level driver state. */
1253 static int pch_uart_startup(struct uart_port *port)
1254 {
1255 struct eg20t_port *priv;
1256 int ret;
1257 int fifo_size;
1258 int trigger_level;
1259
1260 priv = container_of(port, struct eg20t_port, port);
1261 priv->tx_empty = 1;
1262
1263 if (port->uartclk)
1264 priv->uartclk = port->uartclk;
1265 else
1266 port->uartclk = priv->uartclk;
1267
1268 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1269 ret = pch_uart_hal_set_line(priv, default_baud,
1270 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1271 PCH_UART_HAL_STB1);
1272 if (ret)
1273 return ret;
1274
1275 switch (priv->fifo_size) {
1276 case 256:
1277 fifo_size = PCH_UART_HAL_FIFO256;
1278 break;
1279 case 64:
1280 fifo_size = PCH_UART_HAL_FIFO64;
1281 break;
1282 case 16:
1283 fifo_size = PCH_UART_HAL_FIFO16;
1284 break;
1285 case 1:
1286 default:
1287 fifo_size = PCH_UART_HAL_FIFO_DIS;
1288 break;
1289 }
1290
1291 switch (priv->trigger) {
1292 case PCH_UART_HAL_TRIGGER1:
1293 trigger_level = 1;
1294 break;
1295 case PCH_UART_HAL_TRIGGER_L:
1296 trigger_level = priv->fifo_size / 4;
1297 break;
1298 case PCH_UART_HAL_TRIGGER_M:
1299 trigger_level = priv->fifo_size / 2;
1300 break;
1301 case PCH_UART_HAL_TRIGGER_H:
1302 default:
1303 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1304 break;
1305 }
1306
1307 priv->trigger_level = trigger_level;
1308 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1309 fifo_size, priv->trigger);
1310 if (ret < 0)
1311 return ret;
1312
1313 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1314 KBUILD_MODNAME, priv);
1315 if (ret < 0)
1316 return ret;
1317
1318 if (priv->use_dma)
1319 pch_request_dma(port);
1320
1321 priv->start_rx = 1;
1322 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
1323 PCH_UART_HAL_RX_ERR_INT);
1324 uart_update_timeout(port, CS8, default_baud);
1325
1326 return 0;
1327 }
1328
1329 static void pch_uart_shutdown(struct uart_port *port)
1330 {
1331 struct eg20t_port *priv;
1332 int ret;
1333
1334 priv = container_of(port, struct eg20t_port, port);
1335 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1336 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1337 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1338 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1339 if (ret)
1340 dev_err(priv->port.dev,
1341 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1342
1343 pch_free_dma(port);
1344
1345 free_irq(priv->port.irq, priv);
1346 }
1347
1348 /* Change the port parameters, including word length, parity, stop
1349 *bits. Update read_status_mask and ignore_status_mask to indicate
1350 *the types of events we are interested in receiving. */
1351 static void pch_uart_set_termios(struct uart_port *port,
1352 struct ktermios *termios, struct ktermios *old)
1353 {
1354 int baud;
1355 int rtn;
1356 unsigned int parity, bits, stb;
1357 struct eg20t_port *priv;
1358 unsigned long flags;
1359
1360 priv = container_of(port, struct eg20t_port, port);
1361 switch (termios->c_cflag & CSIZE) {
1362 case CS5:
1363 bits = PCH_UART_HAL_5BIT;
1364 break;
1365 case CS6:
1366 bits = PCH_UART_HAL_6BIT;
1367 break;
1368 case CS7:
1369 bits = PCH_UART_HAL_7BIT;
1370 break;
1371 default: /* CS8 */
1372 bits = PCH_UART_HAL_8BIT;
1373 break;
1374 }
1375 if (termios->c_cflag & CSTOPB)
1376 stb = PCH_UART_HAL_STB2;
1377 else
1378 stb = PCH_UART_HAL_STB1;
1379
1380 if (termios->c_cflag & PARENB) {
1381 if (termios->c_cflag & PARODD)
1382 parity = PCH_UART_HAL_PARITY_ODD;
1383 else
1384 parity = PCH_UART_HAL_PARITY_EVEN;
1385
1386 } else
1387 parity = PCH_UART_HAL_PARITY_NONE;
1388
1389 /* Only UART0 has auto hardware flow function */
1390 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1391 priv->mcr |= UART_MCR_AFE;
1392 else
1393 priv->mcr &= ~UART_MCR_AFE;
1394
1395 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1396
1397 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1398
1399 spin_lock_irqsave(&priv->lock, flags);
1400 spin_lock(&port->lock);
1401
1402 uart_update_timeout(port, termios->c_cflag, baud);
1403 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1404 if (rtn)
1405 goto out;
1406
1407 pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1408 /* Don't rewrite B0 */
1409 if (tty_termios_baud_rate(termios))
1410 tty_termios_encode_baud_rate(termios, baud, baud);
1411
1412 out:
1413 spin_unlock(&port->lock);
1414 spin_unlock_irqrestore(&priv->lock, flags);
1415 }
1416
1417 static const char *pch_uart_type(struct uart_port *port)
1418 {
1419 return KBUILD_MODNAME;
1420 }
1421
1422 static void pch_uart_release_port(struct uart_port *port)
1423 {
1424 struct eg20t_port *priv;
1425
1426 priv = container_of(port, struct eg20t_port, port);
1427 pci_iounmap(priv->pdev, priv->membase);
1428 pci_release_regions(priv->pdev);
1429 }
1430
1431 static int pch_uart_request_port(struct uart_port *port)
1432 {
1433 struct eg20t_port *priv;
1434 int ret;
1435 void __iomem *membase;
1436
1437 priv = container_of(port, struct eg20t_port, port);
1438 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1439 if (ret < 0)
1440 return -EBUSY;
1441
1442 membase = pci_iomap(priv->pdev, 1, 0);
1443 if (!membase) {
1444 pci_release_regions(priv->pdev);
1445 return -EBUSY;
1446 }
1447 priv->membase = port->membase = membase;
1448
1449 return 0;
1450 }
1451
1452 static void pch_uart_config_port(struct uart_port *port, int type)
1453 {
1454 struct eg20t_port *priv;
1455
1456 priv = container_of(port, struct eg20t_port, port);
1457 if (type & UART_CONFIG_TYPE) {
1458 port->type = priv->port_type;
1459 pch_uart_request_port(port);
1460 }
1461 }
1462
1463 static int pch_uart_verify_port(struct uart_port *port,
1464 struct serial_struct *serinfo)
1465 {
1466 struct eg20t_port *priv;
1467
1468 priv = container_of(port, struct eg20t_port, port);
1469 if (serinfo->flags & UPF_LOW_LATENCY) {
1470 dev_info(priv->port.dev,
1471 "PCH UART : Use PIO Mode (without DMA)\n");
1472 priv->use_dma = 0;
1473 serinfo->flags &= ~UPF_LOW_LATENCY;
1474 } else {
1475 #ifndef CONFIG_PCH_DMA
1476 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1477 __func__);
1478 return -EOPNOTSUPP;
1479 #endif
1480 priv->use_dma_flag = 1;
1481 dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n");
1482 if (!priv->use_dma)
1483 pch_request_dma(port);
1484 priv->use_dma = 1;
1485 }
1486
1487 return 0;
1488 }
1489
1490 static struct uart_ops pch_uart_ops = {
1491 .tx_empty = pch_uart_tx_empty,
1492 .set_mctrl = pch_uart_set_mctrl,
1493 .get_mctrl = pch_uart_get_mctrl,
1494 .stop_tx = pch_uart_stop_tx,
1495 .start_tx = pch_uart_start_tx,
1496 .stop_rx = pch_uart_stop_rx,
1497 .enable_ms = pch_uart_enable_ms,
1498 .break_ctl = pch_uart_break_ctl,
1499 .startup = pch_uart_startup,
1500 .shutdown = pch_uart_shutdown,
1501 .set_termios = pch_uart_set_termios,
1502 /* .pm = pch_uart_pm, Not supported yet */
1503 /* .set_wake = pch_uart_set_wake, Not supported yet */
1504 .type = pch_uart_type,
1505 .release_port = pch_uart_release_port,
1506 .request_port = pch_uart_request_port,
1507 .config_port = pch_uart_config_port,
1508 .verify_port = pch_uart_verify_port
1509 };
1510
1511 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1512
1513 /*
1514 * Wait for transmitter & holding register to empty
1515 */
1516 static void wait_for_xmitr(struct eg20t_port *up, int bits)
1517 {
1518 unsigned int status, tmout = 10000;
1519
1520 /* Wait up to 10ms for the character(s) to be sent. */
1521 for (;;) {
1522 status = ioread8(up->membase + UART_LSR);
1523
1524 if ((status & bits) == bits)
1525 break;
1526 if (--tmout == 0)
1527 break;
1528 udelay(1);
1529 }
1530
1531 /* Wait up to 1s for flow control if necessary */
1532 if (up->port.flags & UPF_CONS_FLOW) {
1533 unsigned int tmout;
1534 for (tmout = 1000000; tmout; tmout--) {
1535 unsigned int msr = ioread8(up->membase + UART_MSR);
1536 if (msr & UART_MSR_CTS)
1537 break;
1538 udelay(1);
1539 touch_nmi_watchdog();
1540 }
1541 }
1542 }
1543
1544 static void pch_console_putchar(struct uart_port *port, int ch)
1545 {
1546 struct eg20t_port *priv =
1547 container_of(port, struct eg20t_port, port);
1548
1549 wait_for_xmitr(priv, UART_LSR_THRE);
1550 iowrite8(ch, priv->membase + PCH_UART_THR);
1551 }
1552
1553 /*
1554 * Print a string to the serial port trying not to disturb
1555 * any possible real use of the port...
1556 *
1557 * The console_lock must be held when we get here.
1558 */
1559 static void
1560 pch_console_write(struct console *co, const char *s, unsigned int count)
1561 {
1562 struct eg20t_port *priv;
1563 unsigned long flags;
1564 int priv_locked = 1;
1565 int port_locked = 1;
1566 u8 ier;
1567
1568 priv = pch_uart_ports[co->index];
1569
1570 touch_nmi_watchdog();
1571
1572 local_irq_save(flags);
1573 if (priv->port.sysrq) {
1574 spin_lock(&priv->lock);
1575 /* serial8250_handle_port() already took the port lock */
1576 port_locked = 0;
1577 } else if (oops_in_progress) {
1578 priv_locked = spin_trylock(&priv->lock);
1579 port_locked = spin_trylock(&priv->port.lock);
1580 } else {
1581 spin_lock(&priv->lock);
1582 spin_lock(&priv->port.lock);
1583 }
1584
1585 /*
1586 * First save the IER then disable the interrupts
1587 */
1588 ier = ioread8(priv->membase + UART_IER);
1589
1590 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1591
1592 uart_console_write(&priv->port, s, count, pch_console_putchar);
1593
1594 /*
1595 * Finally, wait for transmitter to become empty
1596 * and restore the IER
1597 */
1598 wait_for_xmitr(priv, BOTH_EMPTY);
1599 iowrite8(ier, priv->membase + UART_IER);
1600
1601 if (port_locked)
1602 spin_unlock(&priv->port.lock);
1603 if (priv_locked)
1604 spin_unlock(&priv->lock);
1605 local_irq_restore(flags);
1606 }
1607
1608 static int __init pch_console_setup(struct console *co, char *options)
1609 {
1610 struct uart_port *port;
1611 int baud = default_baud;
1612 int bits = 8;
1613 int parity = 'n';
1614 int flow = 'n';
1615
1616 /*
1617 * Check whether an invalid uart number has been specified, and
1618 * if so, search for the first available port that does have
1619 * console support.
1620 */
1621 if (co->index >= PCH_UART_NR)
1622 co->index = 0;
1623 port = &pch_uart_ports[co->index]->port;
1624
1625 if (!port || (!port->iobase && !port->membase))
1626 return -ENODEV;
1627
1628 port->uartclk = pch_uart_get_uartclk();
1629
1630 if (options)
1631 uart_parse_options(options, &baud, &parity, &bits, &flow);
1632
1633 return uart_set_options(port, co, baud, parity, bits, flow);
1634 }
1635
1636 static struct uart_driver pch_uart_driver;
1637
1638 static struct console pch_console = {
1639 .name = PCH_UART_DRIVER_DEVICE,
1640 .write = pch_console_write,
1641 .device = uart_console_device,
1642 .setup = pch_console_setup,
1643 .flags = CON_PRINTBUFFER | CON_ANYTIME,
1644 .index = -1,
1645 .data = &pch_uart_driver,
1646 };
1647
1648 #define PCH_CONSOLE (&pch_console)
1649 #else
1650 #define PCH_CONSOLE NULL
1651 #endif
1652
1653 static struct uart_driver pch_uart_driver = {
1654 .owner = THIS_MODULE,
1655 .driver_name = KBUILD_MODNAME,
1656 .dev_name = PCH_UART_DRIVER_DEVICE,
1657 .major = 0,
1658 .minor = 0,
1659 .nr = PCH_UART_NR,
1660 .cons = PCH_CONSOLE,
1661 };
1662
1663 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1664 const struct pci_device_id *id)
1665 {
1666 struct eg20t_port *priv;
1667 int ret;
1668 unsigned int iobase;
1669 unsigned int mapbase;
1670 unsigned char *rxbuf;
1671 int fifosize;
1672 int port_type;
1673 struct pch_uart_driver_data *board;
1674 char name[32]; /* for debugfs file name */
1675
1676 board = &drv_dat[id->driver_data];
1677 port_type = board->port_type;
1678
1679 priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1680 if (priv == NULL)
1681 goto init_port_alloc_err;
1682
1683 rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1684 if (!rxbuf)
1685 goto init_port_free_txbuf;
1686
1687 switch (port_type) {
1688 case PORT_UNKNOWN:
1689 fifosize = 256; /* EG20T/ML7213: UART0 */
1690 break;
1691 case PORT_8250:
1692 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/
1693 break;
1694 default:
1695 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1696 goto init_port_hal_free;
1697 }
1698
1699 pci_enable_msi(pdev);
1700 pci_set_master(pdev);
1701
1702 spin_lock_init(&priv->lock);
1703
1704 iobase = pci_resource_start(pdev, 0);
1705 mapbase = pci_resource_start(pdev, 1);
1706 priv->mapbase = mapbase;
1707 priv->iobase = iobase;
1708 priv->pdev = pdev;
1709 priv->tx_empty = 1;
1710 priv->rxbuf.buf = rxbuf;
1711 priv->rxbuf.size = PAGE_SIZE;
1712
1713 priv->fifo_size = fifosize;
1714 priv->uartclk = pch_uart_get_uartclk();
1715 priv->port_type = PORT_MAX_8250 + port_type + 1;
1716 priv->port.dev = &pdev->dev;
1717 priv->port.iobase = iobase;
1718 priv->port.membase = NULL;
1719 priv->port.mapbase = mapbase;
1720 priv->port.irq = pdev->irq;
1721 priv->port.iotype = UPIO_PORT;
1722 priv->port.ops = &pch_uart_ops;
1723 priv->port.flags = UPF_BOOT_AUTOCONF;
1724 priv->port.fifosize = fifosize;
1725 priv->port.line = board->line_no;
1726 priv->trigger = PCH_UART_HAL_TRIGGER_M;
1727
1728 spin_lock_init(&priv->port.lock);
1729
1730 pci_set_drvdata(pdev, priv);
1731 priv->trigger_level = 1;
1732 priv->fcr = 0;
1733
1734 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1735 pch_uart_ports[board->line_no] = priv;
1736 #endif
1737 ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1738 if (ret < 0)
1739 goto init_port_hal_free;
1740
1741 #ifdef CONFIG_DEBUG_FS
1742 snprintf(name, sizeof(name), "uart%d_regs", board->line_no);
1743 priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO,
1744 NULL, priv, &port_regs_ops);
1745 #endif
1746
1747 return priv;
1748
1749 init_port_hal_free:
1750 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1751 pch_uart_ports[board->line_no] = NULL;
1752 #endif
1753 free_page((unsigned long)rxbuf);
1754 init_port_free_txbuf:
1755 kfree(priv);
1756 init_port_alloc_err:
1757
1758 return NULL;
1759 }
1760
1761 static void pch_uart_exit_port(struct eg20t_port *priv)
1762 {
1763
1764 #ifdef CONFIG_DEBUG_FS
1765 if (priv->debugfs)
1766 debugfs_remove(priv->debugfs);
1767 #endif
1768 uart_remove_one_port(&pch_uart_driver, &priv->port);
1769 pci_set_drvdata(priv->pdev, NULL);
1770 free_page((unsigned long)priv->rxbuf.buf);
1771 }
1772
1773 static void pch_uart_pci_remove(struct pci_dev *pdev)
1774 {
1775 struct eg20t_port *priv = pci_get_drvdata(pdev);
1776
1777 pci_disable_msi(pdev);
1778
1779 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1780 pch_uart_ports[priv->port.line] = NULL;
1781 #endif
1782 pch_uart_exit_port(priv);
1783 pci_disable_device(pdev);
1784 kfree(priv);
1785 return;
1786 }
1787 #ifdef CONFIG_PM
1788 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1789 {
1790 struct eg20t_port *priv = pci_get_drvdata(pdev);
1791
1792 uart_suspend_port(&pch_uart_driver, &priv->port);
1793
1794 pci_save_state(pdev);
1795 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1796 return 0;
1797 }
1798
1799 static int pch_uart_pci_resume(struct pci_dev *pdev)
1800 {
1801 struct eg20t_port *priv = pci_get_drvdata(pdev);
1802 int ret;
1803
1804 pci_set_power_state(pdev, PCI_D0);
1805 pci_restore_state(pdev);
1806
1807 ret = pci_enable_device(pdev);
1808 if (ret) {
1809 dev_err(&pdev->dev,
1810 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1811 return ret;
1812 }
1813
1814 uart_resume_port(&pch_uart_driver, &priv->port);
1815
1816 return 0;
1817 }
1818 #else
1819 #define pch_uart_pci_suspend NULL
1820 #define pch_uart_pci_resume NULL
1821 #endif
1822
1823 static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = {
1824 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1825 .driver_data = pch_et20t_uart0},
1826 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1827 .driver_data = pch_et20t_uart1},
1828 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1829 .driver_data = pch_et20t_uart2},
1830 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1831 .driver_data = pch_et20t_uart3},
1832 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1833 .driver_data = pch_ml7213_uart0},
1834 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1835 .driver_data = pch_ml7213_uart1},
1836 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1837 .driver_data = pch_ml7213_uart2},
1838 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1839 .driver_data = pch_ml7223_uart0},
1840 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1841 .driver_data = pch_ml7223_uart1},
1842 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1843 .driver_data = pch_ml7831_uart0},
1844 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1845 .driver_data = pch_ml7831_uart1},
1846 {0,},
1847 };
1848
1849 static int __devinit pch_uart_pci_probe(struct pci_dev *pdev,
1850 const struct pci_device_id *id)
1851 {
1852 int ret;
1853 struct eg20t_port *priv;
1854
1855 ret = pci_enable_device(pdev);
1856 if (ret < 0)
1857 goto probe_error;
1858
1859 priv = pch_uart_init_port(pdev, id);
1860 if (!priv) {
1861 ret = -EBUSY;
1862 goto probe_disable_device;
1863 }
1864 pci_set_drvdata(pdev, priv);
1865
1866 return ret;
1867
1868 probe_disable_device:
1869 pci_disable_msi(pdev);
1870 pci_disable_device(pdev);
1871 probe_error:
1872 return ret;
1873 }
1874
1875 static struct pci_driver pch_uart_pci_driver = {
1876 .name = "pch_uart",
1877 .id_table = pch_uart_pci_id,
1878 .probe = pch_uart_pci_probe,
1879 .remove = __devexit_p(pch_uart_pci_remove),
1880 .suspend = pch_uart_pci_suspend,
1881 .resume = pch_uart_pci_resume,
1882 };
1883
1884 static int __init pch_uart_module_init(void)
1885 {
1886 int ret;
1887
1888 /* register as UART driver */
1889 ret = uart_register_driver(&pch_uart_driver);
1890 if (ret < 0)
1891 return ret;
1892
1893 /* register as PCI driver */
1894 ret = pci_register_driver(&pch_uart_pci_driver);
1895 if (ret < 0)
1896 uart_unregister_driver(&pch_uart_driver);
1897
1898 return ret;
1899 }
1900 module_init(pch_uart_module_init);
1901
1902 static void __exit pch_uart_module_exit(void)
1903 {
1904 pci_unregister_driver(&pch_uart_pci_driver);
1905 uart_unregister_driver(&pch_uart_driver);
1906 }
1907 module_exit(pch_uart_module_exit);
1908
1909 MODULE_LICENSE("GPL v2");
1910 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1911 module_param(default_baud, uint, S_IRUGO);
1912 MODULE_PARM_DESC(default_baud,
1913 "Default BAUD for initial driver state and console (default 9600)");
1914 module_param(user_uartclk, uint, S_IRUGO);
1915 MODULE_PARM_DESC(user_uartclk,
1916 "Override UART default or board specific UART clock");
Linux with added FPC-III support