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Linux 3.4.102
[linux/fpc-iii.git] / drivers / tty / synclink_gt.c
blobaa1debf97cc741e3f5914cb5396c8397bd37f362
1 /*
2 * Device driver for Microgate SyncLink GT serial adapters.
3 *
4 * written by Paul Fulghum for Microgate Corporation
5 * paulkf@microgate.com
6 *
7 * Microgate and SyncLink are trademarks of Microgate Corporation
8 *
9 * This code is released under the GNU General Public License (GPL)
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
13 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
14 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
15 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
16 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
17 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
18 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
19 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
20 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
21 * OF THE POSSIBILITY OF SUCH DAMAGE.
22 */
23
24 /*
25 * DEBUG OUTPUT DEFINITIONS
26 *
27 * uncomment lines below to enable specific types of debug output
28 *
29 * DBGINFO information - most verbose output
30 * DBGERR serious errors
31 * DBGBH bottom half service routine debugging
32 * DBGISR interrupt service routine debugging
33 * DBGDATA output receive and transmit data
34 * DBGTBUF output transmit DMA buffers and registers
35 * DBGRBUF output receive DMA buffers and registers
36 */
37
38 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
39 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
40 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
41 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
42 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
43 /*#define DBGTBUF(info) dump_tbufs(info)*/
44 /*#define DBGRBUF(info) dump_rbufs(info)*/
45
46
47 #include <linux/module.h>
48 #include <linux/errno.h>
49 #include <linux/signal.h>
50 #include <linux/sched.h>
51 #include <linux/timer.h>
52 #include <linux/interrupt.h>
53 #include <linux/pci.h>
54 #include <linux/tty.h>
55 #include <linux/tty_flip.h>
56 #include <linux/serial.h>
57 #include <linux/major.h>
58 #include <linux/string.h>
59 #include <linux/fcntl.h>
60 #include <linux/ptrace.h>
61 #include <linux/ioport.h>
62 #include <linux/mm.h>
63 #include <linux/seq_file.h>
64 #include <linux/slab.h>
65 #include <linux/netdevice.h>
66 #include <linux/vmalloc.h>
67 #include <linux/init.h>
68 #include <linux/delay.h>
69 #include <linux/ioctl.h>
70 #include <linux/termios.h>
71 #include <linux/bitops.h>
72 #include <linux/workqueue.h>
73 #include <linux/hdlc.h>
74 #include <linux/synclink.h>
75
76 #include <asm/io.h>
77 #include <asm/irq.h>
78 #include <asm/dma.h>
79 #include <asm/types.h>
80 #include <asm/uaccess.h>
81
82 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
83 #define SYNCLINK_GENERIC_HDLC 1
84 #else
85 #define SYNCLINK_GENERIC_HDLC 0
86 #endif
87
88 /*
89 * module identification
90 */
91 static char *driver_name = "SyncLink GT";
92 static char *tty_driver_name = "synclink_gt";
93 static char *tty_dev_prefix = "ttySLG";
94 MODULE_LICENSE("GPL");
95 #define MGSL_MAGIC 0x5401
96 #define MAX_DEVICES 32
97
98 static struct pci_device_id pci_table[] = {
99 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
100 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
101 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
102 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
103 {0,}, /* terminate list */
104 };
105 MODULE_DEVICE_TABLE(pci, pci_table);
106
107 static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
108 static void remove_one(struct pci_dev *dev);
109 static struct pci_driver pci_driver = {
110 .name = "synclink_gt",
111 .id_table = pci_table,
112 .probe = init_one,
113 .remove = __devexit_p(remove_one),
114 };
115
116 static bool pci_registered;
117
118 /*
119 * module configuration and status
120 */
121 static struct slgt_info *slgt_device_list;
122 static int slgt_device_count;
123
124 static int ttymajor;
125 static int debug_level;
126 static int maxframe[MAX_DEVICES];
127
128 module_param(ttymajor, int, 0);
129 module_param(debug_level, int, 0);
130 module_param_array(maxframe, int, NULL, 0);
131
132 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
133 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
134 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
135
136 /*
137 * tty support and callbacks
138 */
139 static struct tty_driver *serial_driver;
140
141 static int open(struct tty_struct *tty, struct file * filp);
142 static void close(struct tty_struct *tty, struct file * filp);
143 static void hangup(struct tty_struct *tty);
144 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
145
146 static int write(struct tty_struct *tty, const unsigned char *buf, int count);
147 static int put_char(struct tty_struct *tty, unsigned char ch);
148 static void send_xchar(struct tty_struct *tty, char ch);
149 static void wait_until_sent(struct tty_struct *tty, int timeout);
150 static int write_room(struct tty_struct *tty);
151 static void flush_chars(struct tty_struct *tty);
152 static void flush_buffer(struct tty_struct *tty);
153 static void tx_hold(struct tty_struct *tty);
154 static void tx_release(struct tty_struct *tty);
155
156 static int ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
157 static int chars_in_buffer(struct tty_struct *tty);
158 static void throttle(struct tty_struct * tty);
159 static void unthrottle(struct tty_struct * tty);
160 static int set_break(struct tty_struct *tty, int break_state);
161
162 /*
163 * generic HDLC support and callbacks
164 */
165 #if SYNCLINK_GENERIC_HDLC
166 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
167 static void hdlcdev_tx_done(struct slgt_info *info);
168 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
169 static int hdlcdev_init(struct slgt_info *info);
170 static void hdlcdev_exit(struct slgt_info *info);
171 #endif
172
173
174 /*
175 * device specific structures, macros and functions
176 */
177
178 #define SLGT_MAX_PORTS 4
179 #define SLGT_REG_SIZE 256
180
181 /*
182 * conditional wait facility
183 */
184 struct cond_wait {
185 struct cond_wait *next;
186 wait_queue_head_t q;
187 wait_queue_t wait;
188 unsigned int data;
189 };
190 static void init_cond_wait(struct cond_wait *w, unsigned int data);
191 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
192 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
193 static void flush_cond_wait(struct cond_wait **head);
194
195 /*
196 * DMA buffer descriptor and access macros
197 */
198 struct slgt_desc
199 {
200 __le16 count;
201 __le16 status;
202 __le32 pbuf; /* physical address of data buffer */
203 __le32 next; /* physical address of next descriptor */
204
205 /* driver book keeping */
206 char *buf; /* virtual address of data buffer */
207 unsigned int pdesc; /* physical address of this descriptor */
208 dma_addr_t buf_dma_addr;
209 unsigned short buf_count;
210 };
211
212 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
213 #define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
214 #define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
215 #define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
216 #define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
217 #define desc_count(a) (le16_to_cpu((a).count))
218 #define desc_status(a) (le16_to_cpu((a).status))
219 #define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
220 #define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
221 #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
222 #define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
223 #define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
224
225 struct _input_signal_events {
226 int ri_up;
227 int ri_down;
228 int dsr_up;
229 int dsr_down;
230 int dcd_up;
231 int dcd_down;
232 int cts_up;
233 int cts_down;
234 };
235
236 /*
237 * device instance data structure
238 */
239 struct slgt_info {
240 void *if_ptr; /* General purpose pointer (used by SPPP) */
241 struct tty_port port;
242
243 struct slgt_info *next_device; /* device list link */
244
245 int magic;
246
247 char device_name[25];
248 struct pci_dev *pdev;
249
250 int port_count; /* count of ports on adapter */
251 int adapter_num; /* adapter instance number */
252 int port_num; /* port instance number */
253
254 /* array of pointers to port contexts on this adapter */
255 struct slgt_info *port_array[SLGT_MAX_PORTS];
256
257 int line; /* tty line instance number */
258
259 struct mgsl_icount icount;
260
261 int timeout;
262 int x_char; /* xon/xoff character */
263 unsigned int read_status_mask;
264 unsigned int ignore_status_mask;
265
266 wait_queue_head_t status_event_wait_q;
267 wait_queue_head_t event_wait_q;
268 struct timer_list tx_timer;
269 struct timer_list rx_timer;
270
271 unsigned int gpio_present;
272 struct cond_wait *gpio_wait_q;
273
274 spinlock_t lock; /* spinlock for synchronizing with ISR */
275
276 struct work_struct task;
277 u32 pending_bh;
278 bool bh_requested;
279 bool bh_running;
280
281 int isr_overflow;
282 bool irq_requested; /* true if IRQ requested */
283 bool irq_occurred; /* for diagnostics use */
284
285 /* device configuration */
286
287 unsigned int bus_type;
288 unsigned int irq_level;
289 unsigned long irq_flags;
290
291 unsigned char __iomem * reg_addr; /* memory mapped registers address */
292 u32 phys_reg_addr;
293 bool reg_addr_requested;
294
295 MGSL_PARAMS params; /* communications parameters */
296 u32 idle_mode;
297 u32 max_frame_size; /* as set by device config */
298
299 unsigned int rbuf_fill_level;
300 unsigned int rx_pio;
301 unsigned int if_mode;
302 unsigned int base_clock;
303 unsigned int xsync;
304 unsigned int xctrl;
305
306 /* device status */
307
308 bool rx_enabled;
309 bool rx_restart;
310
311 bool tx_enabled;
312 bool tx_active;
313
314 unsigned char signals; /* serial signal states */
315 int init_error; /* initialization error */
316
317 unsigned char *tx_buf;
318 int tx_count;
319
320 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
321 char char_buf[MAX_ASYNC_BUFFER_SIZE];
322 bool drop_rts_on_tx_done;
323 struct _input_signal_events input_signal_events;
324
325 int dcd_chkcount; /* check counts to prevent */
326 int cts_chkcount; /* too many IRQs if a signal */
327 int dsr_chkcount; /* is floating */
328 int ri_chkcount;
329
330 char *bufs; /* virtual address of DMA buffer lists */
331 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
332
333 unsigned int rbuf_count;
334 struct slgt_desc *rbufs;
335 unsigned int rbuf_current;
336 unsigned int rbuf_index;
337 unsigned int rbuf_fill_index;
338 unsigned short rbuf_fill_count;
339
340 unsigned int tbuf_count;
341 struct slgt_desc *tbufs;
342 unsigned int tbuf_current;
343 unsigned int tbuf_start;
344
345 unsigned char *tmp_rbuf;
346 unsigned int tmp_rbuf_count;
347
348 /* SPPP/Cisco HDLC device parts */
349
350 int netcount;
351 spinlock_t netlock;
352 #if SYNCLINK_GENERIC_HDLC
353 struct net_device *netdev;
354 #endif
355
356 };
357
358 static MGSL_PARAMS default_params = {
359 .mode = MGSL_MODE_HDLC,
360 .loopback = 0,
361 .flags = HDLC_FLAG_UNDERRUN_ABORT15,
362 .encoding = HDLC_ENCODING_NRZI_SPACE,
363 .clock_speed = 0,
364 .addr_filter = 0xff,
365 .crc_type = HDLC_CRC_16_CCITT,
366 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
367 .preamble = HDLC_PREAMBLE_PATTERN_NONE,
368 .data_rate = 9600,
369 .data_bits = 8,
370 .stop_bits = 1,
371 .parity = ASYNC_PARITY_NONE
372 };
373
374
375 #define BH_RECEIVE 1
376 #define BH_TRANSMIT 2
377 #define BH_STATUS 4
378 #define IO_PIN_SHUTDOWN_LIMIT 100
379
380 #define DMABUFSIZE 256
381 #define DESC_LIST_SIZE 4096
382
383 #define MASK_PARITY BIT1
384 #define MASK_FRAMING BIT0
385 #define MASK_BREAK BIT14
386 #define MASK_OVERRUN BIT4
387
388 #define GSR 0x00 /* global status */
389 #define JCR 0x04 /* JTAG control */
390 #define IODR 0x08 /* GPIO direction */
391 #define IOER 0x0c /* GPIO interrupt enable */
392 #define IOVR 0x10 /* GPIO value */
393 #define IOSR 0x14 /* GPIO interrupt status */
394 #define TDR 0x80 /* tx data */
395 #define RDR 0x80 /* rx data */
396 #define TCR 0x82 /* tx control */
397 #define TIR 0x84 /* tx idle */
398 #define TPR 0x85 /* tx preamble */
399 #define RCR 0x86 /* rx control */
400 #define VCR 0x88 /* V.24 control */
401 #define CCR 0x89 /* clock control */
402 #define BDR 0x8a /* baud divisor */
403 #define SCR 0x8c /* serial control */
404 #define SSR 0x8e /* serial status */
405 #define RDCSR 0x90 /* rx DMA control/status */
406 #define TDCSR 0x94 /* tx DMA control/status */
407 #define RDDAR 0x98 /* rx DMA descriptor address */
408 #define TDDAR 0x9c /* tx DMA descriptor address */
409 #define XSR 0x40 /* extended sync pattern */
410 #define XCR 0x44 /* extended control */
411
412 #define RXIDLE BIT14
413 #define RXBREAK BIT14
414 #define IRQ_TXDATA BIT13
415 #define IRQ_TXIDLE BIT12
416 #define IRQ_TXUNDER BIT11 /* HDLC */
417 #define IRQ_RXDATA BIT10
418 #define IRQ_RXIDLE BIT9 /* HDLC */
419 #define IRQ_RXBREAK BIT9 /* async */
420 #define IRQ_RXOVER BIT8
421 #define IRQ_DSR BIT7
422 #define IRQ_CTS BIT6
423 #define IRQ_DCD BIT5
424 #define IRQ_RI BIT4
425 #define IRQ_ALL 0x3ff0
426 #define IRQ_MASTER BIT0
427
428 #define slgt_irq_on(info, mask) \
429 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
430 #define slgt_irq_off(info, mask) \
431 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
432
433 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
434 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
435 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
436 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
437 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
438 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
439
440 static void msc_set_vcr(struct slgt_info *info);
441
442 static int startup(struct slgt_info *info);
443 static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
444 static void shutdown(struct slgt_info *info);
445 static void program_hw(struct slgt_info *info);
446 static void change_params(struct slgt_info *info);
447
448 static int register_test(struct slgt_info *info);
449 static int irq_test(struct slgt_info *info);
450 static int loopback_test(struct slgt_info *info);
451 static int adapter_test(struct slgt_info *info);
452
453 static void reset_adapter(struct slgt_info *info);
454 static void reset_port(struct slgt_info *info);
455 static void async_mode(struct slgt_info *info);
456 static void sync_mode(struct slgt_info *info);
457
458 static void rx_stop(struct slgt_info *info);
459 static void rx_start(struct slgt_info *info);
460 static void reset_rbufs(struct slgt_info *info);
461 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
462 static void rdma_reset(struct slgt_info *info);
463 static bool rx_get_frame(struct slgt_info *info);
464 static bool rx_get_buf(struct slgt_info *info);
465
466 static void tx_start(struct slgt_info *info);
467 static void tx_stop(struct slgt_info *info);
468 static void tx_set_idle(struct slgt_info *info);
469 static unsigned int free_tbuf_count(struct slgt_info *info);
470 static unsigned int tbuf_bytes(struct slgt_info *info);
471 static void reset_tbufs(struct slgt_info *info);
472 static void tdma_reset(struct slgt_info *info);
473 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
474
475 static void get_signals(struct slgt_info *info);
476 static void set_signals(struct slgt_info *info);
477 static void enable_loopback(struct slgt_info *info);
478 static void set_rate(struct slgt_info *info, u32 data_rate);
479
480 static int bh_action(struct slgt_info *info);
481 static void bh_handler(struct work_struct *work);
482 static void bh_transmit(struct slgt_info *info);
483 static void isr_serial(struct slgt_info *info);
484 static void isr_rdma(struct slgt_info *info);
485 static void isr_txeom(struct slgt_info *info, unsigned short status);
486 static void isr_tdma(struct slgt_info *info);
487
488 static int alloc_dma_bufs(struct slgt_info *info);
489 static void free_dma_bufs(struct slgt_info *info);
490 static int alloc_desc(struct slgt_info *info);
491 static void free_desc(struct slgt_info *info);
492 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
493 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
494
495 static int alloc_tmp_rbuf(struct slgt_info *info);
496 static void free_tmp_rbuf(struct slgt_info *info);
497
498 static void tx_timeout(unsigned long context);
499 static void rx_timeout(unsigned long context);
500
501 /*
502 * ioctl handlers
503 */
504 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
505 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
506 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
507 static int get_txidle(struct slgt_info *info, int __user *idle_mode);
508 static int set_txidle(struct slgt_info *info, int idle_mode);
509 static int tx_enable(struct slgt_info *info, int enable);
510 static int tx_abort(struct slgt_info *info);
511 static int rx_enable(struct slgt_info *info, int enable);
512 static int modem_input_wait(struct slgt_info *info,int arg);
513 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
514 static int tiocmget(struct tty_struct *tty);
515 static int tiocmset(struct tty_struct *tty,
516 unsigned int set, unsigned int clear);
517 static int set_break(struct tty_struct *tty, int break_state);
518 static int get_interface(struct slgt_info *info, int __user *if_mode);
519 static int set_interface(struct slgt_info *info, int if_mode);
520 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
521 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
522 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
523 static int get_xsync(struct slgt_info *info, int __user *if_mode);
524 static int set_xsync(struct slgt_info *info, int if_mode);
525 static int get_xctrl(struct slgt_info *info, int __user *if_mode);
526 static int set_xctrl(struct slgt_info *info, int if_mode);
527
528 /*
529 * driver functions
530 */
531 static void add_device(struct slgt_info *info);
532 static void device_init(int adapter_num, struct pci_dev *pdev);
533 static int claim_resources(struct slgt_info *info);
534 static void release_resources(struct slgt_info *info);
535
536 /*
537 * DEBUG OUTPUT CODE
538 */
539 #ifndef DBGINFO
540 #define DBGINFO(fmt)
541 #endif
542 #ifndef DBGERR
543 #define DBGERR(fmt)
544 #endif
545 #ifndef DBGBH
546 #define DBGBH(fmt)
547 #endif
548 #ifndef DBGISR
549 #define DBGISR(fmt)
550 #endif
551
552 #ifdef DBGDATA
553 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
554 {
555 int i;
556 int linecount;
557 printk("%s %s data:\n",info->device_name, label);
558 while(count) {
559 linecount = (count > 16) ? 16 : count;
560 for(i=0; i < linecount; i++)
561 printk("%02X ",(unsigned char)data[i]);
562 for(;i<17;i++)
563 printk(" ");
564 for(i=0;i<linecount;i++) {
565 if (data[i]>=040 && data[i]<=0176)
566 printk("%c",data[i]);
567 else
568 printk(".");
569 }
570 printk("\n");
571 data += linecount;
572 count -= linecount;
573 }
574 }
575 #else
576 #define DBGDATA(info, buf, size, label)
577 #endif
578
579 #ifdef DBGTBUF
580 static void dump_tbufs(struct slgt_info *info)
581 {
582 int i;
583 printk("tbuf_current=%d\n", info->tbuf_current);
584 for (i=0 ; i < info->tbuf_count ; i++) {
585 printk("%d: count=%04X status=%04X\n",
586 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
587 }
588 }
589 #else
590 #define DBGTBUF(info)
591 #endif
592
593 #ifdef DBGRBUF
594 static void dump_rbufs(struct slgt_info *info)
595 {
596 int i;
597 printk("rbuf_current=%d\n", info->rbuf_current);
598 for (i=0 ; i < info->rbuf_count ; i++) {
599 printk("%d: count=%04X status=%04X\n",
600 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
601 }
602 }
603 #else
604 #define DBGRBUF(info)
605 #endif
606
607 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
608 {
609 #ifdef SANITY_CHECK
610 if (!info) {
611 printk("null struct slgt_info for (%s) in %s\n", devname, name);
612 return 1;
613 }
614 if (info->magic != MGSL_MAGIC) {
615 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
616 return 1;
617 }
618 #else
619 if (!info)
620 return 1;
621 #endif
622 return 0;
623 }
624
625 /**
626 * line discipline callback wrappers
627 *
628 * The wrappers maintain line discipline references
629 * while calling into the line discipline.
630 *
631 * ldisc_receive_buf - pass receive data to line discipline
632 */
633 static void ldisc_receive_buf(struct tty_struct *tty,
634 const __u8 *data, char *flags, int count)
635 {
636 struct tty_ldisc *ld;
637 if (!tty)
638 return;
639 ld = tty_ldisc_ref(tty);
640 if (ld) {
641 if (ld->ops->receive_buf)
642 ld->ops->receive_buf(tty, data, flags, count);
643 tty_ldisc_deref(ld);
644 }
645 }
646
647 /* tty callbacks */
648
649 static int open(struct tty_struct *tty, struct file *filp)
650 {
651 struct slgt_info *info;
652 int retval, line;
653 unsigned long flags;
654
655 line = tty->index;
656 if (line >= slgt_device_count) {
657 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
658 return -ENODEV;
659 }
660
661 info = slgt_device_list;
662 while(info && info->line != line)
663 info = info->next_device;
664 if (sanity_check(info, tty->name, "open"))
665 return -ENODEV;
666 if (info->init_error) {
667 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
668 return -ENODEV;
669 }
670
671 tty->driver_data = info;
672 info->port.tty = tty;
673
674 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
675
676 /* If port is closing, signal caller to try again */
677 if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
678 if (info->port.flags & ASYNC_CLOSING)
679 interruptible_sleep_on(&info->port.close_wait);
680 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
681 -EAGAIN : -ERESTARTSYS);
682 goto cleanup;
683 }
684
685 mutex_lock(&info->port.mutex);
686 info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
687
688 spin_lock_irqsave(&info->netlock, flags);
689 if (info->netcount) {
690 retval = -EBUSY;
691 spin_unlock_irqrestore(&info->netlock, flags);
692 mutex_unlock(&info->port.mutex);
693 goto cleanup;
694 }
695 info->port.count++;
696 spin_unlock_irqrestore(&info->netlock, flags);
697
698 if (info->port.count == 1) {
699 /* 1st open on this device, init hardware */
700 retval = startup(info);
701 if (retval < 0) {
702 mutex_unlock(&info->port.mutex);
703 goto cleanup;
704 }
705 }
706 mutex_unlock(&info->port.mutex);
707 retval = block_til_ready(tty, filp, info);
708 if (retval) {
709 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
710 goto cleanup;
711 }
712
713 retval = 0;
714
715 cleanup:
716 if (retval) {
717 if (tty->count == 1)
718 info->port.tty = NULL; /* tty layer will release tty struct */
719 if(info->port.count)
720 info->port.count--;
721 }
722
723 DBGINFO(("%s open rc=%d\n", info->device_name, retval));
724 return retval;
725 }
726
727 static void close(struct tty_struct *tty, struct file *filp)
728 {
729 struct slgt_info *info = tty->driver_data;
730
731 if (sanity_check(info, tty->name, "close"))
732 return;
733 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
734
735 if (tty_port_close_start(&info->port, tty, filp) == 0)
736 goto cleanup;
737
738 mutex_lock(&info->port.mutex);
739 if (info->port.flags & ASYNC_INITIALIZED)
740 wait_until_sent(tty, info->timeout);
741 flush_buffer(tty);
742 tty_ldisc_flush(tty);
743
744 shutdown(info);
745 mutex_unlock(&info->port.mutex);
746
747 tty_port_close_end(&info->port, tty);
748 info->port.tty = NULL;
749 cleanup:
750 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
751 }
752
753 static void hangup(struct tty_struct *tty)
754 {
755 struct slgt_info *info = tty->driver_data;
756 unsigned long flags;
757
758 if (sanity_check(info, tty->name, "hangup"))
759 return;
760 DBGINFO(("%s hangup\n", info->device_name));
761
762 flush_buffer(tty);
763
764 mutex_lock(&info->port.mutex);
765 shutdown(info);
766
767 spin_lock_irqsave(&info->port.lock, flags);
768 info->port.count = 0;
769 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
770 info->port.tty = NULL;
771 spin_unlock_irqrestore(&info->port.lock, flags);
772 mutex_unlock(&info->port.mutex);
773
774 wake_up_interruptible(&info->port.open_wait);
775 }
776
777 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
778 {
779 struct slgt_info *info = tty->driver_data;
780 unsigned long flags;
781
782 DBGINFO(("%s set_termios\n", tty->driver->name));
783
784 change_params(info);
785
786 /* Handle transition to B0 status */
787 if (old_termios->c_cflag & CBAUD &&
788 !(tty->termios->c_cflag & CBAUD)) {
789 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
790 spin_lock_irqsave(&info->lock,flags);
791 set_signals(info);
792 spin_unlock_irqrestore(&info->lock,flags);
793 }
794
795 /* Handle transition away from B0 status */
796 if (!(old_termios->c_cflag & CBAUD) &&
797 tty->termios->c_cflag & CBAUD) {
798 info->signals |= SerialSignal_DTR;
799 if (!(tty->termios->c_cflag & CRTSCTS) ||
800 !test_bit(TTY_THROTTLED, &tty->flags)) {
801 info->signals |= SerialSignal_RTS;
802 }
803 spin_lock_irqsave(&info->lock,flags);
804 set_signals(info);
805 spin_unlock_irqrestore(&info->lock,flags);
806 }
807
808 /* Handle turning off CRTSCTS */
809 if (old_termios->c_cflag & CRTSCTS &&
810 !(tty->termios->c_cflag & CRTSCTS)) {
811 tty->hw_stopped = 0;
812 tx_release(tty);
813 }
814 }
815
816 static void update_tx_timer(struct slgt_info *info)
817 {
818 /*
819 * use worst case speed of 1200bps to calculate transmit timeout
820 * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
821 */
822 if (info->params.mode == MGSL_MODE_HDLC) {
823 int timeout = (tbuf_bytes(info) * 7) + 1000;
824 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
825 }
826 }
827
828 static int write(struct tty_struct *tty,
829 const unsigned char *buf, int count)
830 {
831 int ret = 0;
832 struct slgt_info *info = tty->driver_data;
833 unsigned long flags;
834
835 if (sanity_check(info, tty->name, "write"))
836 return -EIO;
837
838 DBGINFO(("%s write count=%d\n", info->device_name, count));
839
840 if (!info->tx_buf || (count > info->max_frame_size))
841 return -EIO;
842
843 if (!count || tty->stopped || tty->hw_stopped)
844 return 0;
845
846 spin_lock_irqsave(&info->lock, flags);
847
848 if (info->tx_count) {
849 /* send accumulated data from send_char() */
850 if (!tx_load(info, info->tx_buf, info->tx_count))
851 goto cleanup;
852 info->tx_count = 0;
853 }
854
855 if (tx_load(info, buf, count))
856 ret = count;
857
858 cleanup:
859 spin_unlock_irqrestore(&info->lock, flags);
860 DBGINFO(("%s write rc=%d\n", info->device_name, ret));
861 return ret;
862 }
863
864 static int put_char(struct tty_struct *tty, unsigned char ch)
865 {
866 struct slgt_info *info = tty->driver_data;
867 unsigned long flags;
868 int ret = 0;
869
870 if (sanity_check(info, tty->name, "put_char"))
871 return 0;
872 DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
873 if (!info->tx_buf)
874 return 0;
875 spin_lock_irqsave(&info->lock,flags);
876 if (info->tx_count < info->max_frame_size) {
877 info->tx_buf[info->tx_count++] = ch;
878 ret = 1;
879 }
880 spin_unlock_irqrestore(&info->lock,flags);
881 return ret;
882 }
883
884 static void send_xchar(struct tty_struct *tty, char ch)
885 {
886 struct slgt_info *info = tty->driver_data;
887 unsigned long flags;
888
889 if (sanity_check(info, tty->name, "send_xchar"))
890 return;
891 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
892 info->x_char = ch;
893 if (ch) {
894 spin_lock_irqsave(&info->lock,flags);
895 if (!info->tx_enabled)
896 tx_start(info);
897 spin_unlock_irqrestore(&info->lock,flags);
898 }
899 }
900
901 static void wait_until_sent(struct tty_struct *tty, int timeout)
902 {
903 struct slgt_info *info = tty->driver_data;
904 unsigned long orig_jiffies, char_time;
905
906 if (!info )
907 return;
908 if (sanity_check(info, tty->name, "wait_until_sent"))
909 return;
910 DBGINFO(("%s wait_until_sent entry\n", info->device_name));
911 if (!(info->port.flags & ASYNC_INITIALIZED))
912 goto exit;
913
914 orig_jiffies = jiffies;
915
916 /* Set check interval to 1/5 of estimated time to
917 * send a character, and make it at least 1. The check
918 * interval should also be less than the timeout.
919 * Note: use tight timings here to satisfy the NIST-PCTS.
920 */
921
922 if (info->params.data_rate) {
923 char_time = info->timeout/(32 * 5);
924 if (!char_time)
925 char_time++;
926 } else
927 char_time = 1;
928
929 if (timeout)
930 char_time = min_t(unsigned long, char_time, timeout);
931
932 while (info->tx_active) {
933 msleep_interruptible(jiffies_to_msecs(char_time));
934 if (signal_pending(current))
935 break;
936 if (timeout && time_after(jiffies, orig_jiffies + timeout))
937 break;
938 }
939 exit:
940 DBGINFO(("%s wait_until_sent exit\n", info->device_name));
941 }
942
943 static int write_room(struct tty_struct *tty)
944 {
945 struct slgt_info *info = tty->driver_data;
946 int ret;
947
948 if (sanity_check(info, tty->name, "write_room"))
949 return 0;
950 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
951 DBGINFO(("%s write_room=%d\n", info->device_name, ret));
952 return ret;
953 }
954
955 static void flush_chars(struct tty_struct *tty)
956 {
957 struct slgt_info *info = tty->driver_data;
958 unsigned long flags;
959
960 if (sanity_check(info, tty->name, "flush_chars"))
961 return;
962 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
963
964 if (info->tx_count <= 0 || tty->stopped ||
965 tty->hw_stopped || !info->tx_buf)
966 return;
967
968 DBGINFO(("%s flush_chars start transmit\n", info->device_name));
969
970 spin_lock_irqsave(&info->lock,flags);
971 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
972 info->tx_count = 0;
973 spin_unlock_irqrestore(&info->lock,flags);
974 }
975
976 static void flush_buffer(struct tty_struct *tty)
977 {
978 struct slgt_info *info = tty->driver_data;
979 unsigned long flags;
980
981 if (sanity_check(info, tty->name, "flush_buffer"))
982 return;
983 DBGINFO(("%s flush_buffer\n", info->device_name));
984
985 spin_lock_irqsave(&info->lock, flags);
986 info->tx_count = 0;
987 spin_unlock_irqrestore(&info->lock, flags);
988
989 tty_wakeup(tty);
990 }
991
992 /*
993 * throttle (stop) transmitter
994 */
995 static void tx_hold(struct tty_struct *tty)
996 {
997 struct slgt_info *info = tty->driver_data;
998 unsigned long flags;
999
1000 if (sanity_check(info, tty->name, "tx_hold"))
1001 return;
1002 DBGINFO(("%s tx_hold\n", info->device_name));
1003 spin_lock_irqsave(&info->lock,flags);
1004 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
1005 tx_stop(info);
1006 spin_unlock_irqrestore(&info->lock,flags);
1007 }
1008
1009 /*
1010 * release (start) transmitter
1011 */
1012 static void tx_release(struct tty_struct *tty)
1013 {
1014 struct slgt_info *info = tty->driver_data;
1015 unsigned long flags;
1016
1017 if (sanity_check(info, tty->name, "tx_release"))
1018 return;
1019 DBGINFO(("%s tx_release\n", info->device_name));
1020 spin_lock_irqsave(&info->lock, flags);
1021 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
1022 info->tx_count = 0;
1023 spin_unlock_irqrestore(&info->lock, flags);
1024 }
1025
1026 /*
1027 * Service an IOCTL request
1028 *
1029 * Arguments
1030 *
1031 * tty pointer to tty instance data
1032 * cmd IOCTL command code
1033 * arg command argument/context
1034 *
1035 * Return 0 if success, otherwise error code
1036 */
1037 static int ioctl(struct tty_struct *tty,
1038 unsigned int cmd, unsigned long arg)
1039 {
1040 struct slgt_info *info = tty->driver_data;
1041 void __user *argp = (void __user *)arg;
1042 int ret;
1043
1044 if (sanity_check(info, tty->name, "ioctl"))
1045 return -ENODEV;
1046 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1047
1048 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1049 (cmd != TIOCMIWAIT)) {
1050 if (tty->flags & (1 << TTY_IO_ERROR))
1051 return -EIO;
1052 }
1053
1054 switch (cmd) {
1055 case MGSL_IOCWAITEVENT:
1056 return wait_mgsl_event(info, argp);
1057 case TIOCMIWAIT:
1058 return modem_input_wait(info,(int)arg);
1059 case MGSL_IOCSGPIO:
1060 return set_gpio(info, argp);
1061 case MGSL_IOCGGPIO:
1062 return get_gpio(info, argp);
1063 case MGSL_IOCWAITGPIO:
1064 return wait_gpio(info, argp);
1065 case MGSL_IOCGXSYNC:
1066 return get_xsync(info, argp);
1067 case MGSL_IOCSXSYNC:
1068 return set_xsync(info, (int)arg);
1069 case MGSL_IOCGXCTRL:
1070 return get_xctrl(info, argp);
1071 case MGSL_IOCSXCTRL:
1072 return set_xctrl(info, (int)arg);
1073 }
1074 mutex_lock(&info->port.mutex);
1075 switch (cmd) {
1076 case MGSL_IOCGPARAMS:
1077 ret = get_params(info, argp);
1078 break;
1079 case MGSL_IOCSPARAMS:
1080 ret = set_params(info, argp);
1081 break;
1082 case MGSL_IOCGTXIDLE:
1083 ret = get_txidle(info, argp);
1084 break;
1085 case MGSL_IOCSTXIDLE:
1086 ret = set_txidle(info, (int)arg);
1087 break;
1088 case MGSL_IOCTXENABLE:
1089 ret = tx_enable(info, (int)arg);
1090 break;
1091 case MGSL_IOCRXENABLE:
1092 ret = rx_enable(info, (int)arg);
1093 break;
1094 case MGSL_IOCTXABORT:
1095 ret = tx_abort(info);
1096 break;
1097 case MGSL_IOCGSTATS:
1098 ret = get_stats(info, argp);
1099 break;
1100 case MGSL_IOCGIF:
1101 ret = get_interface(info, argp);
1102 break;
1103 case MGSL_IOCSIF:
1104 ret = set_interface(info,(int)arg);
1105 break;
1106 default:
1107 ret = -ENOIOCTLCMD;
1108 }
1109 mutex_unlock(&info->port.mutex);
1110 return ret;
1111 }
1112
1113 static int get_icount(struct tty_struct *tty,
1114 struct serial_icounter_struct *icount)
1115
1116 {
1117 struct slgt_info *info = tty->driver_data;
1118 struct mgsl_icount cnow; /* kernel counter temps */
1119 unsigned long flags;
1120
1121 spin_lock_irqsave(&info->lock,flags);
1122 cnow = info->icount;
1123 spin_unlock_irqrestore(&info->lock,flags);
1124
1125 icount->cts = cnow.cts;
1126 icount->dsr = cnow.dsr;
1127 icount->rng = cnow.rng;
1128 icount->dcd = cnow.dcd;
1129 icount->rx = cnow.rx;
1130 icount->tx = cnow.tx;
1131 icount->frame = cnow.frame;
1132 icount->overrun = cnow.overrun;
1133 icount->parity = cnow.parity;
1134 icount->brk = cnow.brk;
1135 icount->buf_overrun = cnow.buf_overrun;
1136
1137 return 0;
1138 }
1139
1140 /*
1141 * support for 32 bit ioctl calls on 64 bit systems
1142 */
1143 #ifdef CONFIG_COMPAT
1144 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1145 {
1146 struct MGSL_PARAMS32 tmp_params;
1147
1148 DBGINFO(("%s get_params32\n", info->device_name));
1149 memset(&tmp_params, 0, sizeof(tmp_params));
1150 tmp_params.mode = (compat_ulong_t)info->params.mode;
1151 tmp_params.loopback = info->params.loopback;
1152 tmp_params.flags = info->params.flags;
1153 tmp_params.encoding = info->params.encoding;
1154 tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed;
1155 tmp_params.addr_filter = info->params.addr_filter;
1156 tmp_params.crc_type = info->params.crc_type;
1157 tmp_params.preamble_length = info->params.preamble_length;
1158 tmp_params.preamble = info->params.preamble;
1159 tmp_params.data_rate = (compat_ulong_t)info->params.data_rate;
1160 tmp_params.data_bits = info->params.data_bits;
1161 tmp_params.stop_bits = info->params.stop_bits;
1162 tmp_params.parity = info->params.parity;
1163 if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1164 return -EFAULT;
1165 return 0;
1166 }
1167
1168 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1169 {
1170 struct MGSL_PARAMS32 tmp_params;
1171
1172 DBGINFO(("%s set_params32\n", info->device_name));
1173 if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1174 return -EFAULT;
1175
1176 spin_lock(&info->lock);
1177 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1178 info->base_clock = tmp_params.clock_speed;
1179 } else {
1180 info->params.mode = tmp_params.mode;
1181 info->params.loopback = tmp_params.loopback;
1182 info->params.flags = tmp_params.flags;
1183 info->params.encoding = tmp_params.encoding;
1184 info->params.clock_speed = tmp_params.clock_speed;
1185 info->params.addr_filter = tmp_params.addr_filter;
1186 info->params.crc_type = tmp_params.crc_type;
1187 info->params.preamble_length = tmp_params.preamble_length;
1188 info->params.preamble = tmp_params.preamble;
1189 info->params.data_rate = tmp_params.data_rate;
1190 info->params.data_bits = tmp_params.data_bits;
1191 info->params.stop_bits = tmp_params.stop_bits;
1192 info->params.parity = tmp_params.parity;
1193 }
1194 spin_unlock(&info->lock);
1195
1196 program_hw(info);
1197
1198 return 0;
1199 }
1200
1201 static long slgt_compat_ioctl(struct tty_struct *tty,
1202 unsigned int cmd, unsigned long arg)
1203 {
1204 struct slgt_info *info = tty->driver_data;
1205 int rc = -ENOIOCTLCMD;
1206
1207 if (sanity_check(info, tty->name, "compat_ioctl"))
1208 return -ENODEV;
1209 DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1210
1211 switch (cmd) {
1212
1213 case MGSL_IOCSPARAMS32:
1214 rc = set_params32(info, compat_ptr(arg));
1215 break;
1216
1217 case MGSL_IOCGPARAMS32:
1218 rc = get_params32(info, compat_ptr(arg));
1219 break;
1220
1221 case MGSL_IOCGPARAMS:
1222 case MGSL_IOCSPARAMS:
1223 case MGSL_IOCGTXIDLE:
1224 case MGSL_IOCGSTATS:
1225 case MGSL_IOCWAITEVENT:
1226 case MGSL_IOCGIF:
1227 case MGSL_IOCSGPIO:
1228 case MGSL_IOCGGPIO:
1229 case MGSL_IOCWAITGPIO:
1230 case MGSL_IOCGXSYNC:
1231 case MGSL_IOCGXCTRL:
1232 case MGSL_IOCSTXIDLE:
1233 case MGSL_IOCTXENABLE:
1234 case MGSL_IOCRXENABLE:
1235 case MGSL_IOCTXABORT:
1236 case TIOCMIWAIT:
1237 case MGSL_IOCSIF:
1238 case MGSL_IOCSXSYNC:
1239 case MGSL_IOCSXCTRL:
1240 rc = ioctl(tty, cmd, arg);
1241 break;
1242 }
1243
1244 DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1245 return rc;
1246 }
1247 #else
1248 #define slgt_compat_ioctl NULL
1249 #endif /* ifdef CONFIG_COMPAT */
1250
1251 /*
1252 * proc fs support
1253 */
1254 static inline void line_info(struct seq_file *m, struct slgt_info *info)
1255 {
1256 char stat_buf[30];
1257 unsigned long flags;
1258
1259 seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1260 info->device_name, info->phys_reg_addr,
1261 info->irq_level, info->max_frame_size);
1262
1263 /* output current serial signal states */
1264 spin_lock_irqsave(&info->lock,flags);
1265 get_signals(info);
1266 spin_unlock_irqrestore(&info->lock,flags);
1267
1268 stat_buf[0] = 0;
1269 stat_buf[1] = 0;
1270 if (info->signals & SerialSignal_RTS)
1271 strcat(stat_buf, "|RTS");
1272 if (info->signals & SerialSignal_CTS)
1273 strcat(stat_buf, "|CTS");
1274 if (info->signals & SerialSignal_DTR)
1275 strcat(stat_buf, "|DTR");
1276 if (info->signals & SerialSignal_DSR)
1277 strcat(stat_buf, "|DSR");
1278 if (info->signals & SerialSignal_DCD)
1279 strcat(stat_buf, "|CD");
1280 if (info->signals & SerialSignal_RI)
1281 strcat(stat_buf, "|RI");
1282
1283 if (info->params.mode != MGSL_MODE_ASYNC) {
1284 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1285 info->icount.txok, info->icount.rxok);
1286 if (info->icount.txunder)
1287 seq_printf(m, " txunder:%d", info->icount.txunder);
1288 if (info->icount.txabort)
1289 seq_printf(m, " txabort:%d", info->icount.txabort);
1290 if (info->icount.rxshort)
1291 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1292 if (info->icount.rxlong)
1293 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1294 if (info->icount.rxover)
1295 seq_printf(m, " rxover:%d", info->icount.rxover);
1296 if (info->icount.rxcrc)
1297 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1298 } else {
1299 seq_printf(m, "\tASYNC tx:%d rx:%d",
1300 info->icount.tx, info->icount.rx);
1301 if (info->icount.frame)
1302 seq_printf(m, " fe:%d", info->icount.frame);
1303 if (info->icount.parity)
1304 seq_printf(m, " pe:%d", info->icount.parity);
1305 if (info->icount.brk)
1306 seq_printf(m, " brk:%d", info->icount.brk);
1307 if (info->icount.overrun)
1308 seq_printf(m, " oe:%d", info->icount.overrun);
1309 }
1310
1311 /* Append serial signal status to end */
1312 seq_printf(m, " %s\n", stat_buf+1);
1313
1314 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1315 info->tx_active,info->bh_requested,info->bh_running,
1316 info->pending_bh);
1317 }
1318
1319 /* Called to print information about devices
1320 */
1321 static int synclink_gt_proc_show(struct seq_file *m, void *v)
1322 {
1323 struct slgt_info *info;
1324
1325 seq_puts(m, "synclink_gt driver\n");
1326
1327 info = slgt_device_list;
1328 while( info ) {
1329 line_info(m, info);
1330 info = info->next_device;
1331 }
1332 return 0;
1333 }
1334
1335 static int synclink_gt_proc_open(struct inode *inode, struct file *file)
1336 {
1337 return single_open(file, synclink_gt_proc_show, NULL);
1338 }
1339
1340 static const struct file_operations synclink_gt_proc_fops = {
1341 .owner = THIS_MODULE,
1342 .open = synclink_gt_proc_open,
1343 .read = seq_read,
1344 .llseek = seq_lseek,
1345 .release = single_release,
1346 };
1347
1348 /*
1349 * return count of bytes in transmit buffer
1350 */
1351 static int chars_in_buffer(struct tty_struct *tty)
1352 {
1353 struct slgt_info *info = tty->driver_data;
1354 int count;
1355 if (sanity_check(info, tty->name, "chars_in_buffer"))
1356 return 0;
1357 count = tbuf_bytes(info);
1358 DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1359 return count;
1360 }
1361
1362 /*
1363 * signal remote device to throttle send data (our receive data)
1364 */
1365 static void throttle(struct tty_struct * tty)
1366 {
1367 struct slgt_info *info = tty->driver_data;
1368 unsigned long flags;
1369
1370 if (sanity_check(info, tty->name, "throttle"))
1371 return;
1372 DBGINFO(("%s throttle\n", info->device_name));
1373 if (I_IXOFF(tty))
1374 send_xchar(tty, STOP_CHAR(tty));
1375 if (tty->termios->c_cflag & CRTSCTS) {
1376 spin_lock_irqsave(&info->lock,flags);
1377 info->signals &= ~SerialSignal_RTS;
1378 set_signals(info);
1379 spin_unlock_irqrestore(&info->lock,flags);
1380 }
1381 }
1382
1383 /*
1384 * signal remote device to stop throttling send data (our receive data)
1385 */
1386 static void unthrottle(struct tty_struct * tty)
1387 {
1388 struct slgt_info *info = tty->driver_data;
1389 unsigned long flags;
1390
1391 if (sanity_check(info, tty->name, "unthrottle"))
1392 return;
1393 DBGINFO(("%s unthrottle\n", info->device_name));
1394 if (I_IXOFF(tty)) {
1395 if (info->x_char)
1396 info->x_char = 0;
1397 else
1398 send_xchar(tty, START_CHAR(tty));
1399 }
1400 if (tty->termios->c_cflag & CRTSCTS) {
1401 spin_lock_irqsave(&info->lock,flags);
1402 info->signals |= SerialSignal_RTS;
1403 set_signals(info);
1404 spin_unlock_irqrestore(&info->lock,flags);
1405 }
1406 }
1407
1408 /*
1409 * set or clear transmit break condition
1410 * break_state -1=set break condition, 0=clear
1411 */
1412 static int set_break(struct tty_struct *tty, int break_state)
1413 {
1414 struct slgt_info *info = tty->driver_data;
1415 unsigned short value;
1416 unsigned long flags;
1417
1418 if (sanity_check(info, tty->name, "set_break"))
1419 return -EINVAL;
1420 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1421
1422 spin_lock_irqsave(&info->lock,flags);
1423 value = rd_reg16(info, TCR);
1424 if (break_state == -1)
1425 value |= BIT6;
1426 else
1427 value &= ~BIT6;
1428 wr_reg16(info, TCR, value);
1429 spin_unlock_irqrestore(&info->lock,flags);
1430 return 0;
1431 }
1432
1433 #if SYNCLINK_GENERIC_HDLC
1434
1435 /**
1436 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1437 * set encoding and frame check sequence (FCS) options
1438 *
1439 * dev pointer to network device structure
1440 * encoding serial encoding setting
1441 * parity FCS setting
1442 *
1443 * returns 0 if success, otherwise error code
1444 */
1445 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1446 unsigned short parity)
1447 {
1448 struct slgt_info *info = dev_to_port(dev);
1449 unsigned char new_encoding;
1450 unsigned short new_crctype;
1451
1452 /* return error if TTY interface open */
1453 if (info->port.count)
1454 return -EBUSY;
1455
1456 DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1457
1458 switch (encoding)
1459 {
1460 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1461 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1462 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1463 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1464 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1465 default: return -EINVAL;
1466 }
1467
1468 switch (parity)
1469 {
1470 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1471 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1472 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1473 default: return -EINVAL;
1474 }
1475
1476 info->params.encoding = new_encoding;
1477 info->params.crc_type = new_crctype;
1478
1479 /* if network interface up, reprogram hardware */
1480 if (info->netcount)
1481 program_hw(info);
1482
1483 return 0;
1484 }
1485
1486 /**
1487 * called by generic HDLC layer to send frame
1488 *
1489 * skb socket buffer containing HDLC frame
1490 * dev pointer to network device structure
1491 */
1492 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1493 struct net_device *dev)
1494 {
1495 struct slgt_info *info = dev_to_port(dev);
1496 unsigned long flags;
1497
1498 DBGINFO(("%s hdlc_xmit\n", dev->name));
1499
1500 if (!skb->len)
1501 return NETDEV_TX_OK;
1502
1503 /* stop sending until this frame completes */
1504 netif_stop_queue(dev);
1505
1506 /* update network statistics */
1507 dev->stats.tx_packets++;
1508 dev->stats.tx_bytes += skb->len;
1509
1510 /* save start time for transmit timeout detection */
1511 dev->trans_start = jiffies;
1512
1513 spin_lock_irqsave(&info->lock, flags);
1514 tx_load(info, skb->data, skb->len);
1515 spin_unlock_irqrestore(&info->lock, flags);
1516
1517 /* done with socket buffer, so free it */
1518 dev_kfree_skb(skb);
1519
1520 return NETDEV_TX_OK;
1521 }
1522
1523 /**
1524 * called by network layer when interface enabled
1525 * claim resources and initialize hardware
1526 *
1527 * dev pointer to network device structure
1528 *
1529 * returns 0 if success, otherwise error code
1530 */
1531 static int hdlcdev_open(struct net_device *dev)
1532 {
1533 struct slgt_info *info = dev_to_port(dev);
1534 int rc;
1535 unsigned long flags;
1536
1537 if (!try_module_get(THIS_MODULE))
1538 return -EBUSY;
1539
1540 DBGINFO(("%s hdlcdev_open\n", dev->name));
1541
1542 /* generic HDLC layer open processing */
1543 if ((rc = hdlc_open(dev)))
1544 return rc;
1545
1546 /* arbitrate between network and tty opens */
1547 spin_lock_irqsave(&info->netlock, flags);
1548 if (info->port.count != 0 || info->netcount != 0) {
1549 DBGINFO(("%s hdlc_open busy\n", dev->name));
1550 spin_unlock_irqrestore(&info->netlock, flags);
1551 return -EBUSY;
1552 }
1553 info->netcount=1;
1554 spin_unlock_irqrestore(&info->netlock, flags);
1555
1556 /* claim resources and init adapter */
1557 if ((rc = startup(info)) != 0) {
1558 spin_lock_irqsave(&info->netlock, flags);
1559 info->netcount=0;
1560 spin_unlock_irqrestore(&info->netlock, flags);
1561 return rc;
1562 }
1563
1564 /* assert DTR and RTS, apply hardware settings */
1565 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1566 program_hw(info);
1567
1568 /* enable network layer transmit */
1569 dev->trans_start = jiffies;
1570 netif_start_queue(dev);
1571
1572 /* inform generic HDLC layer of current DCD status */
1573 spin_lock_irqsave(&info->lock, flags);
1574 get_signals(info);
1575 spin_unlock_irqrestore(&info->lock, flags);
1576 if (info->signals & SerialSignal_DCD)
1577 netif_carrier_on(dev);
1578 else
1579 netif_carrier_off(dev);
1580 return 0;
1581 }
1582
1583 /**
1584 * called by network layer when interface is disabled
1585 * shutdown hardware and release resources
1586 *
1587 * dev pointer to network device structure
1588 *
1589 * returns 0 if success, otherwise error code
1590 */
1591 static int hdlcdev_close(struct net_device *dev)
1592 {
1593 struct slgt_info *info = dev_to_port(dev);
1594 unsigned long flags;
1595
1596 DBGINFO(("%s hdlcdev_close\n", dev->name));
1597
1598 netif_stop_queue(dev);
1599
1600 /* shutdown adapter and release resources */
1601 shutdown(info);
1602
1603 hdlc_close(dev);
1604
1605 spin_lock_irqsave(&info->netlock, flags);
1606 info->netcount=0;
1607 spin_unlock_irqrestore(&info->netlock, flags);
1608
1609 module_put(THIS_MODULE);
1610 return 0;
1611 }
1612
1613 /**
1614 * called by network layer to process IOCTL call to network device
1615 *
1616 * dev pointer to network device structure
1617 * ifr pointer to network interface request structure
1618 * cmd IOCTL command code
1619 *
1620 * returns 0 if success, otherwise error code
1621 */
1622 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1623 {
1624 const size_t size = sizeof(sync_serial_settings);
1625 sync_serial_settings new_line;
1626 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1627 struct slgt_info *info = dev_to_port(dev);
1628 unsigned int flags;
1629
1630 DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1631
1632 /* return error if TTY interface open */
1633 if (info->port.count)
1634 return -EBUSY;
1635
1636 if (cmd != SIOCWANDEV)
1637 return hdlc_ioctl(dev, ifr, cmd);
1638
1639 memset(&new_line, 0, sizeof(new_line));
1640
1641 switch(ifr->ifr_settings.type) {
1642 case IF_GET_IFACE: /* return current sync_serial_settings */
1643
1644 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1645 if (ifr->ifr_settings.size < size) {
1646 ifr->ifr_settings.size = size; /* data size wanted */
1647 return -ENOBUFS;
1648 }
1649
1650 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1651 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1652 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1653 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1654
1655 switch (flags){
1656 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1657 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1658 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1659 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1660 default: new_line.clock_type = CLOCK_DEFAULT;
1661 }
1662
1663 new_line.clock_rate = info->params.clock_speed;
1664 new_line.loopback = info->params.loopback ? 1:0;
1665
1666 if (copy_to_user(line, &new_line, size))
1667 return -EFAULT;
1668 return 0;
1669
1670 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1671
1672 if(!capable(CAP_NET_ADMIN))
1673 return -EPERM;
1674 if (copy_from_user(&new_line, line, size))
1675 return -EFAULT;
1676
1677 switch (new_line.clock_type)
1678 {
1679 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1680 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1681 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1682 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1683 case CLOCK_DEFAULT: flags = info->params.flags &
1684 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1685 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1686 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1687 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1688 default: return -EINVAL;
1689 }
1690
1691 if (new_line.loopback != 0 && new_line.loopback != 1)
1692 return -EINVAL;
1693
1694 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1695 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1696 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1697 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1698 info->params.flags |= flags;
1699
1700 info->params.loopback = new_line.loopback;
1701
1702 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1703 info->params.clock_speed = new_line.clock_rate;
1704 else
1705 info->params.clock_speed = 0;
1706
1707 /* if network interface up, reprogram hardware */
1708 if (info->netcount)
1709 program_hw(info);
1710 return 0;
1711
1712 default:
1713 return hdlc_ioctl(dev, ifr, cmd);
1714 }
1715 }
1716
1717 /**
1718 * called by network layer when transmit timeout is detected
1719 *
1720 * dev pointer to network device structure
1721 */
1722 static void hdlcdev_tx_timeout(struct net_device *dev)
1723 {
1724 struct slgt_info *info = dev_to_port(dev);
1725 unsigned long flags;
1726
1727 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1728
1729 dev->stats.tx_errors++;
1730 dev->stats.tx_aborted_errors++;
1731
1732 spin_lock_irqsave(&info->lock,flags);
1733 tx_stop(info);
1734 spin_unlock_irqrestore(&info->lock,flags);
1735
1736 netif_wake_queue(dev);
1737 }
1738
1739 /**
1740 * called by device driver when transmit completes
1741 * reenable network layer transmit if stopped
1742 *
1743 * info pointer to device instance information
1744 */
1745 static void hdlcdev_tx_done(struct slgt_info *info)
1746 {
1747 if (netif_queue_stopped(info->netdev))
1748 netif_wake_queue(info->netdev);
1749 }
1750
1751 /**
1752 * called by device driver when frame received
1753 * pass frame to network layer
1754 *
1755 * info pointer to device instance information
1756 * buf pointer to buffer contianing frame data
1757 * size count of data bytes in buf
1758 */
1759 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1760 {
1761 struct sk_buff *skb = dev_alloc_skb(size);
1762 struct net_device *dev = info->netdev;
1763
1764 DBGINFO(("%s hdlcdev_rx\n", dev->name));
1765
1766 if (skb == NULL) {
1767 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1768 dev->stats.rx_dropped++;
1769 return;
1770 }
1771
1772 memcpy(skb_put(skb, size), buf, size);
1773
1774 skb->protocol = hdlc_type_trans(skb, dev);
1775
1776 dev->stats.rx_packets++;
1777 dev->stats.rx_bytes += size;
1778
1779 netif_rx(skb);
1780 }
1781
1782 static const struct net_device_ops hdlcdev_ops = {
1783 .ndo_open = hdlcdev_open,
1784 .ndo_stop = hdlcdev_close,
1785 .ndo_change_mtu = hdlc_change_mtu,
1786 .ndo_start_xmit = hdlc_start_xmit,
1787 .ndo_do_ioctl = hdlcdev_ioctl,
1788 .ndo_tx_timeout = hdlcdev_tx_timeout,
1789 };
1790
1791 /**
1792 * called by device driver when adding device instance
1793 * do generic HDLC initialization
1794 *
1795 * info pointer to device instance information
1796 *
1797 * returns 0 if success, otherwise error code
1798 */
1799 static int hdlcdev_init(struct slgt_info *info)
1800 {
1801 int rc;
1802 struct net_device *dev;
1803 hdlc_device *hdlc;
1804
1805 /* allocate and initialize network and HDLC layer objects */
1806
1807 if (!(dev = alloc_hdlcdev(info))) {
1808 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1809 return -ENOMEM;
1810 }
1811
1812 /* for network layer reporting purposes only */
1813 dev->mem_start = info->phys_reg_addr;
1814 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1815 dev->irq = info->irq_level;
1816
1817 /* network layer callbacks and settings */
1818 dev->netdev_ops = &hdlcdev_ops;
1819 dev->watchdog_timeo = 10 * HZ;
1820 dev->tx_queue_len = 50;
1821
1822 /* generic HDLC layer callbacks and settings */
1823 hdlc = dev_to_hdlc(dev);
1824 hdlc->attach = hdlcdev_attach;
1825 hdlc->xmit = hdlcdev_xmit;
1826
1827 /* register objects with HDLC layer */
1828 if ((rc = register_hdlc_device(dev))) {
1829 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1830 free_netdev(dev);
1831 return rc;
1832 }
1833
1834 info->netdev = dev;
1835 return 0;
1836 }
1837
1838 /**
1839 * called by device driver when removing device instance
1840 * do generic HDLC cleanup
1841 *
1842 * info pointer to device instance information
1843 */
1844 static void hdlcdev_exit(struct slgt_info *info)
1845 {
1846 unregister_hdlc_device(info->netdev);
1847 free_netdev(info->netdev);
1848 info->netdev = NULL;
1849 }
1850
1851 #endif /* ifdef CONFIG_HDLC */
1852
1853 /*
1854 * get async data from rx DMA buffers
1855 */
1856 static void rx_async(struct slgt_info *info)
1857 {
1858 struct tty_struct *tty = info->port.tty;
1859 struct mgsl_icount *icount = &info->icount;
1860 unsigned int start, end;
1861 unsigned char *p;
1862 unsigned char status;
1863 struct slgt_desc *bufs = info->rbufs;
1864 int i, count;
1865 int chars = 0;
1866 int stat;
1867 unsigned char ch;
1868
1869 start = end = info->rbuf_current;
1870
1871 while(desc_complete(bufs[end])) {
1872 count = desc_count(bufs[end]) - info->rbuf_index;
1873 p = bufs[end].buf + info->rbuf_index;
1874
1875 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1876 DBGDATA(info, p, count, "rx");
1877
1878 for(i=0 ; i < count; i+=2, p+=2) {
1879 ch = *p;
1880 icount->rx++;
1881
1882 stat = 0;
1883
1884 if ((status = *(p+1) & (BIT1 + BIT0))) {
1885 if (status & BIT1)
1886 icount->parity++;
1887 else if (status & BIT0)
1888 icount->frame++;
1889 /* discard char if tty control flags say so */
1890 if (status & info->ignore_status_mask)
1891 continue;
1892 if (status & BIT1)
1893 stat = TTY_PARITY;
1894 else if (status & BIT0)
1895 stat = TTY_FRAME;
1896 }
1897 if (tty) {
1898 tty_insert_flip_char(tty, ch, stat);
1899 chars++;
1900 }
1901 }
1902
1903 if (i < count) {
1904 /* receive buffer not completed */
1905 info->rbuf_index += i;
1906 mod_timer(&info->rx_timer, jiffies + 1);
1907 break;
1908 }
1909
1910 info->rbuf_index = 0;
1911 free_rbufs(info, end, end);
1912
1913 if (++end == info->rbuf_count)
1914 end = 0;
1915
1916 /* if entire list searched then no frame available */
1917 if (end == start)
1918 break;
1919 }
1920
1921 if (tty && chars)
1922 tty_flip_buffer_push(tty);
1923 }
1924
1925 /*
1926 * return next bottom half action to perform
1927 */
1928 static int bh_action(struct slgt_info *info)
1929 {
1930 unsigned long flags;
1931 int rc;
1932
1933 spin_lock_irqsave(&info->lock,flags);
1934
1935 if (info->pending_bh & BH_RECEIVE) {
1936 info->pending_bh &= ~BH_RECEIVE;
1937 rc = BH_RECEIVE;
1938 } else if (info->pending_bh & BH_TRANSMIT) {
1939 info->pending_bh &= ~BH_TRANSMIT;
1940 rc = BH_TRANSMIT;
1941 } else if (info->pending_bh & BH_STATUS) {
1942 info->pending_bh &= ~BH_STATUS;
1943 rc = BH_STATUS;
1944 } else {
1945 /* Mark BH routine as complete */
1946 info->bh_running = false;
1947 info->bh_requested = false;
1948 rc = 0;
1949 }
1950
1951 spin_unlock_irqrestore(&info->lock,flags);
1952
1953 return rc;
1954 }
1955
1956 /*
1957 * perform bottom half processing
1958 */
1959 static void bh_handler(struct work_struct *work)
1960 {
1961 struct slgt_info *info = container_of(work, struct slgt_info, task);
1962 int action;
1963
1964 if (!info)
1965 return;
1966 info->bh_running = true;
1967
1968 while((action = bh_action(info))) {
1969 switch (action) {
1970 case BH_RECEIVE:
1971 DBGBH(("%s bh receive\n", info->device_name));
1972 switch(info->params.mode) {
1973 case MGSL_MODE_ASYNC:
1974 rx_async(info);
1975 break;
1976 case MGSL_MODE_HDLC:
1977 while(rx_get_frame(info));
1978 break;
1979 case MGSL_MODE_RAW:
1980 case MGSL_MODE_MONOSYNC:
1981 case MGSL_MODE_BISYNC:
1982 case MGSL_MODE_XSYNC:
1983 while(rx_get_buf(info));
1984 break;
1985 }
1986 /* restart receiver if rx DMA buffers exhausted */
1987 if (info->rx_restart)
1988 rx_start(info);
1989 break;
1990 case BH_TRANSMIT:
1991 bh_transmit(info);
1992 break;
1993 case BH_STATUS:
1994 DBGBH(("%s bh status\n", info->device_name));
1995 info->ri_chkcount = 0;
1996 info->dsr_chkcount = 0;
1997 info->dcd_chkcount = 0;
1998 info->cts_chkcount = 0;
1999 break;
2000 default:
2001 DBGBH(("%s unknown action\n", info->device_name));
2002 break;
2003 }
2004 }
2005 DBGBH(("%s bh_handler exit\n", info->device_name));
2006 }
2007
2008 static void bh_transmit(struct slgt_info *info)
2009 {
2010 struct tty_struct *tty = info->port.tty;
2011
2012 DBGBH(("%s bh_transmit\n", info->device_name));
2013 if (tty)
2014 tty_wakeup(tty);
2015 }
2016
2017 static void dsr_change(struct slgt_info *info, unsigned short status)
2018 {
2019 if (status & BIT3) {
2020 info->signals |= SerialSignal_DSR;
2021 info->input_signal_events.dsr_up++;
2022 } else {
2023 info->signals &= ~SerialSignal_DSR;
2024 info->input_signal_events.dsr_down++;
2025 }
2026 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2027 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2028 slgt_irq_off(info, IRQ_DSR);
2029 return;
2030 }
2031 info->icount.dsr++;
2032 wake_up_interruptible(&info->status_event_wait_q);
2033 wake_up_interruptible(&info->event_wait_q);
2034 info->pending_bh |= BH_STATUS;
2035 }
2036
2037 static void cts_change(struct slgt_info *info, unsigned short status)
2038 {
2039 if (status & BIT2) {
2040 info->signals |= SerialSignal_CTS;
2041 info->input_signal_events.cts_up++;
2042 } else {
2043 info->signals &= ~SerialSignal_CTS;
2044 info->input_signal_events.cts_down++;
2045 }
2046 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2047 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2048 slgt_irq_off(info, IRQ_CTS);
2049 return;
2050 }
2051 info->icount.cts++;
2052 wake_up_interruptible(&info->status_event_wait_q);
2053 wake_up_interruptible(&info->event_wait_q);
2054 info->pending_bh |= BH_STATUS;
2055
2056 if (info->port.flags & ASYNC_CTS_FLOW) {
2057 if (info->port.tty) {
2058 if (info->port.tty->hw_stopped) {
2059 if (info->signals & SerialSignal_CTS) {
2060 info->port.tty->hw_stopped = 0;
2061 info->pending_bh |= BH_TRANSMIT;
2062 return;
2063 }
2064 } else {
2065 if (!(info->signals & SerialSignal_CTS))
2066 info->port.tty->hw_stopped = 1;
2067 }
2068 }
2069 }
2070 }
2071
2072 static void dcd_change(struct slgt_info *info, unsigned short status)
2073 {
2074 if (status & BIT1) {
2075 info->signals |= SerialSignal_DCD;
2076 info->input_signal_events.dcd_up++;
2077 } else {
2078 info->signals &= ~SerialSignal_DCD;
2079 info->input_signal_events.dcd_down++;
2080 }
2081 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2082 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2083 slgt_irq_off(info, IRQ_DCD);
2084 return;
2085 }
2086 info->icount.dcd++;
2087 #if SYNCLINK_GENERIC_HDLC
2088 if (info->netcount) {
2089 if (info->signals & SerialSignal_DCD)
2090 netif_carrier_on(info->netdev);
2091 else
2092 netif_carrier_off(info->netdev);
2093 }
2094 #endif
2095 wake_up_interruptible(&info->status_event_wait_q);
2096 wake_up_interruptible(&info->event_wait_q);
2097 info->pending_bh |= BH_STATUS;
2098
2099 if (info->port.flags & ASYNC_CHECK_CD) {
2100 if (info->signals & SerialSignal_DCD)
2101 wake_up_interruptible(&info->port.open_wait);
2102 else {
2103 if (info->port.tty)
2104 tty_hangup(info->port.tty);
2105 }
2106 }
2107 }
2108
2109 static void ri_change(struct slgt_info *info, unsigned short status)
2110 {
2111 if (status & BIT0) {
2112 info->signals |= SerialSignal_RI;
2113 info->input_signal_events.ri_up++;
2114 } else {
2115 info->signals &= ~SerialSignal_RI;
2116 info->input_signal_events.ri_down++;
2117 }
2118 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2119 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2120 slgt_irq_off(info, IRQ_RI);
2121 return;
2122 }
2123 info->icount.rng++;
2124 wake_up_interruptible(&info->status_event_wait_q);
2125 wake_up_interruptible(&info->event_wait_q);
2126 info->pending_bh |= BH_STATUS;
2127 }
2128
2129 static void isr_rxdata(struct slgt_info *info)
2130 {
2131 unsigned int count = info->rbuf_fill_count;
2132 unsigned int i = info->rbuf_fill_index;
2133 unsigned short reg;
2134
2135 while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2136 reg = rd_reg16(info, RDR);
2137 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2138 if (desc_complete(info->rbufs[i])) {
2139 /* all buffers full */
2140 rx_stop(info);
2141 info->rx_restart = 1;
2142 continue;
2143 }
2144 info->rbufs[i].buf[count++] = (unsigned char)reg;
2145 /* async mode saves status byte to buffer for each data byte */
2146 if (info->params.mode == MGSL_MODE_ASYNC)
2147 info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2148 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2149 /* buffer full or end of frame */
2150 set_desc_count(info->rbufs[i], count);
2151 set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2152 info->rbuf_fill_count = count = 0;
2153 if (++i == info->rbuf_count)
2154 i = 0;
2155 info->pending_bh |= BH_RECEIVE;
2156 }
2157 }
2158
2159 info->rbuf_fill_index = i;
2160 info->rbuf_fill_count = count;
2161 }
2162
2163 static void isr_serial(struct slgt_info *info)
2164 {
2165 unsigned short status = rd_reg16(info, SSR);
2166
2167 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2168
2169 wr_reg16(info, SSR, status); /* clear pending */
2170
2171 info->irq_occurred = true;
2172
2173 if (info->params.mode == MGSL_MODE_ASYNC) {
2174 if (status & IRQ_TXIDLE) {
2175 if (info->tx_active)
2176 isr_txeom(info, status);
2177 }
2178 if (info->rx_pio && (status & IRQ_RXDATA))
2179 isr_rxdata(info);
2180 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2181 info->icount.brk++;
2182 /* process break detection if tty control allows */
2183 if (info->port.tty) {
2184 if (!(status & info->ignore_status_mask)) {
2185 if (info->read_status_mask & MASK_BREAK) {
2186 tty_insert_flip_char(info->port.tty, 0, TTY_BREAK);
2187 if (info->port.flags & ASYNC_SAK)
2188 do_SAK(info->port.tty);
2189 }
2190 }
2191 }
2192 }
2193 } else {
2194 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2195 isr_txeom(info, status);
2196 if (info->rx_pio && (status & IRQ_RXDATA))
2197 isr_rxdata(info);
2198 if (status & IRQ_RXIDLE) {
2199 if (status & RXIDLE)
2200 info->icount.rxidle++;
2201 else
2202 info->icount.exithunt++;
2203 wake_up_interruptible(&info->event_wait_q);
2204 }
2205
2206 if (status & IRQ_RXOVER)
2207 rx_start(info);
2208 }
2209
2210 if (status & IRQ_DSR)
2211 dsr_change(info, status);
2212 if (status & IRQ_CTS)
2213 cts_change(info, status);
2214 if (status & IRQ_DCD)
2215 dcd_change(info, status);
2216 if (status & IRQ_RI)
2217 ri_change(info, status);
2218 }
2219
2220 static void isr_rdma(struct slgt_info *info)
2221 {
2222 unsigned int status = rd_reg32(info, RDCSR);
2223
2224 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2225
2226 /* RDCSR (rx DMA control/status)
2227 *
2228 * 31..07 reserved
2229 * 06 save status byte to DMA buffer
2230 * 05 error
2231 * 04 eol (end of list)
2232 * 03 eob (end of buffer)
2233 * 02 IRQ enable
2234 * 01 reset
2235 * 00 enable
2236 */
2237 wr_reg32(info, RDCSR, status); /* clear pending */
2238
2239 if (status & (BIT5 + BIT4)) {
2240 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2241 info->rx_restart = true;
2242 }
2243 info->pending_bh |= BH_RECEIVE;
2244 }
2245
2246 static void isr_tdma(struct slgt_info *info)
2247 {
2248 unsigned int status = rd_reg32(info, TDCSR);
2249
2250 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2251
2252 /* TDCSR (tx DMA control/status)
2253 *
2254 * 31..06 reserved
2255 * 05 error
2256 * 04 eol (end of list)
2257 * 03 eob (end of buffer)
2258 * 02 IRQ enable
2259 * 01 reset
2260 * 00 enable
2261 */
2262 wr_reg32(info, TDCSR, status); /* clear pending */
2263
2264 if (status & (BIT5 + BIT4 + BIT3)) {
2265 // another transmit buffer has completed
2266 // run bottom half to get more send data from user
2267 info->pending_bh |= BH_TRANSMIT;
2268 }
2269 }
2270
2271 /*
2272 * return true if there are unsent tx DMA buffers, otherwise false
2273 *
2274 * if there are unsent buffers then info->tbuf_start
2275 * is set to index of first unsent buffer
2276 */
2277 static bool unsent_tbufs(struct slgt_info *info)
2278 {
2279 unsigned int i = info->tbuf_current;
2280 bool rc = false;
2281
2282 /*
2283 * search backwards from last loaded buffer (precedes tbuf_current)
2284 * for first unsent buffer (desc_count > 0)
2285 */
2286
2287 do {
2288 if (i)
2289 i--;
2290 else
2291 i = info->tbuf_count - 1;
2292 if (!desc_count(info->tbufs[i]))
2293 break;
2294 info->tbuf_start = i;
2295 rc = true;
2296 } while (i != info->tbuf_current);
2297
2298 return rc;
2299 }
2300
2301 static void isr_txeom(struct slgt_info *info, unsigned short status)
2302 {
2303 DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2304
2305 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2306 tdma_reset(info);
2307 if (status & IRQ_TXUNDER) {
2308 unsigned short val = rd_reg16(info, TCR);
2309 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2310 wr_reg16(info, TCR, val); /* clear reset bit */
2311 }
2312
2313 if (info->tx_active) {
2314 if (info->params.mode != MGSL_MODE_ASYNC) {
2315 if (status & IRQ_TXUNDER)
2316 info->icount.txunder++;
2317 else if (status & IRQ_TXIDLE)
2318 info->icount.txok++;
2319 }
2320
2321 if (unsent_tbufs(info)) {
2322 tx_start(info);
2323 update_tx_timer(info);
2324 return;
2325 }
2326 info->tx_active = false;
2327
2328 del_timer(&info->tx_timer);
2329
2330 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2331 info->signals &= ~SerialSignal_RTS;
2332 info->drop_rts_on_tx_done = false;
2333 set_signals(info);
2334 }
2335
2336 #if SYNCLINK_GENERIC_HDLC
2337 if (info->netcount)
2338 hdlcdev_tx_done(info);
2339 else
2340 #endif
2341 {
2342 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2343 tx_stop(info);
2344 return;
2345 }
2346 info->pending_bh |= BH_TRANSMIT;
2347 }
2348 }
2349 }
2350
2351 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2352 {
2353 struct cond_wait *w, *prev;
2354
2355 /* wake processes waiting for specific transitions */
2356 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2357 if (w->data & changed) {
2358 w->data = state;
2359 wake_up_interruptible(&w->q);
2360 if (prev != NULL)
2361 prev->next = w->next;
2362 else
2363 info->gpio_wait_q = w->next;
2364 } else
2365 prev = w;
2366 }
2367 }
2368
2369 /* interrupt service routine
2370 *
2371 * irq interrupt number
2372 * dev_id device ID supplied during interrupt registration
2373 */
2374 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2375 {
2376 struct slgt_info *info = dev_id;
2377 unsigned int gsr;
2378 unsigned int i;
2379
2380 DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2381
2382 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2383 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2384 info->irq_occurred = true;
2385 for(i=0; i < info->port_count ; i++) {
2386 if (info->port_array[i] == NULL)
2387 continue;
2388 spin_lock(&info->port_array[i]->lock);
2389 if (gsr & (BIT8 << i))
2390 isr_serial(info->port_array[i]);
2391 if (gsr & (BIT16 << (i*2)))
2392 isr_rdma(info->port_array[i]);
2393 if (gsr & (BIT17 << (i*2)))
2394 isr_tdma(info->port_array[i]);
2395 spin_unlock(&info->port_array[i]->lock);
2396 }
2397 }
2398
2399 if (info->gpio_present) {
2400 unsigned int state;
2401 unsigned int changed;
2402 spin_lock(&info->lock);
2403 while ((changed = rd_reg32(info, IOSR)) != 0) {
2404 DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2405 /* read latched state of GPIO signals */
2406 state = rd_reg32(info, IOVR);
2407 /* clear pending GPIO interrupt bits */
2408 wr_reg32(info, IOSR, changed);
2409 for (i=0 ; i < info->port_count ; i++) {
2410 if (info->port_array[i] != NULL)
2411 isr_gpio(info->port_array[i], changed, state);
2412 }
2413 }
2414 spin_unlock(&info->lock);
2415 }
2416
2417 for(i=0; i < info->port_count ; i++) {
2418 struct slgt_info *port = info->port_array[i];
2419 if (port == NULL)
2420 continue;
2421 spin_lock(&port->lock);
2422 if ((port->port.count || port->netcount) &&
2423 port->pending_bh && !port->bh_running &&
2424 !port->bh_requested) {
2425 DBGISR(("%s bh queued\n", port->device_name));
2426 schedule_work(&port->task);
2427 port->bh_requested = true;
2428 }
2429 spin_unlock(&port->lock);
2430 }
2431
2432 DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2433 return IRQ_HANDLED;
2434 }
2435
2436 static int startup(struct slgt_info *info)
2437 {
2438 DBGINFO(("%s startup\n", info->device_name));
2439
2440 if (info->port.flags & ASYNC_INITIALIZED)
2441 return 0;
2442
2443 if (!info->tx_buf) {
2444 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2445 if (!info->tx_buf) {
2446 DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2447 return -ENOMEM;
2448 }
2449 }
2450
2451 info->pending_bh = 0;
2452
2453 memset(&info->icount, 0, sizeof(info->icount));
2454
2455 /* program hardware for current parameters */
2456 change_params(info);
2457
2458 if (info->port.tty)
2459 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2460
2461 info->port.flags |= ASYNC_INITIALIZED;
2462
2463 return 0;
2464 }
2465
2466 /*
2467 * called by close() and hangup() to shutdown hardware
2468 */
2469 static void shutdown(struct slgt_info *info)
2470 {
2471 unsigned long flags;
2472
2473 if (!(info->port.flags & ASYNC_INITIALIZED))
2474 return;
2475
2476 DBGINFO(("%s shutdown\n", info->device_name));
2477
2478 /* clear status wait queue because status changes */
2479 /* can't happen after shutting down the hardware */
2480 wake_up_interruptible(&info->status_event_wait_q);
2481 wake_up_interruptible(&info->event_wait_q);
2482
2483 del_timer_sync(&info->tx_timer);
2484 del_timer_sync(&info->rx_timer);
2485
2486 kfree(info->tx_buf);
2487 info->tx_buf = NULL;
2488
2489 spin_lock_irqsave(&info->lock,flags);
2490
2491 tx_stop(info);
2492 rx_stop(info);
2493
2494 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2495
2496 if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
2497 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2498 set_signals(info);
2499 }
2500
2501 flush_cond_wait(&info->gpio_wait_q);
2502
2503 spin_unlock_irqrestore(&info->lock,flags);
2504
2505 if (info->port.tty)
2506 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2507
2508 info->port.flags &= ~ASYNC_INITIALIZED;
2509 }
2510
2511 static void program_hw(struct slgt_info *info)
2512 {
2513 unsigned long flags;
2514
2515 spin_lock_irqsave(&info->lock,flags);
2516
2517 rx_stop(info);
2518 tx_stop(info);
2519
2520 if (info->params.mode != MGSL_MODE_ASYNC ||
2521 info->netcount)
2522 sync_mode(info);
2523 else
2524 async_mode(info);
2525
2526 set_signals(info);
2527
2528 info->dcd_chkcount = 0;
2529 info->cts_chkcount = 0;
2530 info->ri_chkcount = 0;
2531 info->dsr_chkcount = 0;
2532
2533 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2534 get_signals(info);
2535
2536 if (info->netcount ||
2537 (info->port.tty && info->port.tty->termios->c_cflag & CREAD))
2538 rx_start(info);
2539
2540 spin_unlock_irqrestore(&info->lock,flags);
2541 }
2542
2543 /*
2544 * reconfigure adapter based on new parameters
2545 */
2546 static void change_params(struct slgt_info *info)
2547 {
2548 unsigned cflag;
2549 int bits_per_char;
2550
2551 if (!info->port.tty || !info->port.tty->termios)
2552 return;
2553 DBGINFO(("%s change_params\n", info->device_name));
2554
2555 cflag = info->port.tty->termios->c_cflag;
2556
2557 /* if B0 rate (hangup) specified then negate DTR and RTS */
2558 /* otherwise assert DTR and RTS */
2559 if (cflag & CBAUD)
2560 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2561 else
2562 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2563
2564 /* byte size and parity */
2565
2566 switch (cflag & CSIZE) {
2567 case CS5: info->params.data_bits = 5; break;
2568 case CS6: info->params.data_bits = 6; break;
2569 case CS7: info->params.data_bits = 7; break;
2570 case CS8: info->params.data_bits = 8; break;
2571 default: info->params.data_bits = 7; break;
2572 }
2573
2574 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2575
2576 if (cflag & PARENB)
2577 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2578 else
2579 info->params.parity = ASYNC_PARITY_NONE;
2580
2581 /* calculate number of jiffies to transmit a full
2582 * FIFO (32 bytes) at specified data rate
2583 */
2584 bits_per_char = info->params.data_bits +
2585 info->params.stop_bits + 1;
2586
2587 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2588
2589 if (info->params.data_rate) {
2590 info->timeout = (32*HZ*bits_per_char) /
2591 info->params.data_rate;
2592 }
2593 info->timeout += HZ/50; /* Add .02 seconds of slop */
2594
2595 if (cflag & CRTSCTS)
2596 info->port.flags |= ASYNC_CTS_FLOW;
2597 else
2598 info->port.flags &= ~ASYNC_CTS_FLOW;
2599
2600 if (cflag & CLOCAL)
2601 info->port.flags &= ~ASYNC_CHECK_CD;
2602 else
2603 info->port.flags |= ASYNC_CHECK_CD;
2604
2605 /* process tty input control flags */
2606
2607 info->read_status_mask = IRQ_RXOVER;
2608 if (I_INPCK(info->port.tty))
2609 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2610 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2611 info->read_status_mask |= MASK_BREAK;
2612 if (I_IGNPAR(info->port.tty))
2613 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2614 if (I_IGNBRK(info->port.tty)) {
2615 info->ignore_status_mask |= MASK_BREAK;
2616 /* If ignoring parity and break indicators, ignore
2617 * overruns too. (For real raw support).
2618 */
2619 if (I_IGNPAR(info->port.tty))
2620 info->ignore_status_mask |= MASK_OVERRUN;
2621 }
2622
2623 program_hw(info);
2624 }
2625
2626 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2627 {
2628 DBGINFO(("%s get_stats\n", info->device_name));
2629 if (!user_icount) {
2630 memset(&info->icount, 0, sizeof(info->icount));
2631 } else {
2632 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2633 return -EFAULT;
2634 }
2635 return 0;
2636 }
2637
2638 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2639 {
2640 DBGINFO(("%s get_params\n", info->device_name));
2641 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2642 return -EFAULT;
2643 return 0;
2644 }
2645
2646 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2647 {
2648 unsigned long flags;
2649 MGSL_PARAMS tmp_params;
2650
2651 DBGINFO(("%s set_params\n", info->device_name));
2652 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2653 return -EFAULT;
2654
2655 spin_lock_irqsave(&info->lock, flags);
2656 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2657 info->base_clock = tmp_params.clock_speed;
2658 else
2659 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2660 spin_unlock_irqrestore(&info->lock, flags);
2661
2662 program_hw(info);
2663
2664 return 0;
2665 }
2666
2667 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2668 {
2669 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2670 if (put_user(info->idle_mode, idle_mode))
2671 return -EFAULT;
2672 return 0;
2673 }
2674
2675 static int set_txidle(struct slgt_info *info, int idle_mode)
2676 {
2677 unsigned long flags;
2678 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2679 spin_lock_irqsave(&info->lock,flags);
2680 info->idle_mode = idle_mode;
2681 if (info->params.mode != MGSL_MODE_ASYNC)
2682 tx_set_idle(info);
2683 spin_unlock_irqrestore(&info->lock,flags);
2684 return 0;
2685 }
2686
2687 static int tx_enable(struct slgt_info *info, int enable)
2688 {
2689 unsigned long flags;
2690 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2691 spin_lock_irqsave(&info->lock,flags);
2692 if (enable) {
2693 if (!info->tx_enabled)
2694 tx_start(info);
2695 } else {
2696 if (info->tx_enabled)
2697 tx_stop(info);
2698 }
2699 spin_unlock_irqrestore(&info->lock,flags);
2700 return 0;
2701 }
2702
2703 /*
2704 * abort transmit HDLC frame
2705 */
2706 static int tx_abort(struct slgt_info *info)
2707 {
2708 unsigned long flags;
2709 DBGINFO(("%s tx_abort\n", info->device_name));
2710 spin_lock_irqsave(&info->lock,flags);
2711 tdma_reset(info);
2712 spin_unlock_irqrestore(&info->lock,flags);
2713 return 0;
2714 }
2715
2716 static int rx_enable(struct slgt_info *info, int enable)
2717 {
2718 unsigned long flags;
2719 unsigned int rbuf_fill_level;
2720 DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2721 spin_lock_irqsave(&info->lock,flags);
2722 /*
2723 * enable[31..16] = receive DMA buffer fill level
2724 * 0 = noop (leave fill level unchanged)
2725 * fill level must be multiple of 4 and <= buffer size
2726 */
2727 rbuf_fill_level = ((unsigned int)enable) >> 16;
2728 if (rbuf_fill_level) {
2729 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2730 spin_unlock_irqrestore(&info->lock, flags);
2731 return -EINVAL;
2732 }
2733 info->rbuf_fill_level = rbuf_fill_level;
2734 if (rbuf_fill_level < 128)
2735 info->rx_pio = 1; /* PIO mode */
2736 else
2737 info->rx_pio = 0; /* DMA mode */
2738 rx_stop(info); /* restart receiver to use new fill level */
2739 }
2740
2741 /*
2742 * enable[1..0] = receiver enable command
2743 * 0 = disable
2744 * 1 = enable
2745 * 2 = enable or force hunt mode if already enabled
2746 */
2747 enable &= 3;
2748 if (enable) {
2749 if (!info->rx_enabled)
2750 rx_start(info);
2751 else if (enable == 2) {
2752 /* force hunt mode (write 1 to RCR[3]) */
2753 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2754 }
2755 } else {
2756 if (info->rx_enabled)
2757 rx_stop(info);
2758 }
2759 spin_unlock_irqrestore(&info->lock,flags);
2760 return 0;
2761 }
2762
2763 /*
2764 * wait for specified event to occur
2765 */
2766 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2767 {
2768 unsigned long flags;
2769 int s;
2770 int rc=0;
2771 struct mgsl_icount cprev, cnow;
2772 int events;
2773 int mask;
2774 struct _input_signal_events oldsigs, newsigs;
2775 DECLARE_WAITQUEUE(wait, current);
2776
2777 if (get_user(mask, mask_ptr))
2778 return -EFAULT;
2779
2780 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2781
2782 spin_lock_irqsave(&info->lock,flags);
2783
2784 /* return immediately if state matches requested events */
2785 get_signals(info);
2786 s = info->signals;
2787
2788 events = mask &
2789 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2790 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2791 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2792 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2793 if (events) {
2794 spin_unlock_irqrestore(&info->lock,flags);
2795 goto exit;
2796 }
2797
2798 /* save current irq counts */
2799 cprev = info->icount;
2800 oldsigs = info->input_signal_events;
2801
2802 /* enable hunt and idle irqs if needed */
2803 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2804 unsigned short val = rd_reg16(info, SCR);
2805 if (!(val & IRQ_RXIDLE))
2806 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2807 }
2808
2809 set_current_state(TASK_INTERRUPTIBLE);
2810 add_wait_queue(&info->event_wait_q, &wait);
2811
2812 spin_unlock_irqrestore(&info->lock,flags);
2813
2814 for(;;) {
2815 schedule();
2816 if (signal_pending(current)) {
2817 rc = -ERESTARTSYS;
2818 break;
2819 }
2820
2821 /* get current irq counts */
2822 spin_lock_irqsave(&info->lock,flags);
2823 cnow = info->icount;
2824 newsigs = info->input_signal_events;
2825 set_current_state(TASK_INTERRUPTIBLE);
2826 spin_unlock_irqrestore(&info->lock,flags);
2827
2828 /* if no change, wait aborted for some reason */
2829 if (newsigs.dsr_up == oldsigs.dsr_up &&
2830 newsigs.dsr_down == oldsigs.dsr_down &&
2831 newsigs.dcd_up == oldsigs.dcd_up &&
2832 newsigs.dcd_down == oldsigs.dcd_down &&
2833 newsigs.cts_up == oldsigs.cts_up &&
2834 newsigs.cts_down == oldsigs.cts_down &&
2835 newsigs.ri_up == oldsigs.ri_up &&
2836 newsigs.ri_down == oldsigs.ri_down &&
2837 cnow.exithunt == cprev.exithunt &&
2838 cnow.rxidle == cprev.rxidle) {
2839 rc = -EIO;
2840 break;
2841 }
2842
2843 events = mask &
2844 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2845 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2846 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2847 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2848 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2849 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2850 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2851 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2852 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2853 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2854 if (events)
2855 break;
2856
2857 cprev = cnow;
2858 oldsigs = newsigs;
2859 }
2860
2861 remove_wait_queue(&info->event_wait_q, &wait);
2862 set_current_state(TASK_RUNNING);
2863
2864
2865 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2866 spin_lock_irqsave(&info->lock,flags);
2867 if (!waitqueue_active(&info->event_wait_q)) {
2868 /* disable enable exit hunt mode/idle rcvd IRQs */
2869 wr_reg16(info, SCR,
2870 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2871 }
2872 spin_unlock_irqrestore(&info->lock,flags);
2873 }
2874 exit:
2875 if (rc == 0)
2876 rc = put_user(events, mask_ptr);
2877 return rc;
2878 }
2879
2880 static int get_interface(struct slgt_info *info, int __user *if_mode)
2881 {
2882 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2883 if (put_user(info->if_mode, if_mode))
2884 return -EFAULT;
2885 return 0;
2886 }
2887
2888 static int set_interface(struct slgt_info *info, int if_mode)
2889 {
2890 unsigned long flags;
2891 unsigned short val;
2892
2893 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2894 spin_lock_irqsave(&info->lock,flags);
2895 info->if_mode = if_mode;
2896
2897 msc_set_vcr(info);
2898
2899 /* TCR (tx control) 07 1=RTS driver control */
2900 val = rd_reg16(info, TCR);
2901 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2902 val |= BIT7;
2903 else
2904 val &= ~BIT7;
2905 wr_reg16(info, TCR, val);
2906
2907 spin_unlock_irqrestore(&info->lock,flags);
2908 return 0;
2909 }
2910
2911 static int get_xsync(struct slgt_info *info, int __user *xsync)
2912 {
2913 DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
2914 if (put_user(info->xsync, xsync))
2915 return -EFAULT;
2916 return 0;
2917 }
2918
2919 /*
2920 * set extended sync pattern (1 to 4 bytes) for extended sync mode
2921 *
2922 * sync pattern is contained in least significant bytes of value
2923 * most significant byte of sync pattern is oldest (1st sent/detected)
2924 */
2925 static int set_xsync(struct slgt_info *info, int xsync)
2926 {
2927 unsigned long flags;
2928
2929 DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
2930 spin_lock_irqsave(&info->lock, flags);
2931 info->xsync = xsync;
2932 wr_reg32(info, XSR, xsync);
2933 spin_unlock_irqrestore(&info->lock, flags);
2934 return 0;
2935 }
2936
2937 static int get_xctrl(struct slgt_info *info, int __user *xctrl)
2938 {
2939 DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
2940 if (put_user(info->xctrl, xctrl))
2941 return -EFAULT;
2942 return 0;
2943 }
2944
2945 /*
2946 * set extended control options
2947 *
2948 * xctrl[31:19] reserved, must be zero
2949 * xctrl[18:17] extended sync pattern length in bytes
2950 * 00 = 1 byte in xsr[7:0]
2951 * 01 = 2 bytes in xsr[15:0]
2952 * 10 = 3 bytes in xsr[23:0]
2953 * 11 = 4 bytes in xsr[31:0]
2954 * xctrl[16] 1 = enable terminal count, 0=disabled
2955 * xctrl[15:0] receive terminal count for fixed length packets
2956 * value is count minus one (0 = 1 byte packet)
2957 * when terminal count is reached, receiver
2958 * automatically returns to hunt mode and receive
2959 * FIFO contents are flushed to DMA buffers with
2960 * end of frame (EOF) status
2961 */
2962 static int set_xctrl(struct slgt_info *info, int xctrl)
2963 {
2964 unsigned long flags;
2965
2966 DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
2967 spin_lock_irqsave(&info->lock, flags);
2968 info->xctrl = xctrl;
2969 wr_reg32(info, XCR, xctrl);
2970 spin_unlock_irqrestore(&info->lock, flags);
2971 return 0;
2972 }
2973
2974 /*
2975 * set general purpose IO pin state and direction
2976 *
2977 * user_gpio fields:
2978 * state each bit indicates a pin state
2979 * smask set bit indicates pin state to set
2980 * dir each bit indicates a pin direction (0=input, 1=output)
2981 * dmask set bit indicates pin direction to set
2982 */
2983 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2984 {
2985 unsigned long flags;
2986 struct gpio_desc gpio;
2987 __u32 data;
2988
2989 if (!info->gpio_present)
2990 return -EINVAL;
2991 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2992 return -EFAULT;
2993 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2994 info->device_name, gpio.state, gpio.smask,
2995 gpio.dir, gpio.dmask));
2996
2997 spin_lock_irqsave(&info->port_array[0]->lock, flags);
2998 if (gpio.dmask) {
2999 data = rd_reg32(info, IODR);
3000 data |= gpio.dmask & gpio.dir;
3001 data &= ~(gpio.dmask & ~gpio.dir);
3002 wr_reg32(info, IODR, data);
3003 }
3004 if (gpio.smask) {
3005 data = rd_reg32(info, IOVR);
3006 data |= gpio.smask & gpio.state;
3007 data &= ~(gpio.smask & ~gpio.state);
3008 wr_reg32(info, IOVR, data);
3009 }
3010 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3011
3012 return 0;
3013 }
3014
3015 /*
3016 * get general purpose IO pin state and direction
3017 */
3018 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3019 {
3020 struct gpio_desc gpio;
3021 if (!info->gpio_present)
3022 return -EINVAL;
3023 gpio.state = rd_reg32(info, IOVR);
3024 gpio.smask = 0xffffffff;
3025 gpio.dir = rd_reg32(info, IODR);
3026 gpio.dmask = 0xffffffff;
3027 if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3028 return -EFAULT;
3029 DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
3030 info->device_name, gpio.state, gpio.dir));
3031 return 0;
3032 }
3033
3034 /*
3035 * conditional wait facility
3036 */
3037 static void init_cond_wait(struct cond_wait *w, unsigned int data)
3038 {
3039 init_waitqueue_head(&w->q);
3040 init_waitqueue_entry(&w->wait, current);
3041 w->data = data;
3042 }
3043
3044 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
3045 {
3046 set_current_state(TASK_INTERRUPTIBLE);
3047 add_wait_queue(&w->q, &w->wait);
3048 w->next = *head;
3049 *head = w;
3050 }
3051
3052 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
3053 {
3054 struct cond_wait *w, *prev;
3055 remove_wait_queue(&cw->q, &cw->wait);
3056 set_current_state(TASK_RUNNING);
3057 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
3058 if (w == cw) {
3059 if (prev != NULL)
3060 prev->next = w->next;
3061 else
3062 *head = w->next;
3063 break;
3064 }
3065 }
3066 }
3067
3068 static void flush_cond_wait(struct cond_wait **head)
3069 {
3070 while (*head != NULL) {
3071 wake_up_interruptible(&(*head)->q);
3072 *head = (*head)->next;
3073 }
3074 }
3075
3076 /*
3077 * wait for general purpose I/O pin(s) to enter specified state
3078 *
3079 * user_gpio fields:
3080 * state - bit indicates target pin state
3081 * smask - set bit indicates watched pin
3082 *
3083 * The wait ends when at least one watched pin enters the specified
3084 * state. When 0 (no error) is returned, user_gpio->state is set to the
3085 * state of all GPIO pins when the wait ends.
3086 *
3087 * Note: Each pin may be a dedicated input, dedicated output, or
3088 * configurable input/output. The number and configuration of pins
3089 * varies with the specific adapter model. Only input pins (dedicated
3090 * or configured) can be monitored with this function.
3091 */
3092 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3093 {
3094 unsigned long flags;
3095 int rc = 0;
3096 struct gpio_desc gpio;
3097 struct cond_wait wait;
3098 u32 state;
3099
3100 if (!info->gpio_present)
3101 return -EINVAL;
3102 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
3103 return -EFAULT;
3104 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
3105 info->device_name, gpio.state, gpio.smask));
3106 /* ignore output pins identified by set IODR bit */
3107 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
3108 return -EINVAL;
3109 init_cond_wait(&wait, gpio.smask);
3110
3111 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3112 /* enable interrupts for watched pins */
3113 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
3114 /* get current pin states */
3115 state = rd_reg32(info, IOVR);
3116
3117 if (gpio.smask & ~(state ^ gpio.state)) {
3118 /* already in target state */
3119 gpio.state = state;
3120 } else {
3121 /* wait for target state */
3122 add_cond_wait(&info->gpio_wait_q, &wait);
3123 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3124 schedule();
3125 if (signal_pending(current))
3126 rc = -ERESTARTSYS;
3127 else
3128 gpio.state = wait.data;
3129 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3130 remove_cond_wait(&info->gpio_wait_q, &wait);
3131 }
3132
3133 /* disable all GPIO interrupts if no waiting processes */
3134 if (info->gpio_wait_q == NULL)
3135 wr_reg32(info, IOER, 0);
3136 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3137
3138 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3139 rc = -EFAULT;
3140 return rc;
3141 }
3142
3143 static int modem_input_wait(struct slgt_info *info,int arg)
3144 {
3145 unsigned long flags;
3146 int rc;
3147 struct mgsl_icount cprev, cnow;
3148 DECLARE_WAITQUEUE(wait, current);
3149
3150 /* save current irq counts */
3151 spin_lock_irqsave(&info->lock,flags);
3152 cprev = info->icount;
3153 add_wait_queue(&info->status_event_wait_q, &wait);
3154 set_current_state(TASK_INTERRUPTIBLE);
3155 spin_unlock_irqrestore(&info->lock,flags);
3156
3157 for(;;) {
3158 schedule();
3159 if (signal_pending(current)) {
3160 rc = -ERESTARTSYS;
3161 break;
3162 }
3163
3164 /* get new irq counts */
3165 spin_lock_irqsave(&info->lock,flags);
3166 cnow = info->icount;
3167 set_current_state(TASK_INTERRUPTIBLE);
3168 spin_unlock_irqrestore(&info->lock,flags);
3169
3170 /* if no change, wait aborted for some reason */
3171 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3172 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3173 rc = -EIO;
3174 break;
3175 }
3176
3177 /* check for change in caller specified modem input */
3178 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3179 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3180 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3181 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3182 rc = 0;
3183 break;
3184 }
3185
3186 cprev = cnow;
3187 }
3188 remove_wait_queue(&info->status_event_wait_q, &wait);
3189 set_current_state(TASK_RUNNING);
3190 return rc;
3191 }
3192
3193 /*
3194 * return state of serial control and status signals
3195 */
3196 static int tiocmget(struct tty_struct *tty)
3197 {
3198 struct slgt_info *info = tty->driver_data;
3199 unsigned int result;
3200 unsigned long flags;
3201
3202 spin_lock_irqsave(&info->lock,flags);
3203 get_signals(info);
3204 spin_unlock_irqrestore(&info->lock,flags);
3205
3206 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3207 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3208 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3209 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3210 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3211 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3212
3213 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3214 return result;
3215 }
3216
3217 /*
3218 * set modem control signals (DTR/RTS)
3219 *
3220 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3221 * TIOCMSET = set/clear signal values
3222 * value bit mask for command
3223 */
3224 static int tiocmset(struct tty_struct *tty,
3225 unsigned int set, unsigned int clear)
3226 {
3227 struct slgt_info *info = tty->driver_data;
3228 unsigned long flags;
3229
3230 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3231
3232 if (set & TIOCM_RTS)
3233 info->signals |= SerialSignal_RTS;
3234 if (set & TIOCM_DTR)
3235 info->signals |= SerialSignal_DTR;
3236 if (clear & TIOCM_RTS)
3237 info->signals &= ~SerialSignal_RTS;
3238 if (clear & TIOCM_DTR)
3239 info->signals &= ~SerialSignal_DTR;
3240
3241 spin_lock_irqsave(&info->lock,flags);
3242 set_signals(info);
3243 spin_unlock_irqrestore(&info->lock,flags);
3244 return 0;
3245 }
3246
3247 static int carrier_raised(struct tty_port *port)
3248 {
3249 unsigned long flags;
3250 struct slgt_info *info = container_of(port, struct slgt_info, port);
3251
3252 spin_lock_irqsave(&info->lock,flags);
3253 get_signals(info);
3254 spin_unlock_irqrestore(&info->lock,flags);
3255 return (info->signals & SerialSignal_DCD) ? 1 : 0;
3256 }
3257
3258 static void dtr_rts(struct tty_port *port, int on)
3259 {
3260 unsigned long flags;
3261 struct slgt_info *info = container_of(port, struct slgt_info, port);
3262
3263 spin_lock_irqsave(&info->lock,flags);
3264 if (on)
3265 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
3266 else
3267 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3268 set_signals(info);
3269 spin_unlock_irqrestore(&info->lock,flags);
3270 }
3271
3272
3273 /*
3274 * block current process until the device is ready to open
3275 */
3276 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3277 struct slgt_info *info)
3278 {
3279 DECLARE_WAITQUEUE(wait, current);
3280 int retval;
3281 bool do_clocal = false;
3282 bool extra_count = false;
3283 unsigned long flags;
3284 int cd;
3285 struct tty_port *port = &info->port;
3286
3287 DBGINFO(("%s block_til_ready\n", tty->driver->name));
3288
3289 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3290 /* nonblock mode is set or port is not enabled */
3291 port->flags |= ASYNC_NORMAL_ACTIVE;
3292 return 0;
3293 }
3294
3295 if (tty->termios->c_cflag & CLOCAL)
3296 do_clocal = true;
3297
3298 /* Wait for carrier detect and the line to become
3299 * free (i.e., not in use by the callout). While we are in
3300 * this loop, port->count is dropped by one, so that
3301 * close() knows when to free things. We restore it upon
3302 * exit, either normal or abnormal.
3303 */
3304
3305 retval = 0;
3306 add_wait_queue(&port->open_wait, &wait);
3307
3308 spin_lock_irqsave(&info->lock, flags);
3309 if (!tty_hung_up_p(filp)) {
3310 extra_count = true;
3311 port->count--;
3312 }
3313 spin_unlock_irqrestore(&info->lock, flags);
3314 port->blocked_open++;
3315
3316 while (1) {
3317 if ((tty->termios->c_cflag & CBAUD))
3318 tty_port_raise_dtr_rts(port);
3319
3320 set_current_state(TASK_INTERRUPTIBLE);
3321
3322 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3323 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3324 -EAGAIN : -ERESTARTSYS;
3325 break;
3326 }
3327
3328 cd = tty_port_carrier_raised(port);
3329
3330 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || cd ))
3331 break;
3332
3333 if (signal_pending(current)) {
3334 retval = -ERESTARTSYS;
3335 break;
3336 }
3337
3338 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3339 tty_unlock();
3340 schedule();
3341 tty_lock();
3342 }
3343
3344 set_current_state(TASK_RUNNING);
3345 remove_wait_queue(&port->open_wait, &wait);
3346
3347 if (extra_count)
3348 port->count++;
3349 port->blocked_open--;
3350
3351 if (!retval)
3352 port->flags |= ASYNC_NORMAL_ACTIVE;
3353
3354 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3355 return retval;
3356 }
3357
3358 static int alloc_tmp_rbuf(struct slgt_info *info)
3359 {
3360 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3361 if (info->tmp_rbuf == NULL)
3362 return -ENOMEM;
3363 return 0;
3364 }
3365
3366 static void free_tmp_rbuf(struct slgt_info *info)
3367 {
3368 kfree(info->tmp_rbuf);
3369 info->tmp_rbuf = NULL;
3370 }
3371
3372 /*
3373 * allocate DMA descriptor lists.
3374 */
3375 static int alloc_desc(struct slgt_info *info)
3376 {
3377 unsigned int i;
3378 unsigned int pbufs;
3379
3380 /* allocate memory to hold descriptor lists */
3381 info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3382 if (info->bufs == NULL)
3383 return -ENOMEM;
3384
3385 memset(info->bufs, 0, DESC_LIST_SIZE);
3386
3387 info->rbufs = (struct slgt_desc*)info->bufs;
3388 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3389
3390 pbufs = (unsigned int)info->bufs_dma_addr;
3391
3392 /*
3393 * Build circular lists of descriptors
3394 */
3395
3396 for (i=0; i < info->rbuf_count; i++) {
3397 /* physical address of this descriptor */
3398 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3399
3400 /* physical address of next descriptor */
3401 if (i == info->rbuf_count - 1)
3402 info->rbufs[i].next = cpu_to_le32(pbufs);
3403 else
3404 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3405 set_desc_count(info->rbufs[i], DMABUFSIZE);
3406 }
3407
3408 for (i=0; i < info->tbuf_count; i++) {
3409 /* physical address of this descriptor */
3410 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3411
3412 /* physical address of next descriptor */
3413 if (i == info->tbuf_count - 1)
3414 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3415 else
3416 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3417 }
3418
3419 return 0;
3420 }
3421
3422 static void free_desc(struct slgt_info *info)
3423 {
3424 if (info->bufs != NULL) {
3425 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3426 info->bufs = NULL;
3427 info->rbufs = NULL;
3428 info->tbufs = NULL;
3429 }
3430 }
3431
3432 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3433 {
3434 int i;
3435 for (i=0; i < count; i++) {
3436 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3437 return -ENOMEM;
3438 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3439 }
3440 return 0;
3441 }
3442
3443 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3444 {
3445 int i;
3446 for (i=0; i < count; i++) {
3447 if (bufs[i].buf == NULL)
3448 continue;
3449 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3450 bufs[i].buf = NULL;
3451 }
3452 }
3453
3454 static int alloc_dma_bufs(struct slgt_info *info)
3455 {
3456 info->rbuf_count = 32;
3457 info->tbuf_count = 32;
3458
3459 if (alloc_desc(info) < 0 ||
3460 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3461 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3462 alloc_tmp_rbuf(info) < 0) {
3463 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3464 return -ENOMEM;
3465 }
3466 reset_rbufs(info);
3467 return 0;
3468 }
3469
3470 static void free_dma_bufs(struct slgt_info *info)
3471 {
3472 if (info->bufs) {
3473 free_bufs(info, info->rbufs, info->rbuf_count);
3474 free_bufs(info, info->tbufs, info->tbuf_count);
3475 free_desc(info);
3476 }
3477 free_tmp_rbuf(info);
3478 }
3479
3480 static int claim_resources(struct slgt_info *info)
3481 {
3482 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3483 DBGERR(("%s reg addr conflict, addr=%08X\n",
3484 info->device_name, info->phys_reg_addr));
3485 info->init_error = DiagStatus_AddressConflict;
3486 goto errout;
3487 }
3488 else
3489 info->reg_addr_requested = true;
3490
3491 info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3492 if (!info->reg_addr) {
3493 DBGERR(("%s can't map device registers, addr=%08X\n",
3494 info->device_name, info->phys_reg_addr));
3495 info->init_error = DiagStatus_CantAssignPciResources;
3496 goto errout;
3497 }
3498 return 0;
3499
3500 errout:
3501 release_resources(info);
3502 return -ENODEV;
3503 }
3504
3505 static void release_resources(struct slgt_info *info)
3506 {
3507 if (info->irq_requested) {
3508 free_irq(info->irq_level, info);
3509 info->irq_requested = false;
3510 }
3511
3512 if (info->reg_addr_requested) {
3513 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3514 info->reg_addr_requested = false;
3515 }
3516
3517 if (info->reg_addr) {
3518 iounmap(info->reg_addr);
3519 info->reg_addr = NULL;
3520 }
3521 }
3522
3523 /* Add the specified device instance data structure to the
3524 * global linked list of devices and increment the device count.
3525 */
3526 static void add_device(struct slgt_info *info)
3527 {
3528 char *devstr;
3529
3530 info->next_device = NULL;
3531 info->line = slgt_device_count;
3532 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3533
3534 if (info->line < MAX_DEVICES) {
3535 if (maxframe[info->line])
3536 info->max_frame_size = maxframe[info->line];
3537 }
3538
3539 slgt_device_count++;
3540
3541 if (!slgt_device_list)
3542 slgt_device_list = info;
3543 else {
3544 struct slgt_info *current_dev = slgt_device_list;
3545 while(current_dev->next_device)
3546 current_dev = current_dev->next_device;
3547 current_dev->next_device = info;
3548 }
3549
3550 if (info->max_frame_size < 4096)
3551 info->max_frame_size = 4096;
3552 else if (info->max_frame_size > 65535)
3553 info->max_frame_size = 65535;
3554
3555 switch(info->pdev->device) {
3556 case SYNCLINK_GT_DEVICE_ID:
3557 devstr = "GT";
3558 break;
3559 case SYNCLINK_GT2_DEVICE_ID:
3560 devstr = "GT2";
3561 break;
3562 case SYNCLINK_GT4_DEVICE_ID:
3563 devstr = "GT4";
3564 break;
3565 case SYNCLINK_AC_DEVICE_ID:
3566 devstr = "AC";
3567 info->params.mode = MGSL_MODE_ASYNC;
3568 break;
3569 default:
3570 devstr = "(unknown model)";
3571 }
3572 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3573 devstr, info->device_name, info->phys_reg_addr,
3574 info->irq_level, info->max_frame_size);
3575
3576 #if SYNCLINK_GENERIC_HDLC
3577 hdlcdev_init(info);
3578 #endif
3579 }
3580
3581 static const struct tty_port_operations slgt_port_ops = {
3582 .carrier_raised = carrier_raised,
3583 .dtr_rts = dtr_rts,
3584 };
3585
3586 /*
3587 * allocate device instance structure, return NULL on failure
3588 */
3589 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3590 {
3591 struct slgt_info *info;
3592
3593 info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3594
3595 if (!info) {
3596 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3597 driver_name, adapter_num, port_num));
3598 } else {
3599 tty_port_init(&info->port);
3600 info->port.ops = &slgt_port_ops;
3601 info->magic = MGSL_MAGIC;
3602 INIT_WORK(&info->task, bh_handler);
3603 info->max_frame_size = 4096;
3604 info->base_clock = 14745600;
3605 info->rbuf_fill_level = DMABUFSIZE;
3606 info->port.close_delay = 5*HZ/10;
3607 info->port.closing_wait = 30*HZ;
3608 init_waitqueue_head(&info->status_event_wait_q);
3609 init_waitqueue_head(&info->event_wait_q);
3610 spin_lock_init(&info->netlock);
3611 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3612 info->idle_mode = HDLC_TXIDLE_FLAGS;
3613 info->adapter_num = adapter_num;
3614 info->port_num = port_num;
3615
3616 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3617 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3618
3619 /* Copy configuration info to device instance data */
3620 info->pdev = pdev;
3621 info->irq_level = pdev->irq;
3622 info->phys_reg_addr = pci_resource_start(pdev,0);
3623
3624 info->bus_type = MGSL_BUS_TYPE_PCI;
3625 info->irq_flags = IRQF_SHARED;
3626
3627 info->init_error = -1; /* assume error, set to 0 on successful init */
3628 }
3629
3630 return info;
3631 }
3632
3633 static void device_init(int adapter_num, struct pci_dev *pdev)
3634 {
3635 struct slgt_info *port_array[SLGT_MAX_PORTS];
3636 int i;
3637 int port_count = 1;
3638
3639 if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3640 port_count = 2;
3641 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3642 port_count = 4;
3643
3644 /* allocate device instances for all ports */
3645 for (i=0; i < port_count; ++i) {
3646 port_array[i] = alloc_dev(adapter_num, i, pdev);
3647 if (port_array[i] == NULL) {
3648 for (--i; i >= 0; --i)
3649 kfree(port_array[i]);
3650 return;
3651 }
3652 }
3653
3654 /* give copy of port_array to all ports and add to device list */
3655 for (i=0; i < port_count; ++i) {
3656 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3657 add_device(port_array[i]);
3658 port_array[i]->port_count = port_count;
3659 spin_lock_init(&port_array[i]->lock);
3660 }
3661
3662 /* Allocate and claim adapter resources */
3663 if (!claim_resources(port_array[0])) {
3664
3665 alloc_dma_bufs(port_array[0]);
3666
3667 /* copy resource information from first port to others */
3668 for (i = 1; i < port_count; ++i) {
3669 port_array[i]->irq_level = port_array[0]->irq_level;
3670 port_array[i]->reg_addr = port_array[0]->reg_addr;
3671 alloc_dma_bufs(port_array[i]);
3672 }
3673
3674 if (request_irq(port_array[0]->irq_level,
3675 slgt_interrupt,
3676 port_array[0]->irq_flags,
3677 port_array[0]->device_name,
3678 port_array[0]) < 0) {
3679 DBGERR(("%s request_irq failed IRQ=%d\n",
3680 port_array[0]->device_name,
3681 port_array[0]->irq_level));
3682 } else {
3683 port_array[0]->irq_requested = true;
3684 adapter_test(port_array[0]);
3685 for (i=1 ; i < port_count ; i++) {
3686 port_array[i]->init_error = port_array[0]->init_error;
3687 port_array[i]->gpio_present = port_array[0]->gpio_present;
3688 }
3689 }
3690 }
3691
3692 for (i=0; i < port_count; ++i)
3693 tty_register_device(serial_driver, port_array[i]->line, &(port_array[i]->pdev->dev));
3694 }
3695
3696 static int __devinit init_one(struct pci_dev *dev,
3697 const struct pci_device_id *ent)
3698 {
3699 if (pci_enable_device(dev)) {
3700 printk("error enabling pci device %p\n", dev);
3701 return -EIO;
3702 }
3703 pci_set_master(dev);
3704 device_init(slgt_device_count, dev);
3705 return 0;
3706 }
3707
3708 static void __devexit remove_one(struct pci_dev *dev)
3709 {
3710 }
3711
3712 static const struct tty_operations ops = {
3713 .open = open,
3714 .close = close,
3715 .write = write,
3716 .put_char = put_char,
3717 .flush_chars = flush_chars,
3718 .write_room = write_room,
3719 .chars_in_buffer = chars_in_buffer,
3720 .flush_buffer = flush_buffer,
3721 .ioctl = ioctl,
3722 .compat_ioctl = slgt_compat_ioctl,
3723 .throttle = throttle,
3724 .unthrottle = unthrottle,
3725 .send_xchar = send_xchar,
3726 .break_ctl = set_break,
3727 .wait_until_sent = wait_until_sent,
3728 .set_termios = set_termios,
3729 .stop = tx_hold,
3730 .start = tx_release,
3731 .hangup = hangup,
3732 .tiocmget = tiocmget,
3733 .tiocmset = tiocmset,
3734 .get_icount = get_icount,
3735 .proc_fops = &synclink_gt_proc_fops,
3736 };
3737
3738 static void slgt_cleanup(void)
3739 {
3740 int rc;
3741 struct slgt_info *info;
3742 struct slgt_info *tmp;
3743
3744 printk(KERN_INFO "unload %s\n", driver_name);
3745
3746 if (serial_driver) {
3747 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3748 tty_unregister_device(serial_driver, info->line);
3749 if ((rc = tty_unregister_driver(serial_driver)))
3750 DBGERR(("tty_unregister_driver error=%d\n", rc));
3751 put_tty_driver(serial_driver);
3752 }
3753
3754 /* reset devices */
3755 info = slgt_device_list;
3756 while(info) {
3757 reset_port(info);
3758 info = info->next_device;
3759 }
3760
3761 /* release devices */
3762 info = slgt_device_list;
3763 while(info) {
3764 #if SYNCLINK_GENERIC_HDLC
3765 hdlcdev_exit(info);
3766 #endif
3767 free_dma_bufs(info);
3768 free_tmp_rbuf(info);
3769 if (info->port_num == 0)
3770 release_resources(info);
3771 tmp = info;
3772 info = info->next_device;
3773 kfree(tmp);
3774 }
3775
3776 if (pci_registered)
3777 pci_unregister_driver(&pci_driver);
3778 }
3779
3780 /*
3781 * Driver initialization entry point.
3782 */
3783 static int __init slgt_init(void)
3784 {
3785 int rc;
3786
3787 printk(KERN_INFO "%s\n", driver_name);
3788
3789 serial_driver = alloc_tty_driver(MAX_DEVICES);
3790 if (!serial_driver) {
3791 printk("%s can't allocate tty driver\n", driver_name);
3792 return -ENOMEM;
3793 }
3794
3795 /* Initialize the tty_driver structure */
3796
3797 serial_driver->driver_name = tty_driver_name;
3798 serial_driver->name = tty_dev_prefix;
3799 serial_driver->major = ttymajor;
3800 serial_driver->minor_start = 64;
3801 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3802 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3803 serial_driver->init_termios = tty_std_termios;
3804 serial_driver->init_termios.c_cflag =
3805 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3806 serial_driver->init_termios.c_ispeed = 9600;
3807 serial_driver->init_termios.c_ospeed = 9600;
3808 serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3809 tty_set_operations(serial_driver, &ops);
3810 if ((rc = tty_register_driver(serial_driver)) < 0) {
3811 DBGERR(("%s can't register serial driver\n", driver_name));
3812 put_tty_driver(serial_driver);
3813 serial_driver = NULL;
3814 goto error;
3815 }
3816
3817 printk(KERN_INFO "%s, tty major#%d\n",
3818 driver_name, serial_driver->major);
3819
3820 slgt_device_count = 0;
3821 if ((rc = pci_register_driver(&pci_driver)) < 0) {
3822 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3823 goto error;
3824 }
3825 pci_registered = true;
3826
3827 if (!slgt_device_list)
3828 printk("%s no devices found\n",driver_name);
3829
3830 return 0;
3831
3832 error:
3833 slgt_cleanup();
3834 return rc;
3835 }
3836
3837 static void __exit slgt_exit(void)
3838 {
3839 slgt_cleanup();
3840 }
3841
3842 module_init(slgt_init);
3843 module_exit(slgt_exit);
3844
3845 /*
3846 * register access routines
3847 */
3848
3849 #define CALC_REGADDR() \
3850 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3851 if (addr >= 0x80) \
3852 reg_addr += (info->port_num) * 32; \
3853 else if (addr >= 0x40) \
3854 reg_addr += (info->port_num) * 16;
3855
3856 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3857 {
3858 CALC_REGADDR();
3859 return readb((void __iomem *)reg_addr);
3860 }
3861
3862 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3863 {
3864 CALC_REGADDR();
3865 writeb(value, (void __iomem *)reg_addr);
3866 }
3867
3868 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3869 {
3870 CALC_REGADDR();
3871 return readw((void __iomem *)reg_addr);
3872 }
3873
3874 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3875 {
3876 CALC_REGADDR();
3877 writew(value, (void __iomem *)reg_addr);
3878 }
3879
3880 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3881 {
3882 CALC_REGADDR();
3883 return readl((void __iomem *)reg_addr);
3884 }
3885
3886 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3887 {
3888 CALC_REGADDR();
3889 writel(value, (void __iomem *)reg_addr);
3890 }
3891
3892 static void rdma_reset(struct slgt_info *info)
3893 {
3894 unsigned int i;
3895
3896 /* set reset bit */
3897 wr_reg32(info, RDCSR, BIT1);
3898
3899 /* wait for enable bit cleared */
3900 for(i=0 ; i < 1000 ; i++)
3901 if (!(rd_reg32(info, RDCSR) & BIT0))
3902 break;
3903 }
3904
3905 static void tdma_reset(struct slgt_info *info)
3906 {
3907 unsigned int i;
3908
3909 /* set reset bit */
3910 wr_reg32(info, TDCSR, BIT1);
3911
3912 /* wait for enable bit cleared */
3913 for(i=0 ; i < 1000 ; i++)
3914 if (!(rd_reg32(info, TDCSR) & BIT0))
3915 break;
3916 }
3917
3918 /*
3919 * enable internal loopback
3920 * TxCLK and RxCLK are generated from BRG
3921 * and TxD is looped back to RxD internally.
3922 */
3923 static void enable_loopback(struct slgt_info *info)
3924 {
3925 /* SCR (serial control) BIT2=loopback enable */
3926 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3927
3928 if (info->params.mode != MGSL_MODE_ASYNC) {
3929 /* CCR (clock control)
3930 * 07..05 tx clock source (010 = BRG)
3931 * 04..02 rx clock source (010 = BRG)
3932 * 01 auxclk enable (0 = disable)
3933 * 00 BRG enable (1 = enable)
3934 *
3935 * 0100 1001
3936 */
3937 wr_reg8(info, CCR, 0x49);
3938
3939 /* set speed if available, otherwise use default */
3940 if (info->params.clock_speed)
3941 set_rate(info, info->params.clock_speed);
3942 else
3943 set_rate(info, 3686400);
3944 }
3945 }
3946
3947 /*
3948 * set baud rate generator to specified rate
3949 */
3950 static void set_rate(struct slgt_info *info, u32 rate)
3951 {
3952 unsigned int div;
3953 unsigned int osc = info->base_clock;
3954
3955 /* div = osc/rate - 1
3956 *
3957 * Round div up if osc/rate is not integer to
3958 * force to next slowest rate.
3959 */
3960
3961 if (rate) {
3962 div = osc/rate;
3963 if (!(osc % rate) && div)
3964 div--;
3965 wr_reg16(info, BDR, (unsigned short)div);
3966 }
3967 }
3968
3969 static void rx_stop(struct slgt_info *info)
3970 {
3971 unsigned short val;
3972
3973 /* disable and reset receiver */
3974 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3975 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3976 wr_reg16(info, RCR, val); /* clear reset bit */
3977
3978 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3979
3980 /* clear pending rx interrupts */
3981 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3982
3983 rdma_reset(info);
3984
3985 info->rx_enabled = false;
3986 info->rx_restart = false;
3987 }
3988
3989 static void rx_start(struct slgt_info *info)
3990 {
3991 unsigned short val;
3992
3993 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3994
3995 /* clear pending rx overrun IRQ */
3996 wr_reg16(info, SSR, IRQ_RXOVER);
3997
3998 /* reset and disable receiver */
3999 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
4000 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
4001 wr_reg16(info, RCR, val); /* clear reset bit */
4002
4003 rdma_reset(info);
4004 reset_rbufs(info);
4005
4006 if (info->rx_pio) {
4007 /* rx request when rx FIFO not empty */
4008 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
4009 slgt_irq_on(info, IRQ_RXDATA);
4010 if (info->params.mode == MGSL_MODE_ASYNC) {
4011 /* enable saving of rx status */
4012 wr_reg32(info, RDCSR, BIT6);
4013 }
4014 } else {
4015 /* rx request when rx FIFO half full */
4016 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
4017 /* set 1st descriptor address */
4018 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
4019
4020 if (info->params.mode != MGSL_MODE_ASYNC) {
4021 /* enable rx DMA and DMA interrupt */
4022 wr_reg32(info, RDCSR, (BIT2 + BIT0));
4023 } else {
4024 /* enable saving of rx status, rx DMA and DMA interrupt */
4025 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
4026 }
4027 }
4028
4029 slgt_irq_on(info, IRQ_RXOVER);
4030
4031 /* enable receiver */
4032 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
4033
4034 info->rx_restart = false;
4035 info->rx_enabled = true;
4036 }
4037
4038 static void tx_start(struct slgt_info *info)
4039 {
4040 if (!info->tx_enabled) {
4041 wr_reg16(info, TCR,
4042 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
4043 info->tx_enabled = true;
4044 }
4045
4046 if (desc_count(info->tbufs[info->tbuf_start])) {
4047 info->drop_rts_on_tx_done = false;
4048
4049 if (info->params.mode != MGSL_MODE_ASYNC) {
4050 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
4051 get_signals(info);
4052 if (!(info->signals & SerialSignal_RTS)) {
4053 info->signals |= SerialSignal_RTS;
4054 set_signals(info);
4055 info->drop_rts_on_tx_done = true;
4056 }
4057 }
4058
4059 slgt_irq_off(info, IRQ_TXDATA);
4060 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
4061 /* clear tx idle and underrun status bits */
4062 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4063 } else {
4064 slgt_irq_off(info, IRQ_TXDATA);
4065 slgt_irq_on(info, IRQ_TXIDLE);
4066 /* clear tx idle status bit */
4067 wr_reg16(info, SSR, IRQ_TXIDLE);
4068 }
4069 /* set 1st descriptor address and start DMA */
4070 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
4071 wr_reg32(info, TDCSR, BIT2 + BIT0);
4072 info->tx_active = true;
4073 }
4074 }
4075
4076 static void tx_stop(struct slgt_info *info)
4077 {
4078 unsigned short val;
4079
4080 del_timer(&info->tx_timer);
4081
4082 tdma_reset(info);
4083
4084 /* reset and disable transmitter */
4085 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
4086 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
4087
4088 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
4089
4090 /* clear tx idle and underrun status bit */
4091 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4092
4093 reset_tbufs(info);
4094
4095 info->tx_enabled = false;
4096 info->tx_active = false;
4097 }
4098
4099 static void reset_port(struct slgt_info *info)
4100 {
4101 if (!info->reg_addr)
4102 return;
4103
4104 tx_stop(info);
4105 rx_stop(info);
4106
4107 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4108 set_signals(info);
4109
4110 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4111 }
4112
4113 static void reset_adapter(struct slgt_info *info)
4114 {
4115 int i;
4116 for (i=0; i < info->port_count; ++i) {
4117 if (info->port_array[i])
4118 reset_port(info->port_array[i]);
4119 }
4120 }
4121
4122 static void async_mode(struct slgt_info *info)
4123 {
4124 unsigned short val;
4125
4126 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4127 tx_stop(info);
4128 rx_stop(info);
4129
4130 /* TCR (tx control)
4131 *
4132 * 15..13 mode, 010=async
4133 * 12..10 encoding, 000=NRZ
4134 * 09 parity enable
4135 * 08 1=odd parity, 0=even parity
4136 * 07 1=RTS driver control
4137 * 06 1=break enable
4138 * 05..04 character length
4139 * 00=5 bits
4140 * 01=6 bits
4141 * 10=7 bits
4142 * 11=8 bits
4143 * 03 0=1 stop bit, 1=2 stop bits
4144 * 02 reset
4145 * 01 enable
4146 * 00 auto-CTS enable
4147 */
4148 val = 0x4000;
4149
4150 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4151 val |= BIT7;
4152
4153 if (info->params.parity != ASYNC_PARITY_NONE) {
4154 val |= BIT9;
4155 if (info->params.parity == ASYNC_PARITY_ODD)
4156 val |= BIT8;
4157 }
4158
4159 switch (info->params.data_bits)
4160 {
4161 case 6: val |= BIT4; break;
4162 case 7: val |= BIT5; break;
4163 case 8: val |= BIT5 + BIT4; break;
4164 }
4165
4166 if (info->params.stop_bits != 1)
4167 val |= BIT3;
4168
4169 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4170 val |= BIT0;
4171
4172 wr_reg16(info, TCR, val);
4173
4174 /* RCR (rx control)
4175 *
4176 * 15..13 mode, 010=async
4177 * 12..10 encoding, 000=NRZ
4178 * 09 parity enable
4179 * 08 1=odd parity, 0=even parity
4180 * 07..06 reserved, must be 0
4181 * 05..04 character length
4182 * 00=5 bits
4183 * 01=6 bits
4184 * 10=7 bits
4185 * 11=8 bits
4186 * 03 reserved, must be zero
4187 * 02 reset
4188 * 01 enable
4189 * 00 auto-DCD enable
4190 */
4191 val = 0x4000;
4192
4193 if (info->params.parity != ASYNC_PARITY_NONE) {
4194 val |= BIT9;
4195 if (info->params.parity == ASYNC_PARITY_ODD)
4196 val |= BIT8;
4197 }
4198
4199 switch (info->params.data_bits)
4200 {
4201 case 6: val |= BIT4; break;
4202 case 7: val |= BIT5; break;
4203 case 8: val |= BIT5 + BIT4; break;
4204 }
4205
4206 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4207 val |= BIT0;
4208
4209 wr_reg16(info, RCR, val);
4210
4211 /* CCR (clock control)
4212 *
4213 * 07..05 011 = tx clock source is BRG/16
4214 * 04..02 010 = rx clock source is BRG
4215 * 01 0 = auxclk disabled
4216 * 00 1 = BRG enabled
4217 *
4218 * 0110 1001
4219 */
4220 wr_reg8(info, CCR, 0x69);
4221
4222 msc_set_vcr(info);
4223
4224 /* SCR (serial control)
4225 *
4226 * 15 1=tx req on FIFO half empty
4227 * 14 1=rx req on FIFO half full
4228 * 13 tx data IRQ enable
4229 * 12 tx idle IRQ enable
4230 * 11 rx break on IRQ enable
4231 * 10 rx data IRQ enable
4232 * 09 rx break off IRQ enable
4233 * 08 overrun IRQ enable
4234 * 07 DSR IRQ enable
4235 * 06 CTS IRQ enable
4236 * 05 DCD IRQ enable
4237 * 04 RI IRQ enable
4238 * 03 0=16x sampling, 1=8x sampling
4239 * 02 1=txd->rxd internal loopback enable
4240 * 01 reserved, must be zero
4241 * 00 1=master IRQ enable
4242 */
4243 val = BIT15 + BIT14 + BIT0;
4244 /* JCR[8] : 1 = x8 async mode feature available */
4245 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4246 ((info->base_clock < (info->params.data_rate * 16)) ||
4247 (info->base_clock % (info->params.data_rate * 16)))) {
4248 /* use 8x sampling */
4249 val |= BIT3;
4250 set_rate(info, info->params.data_rate * 8);
4251 } else {
4252 /* use 16x sampling */
4253 set_rate(info, info->params.data_rate * 16);
4254 }
4255 wr_reg16(info, SCR, val);
4256
4257 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4258
4259 if (info->params.loopback)
4260 enable_loopback(info);
4261 }
4262
4263 static void sync_mode(struct slgt_info *info)
4264 {
4265 unsigned short val;
4266
4267 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4268 tx_stop(info);
4269 rx_stop(info);
4270
4271 /* TCR (tx control)
4272 *
4273 * 15..13 mode
4274 * 000=HDLC/SDLC
4275 * 001=raw bit synchronous
4276 * 010=asynchronous/isochronous
4277 * 011=monosync byte synchronous
4278 * 100=bisync byte synchronous
4279 * 101=xsync byte synchronous
4280 * 12..10 encoding
4281 * 09 CRC enable
4282 * 08 CRC32
4283 * 07 1=RTS driver control
4284 * 06 preamble enable
4285 * 05..04 preamble length
4286 * 03 share open/close flag
4287 * 02 reset
4288 * 01 enable
4289 * 00 auto-CTS enable
4290 */
4291 val = BIT2;
4292
4293 switch(info->params.mode) {
4294 case MGSL_MODE_XSYNC:
4295 val |= BIT15 + BIT13;
4296 break;
4297 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4298 case MGSL_MODE_BISYNC: val |= BIT15; break;
4299 case MGSL_MODE_RAW: val |= BIT13; break;
4300 }
4301 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4302 val |= BIT7;
4303
4304 switch(info->params.encoding)
4305 {
4306 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4307 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4308 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4309 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4310 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4311 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4312 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4313 }
4314
4315 switch (info->params.crc_type & HDLC_CRC_MASK)
4316 {
4317 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4318 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4319 }
4320
4321 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4322 val |= BIT6;
4323
4324 switch (info->params.preamble_length)
4325 {
4326 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4327 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4328 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4329 }
4330
4331 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4332 val |= BIT0;
4333
4334 wr_reg16(info, TCR, val);
4335
4336 /* TPR (transmit preamble) */
4337
4338 switch (info->params.preamble)
4339 {
4340 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4341 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
4342 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4343 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
4344 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
4345 default: val = 0x7e; break;
4346 }
4347 wr_reg8(info, TPR, (unsigned char)val);
4348
4349 /* RCR (rx control)
4350 *
4351 * 15..13 mode
4352 * 000=HDLC/SDLC
4353 * 001=raw bit synchronous
4354 * 010=asynchronous/isochronous
4355 * 011=monosync byte synchronous
4356 * 100=bisync byte synchronous
4357 * 101=xsync byte synchronous
4358 * 12..10 encoding
4359 * 09 CRC enable
4360 * 08 CRC32
4361 * 07..03 reserved, must be 0
4362 * 02 reset
4363 * 01 enable
4364 * 00 auto-DCD enable
4365 */
4366 val = 0;
4367
4368 switch(info->params.mode) {
4369 case MGSL_MODE_XSYNC:
4370 val |= BIT15 + BIT13;
4371 break;
4372 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4373 case MGSL_MODE_BISYNC: val |= BIT15; break;
4374 case MGSL_MODE_RAW: val |= BIT13; break;
4375 }
4376
4377 switch(info->params.encoding)
4378 {
4379 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4380 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4381 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4382 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4383 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4384 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4385 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4386 }
4387
4388 switch (info->params.crc_type & HDLC_CRC_MASK)
4389 {
4390 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4391 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4392 }
4393
4394 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4395 val |= BIT0;
4396
4397 wr_reg16(info, RCR, val);
4398
4399 /* CCR (clock control)
4400 *
4401 * 07..05 tx clock source
4402 * 04..02 rx clock source
4403 * 01 auxclk enable
4404 * 00 BRG enable
4405 */
4406 val = 0;
4407
4408 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4409 {
4410 // when RxC source is DPLL, BRG generates 16X DPLL
4411 // reference clock, so take TxC from BRG/16 to get
4412 // transmit clock at actual data rate
4413 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4414 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
4415 else
4416 val |= BIT6; /* 010, txclk = BRG */
4417 }
4418 else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4419 val |= BIT7; /* 100, txclk = DPLL Input */
4420 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4421 val |= BIT5; /* 001, txclk = RXC Input */
4422
4423 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4424 val |= BIT3; /* 010, rxclk = BRG */
4425 else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4426 val |= BIT4; /* 100, rxclk = DPLL */
4427 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4428 val |= BIT2; /* 001, rxclk = TXC Input */
4429
4430 if (info->params.clock_speed)
4431 val |= BIT1 + BIT0;
4432
4433 wr_reg8(info, CCR, (unsigned char)val);
4434
4435 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4436 {
4437 // program DPLL mode
4438 switch(info->params.encoding)
4439 {
4440 case HDLC_ENCODING_BIPHASE_MARK:
4441 case HDLC_ENCODING_BIPHASE_SPACE:
4442 val = BIT7; break;
4443 case HDLC_ENCODING_BIPHASE_LEVEL:
4444 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4445 val = BIT7 + BIT6; break;
4446 default: val = BIT6; // NRZ encodings
4447 }
4448 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4449
4450 // DPLL requires a 16X reference clock from BRG
4451 set_rate(info, info->params.clock_speed * 16);
4452 }
4453 else
4454 set_rate(info, info->params.clock_speed);
4455
4456 tx_set_idle(info);
4457
4458 msc_set_vcr(info);
4459
4460 /* SCR (serial control)
4461 *
4462 * 15 1=tx req on FIFO half empty
4463 * 14 1=rx req on FIFO half full
4464 * 13 tx data IRQ enable
4465 * 12 tx idle IRQ enable
4466 * 11 underrun IRQ enable
4467 * 10 rx data IRQ enable
4468 * 09 rx idle IRQ enable
4469 * 08 overrun IRQ enable
4470 * 07 DSR IRQ enable
4471 * 06 CTS IRQ enable
4472 * 05 DCD IRQ enable
4473 * 04 RI IRQ enable
4474 * 03 reserved, must be zero
4475 * 02 1=txd->rxd internal loopback enable
4476 * 01 reserved, must be zero
4477 * 00 1=master IRQ enable
4478 */
4479 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4480
4481 if (info->params.loopback)
4482 enable_loopback(info);
4483 }
4484
4485 /*
4486 * set transmit idle mode
4487 */
4488 static void tx_set_idle(struct slgt_info *info)
4489 {
4490 unsigned char val;
4491 unsigned short tcr;
4492
4493 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4494 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4495 */
4496 tcr = rd_reg16(info, TCR);
4497 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4498 /* disable preamble, set idle size to 16 bits */
4499 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4500 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4501 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4502 } else if (!(tcr & BIT6)) {
4503 /* preamble is disabled, set idle size to 8 bits */
4504 tcr &= ~(BIT5 + BIT4);
4505 }
4506 wr_reg16(info, TCR, tcr);
4507
4508 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4509 /* LSB of custom tx idle specified in tx idle register */
4510 val = (unsigned char)(info->idle_mode & 0xff);
4511 } else {
4512 /* standard 8 bit idle patterns */
4513 switch(info->idle_mode)
4514 {
4515 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
4516 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4517 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4518 case HDLC_TXIDLE_ZEROS:
4519 case HDLC_TXIDLE_SPACE: val = 0x00; break;
4520 default: val = 0xff;
4521 }
4522 }
4523
4524 wr_reg8(info, TIR, val);
4525 }
4526
4527 /*
4528 * get state of V24 status (input) signals
4529 */
4530 static void get_signals(struct slgt_info *info)
4531 {
4532 unsigned short status = rd_reg16(info, SSR);
4533
4534 /* clear all serial signals except DTR and RTS */
4535 info->signals &= SerialSignal_DTR + SerialSignal_RTS;
4536
4537 if (status & BIT3)
4538 info->signals |= SerialSignal_DSR;
4539 if (status & BIT2)
4540 info->signals |= SerialSignal_CTS;
4541 if (status & BIT1)
4542 info->signals |= SerialSignal_DCD;
4543 if (status & BIT0)
4544 info->signals |= SerialSignal_RI;
4545 }
4546
4547 /*
4548 * set V.24 Control Register based on current configuration
4549 */
4550 static void msc_set_vcr(struct slgt_info *info)
4551 {
4552 unsigned char val = 0;
4553
4554 /* VCR (V.24 control)
4555 *
4556 * 07..04 serial IF select
4557 * 03 DTR
4558 * 02 RTS
4559 * 01 LL
4560 * 00 RL
4561 */
4562
4563 switch(info->if_mode & MGSL_INTERFACE_MASK)
4564 {
4565 case MGSL_INTERFACE_RS232:
4566 val |= BIT5; /* 0010 */
4567 break;
4568 case MGSL_INTERFACE_V35:
4569 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4570 break;
4571 case MGSL_INTERFACE_RS422:
4572 val |= BIT6; /* 0100 */
4573 break;
4574 }
4575
4576 if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4577 val |= BIT4;
4578 if (info->signals & SerialSignal_DTR)
4579 val |= BIT3;
4580 if (info->signals & SerialSignal_RTS)
4581 val |= BIT2;
4582 if (info->if_mode & MGSL_INTERFACE_LL)
4583 val |= BIT1;
4584 if (info->if_mode & MGSL_INTERFACE_RL)
4585 val |= BIT0;
4586 wr_reg8(info, VCR, val);
4587 }
4588
4589 /*
4590 * set state of V24 control (output) signals
4591 */
4592 static void set_signals(struct slgt_info *info)
4593 {
4594 unsigned char val = rd_reg8(info, VCR);
4595 if (info->signals & SerialSignal_DTR)
4596 val |= BIT3;
4597 else
4598 val &= ~BIT3;
4599 if (info->signals & SerialSignal_RTS)
4600 val |= BIT2;
4601 else
4602 val &= ~BIT2;
4603 wr_reg8(info, VCR, val);
4604 }
4605
4606 /*
4607 * free range of receive DMA buffers (i to last)
4608 */
4609 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4610 {
4611 int done = 0;
4612
4613 while(!done) {
4614 /* reset current buffer for reuse */
4615 info->rbufs[i].status = 0;
4616 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4617 if (i == last)
4618 done = 1;
4619 if (++i == info->rbuf_count)
4620 i = 0;
4621 }
4622 info->rbuf_current = i;
4623 }
4624
4625 /*
4626 * mark all receive DMA buffers as free
4627 */
4628 static void reset_rbufs(struct slgt_info *info)
4629 {
4630 free_rbufs(info, 0, info->rbuf_count - 1);
4631 info->rbuf_fill_index = 0;
4632 info->rbuf_fill_count = 0;
4633 }
4634
4635 /*
4636 * pass receive HDLC frame to upper layer
4637 *
4638 * return true if frame available, otherwise false
4639 */
4640 static bool rx_get_frame(struct slgt_info *info)
4641 {
4642 unsigned int start, end;
4643 unsigned short status;
4644 unsigned int framesize = 0;
4645 unsigned long flags;
4646 struct tty_struct *tty = info->port.tty;
4647 unsigned char addr_field = 0xff;
4648 unsigned int crc_size = 0;
4649
4650 switch (info->params.crc_type & HDLC_CRC_MASK) {
4651 case HDLC_CRC_16_CCITT: crc_size = 2; break;
4652 case HDLC_CRC_32_CCITT: crc_size = 4; break;
4653 }
4654
4655 check_again:
4656
4657 framesize = 0;
4658 addr_field = 0xff;
4659 start = end = info->rbuf_current;
4660
4661 for (;;) {
4662 if (!desc_complete(info->rbufs[end]))
4663 goto cleanup;
4664
4665 if (framesize == 0 && info->params.addr_filter != 0xff)
4666 addr_field = info->rbufs[end].buf[0];
4667
4668 framesize += desc_count(info->rbufs[end]);
4669
4670 if (desc_eof(info->rbufs[end]))
4671 break;
4672
4673 if (++end == info->rbuf_count)
4674 end = 0;
4675
4676 if (end == info->rbuf_current) {
4677 if (info->rx_enabled){
4678 spin_lock_irqsave(&info->lock,flags);
4679 rx_start(info);
4680 spin_unlock_irqrestore(&info->lock,flags);
4681 }
4682 goto cleanup;
4683 }
4684 }
4685
4686 /* status
4687 *
4688 * 15 buffer complete
4689 * 14..06 reserved
4690 * 05..04 residue
4691 * 02 eof (end of frame)
4692 * 01 CRC error
4693 * 00 abort
4694 */
4695 status = desc_status(info->rbufs[end]);
4696
4697 /* ignore CRC bit if not using CRC (bit is undefined) */
4698 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4699 status &= ~BIT1;
4700
4701 if (framesize == 0 ||
4702 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4703 free_rbufs(info, start, end);
4704 goto check_again;
4705 }
4706
4707 if (framesize < (2 + crc_size) || status & BIT0) {
4708 info->icount.rxshort++;
4709 framesize = 0;
4710 } else if (status & BIT1) {
4711 info->icount.rxcrc++;
4712 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4713 framesize = 0;
4714 }
4715
4716 #if SYNCLINK_GENERIC_HDLC
4717 if (framesize == 0) {
4718 info->netdev->stats.rx_errors++;
4719 info->netdev->stats.rx_frame_errors++;
4720 }
4721 #endif
4722
4723 DBGBH(("%s rx frame status=%04X size=%d\n",
4724 info->device_name, status, framesize));
4725 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4726
4727 if (framesize) {
4728 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4729 framesize -= crc_size;
4730 crc_size = 0;
4731 }
4732
4733 if (framesize > info->max_frame_size + crc_size)
4734 info->icount.rxlong++;
4735 else {
4736 /* copy dma buffer(s) to contiguous temp buffer */
4737 int copy_count = framesize;
4738 int i = start;
4739 unsigned char *p = info->tmp_rbuf;
4740 info->tmp_rbuf_count = framesize;
4741
4742 info->icount.rxok++;
4743
4744 while(copy_count) {
4745 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4746 memcpy(p, info->rbufs[i].buf, partial_count);
4747 p += partial_count;
4748 copy_count -= partial_count;
4749 if (++i == info->rbuf_count)
4750 i = 0;
4751 }
4752
4753 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4754 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4755 framesize++;
4756 }
4757
4758 #if SYNCLINK_GENERIC_HDLC
4759 if (info->netcount)
4760 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4761 else
4762 #endif
4763 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4764 }
4765 }
4766 free_rbufs(info, start, end);
4767 return true;
4768
4769 cleanup:
4770 return false;
4771 }
4772
4773 /*
4774 * pass receive buffer (RAW synchronous mode) to tty layer
4775 * return true if buffer available, otherwise false
4776 */
4777 static bool rx_get_buf(struct slgt_info *info)
4778 {
4779 unsigned int i = info->rbuf_current;
4780 unsigned int count;
4781
4782 if (!desc_complete(info->rbufs[i]))
4783 return false;
4784 count = desc_count(info->rbufs[i]);
4785 switch(info->params.mode) {
4786 case MGSL_MODE_MONOSYNC:
4787 case MGSL_MODE_BISYNC:
4788 case MGSL_MODE_XSYNC:
4789 /* ignore residue in byte synchronous modes */
4790 if (desc_residue(info->rbufs[i]))
4791 count--;
4792 break;
4793 }
4794 DBGDATA(info, info->rbufs[i].buf, count, "rx");
4795 DBGINFO(("rx_get_buf size=%d\n", count));
4796 if (count)
4797 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4798 info->flag_buf, count);
4799 free_rbufs(info, i, i);
4800 return true;
4801 }
4802
4803 static void reset_tbufs(struct slgt_info *info)
4804 {
4805 unsigned int i;
4806 info->tbuf_current = 0;
4807 for (i=0 ; i < info->tbuf_count ; i++) {
4808 info->tbufs[i].status = 0;
4809 info->tbufs[i].count = 0;
4810 }
4811 }
4812
4813 /*
4814 * return number of free transmit DMA buffers
4815 */
4816 static unsigned int free_tbuf_count(struct slgt_info *info)
4817 {
4818 unsigned int count = 0;
4819 unsigned int i = info->tbuf_current;
4820
4821 do
4822 {
4823 if (desc_count(info->tbufs[i]))
4824 break; /* buffer in use */
4825 ++count;
4826 if (++i == info->tbuf_count)
4827 i=0;
4828 } while (i != info->tbuf_current);
4829
4830 /* if tx DMA active, last zero count buffer is in use */
4831 if (count && (rd_reg32(info, TDCSR) & BIT0))
4832 --count;
4833
4834 return count;
4835 }
4836
4837 /*
4838 * return number of bytes in unsent transmit DMA buffers
4839 * and the serial controller tx FIFO
4840 */
4841 static unsigned int tbuf_bytes(struct slgt_info *info)
4842 {
4843 unsigned int total_count = 0;
4844 unsigned int i = info->tbuf_current;
4845 unsigned int reg_value;
4846 unsigned int count;
4847 unsigned int active_buf_count = 0;
4848
4849 /*
4850 * Add descriptor counts for all tx DMA buffers.
4851 * If count is zero (cleared by DMA controller after read),
4852 * the buffer is complete or is actively being read from.
4853 *
4854 * Record buf_count of last buffer with zero count starting
4855 * from current ring position. buf_count is mirror
4856 * copy of count and is not cleared by serial controller.
4857 * If DMA controller is active, that buffer is actively
4858 * being read so add to total.
4859 */
4860 do {
4861 count = desc_count(info->tbufs[i]);
4862 if (count)
4863 total_count += count;
4864 else if (!total_count)
4865 active_buf_count = info->tbufs[i].buf_count;
4866 if (++i == info->tbuf_count)
4867 i = 0;
4868 } while (i != info->tbuf_current);
4869
4870 /* read tx DMA status register */
4871 reg_value = rd_reg32(info, TDCSR);
4872
4873 /* if tx DMA active, last zero count buffer is in use */
4874 if (reg_value & BIT0)
4875 total_count += active_buf_count;
4876
4877 /* add tx FIFO count = reg_value[15..8] */
4878 total_count += (reg_value >> 8) & 0xff;
4879
4880 /* if transmitter active add one byte for shift register */
4881 if (info->tx_active)
4882 total_count++;
4883
4884 return total_count;
4885 }
4886
4887 /*
4888 * load data into transmit DMA buffer ring and start transmitter if needed
4889 * return true if data accepted, otherwise false (buffers full)
4890 */
4891 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4892 {
4893 unsigned short count;
4894 unsigned int i;
4895 struct slgt_desc *d;
4896
4897 /* check required buffer space */
4898 if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4899 return false;
4900
4901 DBGDATA(info, buf, size, "tx");
4902
4903 /*
4904 * copy data to one or more DMA buffers in circular ring
4905 * tbuf_start = first buffer for this data
4906 * tbuf_current = next free buffer
4907 *
4908 * Copy all data before making data visible to DMA controller by
4909 * setting descriptor count of the first buffer.
4910 * This prevents an active DMA controller from reading the first DMA
4911 * buffers of a frame and stopping before the final buffers are filled.
4912 */
4913
4914 info->tbuf_start = i = info->tbuf_current;
4915
4916 while (size) {
4917 d = &info->tbufs[i];
4918
4919 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4920 memcpy(d->buf, buf, count);
4921
4922 size -= count;
4923 buf += count;
4924
4925 /*
4926 * set EOF bit for last buffer of HDLC frame or
4927 * for every buffer in raw mode
4928 */
4929 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4930 info->params.mode == MGSL_MODE_RAW)
4931 set_desc_eof(*d, 1);
4932 else
4933 set_desc_eof(*d, 0);
4934
4935 /* set descriptor count for all but first buffer */
4936 if (i != info->tbuf_start)
4937 set_desc_count(*d, count);
4938 d->buf_count = count;
4939
4940 if (++i == info->tbuf_count)
4941 i = 0;
4942 }
4943
4944 info->tbuf_current = i;
4945
4946 /* set first buffer count to make new data visible to DMA controller */
4947 d = &info->tbufs[info->tbuf_start];
4948 set_desc_count(*d, d->buf_count);
4949
4950 /* start transmitter if needed and update transmit timeout */
4951 if (!info->tx_active)
4952 tx_start(info);
4953 update_tx_timer(info);
4954
4955 return true;
4956 }
4957
4958 static int register_test(struct slgt_info *info)
4959 {
4960 static unsigned short patterns[] =
4961 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4962 static unsigned int count = ARRAY_SIZE(patterns);
4963 unsigned int i;
4964 int rc = 0;
4965
4966 for (i=0 ; i < count ; i++) {
4967 wr_reg16(info, TIR, patterns[i]);
4968 wr_reg16(info, BDR, patterns[(i+1)%count]);
4969 if ((rd_reg16(info, TIR) != patterns[i]) ||
4970 (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4971 rc = -ENODEV;
4972 break;
4973 }
4974 }
4975 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4976 info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4977 return rc;
4978 }
4979
4980 static int irq_test(struct slgt_info *info)
4981 {
4982 unsigned long timeout;
4983 unsigned long flags;
4984 struct tty_struct *oldtty = info->port.tty;
4985 u32 speed = info->params.data_rate;
4986
4987 info->params.data_rate = 921600;
4988 info->port.tty = NULL;
4989
4990 spin_lock_irqsave(&info->lock, flags);
4991 async_mode(info);
4992 slgt_irq_on(info, IRQ_TXIDLE);
4993
4994 /* enable transmitter */
4995 wr_reg16(info, TCR,
4996 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4997
4998 /* write one byte and wait for tx idle */
4999 wr_reg16(info, TDR, 0);
5000
5001 /* assume failure */
5002 info->init_error = DiagStatus_IrqFailure;
5003 info->irq_occurred = false;
5004
5005 spin_unlock_irqrestore(&info->lock, flags);
5006
5007 timeout=100;
5008 while(timeout-- && !info->irq_occurred)
5009 msleep_interruptible(10);
5010
5011 spin_lock_irqsave(&info->lock,flags);
5012 reset_port(info);
5013 spin_unlock_irqrestore(&info->lock,flags);
5014
5015 info->params.data_rate = speed;
5016 info->port.tty = oldtty;
5017
5018 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
5019 return info->irq_occurred ? 0 : -ENODEV;
5020 }
5021
5022 static int loopback_test_rx(struct slgt_info *info)
5023 {
5024 unsigned char *src, *dest;
5025 int count;
5026
5027 if (desc_complete(info->rbufs[0])) {
5028 count = desc_count(info->rbufs[0]);
5029 src = info->rbufs[0].buf;
5030 dest = info->tmp_rbuf;
5031
5032 for( ; count ; count-=2, src+=2) {
5033 /* src=data byte (src+1)=status byte */
5034 if (!(*(src+1) & (BIT9 + BIT8))) {
5035 *dest = *src;
5036 dest++;
5037 info->tmp_rbuf_count++;
5038 }
5039 }
5040 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
5041 return 1;
5042 }
5043 return 0;
5044 }
5045
5046 static int loopback_test(struct slgt_info *info)
5047 {
5048 #define TESTFRAMESIZE 20
5049
5050 unsigned long timeout;
5051 u16 count = TESTFRAMESIZE;
5052 unsigned char buf[TESTFRAMESIZE];
5053 int rc = -ENODEV;
5054 unsigned long flags;
5055
5056 struct tty_struct *oldtty = info->port.tty;
5057 MGSL_PARAMS params;
5058
5059 memcpy(&params, &info->params, sizeof(params));
5060
5061 info->params.mode = MGSL_MODE_ASYNC;
5062 info->params.data_rate = 921600;
5063 info->params.loopback = 1;
5064 info->port.tty = NULL;
5065
5066 /* build and send transmit frame */
5067 for (count = 0; count < TESTFRAMESIZE; ++count)
5068 buf[count] = (unsigned char)count;
5069
5070 info->tmp_rbuf_count = 0;
5071 memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
5072
5073 /* program hardware for HDLC and enabled receiver */
5074 spin_lock_irqsave(&info->lock,flags);
5075 async_mode(info);
5076 rx_start(info);
5077 tx_load(info, buf, count);
5078 spin_unlock_irqrestore(&info->lock, flags);
5079
5080 /* wait for receive complete */
5081 for (timeout = 100; timeout; --timeout) {
5082 msleep_interruptible(10);
5083 if (loopback_test_rx(info)) {
5084 rc = 0;
5085 break;
5086 }
5087 }
5088
5089 /* verify received frame length and contents */
5090 if (!rc && (info->tmp_rbuf_count != count ||
5091 memcmp(buf, info->tmp_rbuf, count))) {
5092 rc = -ENODEV;
5093 }
5094
5095 spin_lock_irqsave(&info->lock,flags);
5096 reset_adapter(info);
5097 spin_unlock_irqrestore(&info->lock,flags);
5098
5099 memcpy(&info->params, &params, sizeof(info->params));
5100 info->port.tty = oldtty;
5101
5102 info->init_error = rc ? DiagStatus_DmaFailure : 0;
5103 return rc;
5104 }
5105
5106 static int adapter_test(struct slgt_info *info)
5107 {
5108 DBGINFO(("testing %s\n", info->device_name));
5109 if (register_test(info) < 0) {
5110 printk("register test failure %s addr=%08X\n",
5111 info->device_name, info->phys_reg_addr);
5112 } else if (irq_test(info) < 0) {
5113 printk("IRQ test failure %s IRQ=%d\n",
5114 info->device_name, info->irq_level);
5115 } else if (loopback_test(info) < 0) {
5116 printk("loopback test failure %s\n", info->device_name);
5117 }
5118 return info->init_error;
5119 }
5120
5121 /*
5122 * transmit timeout handler
5123 */
5124 static void tx_timeout(unsigned long context)
5125 {
5126 struct slgt_info *info = (struct slgt_info*)context;
5127 unsigned long flags;
5128
5129 DBGINFO(("%s tx_timeout\n", info->device_name));
5130 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5131 info->icount.txtimeout++;
5132 }
5133 spin_lock_irqsave(&info->lock,flags);
5134 tx_stop(info);
5135 spin_unlock_irqrestore(&info->lock,flags);
5136
5137 #if SYNCLINK_GENERIC_HDLC
5138 if (info->netcount)
5139 hdlcdev_tx_done(info);
5140 else
5141 #endif
5142 bh_transmit(info);
5143 }
5144
5145 /*
5146 * receive buffer polling timer
5147 */
5148 static void rx_timeout(unsigned long context)
5149 {
5150 struct slgt_info *info = (struct slgt_info*)context;
5151 unsigned long flags;
5152
5153 DBGINFO(("%s rx_timeout\n", info->device_name));
5154 spin_lock_irqsave(&info->lock, flags);
5155 info->pending_bh |= BH_RECEIVE;
5156 spin_unlock_irqrestore(&info->lock, flags);
5157 bh_handler(&info->task);
5158 }
5159
Linux with added FPC-III support