drivers/media/dvb-frontends/au8522_decoder.c

   1 /*
   2  * Auvitek AU8522 QAM/8VSB demodulator driver and video decoder
   3  *
   4  * Copyright (C) 2009 Devin Heitmueller <dheitmueller@linuxtv.org>
   5  * Copyright (C) 2005-2008 Auvitek International, Ltd.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * As published by the Free Software Foundation; either version 2
  10  * of the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  20  * 02110-1301, USA.
  21  */
  22
  23 /* Developer notes:
  24  *
  25  * VBI support is not yet working
  26  * Enough is implemented here for CVBS and S-Video inputs, but the actual
  27  *  analog demodulator code isn't implemented (not needed for xc5000 since it
  28  *  has its own demodulator and outputs CVBS)
  29  *
  30  */
  31
  32 #include <linux/kernel.h>
  33 #include <linux/slab.h>
  34 #include <linux/videodev2.h>
  35 #include <linux/i2c.h>
  36 #include <linux/delay.h>
  37 #include <media/v4l2-common.h>
  38 #include <media/v4l2-device.h>
  39 #include "au8522.h"
  40 #include "au8522_priv.h"
  41
  42 MODULE_AUTHOR("Devin Heitmueller");
  43 MODULE_LICENSE("GPL");
  44
  45 static int au8522_analog_debug;
  46
  47
  48 module_param_named(analog_debug, au8522_analog_debug, int, 0644);
  49
  50 MODULE_PARM_DESC(analog_debug,
  51                  "Analog debugging messages [0=Off (default) 1=On]");
  52
  53 struct au8522_register_config {
  54         u16 reg_name;
  55         u8 reg_val[8];
  56 };
  57
  58
  59 /* Video Decoder Filter Coefficients
  60    The values are as follows from left to right
  61    0="ATV RF" 1="ATV RF13" 2="CVBS" 3="S-Video" 4="PAL" 5=CVBS13" 6="SVideo13"
  62 */
  63 static const struct au8522_register_config filter_coef[] = {
  64         {AU8522_FILTER_COEF_R410, {0x25, 0x00, 0x25, 0x25, 0x00, 0x00, 0x00} },
  65         {AU8522_FILTER_COEF_R411, {0x20, 0x00, 0x20, 0x20, 0x00, 0x00, 0x00} },
  66         {AU8522_FILTER_COEF_R412, {0x03, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00} },
  67         {AU8522_FILTER_COEF_R413, {0xe6, 0x00, 0xe6, 0xe6, 0x00, 0x00, 0x00} },
  68         {AU8522_FILTER_COEF_R414, {0x40, 0x00, 0x40, 0x40, 0x00, 0x00, 0x00} },
  69         {AU8522_FILTER_COEF_R415, {0x1b, 0x00, 0x1b, 0x1b, 0x00, 0x00, 0x00} },
  70         {AU8522_FILTER_COEF_R416, {0xc0, 0x00, 0xc0, 0x04, 0x00, 0x00, 0x00} },
  71         {AU8522_FILTER_COEF_R417, {0x04, 0x00, 0x04, 0x04, 0x00, 0x00, 0x00} },
  72         {AU8522_FILTER_COEF_R418, {0x8c, 0x00, 0x8c, 0x8c, 0x00, 0x00, 0x00} },
  73         {AU8522_FILTER_COEF_R419, {0xa0, 0x40, 0xa0, 0xa0, 0x40, 0x40, 0x40} },
  74         {AU8522_FILTER_COEF_R41A, {0x21, 0x09, 0x21, 0x21, 0x09, 0x09, 0x09} },
  75         {AU8522_FILTER_COEF_R41B, {0x6c, 0x38, 0x6c, 0x6c, 0x38, 0x38, 0x38} },
  76         {AU8522_FILTER_COEF_R41C, {0x03, 0xff, 0x03, 0x03, 0xff, 0xff, 0xff} },
  77         {AU8522_FILTER_COEF_R41D, {0xbf, 0xc7, 0xbf, 0xbf, 0xc7, 0xc7, 0xc7} },
  78         {AU8522_FILTER_COEF_R41E, {0xa0, 0xdf, 0xa0, 0xa0, 0xdf, 0xdf, 0xdf} },
  79         {AU8522_FILTER_COEF_R41F, {0x10, 0x06, 0x10, 0x10, 0x06, 0x06, 0x06} },
  80         {AU8522_FILTER_COEF_R420, {0xae, 0x30, 0xae, 0xae, 0x30, 0x30, 0x30} },
  81         {AU8522_FILTER_COEF_R421, {0xc4, 0x01, 0xc4, 0xc4, 0x01, 0x01, 0x01} },
  82         {AU8522_FILTER_COEF_R422, {0x54, 0xdd, 0x54, 0x54, 0xdd, 0xdd, 0xdd} },
  83         {AU8522_FILTER_COEF_R423, {0xd0, 0xaf, 0xd0, 0xd0, 0xaf, 0xaf, 0xaf} },
  84         {AU8522_FILTER_COEF_R424, {0x1c, 0xf7, 0x1c, 0x1c, 0xf7, 0xf7, 0xf7} },
  85         {AU8522_FILTER_COEF_R425, {0x76, 0xdb, 0x76, 0x76, 0xdb, 0xdb, 0xdb} },
  86         {AU8522_FILTER_COEF_R426, {0x61, 0xc0, 0x61, 0x61, 0xc0, 0xc0, 0xc0} },
  87         {AU8522_FILTER_COEF_R427, {0xd1, 0x2f, 0xd1, 0xd1, 0x2f, 0x2f, 0x2f} },
  88         {AU8522_FILTER_COEF_R428, {0x84, 0xd8, 0x84, 0x84, 0xd8, 0xd8, 0xd8} },
  89         {AU8522_FILTER_COEF_R429, {0x06, 0xfb, 0x06, 0x06, 0xfb, 0xfb, 0xfb} },
  90         {AU8522_FILTER_COEF_R42A, {0x21, 0xd5, 0x21, 0x21, 0xd5, 0xd5, 0xd5} },
  91         {AU8522_FILTER_COEF_R42B, {0x0a, 0x3e, 0x0a, 0x0a, 0x3e, 0x3e, 0x3e} },
  92         {AU8522_FILTER_COEF_R42C, {0xe6, 0x15, 0xe6, 0xe6, 0x15, 0x15, 0x15} },
  93         {AU8522_FILTER_COEF_R42D, {0x01, 0x34, 0x01, 0x01, 0x34, 0x34, 0x34} },
  94
  95 };
  96 #define NUM_FILTER_COEF (sizeof(filter_coef)\
  97                          / sizeof(struct au8522_register_config))
  98
  99
 100 /* Registers 0x060b through 0x0652 are the LP Filter coefficients
 101    The values are as follows from left to right
 102    0="SIF" 1="ATVRF/ATVRF13"
 103    Note: the "ATVRF/ATVRF13" mode has never been tested
 104 */
 105 static const struct au8522_register_config lpfilter_coef[] = {
 106         {0x060b, {0x21, 0x0b} },
 107         {0x060c, {0xad, 0xad} },
 108         {0x060d, {0x70, 0xf0} },
 109         {0x060e, {0xea, 0xe9} },
 110         {0x060f, {0xdd, 0xdd} },
 111         {0x0610, {0x08, 0x64} },
 112         {0x0611, {0x60, 0x60} },
 113         {0x0612, {0xf8, 0xb2} },
 114         {0x0613, {0x01, 0x02} },
 115         {0x0614, {0xe4, 0xb4} },
 116         {0x0615, {0x19, 0x02} },
 117         {0x0616, {0xae, 0x2e} },
 118         {0x0617, {0xee, 0xc5} },
 119         {0x0618, {0x56, 0x56} },
 120         {0x0619, {0x30, 0x58} },
 121         {0x061a, {0xf9, 0xf8} },
 122         {0x061b, {0x24, 0x64} },
 123         {0x061c, {0x07, 0x07} },
 124         {0x061d, {0x30, 0x30} },
 125         {0x061e, {0xa9, 0xed} },
 126         {0x061f, {0x09, 0x0b} },
 127         {0x0620, {0x42, 0xc2} },
 128         {0x0621, {0x1d, 0x2a} },
 129         {0x0622, {0xd6, 0x56} },
 130         {0x0623, {0x95, 0x8b} },
 131         {0x0624, {0x2b, 0x2b} },
 132         {0x0625, {0x30, 0x24} },
 133         {0x0626, {0x3e, 0x3e} },
 134         {0x0627, {0x62, 0xe2} },
 135         {0x0628, {0xe9, 0xf5} },
 136         {0x0629, {0x99, 0x19} },
 137         {0x062a, {0xd4, 0x11} },
 138         {0x062b, {0x03, 0x04} },
 139         {0x062c, {0xb5, 0x85} },
 140         {0x062d, {0x1e, 0x20} },
 141         {0x062e, {0x2a, 0xea} },
 142         {0x062f, {0xd7, 0xd2} },
 143         {0x0630, {0x15, 0x15} },
 144         {0x0631, {0xa3, 0xa9} },
 145         {0x0632, {0x1f, 0x1f} },
 146         {0x0633, {0xf9, 0xd1} },
 147         {0x0634, {0xc0, 0xc3} },
 148         {0x0635, {0x4d, 0x8d} },
 149         {0x0636, {0x21, 0x31} },
 150         {0x0637, {0x83, 0x83} },
 151         {0x0638, {0x08, 0x8c} },
 152         {0x0639, {0x19, 0x19} },
 153         {0x063a, {0x45, 0xa5} },
 154         {0x063b, {0xef, 0xec} },
 155         {0x063c, {0x8a, 0x8a} },
 156         {0x063d, {0xf4, 0xf6} },
 157         {0x063e, {0x8f, 0x8f} },
 158         {0x063f, {0x44, 0x0c} },
 159         {0x0640, {0xef, 0xf0} },
 160         {0x0641, {0x66, 0x66} },
 161         {0x0642, {0xcc, 0xd2} },
 162         {0x0643, {0x41, 0x41} },
 163         {0x0644, {0x63, 0x93} },
 164         {0x0645, {0x8e, 0x8e} },
 165         {0x0646, {0xa2, 0x42} },
 166         {0x0647, {0x7b, 0x7b} },
 167         {0x0648, {0x04, 0x04} },
 168         {0x0649, {0x00, 0x00} },
 169         {0x064a, {0x40, 0x40} },
 170         {0x064b, {0x8c, 0x98} },
 171         {0x064c, {0x00, 0x00} },
 172         {0x064d, {0x63, 0xc3} },
 173         {0x064e, {0x04, 0x04} },
 174         {0x064f, {0x20, 0x20} },
 175         {0x0650, {0x00, 0x00} },
 176         {0x0651, {0x40, 0x40} },
 177         {0x0652, {0x01, 0x01} },
 178 };
 179 #define NUM_LPFILTER_COEF (sizeof(lpfilter_coef)\
 180                            / sizeof(struct au8522_register_config))
 181
 182 static inline struct au8522_state *to_state(struct v4l2_subdev *sd)
 183 {
 184         return container_of(sd, struct au8522_state, sd);
 185 }
 186
 187 static void setup_vbi(struct au8522_state *state, int aud_input)
 188 {
 189         int i;
 190
 191         /* These are set to zero regardless of what mode we're in */
 192         au8522_writereg(state, AU8522_TVDEC_VBI_CTRL_H_REG017H, 0x00);
 193         au8522_writereg(state, AU8522_TVDEC_VBI_CTRL_L_REG018H, 0x00);
 194         au8522_writereg(state, AU8522_TVDEC_VBI_USER_TOTAL_BITS_REG019H, 0x00);
 195         au8522_writereg(state, AU8522_TVDEC_VBI_USER_TUNIT_H_REG01AH, 0x00);
 196         au8522_writereg(state, AU8522_TVDEC_VBI_USER_TUNIT_L_REG01BH, 0x00);
 197         au8522_writereg(state, AU8522_TVDEC_VBI_USER_THRESH1_REG01CH, 0x00);
 198         au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_PAT2_REG01EH, 0x00);
 199         au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_PAT1_REG01FH, 0x00);
 200         au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_PAT0_REG020H, 0x00);
 201         au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_MASK2_REG021H,
 202                         0x00);
 203         au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_MASK1_REG022H,
 204                         0x00);
 205         au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_MASK0_REG023H,
 206                         0x00);
 207
 208         /* Setup the VBI registers */
 209         for (i = 0x30; i < 0x60; i++)
 210                 au8522_writereg(state, i, 0x40);
 211
 212         /* For some reason, every register is 0x40 except register 0x44
 213            (confirmed via the HVR-950q USB capture) */
 214         au8522_writereg(state, 0x44, 0x60);
 215
 216         /* Enable VBI (we always do this regardless of whether the user is
 217            viewing closed caption info) */
 218         au8522_writereg(state, AU8522_TVDEC_VBI_CTRL_H_REG017H,
 219                         AU8522_TVDEC_VBI_CTRL_H_REG017H_CCON);
 220
 221 }
 222
 223 static void setup_decoder_defaults(struct au8522_state *state, u8 input_mode)
 224 {
 225         int i;
 226         int filter_coef_type;
 227
 228         /* Provide reasonable defaults for picture tuning values */
 229         au8522_writereg(state, AU8522_TVDEC_SHARPNESSREG009H, 0x07);
 230         au8522_writereg(state, AU8522_TVDEC_BRIGHTNESS_REG00AH, 0xed);
 231         au8522_writereg(state, AU8522_TVDEC_CONTRAST_REG00BH, 0x79);
 232         au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH, 0x80);
 233         au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH, 0x80);
 234         au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH, 0x00);
 235         au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH, 0x00);
 236
 237         /* Other decoder registers */
 238         au8522_writereg(state, AU8522_TVDEC_INT_MASK_REG010H, 0x00);
 239
 240         if (input_mode == 0x23) {
 241                 /* S-Video input mapping */
 242                 au8522_writereg(state, AU8522_VIDEO_MODE_REG011H, 0x04);
 243         } else {
 244                 /* All other modes (CVBS/ATVRF etc.) */
 245                 au8522_writereg(state, AU8522_VIDEO_MODE_REG011H, 0x00);
 246         }
 247
 248         au8522_writereg(state, AU8522_TVDEC_PGA_REG012H,
 249                         AU8522_TVDEC_PGA_REG012H_CVBS);
 250         au8522_writereg(state, AU8522_TVDEC_COMB_MODE_REG015H,
 251                         AU8522_TVDEC_COMB_MODE_REG015H_CVBS);
 252         au8522_writereg(state, AU8522_TVDED_DBG_MODE_REG060H,
 253                         AU8522_TVDED_DBG_MODE_REG060H_CVBS);
 254         au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL1_REG061H,
 255                         AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_525 |
 256                         AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_63_492 |
 257                         AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_MN);
 258         au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL2_REG062H,
 259                         AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_NTSC);
 260         au8522_writereg(state, AU8522_TVDEC_VCR_DET_LLIM_REG063H,
 261                         AU8522_TVDEC_VCR_DET_LLIM_REG063H_CVBS);
 262         au8522_writereg(state, AU8522_TVDEC_VCR_DET_HLIM_REG064H,
 263                         AU8522_TVDEC_VCR_DET_HLIM_REG064H_CVBS);
 264         au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR1_REG065H,
 265                         AU8522_TVDEC_COMB_VDIF_THR1_REG065H_CVBS);
 266         au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR2_REG066H,
 267                         AU8522_TVDEC_COMB_VDIF_THR2_REG066H_CVBS);
 268         au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR3_REG067H,
 269                         AU8522_TVDEC_COMB_VDIF_THR3_REG067H_CVBS);
 270         au8522_writereg(state, AU8522_TVDEC_COMB_NOTCH_THR_REG068H,
 271                         AU8522_TVDEC_COMB_NOTCH_THR_REG068H_CVBS);
 272         au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR1_REG069H,
 273                         AU8522_TVDEC_COMB_HDIF_THR1_REG069H_CVBS);
 274         au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR2_REG06AH,
 275                         AU8522_TVDEC_COMB_HDIF_THR2_REG06AH_CVBS);
 276         au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR3_REG06BH,
 277                         AU8522_TVDEC_COMB_HDIF_THR3_REG06BH_CVBS);
 278         if (input_mode == AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13 ||
 279             input_mode == AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH24) {
 280                 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH,
 281                                 AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_SVIDEO);
 282                 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH,
 283                                 AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_SVIDEO);
 284         } else {
 285                 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH,
 286                                 AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_CVBS);
 287                 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH,
 288                                 AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_CVBS);
 289         }
 290         au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH,
 291                         AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH_CVBS);
 292         au8522_writereg(state, AU8522_TVDEC_UV_SEP_THR_REG06FH,
 293                         AU8522_TVDEC_UV_SEP_THR_REG06FH_CVBS);
 294         au8522_writereg(state, AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H,
 295                         AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H_CVBS);
 296         au8522_writereg(state, AU8522_REG071H, AU8522_REG071H_CVBS);
 297         au8522_writereg(state, AU8522_REG072H, AU8522_REG072H_CVBS);
 298         au8522_writereg(state, AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H,
 299                         AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H_CVBS);
 300         au8522_writereg(state, AU8522_REG074H, AU8522_REG074H_CVBS);
 301         au8522_writereg(state, AU8522_REG075H, AU8522_REG075H_CVBS);
 302         au8522_writereg(state, AU8522_TVDEC_DCAGC_CTRL_REG077H,
 303                         AU8522_TVDEC_DCAGC_CTRL_REG077H_CVBS);
 304         au8522_writereg(state, AU8522_TVDEC_PIC_START_ADJ_REG078H,
 305                         AU8522_TVDEC_PIC_START_ADJ_REG078H_CVBS);
 306         au8522_writereg(state, AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H,
 307                         AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H_CVBS);
 308         au8522_writereg(state, AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH,
 309                         AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH_CVBS);
 310         au8522_writereg(state, AU8522_TVDEC_INTRP_CTRL_REG07BH,
 311                         AU8522_TVDEC_INTRP_CTRL_REG07BH_CVBS);
 312         au8522_writereg(state, AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H,
 313                         AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H_CVBS);
 314         au8522_writereg(state, AU8522_TOREGAAGC_REG0E5H,
 315                         AU8522_TOREGAAGC_REG0E5H_CVBS);
 316         au8522_writereg(state, AU8522_REG016H, AU8522_REG016H_CVBS);
 317
 318         setup_vbi(state, 0);
 319
 320         if (input_mode == AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13 ||
 321             input_mode == AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH24) {
 322                 /* Despite what the table says, for the HVR-950q we still need
 323                    to be in CVBS mode for the S-Video input (reason unknown). */
 324                 /* filter_coef_type = 3; */
 325                 filter_coef_type = 5;
 326         } else {
 327                 filter_coef_type = 5;
 328         }
 329
 330         /* Load the Video Decoder Filter Coefficients */
 331         for (i = 0; i < NUM_FILTER_COEF; i++) {
 332                 au8522_writereg(state, filter_coef[i].reg_name,
 333                                 filter_coef[i].reg_val[filter_coef_type]);
 334         }
 335
 336         /* It's not clear what these registers are for, but they are always
 337            set to the same value regardless of what mode we're in */
 338         au8522_writereg(state, AU8522_REG42EH, 0x87);
 339         au8522_writereg(state, AU8522_REG42FH, 0xa2);
 340         au8522_writereg(state, AU8522_REG430H, 0xbf);
 341         au8522_writereg(state, AU8522_REG431H, 0xcb);
 342         au8522_writereg(state, AU8522_REG432H, 0xa1);
 343         au8522_writereg(state, AU8522_REG433H, 0x41);
 344         au8522_writereg(state, AU8522_REG434H, 0x88);
 345         au8522_writereg(state, AU8522_REG435H, 0xc2);
 346         au8522_writereg(state, AU8522_REG436H, 0x3c);
 347 }
 348
 349 static void au8522_setup_cvbs_mode(struct au8522_state *state)
 350 {
 351         /* here we're going to try the pre-programmed route */
 352         au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
 353                         AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS);
 354
 355         /* PGA in automatic mode */
 356         au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
 357
 358         /* Enable clamping control */
 359         au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x00);
 360
 361         au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H,
 362                         AU8522_INPUT_CONTROL_REG081H_CVBS_CH1);
 363
 364         setup_decoder_defaults(state, AU8522_INPUT_CONTROL_REG081H_CVBS_CH1);
 365
 366         au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
 367                         AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS);
 368 }
 369
 370 static void au8522_setup_cvbs_tuner_mode(struct au8522_state *state)
 371 {
 372         /* here we're going to try the pre-programmed route */
 373         au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
 374                         AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS);
 375
 376         /* It's not clear why we have to have the PGA in automatic mode while
 377            enabling clamp control, but it's what Windows does */
 378         au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
 379
 380         /* Enable clamping control */
 381         au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x0e);
 382
 383         /* Disable automatic PGA (since the CVBS is coming from the tuner) */
 384         au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x10);
 385
 386         /* Set input mode to CVBS on channel 4 with SIF audio input enabled */
 387         au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H,
 388                         AU8522_INPUT_CONTROL_REG081H_CVBS_CH4_SIF);
 389
 390         setup_decoder_defaults(state,
 391                                AU8522_INPUT_CONTROL_REG081H_CVBS_CH4_SIF);
 392
 393         au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
 394                         AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS);
 395 }
 396
 397 static void au8522_setup_svideo_mode(struct au8522_state *state)
 398 {
 399         au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
 400                         AU8522_MODULE_CLOCK_CONTROL_REG0A3H_SVIDEO);
 401
 402         /* Set input to Y on Channe1, C on Channel 3 */
 403         au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H,
 404                         AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13);
 405
 406         /* PGA in automatic mode */
 407         au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
 408
 409         /* Enable clamping control */
 410         au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x00);
 411
 412         setup_decoder_defaults(state,
 413                                AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13);
 414
 415         au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
 416                         AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS);
 417 }
 418
 419 /* ----------------------------------------------------------------------- */
 420
 421 static void disable_audio_input(struct au8522_state *state)
 422 {
 423         au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x00);
 424         au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x00);
 425         au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0x00);
 426
 427         au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H, 0x04);
 428         au8522_writereg(state, AU8522_I2S_CTRL_2_REG112H, 0x02);
 429
 430         au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
 431                         AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_SVIDEO);
 432 }
 433
 434 /* 0=disable, 1=SIF */
 435 static void set_audio_input(struct au8522_state *state, int aud_input)
 436 {
 437         int i;
 438
 439         /* Note that this function needs to be used in conjunction with setting
 440            the input routing via register 0x81 */
 441
 442         if (aud_input == AU8522_AUDIO_NONE) {
 443                 disable_audio_input(state);
 444                 return;
 445         }
 446
 447         if (aud_input != AU8522_AUDIO_SIF) {
 448                 /* The caller asked for a mode we don't currently support */
 449                 printk(KERN_ERR "Unsupported audio mode requested! mode=%d\n",
 450                        aud_input);
 451                 return;
 452         }
 453
 454         /* Load the Audio Decoder Filter Coefficients */
 455         for (i = 0; i < NUM_LPFILTER_COEF; i++) {
 456                 au8522_writereg(state, lpfilter_coef[i].reg_name,
 457                                 lpfilter_coef[i].reg_val[0]);
 458         }
 459
 460         /* Setup audio */
 461         au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x00);
 462         au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x00);
 463         au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0x00);
 464         au8522_writereg(state, AU8522_I2C_CONTROL_REG1_REG091H, 0x80);
 465         au8522_writereg(state, AU8522_I2C_CONTROL_REG0_REG090H, 0x84);
 466         msleep(150);
 467         au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H, 0x00);
 468         msleep(1);
 469         au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H, 0x9d);
 470         msleep(50);
 471         au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x7F);
 472         au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x7F);
 473         au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0xff);
 474         msleep(80);
 475         au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x7F);
 476         au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x7F);
 477         au8522_writereg(state, AU8522_REG0F9H, AU8522_REG0F9H_AUDIO);
 478         au8522_writereg(state, AU8522_AUDIO_MODE_REG0F1H, 0x82);
 479         msleep(70);
 480         au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H, 0x09);
 481         au8522_writereg(state, AU8522_AUDIOFREQ_REG606H, 0x03);
 482         au8522_writereg(state, AU8522_I2S_CTRL_2_REG112H, 0xc2);
 483 }
 484
 485 /* ----------------------------------------------------------------------- */
 486
 487 static int au8522_s_ctrl(struct v4l2_ctrl *ctrl)
 488 {
 489         struct au8522_state *state =
 490                 container_of(ctrl->handler, struct au8522_state, hdl);
 491
 492         switch (ctrl->id) {
 493         case V4L2_CID_BRIGHTNESS:
 494                 au8522_writereg(state, AU8522_TVDEC_BRIGHTNESS_REG00AH,
 495                                 ctrl->val - 128);
 496                 break;
 497         case V4L2_CID_CONTRAST:
 498                 au8522_writereg(state, AU8522_TVDEC_CONTRAST_REG00BH,
 499                                 ctrl->val);
 500                 break;
 501         case V4L2_CID_SATURATION:
 502                 au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH,
 503                                 ctrl->val);
 504                 au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH,
 505                                 ctrl->val);
 506                 break;
 507         case V4L2_CID_HUE:
 508                 au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH,
 509                                 ctrl->val >> 8);
 510                 au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH,
 511                                 ctrl->val & 0xFF);
 512                 break;
 513         default:
 514                 return -EINVAL;
 515         }
 516
 517         return 0;
 518 }
 519
 520 /* ----------------------------------------------------------------------- */
 521
 522 #ifdef CONFIG_VIDEO_ADV_DEBUG
 523 static int au8522_g_register(struct v4l2_subdev *sd,
 524                              struct v4l2_dbg_register *reg)
 525 {
 526         struct au8522_state *state = to_state(sd);
 527
 528         reg->val = au8522_readreg(state, reg->reg & 0xffff);
 529         return 0;
 530 }
 531
 532 static int au8522_s_register(struct v4l2_subdev *sd,
 533                              const struct v4l2_dbg_register *reg)
 534 {
 535         struct au8522_state *state = to_state(sd);
 536
 537         au8522_writereg(state, reg->reg, reg->val & 0xff);
 538         return 0;
 539 }
 540 #endif
 541
 542 static int au8522_s_stream(struct v4l2_subdev *sd, int enable)
 543 {
 544         struct au8522_state *state = to_state(sd);
 545
 546         if (enable) {
 547                 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
 548                                 0x01);
 549                 msleep(1);
 550                 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
 551                                 AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS);
 552         } else {
 553                 /* This does not completely power down the device
 554                    (it only reduces it from around 140ma to 80ma) */
 555                 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
 556                                 1 << 5);
 557         }
 558         return 0;
 559 }
 560
 561 static int au8522_reset(struct v4l2_subdev *sd, u32 val)
 562 {
 563         struct au8522_state *state = to_state(sd);
 564
 565         state->operational_mode = AU8522_ANALOG_MODE;
 566
 567         /* Clear out any state associated with the digital side of the
 568            chip, so that when it gets powered back up it won't think
 569            that it is already tuned */
 570         state->current_frequency = 0;
 571
 572         au8522_writereg(state, 0xa4, 1 << 5);
 573
 574         return 0;
 575 }
 576
 577 static int au8522_s_video_routing(struct v4l2_subdev *sd,
 578                                         u32 input, u32 output, u32 config)
 579 {
 580         struct au8522_state *state = to_state(sd);
 581
 582         au8522_reset(sd, 0);
 583
 584         if (input == AU8522_COMPOSITE_CH1) {
 585                 au8522_setup_cvbs_mode(state);
 586         } else if (input == AU8522_SVIDEO_CH13) {
 587                 au8522_setup_svideo_mode(state);
 588         } else if (input == AU8522_COMPOSITE_CH4_SIF) {
 589                 au8522_setup_cvbs_tuner_mode(state);
 590         } else {
 591                 printk(KERN_ERR "au8522 mode not currently supported\n");
 592                 return -EINVAL;
 593         }
 594         return 0;
 595 }
 596
 597 static int au8522_s_audio_routing(struct v4l2_subdev *sd,
 598                                         u32 input, u32 output, u32 config)
 599 {
 600         struct au8522_state *state = to_state(sd);
 601         set_audio_input(state, input);
 602         return 0;
 603 }
 604
 605 static int au8522_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
 606 {
 607         int val = 0;
 608         struct au8522_state *state = to_state(sd);
 609         u8 lock_status;
 610
 611         /* Interrogate the decoder to see if we are getting a real signal */
 612         lock_status = au8522_readreg(state, 0x00);
 613         if (lock_status == 0xa2)
 614                 vt->signal = 0xffff;
 615         else
 616                 vt->signal = 0x00;
 617
 618         vt->capability |=
 619                 V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_LANG1 |
 620                 V4L2_TUNER_CAP_LANG2 | V4L2_TUNER_CAP_SAP;
 621
 622         val = V4L2_TUNER_SUB_MONO;
 623         vt->rxsubchans = val;
 624         vt->audmode = V4L2_TUNER_MODE_STEREO;
 625         return 0;
 626 }
 627
 628 /* ----------------------------------------------------------------------- */
 629
 630 static const struct v4l2_subdev_core_ops au8522_core_ops = {
 631         .log_status = v4l2_ctrl_subdev_log_status,
 632         .reset = au8522_reset,
 633 #ifdef CONFIG_VIDEO_ADV_DEBUG
 634         .g_register = au8522_g_register,
 635         .s_register = au8522_s_register,
 636 #endif
 637 };
 638
 639 static const struct v4l2_subdev_tuner_ops au8522_tuner_ops = {
 640         .g_tuner = au8522_g_tuner,
 641 };
 642
 643 static const struct v4l2_subdev_audio_ops au8522_audio_ops = {
 644         .s_routing = au8522_s_audio_routing,
 645 };
 646
 647 static const struct v4l2_subdev_video_ops au8522_video_ops = {
 648         .s_routing = au8522_s_video_routing,
 649         .s_stream = au8522_s_stream,
 650 };
 651
 652 static const struct v4l2_subdev_ops au8522_ops = {
 653         .core = &au8522_core_ops,
 654         .tuner = &au8522_tuner_ops,
 655         .audio = &au8522_audio_ops,
 656         .video = &au8522_video_ops,
 657 };
 658
 659 static const struct v4l2_ctrl_ops au8522_ctrl_ops = {
 660         .s_ctrl = au8522_s_ctrl,
 661 };
 662
 663 /* ----------------------------------------------------------------------- */
 664
 665 static int au8522_probe(struct i2c_client *client,
 666                         const struct i2c_device_id *did)
 667 {
 668         struct au8522_state *state;
 669         struct v4l2_ctrl_handler *hdl;
 670         struct v4l2_subdev *sd;
 671         int instance;
 672         struct au8522_config *demod_config;
 673
 674         /* Check if the adapter supports the needed features */
 675         if (!i2c_check_functionality(client->adapter,
 676                                      I2C_FUNC_SMBUS_BYTE_DATA)) {
 677                 return -EIO;
 678         }
 679
 680         /* allocate memory for the internal state */
 681         instance = au8522_get_state(&state, client->adapter, client->addr);
 682         switch (instance) {
 683         case 0:
 684                 printk(KERN_ERR "au8522_decoder allocation failed\n");
 685                 return -EIO;
 686         case 1:
 687                 /* new demod instance */
 688                 printk(KERN_INFO "au8522_decoder creating new instance...\n");
 689                 break;
 690         default:
 691                 /* existing demod instance */
 692                 printk(KERN_INFO "au8522_decoder attach existing instance.\n");
 693                 break;
 694         }
 695
 696         demod_config = kzalloc(sizeof(struct au8522_config), GFP_KERNEL);
 697         if (demod_config == NULL) {
 698                 if (instance == 1)
 699                         kfree(state);
 700                 return -ENOMEM;
 701         }
 702         demod_config->demod_address = 0x8e >> 1;
 703
 704         state->config = demod_config;
 705         state->i2c = client->adapter;
 706
 707         sd = &state->sd;
 708         v4l2_i2c_subdev_init(sd, client, &au8522_ops);
 709
 710         hdl = &state->hdl;
 711         v4l2_ctrl_handler_init(hdl, 4);
 712         v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops,
 713                         V4L2_CID_BRIGHTNESS, 0, 255, 1, 109);
 714         v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops,
 715                         V4L2_CID_CONTRAST, 0, 255, 1,
 716                         AU8522_TVDEC_CONTRAST_REG00BH_CVBS);
 717         v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops,
 718                         V4L2_CID_SATURATION, 0, 255, 1, 128);
 719         v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops,
 720                         V4L2_CID_HUE, -32768, 32767, 1, 0);
 721         sd->ctrl_handler = hdl;
 722         if (hdl->error) {
 723                 int err = hdl->error;
 724
 725                 v4l2_ctrl_handler_free(hdl);
 726                 kfree(demod_config);
 727                 kfree(state);
 728                 return err;
 729         }
 730
 731         state->c = client;
 732         state->vid_input = AU8522_COMPOSITE_CH1;
 733         state->aud_input = AU8522_AUDIO_NONE;
 734         state->id = 8522;
 735         state->rev = 0;
 736
 737         /* Jam open the i2c gate to the tuner */
 738         au8522_writereg(state, 0x106, 1);
 739
 740         return 0;
 741 }
 742
 743 static int au8522_remove(struct i2c_client *client)
 744 {
 745         struct v4l2_subdev *sd = i2c_get_clientdata(client);
 746         v4l2_device_unregister_subdev(sd);
 747         v4l2_ctrl_handler_free(sd->ctrl_handler);
 748         au8522_release_state(to_state(sd));
 749         return 0;
 750 }
 751
 752 static const struct i2c_device_id au8522_id[] = {
 753         {"au8522", 0},
 754         {}
 755 };
 756
 757 MODULE_DEVICE_TABLE(i2c, au8522_id);
 758
 759 static struct i2c_driver au8522_driver = {
 760         .driver = {
 761                 .owner  = THIS_MODULE,
 762                 .name   = "au8522",
 763         },
 764         .probe          = au8522_probe,
 765         .remove         = au8522_remove,
 766         .id_table       = au8522_id,
 767 };
 768
 769 module_i2c_driver(au8522_driver);