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Linux 3.12.39
[linux/fpc-iii.git] / drivers / media / dvb-frontends / stb0899_algo.c
blob93596e0e640b2a084f65e591c7be6ab3c1107f81
1 /*
2 STB0899 Multistandard Frontend driver
3 Copyright (C) Manu Abraham (abraham.manu@gmail.com)
4
5 Copyright (C) ST Microelectronics
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22 #include "stb0899_drv.h"
23 #include "stb0899_priv.h"
24 #include "stb0899_reg.h"
25
26 static inline u32 stb0899_do_div(u64 n, u32 d)
27 {
28 /* wrap do_div() for ease of use */
29
30 do_div(n, d);
31 return n;
32 }
33
34 #if 0
35 /* These functions are currently unused */
36 /*
37 * stb0899_calc_srate
38 * Compute symbol rate
39 */
40 static u32 stb0899_calc_srate(u32 master_clk, u8 *sfr)
41 {
42 u64 tmp;
43
44 /* srate = (SFR * master_clk) >> 20 */
45
46 /* sfr is of size 20 bit, stored with an offset of 4 bit */
47 tmp = (((u32)sfr[0]) << 16) | (((u32)sfr[1]) << 8) | sfr[2];
48 tmp &= ~0xf;
49 tmp *= master_clk;
50 tmp >>= 24;
51
52 return tmp;
53 }
54
55 /*
56 * stb0899_get_srate
57 * Get the current symbol rate
58 */
59 static u32 stb0899_get_srate(struct stb0899_state *state)
60 {
61 struct stb0899_internal *internal = &state->internal;
62 u8 sfr[3];
63
64 stb0899_read_regs(state, STB0899_SFRH, sfr, 3);
65
66 return stb0899_calc_srate(internal->master_clk, sfr);
67 }
68 #endif
69
70 /*
71 * stb0899_set_srate
72 * Set symbol frequency
73 * MasterClock: master clock frequency (hz)
74 * SymbolRate: symbol rate (bauds)
75 * return symbol frequency
76 */
77 static u32 stb0899_set_srate(struct stb0899_state *state, u32 master_clk, u32 srate)
78 {
79 u32 tmp;
80 u8 sfr[3];
81
82 dprintk(state->verbose, FE_DEBUG, 1, "-->");
83 /*
84 * in order to have the maximum precision, the symbol rate entered into
85 * the chip is computed as the closest value of the "true value".
86 * In this purpose, the symbol rate value is rounded (1 is added on the bit
87 * below the LSB )
88 *
89 * srate = (SFR * master_clk) >> 20
90 * <=>
91 * SFR = srate << 20 / master_clk
92 *
93 * rounded:
94 * SFR = (srate << 21 + master_clk) / (2 * master_clk)
95 *
96 * stored as 20 bit number with an offset of 4 bit:
97 * sfr = SFR << 4;
98 */
99
100 tmp = stb0899_do_div((((u64)srate) << 21) + master_clk, 2 * master_clk);
101 tmp <<= 4;
102
103 sfr[0] = tmp >> 16;
104 sfr[1] = tmp >> 8;
105 sfr[2] = tmp;
106
107 stb0899_write_regs(state, STB0899_SFRH, sfr, 3);
108
109 return srate;
110 }
111
112 /*
113 * stb0899_calc_derot_time
114 * Compute the amount of time needed by the derotator to lock
115 * SymbolRate: Symbol rate
116 * return: derotator time constant (ms)
117 */
118 static long stb0899_calc_derot_time(long srate)
119 {
120 if (srate > 0)
121 return (100000 / (srate / 1000));
122 else
123 return 0;
124 }
125
126 /*
127 * stb0899_carr_width
128 * Compute the width of the carrier
129 * return: width of carrier (kHz or Mhz)
130 */
131 long stb0899_carr_width(struct stb0899_state *state)
132 {
133 struct stb0899_internal *internal = &state->internal;
134
135 return (internal->srate + (internal->srate * internal->rolloff) / 100);
136 }
137
138 /*
139 * stb0899_first_subrange
140 * Compute the first subrange of the search
141 */
142 static void stb0899_first_subrange(struct stb0899_state *state)
143 {
144 struct stb0899_internal *internal = &state->internal;
145 struct stb0899_params *params = &state->params;
146 struct stb0899_config *config = state->config;
147
148 int range = 0;
149 u32 bandwidth = 0;
150
151 if (config->tuner_get_bandwidth) {
152 stb0899_i2c_gate_ctrl(&state->frontend, 1);
153 config->tuner_get_bandwidth(&state->frontend, &bandwidth);
154 stb0899_i2c_gate_ctrl(&state->frontend, 0);
155 range = bandwidth - stb0899_carr_width(state) / 2;
156 }
157
158 if (range > 0)
159 internal->sub_range = min(internal->srch_range, range);
160 else
161 internal->sub_range = 0;
162
163 internal->freq = params->freq;
164 internal->tuner_offst = 0L;
165 internal->sub_dir = 1;
166 }
167
168 /*
169 * stb0899_check_tmg
170 * check for timing lock
171 * internal.Ttiming: time to wait for loop lock
172 */
173 static enum stb0899_status stb0899_check_tmg(struct stb0899_state *state)
174 {
175 struct stb0899_internal *internal = &state->internal;
176 int lock;
177 u8 reg;
178 s8 timing;
179
180 msleep(internal->t_derot);
181
182 stb0899_write_reg(state, STB0899_RTF, 0xf2);
183 reg = stb0899_read_reg(state, STB0899_TLIR);
184 lock = STB0899_GETFIELD(TLIR_TMG_LOCK_IND, reg);
185 timing = stb0899_read_reg(state, STB0899_RTF);
186
187 if (lock >= 42) {
188 if ((lock > 48) && (abs(timing) >= 110)) {
189 internal->status = ANALOGCARRIER;
190 dprintk(state->verbose, FE_DEBUG, 1, "-->ANALOG Carrier !");
191 } else {
192 internal->status = TIMINGOK;
193 dprintk(state->verbose, FE_DEBUG, 1, "------->TIMING OK !");
194 }
195 } else {
196 internal->status = NOTIMING;
197 dprintk(state->verbose, FE_DEBUG, 1, "-->NO TIMING !");
198 }
199 return internal->status;
200 }
201
202 /*
203 * stb0899_search_tmg
204 * perform a fs/2 zig-zag to find timing
205 */
206 static enum stb0899_status stb0899_search_tmg(struct stb0899_state *state)
207 {
208 struct stb0899_internal *internal = &state->internal;
209 struct stb0899_params *params = &state->params;
210
211 short int derot_step, derot_freq = 0, derot_limit, next_loop = 3;
212 int index = 0;
213 u8 cfr[2];
214
215 internal->status = NOTIMING;
216
217 /* timing loop computation & symbol rate optimisation */
218 derot_limit = (internal->sub_range / 2L) / internal->mclk;
219 derot_step = (params->srate / 2L) / internal->mclk;
220
221 while ((stb0899_check_tmg(state) != TIMINGOK) && next_loop) {
222 index++;
223 derot_freq += index * internal->direction * derot_step; /* next derot zig zag position */
224
225 if (abs(derot_freq) > derot_limit)
226 next_loop--;
227
228 if (next_loop) {
229 STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(internal->inversion * derot_freq));
230 STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(internal->inversion * derot_freq));
231 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */
232 }
233 internal->direction = -internal->direction; /* Change zigzag direction */
234 }
235
236 if (internal->status == TIMINGOK) {
237 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */
238 internal->derot_freq = internal->inversion * MAKEWORD16(cfr[0], cfr[1]);
239 dprintk(state->verbose, FE_DEBUG, 1, "------->TIMING OK ! Derot Freq = %d", internal->derot_freq);
240 }
241
242 return internal->status;
243 }
244
245 /*
246 * stb0899_check_carrier
247 * Check for carrier found
248 */
249 static enum stb0899_status stb0899_check_carrier(struct stb0899_state *state)
250 {
251 struct stb0899_internal *internal = &state->internal;
252 u8 reg;
253
254 msleep(internal->t_derot); /* wait for derotator ok */
255
256 reg = stb0899_read_reg(state, STB0899_CFD);
257 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
258 stb0899_write_reg(state, STB0899_CFD, reg);
259
260 reg = stb0899_read_reg(state, STB0899_DSTATUS);
261 dprintk(state->verbose, FE_DEBUG, 1, "--------------------> STB0899_DSTATUS=[0x%02x]", reg);
262 if (STB0899_GETFIELD(CARRIER_FOUND, reg)) {
263 internal->status = CARRIEROK;
264 dprintk(state->verbose, FE_DEBUG, 1, "-------------> CARRIEROK !");
265 } else {
266 internal->status = NOCARRIER;
267 dprintk(state->verbose, FE_DEBUG, 1, "-------------> NOCARRIER !");
268 }
269
270 return internal->status;
271 }
272
273 /*
274 * stb0899_search_carrier
275 * Search for a QPSK carrier with the derotator
276 */
277 static enum stb0899_status stb0899_search_carrier(struct stb0899_state *state)
278 {
279 struct stb0899_internal *internal = &state->internal;
280
281 short int derot_freq = 0, last_derot_freq = 0, derot_limit, next_loop = 3;
282 int index = 0;
283 u8 cfr[2];
284 u8 reg;
285
286 internal->status = NOCARRIER;
287 derot_limit = (internal->sub_range / 2L) / internal->mclk;
288 derot_freq = internal->derot_freq;
289
290 reg = stb0899_read_reg(state, STB0899_CFD);
291 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
292 stb0899_write_reg(state, STB0899_CFD, reg);
293
294 do {
295 dprintk(state->verbose, FE_DEBUG, 1, "Derot Freq=%d, mclk=%d", derot_freq, internal->mclk);
296 if (stb0899_check_carrier(state) == NOCARRIER) {
297 index++;
298 last_derot_freq = derot_freq;
299 derot_freq += index * internal->direction * internal->derot_step; /* next zig zag derotator position */
300
301 if(abs(derot_freq) > derot_limit)
302 next_loop--;
303
304 if (next_loop) {
305 reg = stb0899_read_reg(state, STB0899_CFD);
306 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
307 stb0899_write_reg(state, STB0899_CFD, reg);
308
309 STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(internal->inversion * derot_freq));
310 STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(internal->inversion * derot_freq));
311 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */
312 }
313 }
314
315 internal->direction = -internal->direction; /* Change zigzag direction */
316 } while ((internal->status != CARRIEROK) && next_loop);
317
318 if (internal->status == CARRIEROK) {
319 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */
320 internal->derot_freq = internal->inversion * MAKEWORD16(cfr[0], cfr[1]);
321 dprintk(state->verbose, FE_DEBUG, 1, "----> CARRIER OK !, Derot Freq=%d", internal->derot_freq);
322 } else {
323 internal->derot_freq = last_derot_freq;
324 }
325
326 return internal->status;
327 }
328
329 /*
330 * stb0899_check_data
331 * Check for data found
332 */
333 static enum stb0899_status stb0899_check_data(struct stb0899_state *state)
334 {
335 struct stb0899_internal *internal = &state->internal;
336 struct stb0899_params *params = &state->params;
337
338 int lock = 0, index = 0, dataTime = 500, loop;
339 u8 reg;
340
341 internal->status = NODATA;
342
343 /* RESET FEC */
344 reg = stb0899_read_reg(state, STB0899_TSTRES);
345 STB0899_SETFIELD_VAL(FRESACS, reg, 1);
346 stb0899_write_reg(state, STB0899_TSTRES, reg);
347 msleep(1);
348 reg = stb0899_read_reg(state, STB0899_TSTRES);
349 STB0899_SETFIELD_VAL(FRESACS, reg, 0);
350 stb0899_write_reg(state, STB0899_TSTRES, reg);
351
352 if (params->srate <= 2000000)
353 dataTime = 2000;
354 else if (params->srate <= 5000000)
355 dataTime = 1500;
356 else if (params->srate <= 15000000)
357 dataTime = 1000;
358 else
359 dataTime = 500;
360
361 /* clear previous failed END_LOOPVIT */
362 stb0899_read_reg(state, STB0899_VSTATUS);
363
364 stb0899_write_reg(state, STB0899_DSTATUS2, 0x00); /* force search loop */
365 while (1) {
366 /* WARNING! VIT LOCKED has to be tested before VIT_END_LOOOP */
367 reg = stb0899_read_reg(state, STB0899_VSTATUS);
368 lock = STB0899_GETFIELD(VSTATUS_LOCKEDVIT, reg);
369 loop = STB0899_GETFIELD(VSTATUS_END_LOOPVIT, reg);
370
371 if (lock || loop || (index > dataTime))
372 break;
373 index++;
374 }
375
376 if (lock) { /* DATA LOCK indicator */
377 internal->status = DATAOK;
378 dprintk(state->verbose, FE_DEBUG, 1, "-----------------> DATA OK !");
379 }
380
381 return internal->status;
382 }
383
384 /*
385 * stb0899_search_data
386 * Search for a QPSK carrier with the derotator
387 */
388 static enum stb0899_status stb0899_search_data(struct stb0899_state *state)
389 {
390 short int derot_freq, derot_step, derot_limit, next_loop = 3;
391 u8 cfr[2];
392 u8 reg;
393 int index = 1;
394
395 struct stb0899_internal *internal = &state->internal;
396 struct stb0899_params *params = &state->params;
397
398 derot_step = (params->srate / 4L) / internal->mclk;
399 derot_limit = (internal->sub_range / 2L) / internal->mclk;
400 derot_freq = internal->derot_freq;
401
402 do {
403 if ((internal->status != CARRIEROK) || (stb0899_check_data(state) != DATAOK)) {
404
405 derot_freq += index * internal->direction * derot_step; /* next zig zag derotator position */
406 if (abs(derot_freq) > derot_limit)
407 next_loop--;
408
409 if (next_loop) {
410 dprintk(state->verbose, FE_DEBUG, 1, "Derot freq=%d, mclk=%d", derot_freq, internal->mclk);
411 reg = stb0899_read_reg(state, STB0899_CFD);
412 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
413 stb0899_write_reg(state, STB0899_CFD, reg);
414
415 STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(internal->inversion * derot_freq));
416 STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(internal->inversion * derot_freq));
417 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */
418
419 stb0899_check_carrier(state);
420 index++;
421 }
422 }
423 internal->direction = -internal->direction; /* change zig zag direction */
424 } while ((internal->status != DATAOK) && next_loop);
425
426 if (internal->status == DATAOK) {
427 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */
428
429 /* store autodetected IQ swapping as default for DVB-S2 tuning */
430 reg = stb0899_read_reg(state, STB0899_IQSWAP);
431 if (STB0899_GETFIELD(SYM, reg))
432 internal->inversion = IQ_SWAP_ON;
433 else
434 internal->inversion = IQ_SWAP_OFF;
435
436 internal->derot_freq = internal->inversion * MAKEWORD16(cfr[0], cfr[1]);
437 dprintk(state->verbose, FE_DEBUG, 1, "------> DATAOK ! Derot Freq=%d", internal->derot_freq);
438 }
439
440 return internal->status;
441 }
442
443 /*
444 * stb0899_check_range
445 * check if the found frequency is in the correct range
446 */
447 static enum stb0899_status stb0899_check_range(struct stb0899_state *state)
448 {
449 struct stb0899_internal *internal = &state->internal;
450 struct stb0899_params *params = &state->params;
451
452 int range_offst, tp_freq;
453
454 range_offst = internal->srch_range / 2000;
455 tp_freq = internal->freq - (internal->derot_freq * internal->mclk) / 1000;
456
457 if ((tp_freq >= params->freq - range_offst) && (tp_freq <= params->freq + range_offst)) {
458 internal->status = RANGEOK;
459 dprintk(state->verbose, FE_DEBUG, 1, "----> RANGEOK !");
460 } else {
461 internal->status = OUTOFRANGE;
462 dprintk(state->verbose, FE_DEBUG, 1, "----> OUT OF RANGE !");
463 }
464
465 return internal->status;
466 }
467
468 /*
469 * NextSubRange
470 * Compute the next subrange of the search
471 */
472 static void next_sub_range(struct stb0899_state *state)
473 {
474 struct stb0899_internal *internal = &state->internal;
475 struct stb0899_params *params = &state->params;
476
477 long old_sub_range;
478
479 if (internal->sub_dir > 0) {
480 old_sub_range = internal->sub_range;
481 internal->sub_range = min((internal->srch_range / 2) -
482 (internal->tuner_offst + internal->sub_range / 2),
483 internal->sub_range);
484
485 if (internal->sub_range < 0)
486 internal->sub_range = 0;
487
488 internal->tuner_offst += (old_sub_range + internal->sub_range) / 2;
489 }
490
491 internal->freq = params->freq + (internal->sub_dir * internal->tuner_offst) / 1000;
492 internal->sub_dir = -internal->sub_dir;
493 }
494
495 /*
496 * stb0899_dvbs_algo
497 * Search for a signal, timing, carrier and data for a
498 * given frequency in a given range
499 */
500 enum stb0899_status stb0899_dvbs_algo(struct stb0899_state *state)
501 {
502 struct stb0899_params *params = &state->params;
503 struct stb0899_internal *internal = &state->internal;
504 struct stb0899_config *config = state->config;
505
506 u8 bclc, reg;
507 u8 cfr[2];
508 u8 eq_const[10];
509 s32 clnI = 3;
510 u32 bandwidth = 0;
511
512 /* BETA values rated @ 99MHz */
513 s32 betaTab[5][4] = {
514 /* 5 10 20 30MBps */
515 { 37, 34, 32, 31 }, /* QPSK 1/2 */
516 { 37, 35, 33, 31 }, /* QPSK 2/3 */
517 { 37, 35, 33, 31 }, /* QPSK 3/4 */
518 { 37, 36, 33, 32 }, /* QPSK 5/6 */
519 { 37, 36, 33, 32 } /* QPSK 7/8 */
520 };
521
522 internal->direction = 1;
523
524 stb0899_set_srate(state, internal->master_clk, params->srate);
525 /* Carrier loop optimization versus symbol rate for acquisition*/
526 if (params->srate <= 5000000) {
527 stb0899_write_reg(state, STB0899_ACLC, 0x89);
528 bclc = stb0899_read_reg(state, STB0899_BCLC);
529 STB0899_SETFIELD_VAL(BETA, bclc, 0x1c);
530 stb0899_write_reg(state, STB0899_BCLC, bclc);
531 clnI = 0;
532 } else if (params->srate <= 15000000) {
533 stb0899_write_reg(state, STB0899_ACLC, 0xc9);
534 bclc = stb0899_read_reg(state, STB0899_BCLC);
535 STB0899_SETFIELD_VAL(BETA, bclc, 0x22);
536 stb0899_write_reg(state, STB0899_BCLC, bclc);
537 clnI = 1;
538 } else if(params->srate <= 25000000) {
539 stb0899_write_reg(state, STB0899_ACLC, 0x89);
540 bclc = stb0899_read_reg(state, STB0899_BCLC);
541 STB0899_SETFIELD_VAL(BETA, bclc, 0x27);
542 stb0899_write_reg(state, STB0899_BCLC, bclc);
543 clnI = 2;
544 } else {
545 stb0899_write_reg(state, STB0899_ACLC, 0xc8);
546 bclc = stb0899_read_reg(state, STB0899_BCLC);
547 STB0899_SETFIELD_VAL(BETA, bclc, 0x29);
548 stb0899_write_reg(state, STB0899_BCLC, bclc);
549 clnI = 3;
550 }
551
552 dprintk(state->verbose, FE_DEBUG, 1, "Set the timing loop to acquisition");
553 /* Set the timing loop to acquisition */
554 stb0899_write_reg(state, STB0899_RTC, 0x46);
555 stb0899_write_reg(state, STB0899_CFD, 0xee);
556
557 /* !! WARNING !!
558 * Do not read any status variables while acquisition,
559 * If any needed, read before the acquisition starts
560 * querying status while acquiring causes the
561 * acquisition to go bad and hence no locks.
562 */
563 dprintk(state->verbose, FE_DEBUG, 1, "Derot Percent=%d Srate=%d mclk=%d",
564 internal->derot_percent, params->srate, internal->mclk);
565
566 /* Initial calculations */
567 internal->derot_step = internal->derot_percent * (params->srate / 1000L) / internal->mclk; /* DerotStep/1000 * Fsymbol */
568 internal->t_derot = stb0899_calc_derot_time(params->srate);
569 internal->t_data = 500;
570
571 dprintk(state->verbose, FE_DEBUG, 1, "RESET stream merger");
572 /* RESET Stream merger */
573 reg = stb0899_read_reg(state, STB0899_TSTRES);
574 STB0899_SETFIELD_VAL(FRESRS, reg, 1);
575 stb0899_write_reg(state, STB0899_TSTRES, reg);
576
577 /*
578 * Set KDIVIDER to an intermediate value between
579 * 1/2 and 7/8 for acquisition
580 */
581 reg = stb0899_read_reg(state, STB0899_DEMAPVIT);
582 STB0899_SETFIELD_VAL(DEMAPVIT_KDIVIDER, reg, 60);
583 stb0899_write_reg(state, STB0899_DEMAPVIT, reg);
584
585 stb0899_write_reg(state, STB0899_EQON, 0x01); /* Equalizer OFF while acquiring */
586 stb0899_write_reg(state, STB0899_VITSYNC, 0x19);
587
588 stb0899_first_subrange(state);
589 do {
590 /* Initialisations */
591 cfr[0] = cfr[1] = 0;
592 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* RESET derotator frequency */
593
594 stb0899_write_reg(state, STB0899_RTF, 0);
595 reg = stb0899_read_reg(state, STB0899_CFD);
596 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
597 stb0899_write_reg(state, STB0899_CFD, reg);
598
599 internal->derot_freq = 0;
600 internal->status = NOAGC1;
601
602 /* enable tuner I/O */
603 stb0899_i2c_gate_ctrl(&state->frontend, 1);
604
605 /* Move tuner to frequency */
606 dprintk(state->verbose, FE_DEBUG, 1, "Tuner set frequency");
607 if (state->config->tuner_set_frequency)
608 state->config->tuner_set_frequency(&state->frontend, internal->freq);
609
610 if (state->config->tuner_get_frequency)
611 state->config->tuner_get_frequency(&state->frontend, &internal->freq);
612
613 msleep(internal->t_agc1 + internal->t_agc2 + internal->t_derot); /* AGC1, AGC2 and timing loop */
614 dprintk(state->verbose, FE_DEBUG, 1, "current derot freq=%d", internal->derot_freq);
615 internal->status = AGC1OK;
616
617 /* There is signal in the band */
618 if (config->tuner_get_bandwidth)
619 config->tuner_get_bandwidth(&state->frontend, &bandwidth);
620
621 /* disable tuner I/O */
622 stb0899_i2c_gate_ctrl(&state->frontend, 0);
623
624 if (params->srate <= bandwidth / 2)
625 stb0899_search_tmg(state); /* For low rates (SCPC) */
626 else
627 stb0899_check_tmg(state); /* For high rates (MCPC) */
628
629 if (internal->status == TIMINGOK) {
630 dprintk(state->verbose, FE_DEBUG, 1,
631 "TIMING OK ! Derot freq=%d, mclk=%d",
632 internal->derot_freq, internal->mclk);
633
634 if (stb0899_search_carrier(state) == CARRIEROK) { /* Search for carrier */
635 dprintk(state->verbose, FE_DEBUG, 1,
636 "CARRIER OK ! Derot freq=%d, mclk=%d",
637 internal->derot_freq, internal->mclk);
638
639 if (stb0899_search_data(state) == DATAOK) { /* Check for data */
640 dprintk(state->verbose, FE_DEBUG, 1,
641 "DATA OK ! Derot freq=%d, mclk=%d",
642 internal->derot_freq, internal->mclk);
643
644 if (stb0899_check_range(state) == RANGEOK) {
645 dprintk(state->verbose, FE_DEBUG, 1,
646 "RANGE OK ! derot freq=%d, mclk=%d",
647 internal->derot_freq, internal->mclk);
648
649 internal->freq = params->freq - ((internal->derot_freq * internal->mclk) / 1000);
650 reg = stb0899_read_reg(state, STB0899_PLPARM);
651 internal->fecrate = STB0899_GETFIELD(VITCURPUN, reg);
652 dprintk(state->verbose, FE_DEBUG, 1,
653 "freq=%d, internal resultant freq=%d",
654 params->freq, internal->freq);
655
656 dprintk(state->verbose, FE_DEBUG, 1,
657 "internal puncture rate=%d",
658 internal->fecrate);
659 }
660 }
661 }
662 }
663 if (internal->status != RANGEOK)
664 next_sub_range(state);
665
666 } while (internal->sub_range && internal->status != RANGEOK);
667
668 /* Set the timing loop to tracking */
669 stb0899_write_reg(state, STB0899_RTC, 0x33);
670 stb0899_write_reg(state, STB0899_CFD, 0xf7);
671 /* if locked and range ok, set Kdiv */
672 if (internal->status == RANGEOK) {
673 dprintk(state->verbose, FE_DEBUG, 1, "Locked & Range OK !");
674 stb0899_write_reg(state, STB0899_EQON, 0x41); /* Equalizer OFF while acquiring */
675 stb0899_write_reg(state, STB0899_VITSYNC, 0x39); /* SN to b'11 for acquisition */
676
677 /*
678 * Carrier loop optimization versus
679 * symbol Rate/Puncture Rate for Tracking
680 */
681 reg = stb0899_read_reg(state, STB0899_BCLC);
682 switch (internal->fecrate) {
683 case STB0899_FEC_1_2: /* 13 */
684 stb0899_write_reg(state, STB0899_DEMAPVIT, 0x1a);
685 STB0899_SETFIELD_VAL(BETA, reg, betaTab[0][clnI]);
686 stb0899_write_reg(state, STB0899_BCLC, reg);
687 break;
688 case STB0899_FEC_2_3: /* 18 */
689 stb0899_write_reg(state, STB0899_DEMAPVIT, 44);
690 STB0899_SETFIELD_VAL(BETA, reg, betaTab[1][clnI]);
691 stb0899_write_reg(state, STB0899_BCLC, reg);
692 break;
693 case STB0899_FEC_3_4: /* 21 */
694 stb0899_write_reg(state, STB0899_DEMAPVIT, 60);
695 STB0899_SETFIELD_VAL(BETA, reg, betaTab[2][clnI]);
696 stb0899_write_reg(state, STB0899_BCLC, reg);
697 break;
698 case STB0899_FEC_5_6: /* 24 */
699 stb0899_write_reg(state, STB0899_DEMAPVIT, 75);
700 STB0899_SETFIELD_VAL(BETA, reg, betaTab[3][clnI]);
701 stb0899_write_reg(state, STB0899_BCLC, reg);
702 break;
703 case STB0899_FEC_6_7: /* 25 */
704 stb0899_write_reg(state, STB0899_DEMAPVIT, 88);
705 stb0899_write_reg(state, STB0899_ACLC, 0x88);
706 stb0899_write_reg(state, STB0899_BCLC, 0x9a);
707 break;
708 case STB0899_FEC_7_8: /* 26 */
709 stb0899_write_reg(state, STB0899_DEMAPVIT, 94);
710 STB0899_SETFIELD_VAL(BETA, reg, betaTab[4][clnI]);
711 stb0899_write_reg(state, STB0899_BCLC, reg);
712 break;
713 default:
714 dprintk(state->verbose, FE_DEBUG, 1, "Unsupported Puncture Rate");
715 break;
716 }
717 /* release stream merger RESET */
718 reg = stb0899_read_reg(state, STB0899_TSTRES);
719 STB0899_SETFIELD_VAL(FRESRS, reg, 0);
720 stb0899_write_reg(state, STB0899_TSTRES, reg);
721
722 /* disable carrier detector */
723 reg = stb0899_read_reg(state, STB0899_CFD);
724 STB0899_SETFIELD_VAL(CFD_ON, reg, 0);
725 stb0899_write_reg(state, STB0899_CFD, reg);
726
727 stb0899_read_regs(state, STB0899_EQUAI1, eq_const, 10);
728 }
729
730 return internal->status;
731 }
732
733 /*
734 * stb0899_dvbs2_config_uwp
735 * Configure UWP state machine
736 */
737 static void stb0899_dvbs2_config_uwp(struct stb0899_state *state)
738 {
739 struct stb0899_internal *internal = &state->internal;
740 struct stb0899_config *config = state->config;
741 u32 uwp1, uwp2, uwp3, reg;
742
743 uwp1 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL1);
744 uwp2 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL2);
745 uwp3 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL3);
746
747 STB0899_SETFIELD_VAL(UWP_ESN0_AVE, uwp1, config->esno_ave);
748 STB0899_SETFIELD_VAL(UWP_ESN0_QUANT, uwp1, config->esno_quant);
749 STB0899_SETFIELD_VAL(UWP_TH_SOF, uwp1, config->uwp_threshold_sof);
750
751 STB0899_SETFIELD_VAL(FE_COARSE_TRK, uwp2, internal->av_frame_coarse);
752 STB0899_SETFIELD_VAL(FE_FINE_TRK, uwp2, internal->av_frame_fine);
753 STB0899_SETFIELD_VAL(UWP_MISS_TH, uwp2, config->miss_threshold);
754
755 STB0899_SETFIELD_VAL(UWP_TH_ACQ, uwp3, config->uwp_threshold_acq);
756 STB0899_SETFIELD_VAL(UWP_TH_TRACK, uwp3, config->uwp_threshold_track);
757
758 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL1, STB0899_OFF0_UWP_CNTRL1, uwp1);
759 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL2, STB0899_OFF0_UWP_CNTRL2, uwp2);
760 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL3, STB0899_OFF0_UWP_CNTRL3, uwp3);
761
762 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, SOF_SRCH_TO);
763 STB0899_SETFIELD_VAL(SOF_SEARCH_TIMEOUT, reg, config->sof_search_timeout);
764 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_SOF_SRCH_TO, STB0899_OFF0_SOF_SRCH_TO, reg);
765 }
766
767 /*
768 * stb0899_dvbs2_config_csm_auto
769 * Set CSM to AUTO mode
770 */
771 static void stb0899_dvbs2_config_csm_auto(struct stb0899_state *state)
772 {
773 u32 reg;
774
775 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
776 STB0899_SETFIELD_VAL(CSM_AUTO_PARAM, reg, 1);
777 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, reg);
778 }
779
780 static long Log2Int(int number)
781 {
782 int i;
783
784 i = 0;
785 while ((1 << i) <= abs(number))
786 i++;
787
788 if (number == 0)
789 i = 1;
790
791 return i - 1;
792 }
793
794 /*
795 * stb0899_dvbs2_calc_srate
796 * compute BTR_NOM_FREQ for the symbol rate
797 */
798 static u32 stb0899_dvbs2_calc_srate(struct stb0899_state *state)
799 {
800 struct stb0899_internal *internal = &state->internal;
801 struct stb0899_config *config = state->config;
802
803 u32 dec_ratio, dec_rate, decim, remain, intval, btr_nom_freq;
804 u32 master_clk, srate;
805
806 dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
807 dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
808 dec_rate = Log2Int(dec_ratio);
809 decim = 1 << dec_rate;
810 master_clk = internal->master_clk / 1000;
811 srate = internal->srate / 1000;
812
813 if (decim <= 4) {
814 intval = (decim * (1 << (config->btr_nco_bits - 1))) / master_clk;
815 remain = (decim * (1 << (config->btr_nco_bits - 1))) % master_clk;
816 } else {
817 intval = (1 << (config->btr_nco_bits - 1)) / (master_clk / 100) * decim / 100;
818 remain = (decim * (1 << (config->btr_nco_bits - 1))) % master_clk;
819 }
820 btr_nom_freq = (intval * srate) + ((remain * srate) / master_clk);
821
822 return btr_nom_freq;
823 }
824
825 /*
826 * stb0899_dvbs2_calc_dev
827 * compute the correction to be applied to symbol rate
828 */
829 static u32 stb0899_dvbs2_calc_dev(struct stb0899_state *state)
830 {
831 struct stb0899_internal *internal = &state->internal;
832 u32 dec_ratio, correction, master_clk, srate;
833
834 dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
835 dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
836
837 master_clk = internal->master_clk / 1000; /* for integer Caculation*/
838 srate = internal->srate / 1000; /* for integer Caculation*/
839 correction = (512 * master_clk) / (2 * dec_ratio * srate);
840
841 return correction;
842 }
843
844 /*
845 * stb0899_dvbs2_set_srate
846 * Set DVBS2 symbol rate
847 */
848 static void stb0899_dvbs2_set_srate(struct stb0899_state *state)
849 {
850 struct stb0899_internal *internal = &state->internal;
851
852 u32 dec_ratio, dec_rate, win_sel, decim, f_sym, btr_nom_freq;
853 u32 correction, freq_adj, band_lim, decim_cntrl, reg;
854 u8 anti_alias;
855
856 /*set decimation to 1*/
857 dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
858 dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
859 dec_rate = Log2Int(dec_ratio);
860
861 win_sel = 0;
862 if (dec_rate >= 5)
863 win_sel = dec_rate - 4;
864
865 decim = (1 << dec_rate);
866 /* (FSamp/Fsymbol *100) for integer Caculation */
867 f_sym = internal->master_clk / ((decim * internal->srate) / 1000);
868
869 if (f_sym <= 2250) /* don't band limit signal going into btr block*/
870 band_lim = 1;
871 else
872 band_lim = 0; /* band limit signal going into btr block*/
873
874 decim_cntrl = ((win_sel << 3) & 0x18) + ((band_lim << 5) & 0x20) + (dec_rate & 0x7);
875 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DECIM_CNTRL, STB0899_OFF0_DECIM_CNTRL, decim_cntrl);
876
877 if (f_sym <= 3450)
878 anti_alias = 0;
879 else if (f_sym <= 4250)
880 anti_alias = 1;
881 else
882 anti_alias = 2;
883
884 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ANTI_ALIAS_SEL, STB0899_OFF0_ANTI_ALIAS_SEL, anti_alias);
885 btr_nom_freq = stb0899_dvbs2_calc_srate(state);
886 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_NOM_FREQ, STB0899_OFF0_BTR_NOM_FREQ, btr_nom_freq);
887
888 correction = stb0899_dvbs2_calc_dev(state);
889 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_CNTRL);
890 STB0899_SETFIELD_VAL(BTR_FREQ_CORR, reg, correction);
891 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg);
892
893 /* scale UWP+CSM frequency to sample rate*/
894 freq_adj = internal->srate / (internal->master_clk / 4096);
895 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_FREQ_ADJ_SCALE, STB0899_OFF0_FREQ_ADJ_SCALE, freq_adj);
896 }
897
898 /*
899 * stb0899_dvbs2_set_btr_loopbw
900 * set bit timing loop bandwidth as a percentage of the symbol rate
901 */
902 static void stb0899_dvbs2_set_btr_loopbw(struct stb0899_state *state)
903 {
904 struct stb0899_internal *internal = &state->internal;
905 struct stb0899_config *config = state->config;
906
907 u32 sym_peak = 23, zeta = 707, loopbw_percent = 60;
908 s32 dec_ratio, dec_rate, k_btr1_rshft, k_btr1, k_btr0_rshft;
909 s32 k_btr0, k_btr2_rshft, k_direct_shift, k_indirect_shift;
910 u32 decim, K, wn, k_direct, k_indirect;
911 u32 reg;
912
913 dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
914 dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
915 dec_rate = Log2Int(dec_ratio);
916 decim = (1 << dec_rate);
917
918 sym_peak *= 576000;
919 K = (1 << config->btr_nco_bits) / (internal->master_clk / 1000);
920 K *= (internal->srate / 1000000) * decim; /*k=k 10^-8*/
921
922 if (K != 0) {
923 K = sym_peak / K;
924 wn = (4 * zeta * zeta) + 1000000;
925 wn = (2 * (loopbw_percent * 1000) * 40 * zeta) /wn; /*wn =wn 10^-8*/
926
927 k_indirect = (wn * wn) / K;
928 k_indirect = k_indirect; /*kindirect = kindirect 10^-6*/
929 k_direct = (2 * wn * zeta) / K; /*kDirect = kDirect 10^-2*/
930 k_direct *= 100;
931
932 k_direct_shift = Log2Int(k_direct) - Log2Int(10000) - 2;
933 k_btr1_rshft = (-1 * k_direct_shift) + config->btr_gain_shift_offset;
934 k_btr1 = k_direct / (1 << k_direct_shift);
935 k_btr1 /= 10000;
936
937 k_indirect_shift = Log2Int(k_indirect + 15) - 20 /*- 2*/;
938 k_btr0_rshft = (-1 * k_indirect_shift) + config->btr_gain_shift_offset;
939 k_btr0 = k_indirect * (1 << (-k_indirect_shift));
940 k_btr0 /= 1000000;
941
942 k_btr2_rshft = 0;
943 if (k_btr0_rshft > 15) {
944 k_btr2_rshft = k_btr0_rshft - 15;
945 k_btr0_rshft = 15;
946 }
947 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_LOOP_GAIN);
948 STB0899_SETFIELD_VAL(KBTR0_RSHFT, reg, k_btr0_rshft);
949 STB0899_SETFIELD_VAL(KBTR0, reg, k_btr0);
950 STB0899_SETFIELD_VAL(KBTR1_RSHFT, reg, k_btr1_rshft);
951 STB0899_SETFIELD_VAL(KBTR1, reg, k_btr1);
952 STB0899_SETFIELD_VAL(KBTR2_RSHFT, reg, k_btr2_rshft);
953 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, reg);
954 } else
955 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, 0xc4c4f);
956 }
957
958 /*
959 * stb0899_dvbs2_set_carr_freq
960 * set nominal frequency for carrier search
961 */
962 static void stb0899_dvbs2_set_carr_freq(struct stb0899_state *state, s32 carr_freq, u32 master_clk)
963 {
964 struct stb0899_config *config = state->config;
965 s32 crl_nom_freq;
966 u32 reg;
967
968 crl_nom_freq = (1 << config->crl_nco_bits) / master_clk;
969 crl_nom_freq *= carr_freq;
970 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
971 STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, crl_nom_freq);
972 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
973 }
974
975 /*
976 * stb0899_dvbs2_init_calc
977 * Initialize DVBS2 UWP, CSM, carrier and timing loops
978 */
979 static void stb0899_dvbs2_init_calc(struct stb0899_state *state)
980 {
981 struct stb0899_internal *internal = &state->internal;
982 s32 steps, step_size;
983 u32 range, reg;
984
985 /* config uwp and csm */
986 stb0899_dvbs2_config_uwp(state);
987 stb0899_dvbs2_config_csm_auto(state);
988
989 /* initialize BTR */
990 stb0899_dvbs2_set_srate(state);
991 stb0899_dvbs2_set_btr_loopbw(state);
992
993 if (internal->srate / 1000000 >= 15)
994 step_size = (1 << 17) / 5;
995 else if (internal->srate / 1000000 >= 10)
996 step_size = (1 << 17) / 7;
997 else if (internal->srate / 1000000 >= 5)
998 step_size = (1 << 17) / 10;
999 else
1000 step_size = (1 << 17) / 4;
1001
1002 range = internal->srch_range / 1000000;
1003 steps = (10 * range * (1 << 17)) / (step_size * (internal->srate / 1000000));
1004 steps = (steps + 6) / 10;
1005 steps = (steps == 0) ? 1 : steps;
1006 if (steps % 2 == 0)
1007 stb0899_dvbs2_set_carr_freq(state, internal->center_freq -
1008 (internal->step_size * (internal->srate / 20000000)),
1009 (internal->master_clk) / 1000000);
1010 else
1011 stb0899_dvbs2_set_carr_freq(state, internal->center_freq, (internal->master_clk) / 1000000);
1012
1013 /*Set Carrier Search params (zigzag, num steps and freq step size*/
1014 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, ACQ_CNTRL2);
1015 STB0899_SETFIELD_VAL(ZIGZAG, reg, 1);
1016 STB0899_SETFIELD_VAL(NUM_STEPS, reg, steps);
1017 STB0899_SETFIELD_VAL(FREQ_STEPSIZE, reg, step_size);
1018 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ACQ_CNTRL2, STB0899_OFF0_ACQ_CNTRL2, reg);
1019 }
1020
1021 /*
1022 * stb0899_dvbs2_btr_init
1023 * initialize the timing loop
1024 */
1025 static void stb0899_dvbs2_btr_init(struct stb0899_state *state)
1026 {
1027 u32 reg;
1028
1029 /* set enable BTR loopback */
1030 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_CNTRL);
1031 STB0899_SETFIELD_VAL(INTRP_PHS_SENSE, reg, 1);
1032 STB0899_SETFIELD_VAL(BTR_ERR_ENA, reg, 1);
1033 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg);
1034
1035 /* fix btr freq accum at 0 */
1036 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_FREQ_INIT, STB0899_OFF0_BTR_FREQ_INIT, 0x10000000);
1037 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_FREQ_INIT, STB0899_OFF0_BTR_FREQ_INIT, 0x00000000);
1038
1039 /* fix btr freq accum at 0 */
1040 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_PHS_INIT, STB0899_OFF0_BTR_PHS_INIT, 0x10000000);
1041 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_PHS_INIT, STB0899_OFF0_BTR_PHS_INIT, 0x00000000);
1042 }
1043
1044 /*
1045 * stb0899_dvbs2_reacquire
1046 * trigger a DVB-S2 acquisition
1047 */
1048 static void stb0899_dvbs2_reacquire(struct stb0899_state *state)
1049 {
1050 u32 reg = 0;
1051
1052 /* demod soft reset */
1053 STB0899_SETFIELD_VAL(DVBS2_RESET, reg, 1);
1054 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg);
1055
1056 /*Reset Timing Loop */
1057 stb0899_dvbs2_btr_init(state);
1058
1059 /* reset Carrier loop */
1060 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_FREQ_INIT, STB0899_OFF0_CRL_FREQ_INIT, (1 << 30));
1061 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_FREQ_INIT, STB0899_OFF0_CRL_FREQ_INIT, 0);
1062 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_LOOP_GAIN, STB0899_OFF0_CRL_LOOP_GAIN, 0);
1063 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_PHS_INIT, STB0899_OFF0_CRL_PHS_INIT, (1 << 30));
1064 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_PHS_INIT, STB0899_OFF0_CRL_PHS_INIT, 0);
1065
1066 /*release demod soft reset */
1067 reg = 0;
1068 STB0899_SETFIELD_VAL(DVBS2_RESET, reg, 0);
1069 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg);
1070
1071 /* start acquisition process */
1072 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ACQUIRE_TRIG, STB0899_OFF0_ACQUIRE_TRIG, 1);
1073 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_LOCK_LOST, STB0899_OFF0_LOCK_LOST, 0);
1074
1075 /* equalizer Init */
1076 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQUALIZER_INIT, STB0899_OFF0_EQUALIZER_INIT, 1);
1077
1078 /*Start equilizer */
1079 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQUALIZER_INIT, STB0899_OFF0_EQUALIZER_INIT, 0);
1080
1081 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1082 STB0899_SETFIELD_VAL(EQ_SHIFT, reg, 0);
1083 STB0899_SETFIELD_VAL(EQ_DISABLE_UPDATE, reg, 0);
1084 STB0899_SETFIELD_VAL(EQ_DELAY, reg, 0x05);
1085 STB0899_SETFIELD_VAL(EQ_ADAPT_MODE, reg, 0x01);
1086 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1087
1088 /* RESET Packet delineator */
1089 stb0899_write_reg(state, STB0899_PDELCTRL, 0x4a);
1090 }
1091
1092 /*
1093 * stb0899_dvbs2_get_dmd_status
1094 * get DVB-S2 Demod LOCK status
1095 */
1096 static enum stb0899_status stb0899_dvbs2_get_dmd_status(struct stb0899_state *state, int timeout)
1097 {
1098 int time = -10, lock = 0, uwp, csm;
1099 u32 reg;
1100
1101 do {
1102 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STATUS);
1103 dprintk(state->verbose, FE_DEBUG, 1, "DMD_STATUS=[0x%02x]", reg);
1104 if (STB0899_GETFIELD(IF_AGC_LOCK, reg))
1105 dprintk(state->verbose, FE_DEBUG, 1, "------------->IF AGC LOCKED !");
1106 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STAT2);
1107 dprintk(state->verbose, FE_DEBUG, 1, "----------->DMD STAT2=[0x%02x]", reg);
1108 uwp = STB0899_GETFIELD(UWP_LOCK, reg);
1109 csm = STB0899_GETFIELD(CSM_LOCK, reg);
1110 if (uwp && csm)
1111 lock = 1;
1112
1113 time += 10;
1114 msleep(10);
1115
1116 } while ((!lock) && (time <= timeout));
1117
1118 if (lock) {
1119 dprintk(state->verbose, FE_DEBUG, 1, "----------------> DVB-S2 LOCK !");
1120 return DVBS2_DEMOD_LOCK;
1121 } else {
1122 return DVBS2_DEMOD_NOLOCK;
1123 }
1124 }
1125
1126 /*
1127 * stb0899_dvbs2_get_data_lock
1128 * get FEC status
1129 */
1130 static int stb0899_dvbs2_get_data_lock(struct stb0899_state *state, int timeout)
1131 {
1132 int time = 0, lock = 0;
1133 u8 reg;
1134
1135 while ((!lock) && (time < timeout)) {
1136 reg = stb0899_read_reg(state, STB0899_CFGPDELSTATUS1);
1137 dprintk(state->verbose, FE_DEBUG, 1, "---------> CFGPDELSTATUS=[0x%02x]", reg);
1138 lock = STB0899_GETFIELD(CFGPDELSTATUS_LOCK, reg);
1139 time++;
1140 }
1141
1142 return lock;
1143 }
1144
1145 /*
1146 * stb0899_dvbs2_get_fec_status
1147 * get DVB-S2 FEC LOCK status
1148 */
1149 static enum stb0899_status stb0899_dvbs2_get_fec_status(struct stb0899_state *state, int timeout)
1150 {
1151 int time = 0, Locked;
1152
1153 do {
1154 Locked = stb0899_dvbs2_get_data_lock(state, 1);
1155 time++;
1156 msleep(1);
1157
1158 } while ((!Locked) && (time < timeout));
1159
1160 if (Locked) {
1161 dprintk(state->verbose, FE_DEBUG, 1, "---------->DVB-S2 FEC LOCK !");
1162 return DVBS2_FEC_LOCK;
1163 } else {
1164 return DVBS2_FEC_NOLOCK;
1165 }
1166 }
1167
1168
1169 /*
1170 * stb0899_dvbs2_init_csm
1171 * set parameters for manual mode
1172 */
1173 static void stb0899_dvbs2_init_csm(struct stb0899_state *state, int pilots, enum stb0899_modcod modcod)
1174 {
1175 struct stb0899_internal *internal = &state->internal;
1176
1177 s32 dvt_tbl = 1, two_pass = 0, agc_gain = 6, agc_shift = 0, loop_shift = 0, phs_diff_thr = 0x80;
1178 s32 gamma_acq, gamma_rho_acq, gamma_trk, gamma_rho_trk, lock_count_thr;
1179 u32 csm1, csm2, csm3, csm4;
1180
1181 if (((internal->master_clk / internal->srate) <= 4) && (modcod <= 11) && (pilots == 1)) {
1182 switch (modcod) {
1183 case STB0899_QPSK_12:
1184 gamma_acq = 25;
1185 gamma_rho_acq = 2700;
1186 gamma_trk = 12;
1187 gamma_rho_trk = 180;
1188 lock_count_thr = 8;
1189 break;
1190 case STB0899_QPSK_35:
1191 gamma_acq = 38;
1192 gamma_rho_acq = 7182;
1193 gamma_trk = 14;
1194 gamma_rho_trk = 308;
1195 lock_count_thr = 8;
1196 break;
1197 case STB0899_QPSK_23:
1198 gamma_acq = 42;
1199 gamma_rho_acq = 9408;
1200 gamma_trk = 17;
1201 gamma_rho_trk = 476;
1202 lock_count_thr = 8;
1203 break;
1204 case STB0899_QPSK_34:
1205 gamma_acq = 53;
1206 gamma_rho_acq = 16642;
1207 gamma_trk = 19;
1208 gamma_rho_trk = 646;
1209 lock_count_thr = 8;
1210 break;
1211 case STB0899_QPSK_45:
1212 gamma_acq = 53;
1213 gamma_rho_acq = 17119;
1214 gamma_trk = 22;
1215 gamma_rho_trk = 880;
1216 lock_count_thr = 8;
1217 break;
1218 case STB0899_QPSK_56:
1219 gamma_acq = 55;
1220 gamma_rho_acq = 19250;
1221 gamma_trk = 23;
1222 gamma_rho_trk = 989;
1223 lock_count_thr = 8;
1224 break;
1225 case STB0899_QPSK_89:
1226 gamma_acq = 60;
1227 gamma_rho_acq = 24240;
1228 gamma_trk = 24;
1229 gamma_rho_trk = 1176;
1230 lock_count_thr = 8;
1231 break;
1232 case STB0899_QPSK_910:
1233 gamma_acq = 66;
1234 gamma_rho_acq = 29634;
1235 gamma_trk = 24;
1236 gamma_rho_trk = 1176;
1237 lock_count_thr = 8;
1238 break;
1239 default:
1240 gamma_acq = 66;
1241 gamma_rho_acq = 29634;
1242 gamma_trk = 24;
1243 gamma_rho_trk = 1176;
1244 lock_count_thr = 8;
1245 break;
1246 }
1247
1248 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1249 STB0899_SETFIELD_VAL(CSM_AUTO_PARAM, csm1, 0);
1250 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1251
1252 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1253 csm2 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL2);
1254 csm3 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL3);
1255 csm4 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL4);
1256
1257 STB0899_SETFIELD_VAL(CSM_DVT_TABLE, csm1, dvt_tbl);
1258 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, two_pass);
1259 STB0899_SETFIELD_VAL(CSM_AGC_GAIN, csm1, agc_gain);
1260 STB0899_SETFIELD_VAL(CSM_AGC_SHIFT, csm1, agc_shift);
1261 STB0899_SETFIELD_VAL(FE_LOOP_SHIFT, csm1, loop_shift);
1262 STB0899_SETFIELD_VAL(CSM_GAMMA_ACQ, csm2, gamma_acq);
1263 STB0899_SETFIELD_VAL(CSM_GAMMA_RHOACQ, csm2, gamma_rho_acq);
1264 STB0899_SETFIELD_VAL(CSM_GAMMA_TRACK, csm3, gamma_trk);
1265 STB0899_SETFIELD_VAL(CSM_GAMMA_RHOTRACK, csm3, gamma_rho_trk);
1266 STB0899_SETFIELD_VAL(CSM_LOCKCOUNT_THRESH, csm4, lock_count_thr);
1267 STB0899_SETFIELD_VAL(CSM_PHASEDIFF_THRESH, csm4, phs_diff_thr);
1268
1269 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1270 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL2, STB0899_OFF0_CSM_CNTRL2, csm2);
1271 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL3, STB0899_OFF0_CSM_CNTRL3, csm3);
1272 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL4, STB0899_OFF0_CSM_CNTRL4, csm4);
1273 }
1274 }
1275
1276 /*
1277 * stb0899_dvbs2_get_srate
1278 * get DVB-S2 Symbol Rate
1279 */
1280 static u32 stb0899_dvbs2_get_srate(struct stb0899_state *state)
1281 {
1282 struct stb0899_internal *internal = &state->internal;
1283 struct stb0899_config *config = state->config;
1284
1285 u32 bTrNomFreq, srate, decimRate, intval1, intval2, reg;
1286 int div1, div2, rem1, rem2;
1287
1288 div1 = config->btr_nco_bits / 2;
1289 div2 = config->btr_nco_bits - div1 - 1;
1290
1291 bTrNomFreq = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_NOM_FREQ);
1292
1293 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DECIM_CNTRL);
1294 decimRate = STB0899_GETFIELD(DECIM_RATE, reg);
1295 decimRate = (1 << decimRate);
1296
1297 intval1 = internal->master_clk / (1 << div1);
1298 intval2 = bTrNomFreq / (1 << div2);
1299
1300 rem1 = internal->master_clk % (1 << div1);
1301 rem2 = bTrNomFreq % (1 << div2);
1302 /* only for integer calculation */
1303 srate = (intval1 * intval2) + ((intval1 * rem2) / (1 << div2)) + ((intval2 * rem1) / (1 << div1));
1304 srate /= decimRate; /*symbrate = (btrnomfreq_register_val*MasterClock)/2^(27+decim_rate_field) */
1305
1306 return srate;
1307 }
1308
1309 /*
1310 * stb0899_dvbs2_algo
1311 * Search for signal, timing, carrier and data for a given
1312 * frequency in a given range
1313 */
1314 enum stb0899_status stb0899_dvbs2_algo(struct stb0899_state *state)
1315 {
1316 struct stb0899_internal *internal = &state->internal;
1317 enum stb0899_modcod modcod;
1318
1319 s32 offsetfreq, searchTime, FecLockTime, pilots, iqSpectrum;
1320 int i = 0;
1321 u32 reg, csm1;
1322
1323 if (internal->srate <= 2000000) {
1324 searchTime = 5000; /* 5000 ms max time to lock UWP and CSM, SYMB <= 2Mbs */
1325 FecLockTime = 350; /* 350 ms max time to lock FEC, SYMB <= 2Mbs */
1326 } else if (internal->srate <= 5000000) {
1327 searchTime = 2500; /* 2500 ms max time to lock UWP and CSM, 2Mbs < SYMB <= 5Mbs */
1328 FecLockTime = 170; /* 170 ms max time to lock FEC, 2Mbs< SYMB <= 5Mbs */
1329 } else if (internal->srate <= 10000000) {
1330 searchTime = 1500; /* 1500 ms max time to lock UWP and CSM, 5Mbs <SYMB <= 10Mbs */
1331 FecLockTime = 80; /* 80 ms max time to lock FEC, 5Mbs< SYMB <= 10Mbs */
1332 } else if (internal->srate <= 15000000) {
1333 searchTime = 500; /* 500 ms max time to lock UWP and CSM, 10Mbs <SYMB <= 15Mbs */
1334 FecLockTime = 50; /* 50 ms max time to lock FEC, 10Mbs< SYMB <= 15Mbs */
1335 } else if (internal->srate <= 20000000) {
1336 searchTime = 300; /* 300 ms max time to lock UWP and CSM, 15Mbs < SYMB <= 20Mbs */
1337 FecLockTime = 30; /* 50 ms max time to lock FEC, 15Mbs< SYMB <= 20Mbs */
1338 } else if (internal->srate <= 25000000) {
1339 searchTime = 250; /* 250 ms max time to lock UWP and CSM, 20 Mbs < SYMB <= 25Mbs */
1340 FecLockTime = 25; /* 25 ms max time to lock FEC, 20Mbs< SYMB <= 25Mbs */
1341 } else {
1342 searchTime = 150; /* 150 ms max time to lock UWP and CSM, SYMB > 25Mbs */
1343 FecLockTime = 20; /* 20 ms max time to lock FEC, 20Mbs< SYMB <= 25Mbs */
1344 }
1345
1346 /* Maintain Stream Merger in reset during acquisition */
1347 reg = stb0899_read_reg(state, STB0899_TSTRES);
1348 STB0899_SETFIELD_VAL(FRESRS, reg, 1);
1349 stb0899_write_reg(state, STB0899_TSTRES, reg);
1350
1351 /* enable tuner I/O */
1352 stb0899_i2c_gate_ctrl(&state->frontend, 1);
1353
1354 /* Move tuner to frequency */
1355 if (state->config->tuner_set_frequency)
1356 state->config->tuner_set_frequency(&state->frontend, internal->freq);
1357 if (state->config->tuner_get_frequency)
1358 state->config->tuner_get_frequency(&state->frontend, &internal->freq);
1359
1360 /* disable tuner I/O */
1361 stb0899_i2c_gate_ctrl(&state->frontend, 0);
1362
1363 /* Set IF AGC to acquisition */
1364 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL);
1365 STB0899_SETFIELD_VAL(IF_LOOP_GAIN, reg, 4);
1366 STB0899_SETFIELD_VAL(IF_AGC_REF, reg, 32);
1367 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg);
1368
1369 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL2);
1370 STB0899_SETFIELD_VAL(IF_AGC_DUMP_PER, reg, 0);
1371 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg);
1372
1373 /* Initialisation */
1374 stb0899_dvbs2_init_calc(state);
1375
1376 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1377 switch (internal->inversion) {
1378 case IQ_SWAP_OFF:
1379 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 0);
1380 break;
1381 case IQ_SWAP_ON:
1382 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 1);
1383 break;
1384 }
1385 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg);
1386 stb0899_dvbs2_reacquire(state);
1387
1388 /* Wait for demod lock (UWP and CSM) */
1389 internal->status = stb0899_dvbs2_get_dmd_status(state, searchTime);
1390
1391 if (internal->status == DVBS2_DEMOD_LOCK) {
1392 dprintk(state->verbose, FE_DEBUG, 1, "------------> DVB-S2 DEMOD LOCK !");
1393 i = 0;
1394 /* Demod Locked, check FEC status */
1395 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1396
1397 /*If false lock (UWP and CSM Locked but no FEC) try 3 time max*/
1398 while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
1399 /* Read the frequency offset*/
1400 offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
1401
1402 /* Set the Nominal frequency to the found frequency offset for the next reacquire*/
1403 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
1404 STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, offsetfreq);
1405 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
1406 stb0899_dvbs2_reacquire(state);
1407 internal->status = stb0899_dvbs2_get_fec_status(state, searchTime);
1408 i++;
1409 }
1410 }
1411
1412 if (internal->status != DVBS2_FEC_LOCK) {
1413 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1414 iqSpectrum = STB0899_GETFIELD(SPECTRUM_INVERT, reg);
1415 /* IQ Spectrum Inversion */
1416 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, !iqSpectrum);
1417 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg);
1418 /* start acquistion process */
1419 stb0899_dvbs2_reacquire(state);
1420
1421 /* Wait for demod lock (UWP and CSM) */
1422 internal->status = stb0899_dvbs2_get_dmd_status(state, searchTime);
1423 if (internal->status == DVBS2_DEMOD_LOCK) {
1424 i = 0;
1425 /* Demod Locked, check FEC */
1426 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1427 /*try thrice for false locks, (UWP and CSM Locked but no FEC) */
1428 while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
1429 /* Read the frequency offset*/
1430 offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
1431
1432 /* Set the Nominal frequency to the found frequency offset for the next reacquire*/
1433 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
1434 STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, offsetfreq);
1435 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
1436
1437 stb0899_dvbs2_reacquire(state);
1438 internal->status = stb0899_dvbs2_get_fec_status(state, searchTime);
1439 i++;
1440 }
1441 }
1442 /*
1443 if (pParams->DVBS2State == FE_DVBS2_FEC_LOCKED)
1444 pParams->IQLocked = !iqSpectrum;
1445 */
1446 }
1447 if (internal->status == DVBS2_FEC_LOCK) {
1448 dprintk(state->verbose, FE_DEBUG, 1, "----------------> DVB-S2 FEC Lock !");
1449 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2);
1450 modcod = STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 2;
1451 pilots = STB0899_GETFIELD(UWP_DECODE_MOD, reg) & 0x01;
1452
1453 if ((((10 * internal->master_clk) / (internal->srate / 10)) <= 410) &&
1454 (INRANGE(STB0899_QPSK_23, modcod, STB0899_QPSK_910)) &&
1455 (pilots == 1)) {
1456
1457 stb0899_dvbs2_init_csm(state, pilots, modcod);
1458 /* Wait for UWP,CSM and data LOCK 20ms max */
1459 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1460
1461 i = 0;
1462 while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
1463 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1464 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, 1);
1465 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1466 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1467 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, 0);
1468 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1469
1470 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1471 i++;
1472 }
1473 }
1474
1475 if ((((10 * internal->master_clk) / (internal->srate / 10)) <= 410) &&
1476 (INRANGE(STB0899_QPSK_12, modcod, STB0899_QPSK_35)) &&
1477 (pilots == 1)) {
1478
1479 /* Equalizer Disable update */
1480 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1481 STB0899_SETFIELD_VAL(EQ_DISABLE_UPDATE, reg, 1);
1482 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1483 }
1484
1485 /* slow down the Equalizer once locked */
1486 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1487 STB0899_SETFIELD_VAL(EQ_SHIFT, reg, 0x02);
1488 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1489
1490 /* Store signal parameters */
1491 offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
1492
1493 /* sign extend 30 bit value before using it in calculations */
1494 if (offsetfreq & (1 << 29))
1495 offsetfreq |= -1 << 30;
1496
1497 offsetfreq = offsetfreq / ((1 << 30) / 1000);
1498 offsetfreq *= (internal->master_clk / 1000000);
1499
1500 /* store current inversion for next run */
1501 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1502 if (STB0899_GETFIELD(SPECTRUM_INVERT, reg))
1503 internal->inversion = IQ_SWAP_ON;
1504 else
1505 internal->inversion = IQ_SWAP_OFF;
1506
1507 internal->freq = internal->freq + offsetfreq;
1508 internal->srate = stb0899_dvbs2_get_srate(state);
1509
1510 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2);
1511 internal->modcod = STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 2;
1512 internal->pilots = STB0899_GETFIELD(UWP_DECODE_MOD, reg) & 0x01;
1513 internal->frame_length = (STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 1) & 0x01;
1514
1515 /* Set IF AGC to tracking */
1516 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL);
1517 STB0899_SETFIELD_VAL(IF_LOOP_GAIN, reg, 3);
1518
1519 /* if QPSK 1/2,QPSK 3/5 or QPSK 2/3 set IF AGC reference to 16 otherwise 32*/
1520 if (INRANGE(STB0899_QPSK_12, internal->modcod, STB0899_QPSK_23))
1521 STB0899_SETFIELD_VAL(IF_AGC_REF, reg, 16);
1522
1523 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg);
1524
1525 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL2);
1526 STB0899_SETFIELD_VAL(IF_AGC_DUMP_PER, reg, 7);
1527 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg);
1528 }
1529
1530 /* Release Stream Merger Reset */
1531 reg = stb0899_read_reg(state, STB0899_TSTRES);
1532 STB0899_SETFIELD_VAL(FRESRS, reg, 0);
1533 stb0899_write_reg(state, STB0899_TSTRES, reg);
1534
1535 return internal->status;
1536 }
Linux with added FPC-III support