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Linux 3.12.39
[linux/fpc-iii.git] / drivers / mtd / devices / m25p80.c
blobf111f04f51973bdc7f0361bb08d43bbdfdde2ce8
1 /*
2 * MTD SPI driver for ST M25Pxx (and similar) serial flash chips
3 *
4 * Author: Mike Lavender, mike@steroidmicros.com
5 *
6 * Copyright (c) 2005, Intec Automation Inc.
7 *
8 * Some parts are based on lart.c by Abraham Van Der Merwe
9 *
10 * Cleaned up and generalized based on mtd_dataflash.c
11 *
12 * This code is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 */
17
18 #include <linux/init.h>
19 #include <linux/err.h>
20 #include <linux/errno.h>
21 #include <linux/module.h>
22 #include <linux/device.h>
23 #include <linux/interrupt.h>
24 #include <linux/mutex.h>
25 #include <linux/math64.h>
26 #include <linux/slab.h>
27 #include <linux/sched.h>
28 #include <linux/mod_devicetable.h>
29
30 #include <linux/mtd/cfi.h>
31 #include <linux/mtd/mtd.h>
32 #include <linux/mtd/partitions.h>
33 #include <linux/of_platform.h>
34
35 #include <linux/spi/spi.h>
36 #include <linux/spi/flash.h>
37
38 /* Flash opcodes. */
39 #define OPCODE_WREN 0x06 /* Write enable */
40 #define OPCODE_RDSR 0x05 /* Read status register */
41 #define OPCODE_WRSR 0x01 /* Write status register 1 byte */
42 #define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */
43 #define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */
44 #define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */
45 #define OPCODE_BE_4K 0x20 /* Erase 4KiB block */
46 #define OPCODE_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
47 #define OPCODE_BE_32K 0x52 /* Erase 32KiB block */
48 #define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */
49 #define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */
50 #define OPCODE_RDID 0x9f /* Read JEDEC ID */
51
52 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
53 #define OPCODE_NORM_READ_4B 0x13 /* Read data bytes (low frequency) */
54 #define OPCODE_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */
55 #define OPCODE_PP_4B 0x12 /* Page program (up to 256 bytes) */
56 #define OPCODE_SE_4B 0xdc /* Sector erase (usually 64KiB) */
57
58 /* Used for SST flashes only. */
59 #define OPCODE_BP 0x02 /* Byte program */
60 #define OPCODE_WRDI 0x04 /* Write disable */
61 #define OPCODE_AAI_WP 0xad /* Auto address increment word program */
62
63 /* Used for Macronix and Winbond flashes. */
64 #define OPCODE_EN4B 0xb7 /* Enter 4-byte mode */
65 #define OPCODE_EX4B 0xe9 /* Exit 4-byte mode */
66
67 /* Used for Spansion flashes only. */
68 #define OPCODE_BRWR 0x17 /* Bank register write */
69
70 /* Status Register bits. */
71 #define SR_WIP 1 /* Write in progress */
72 #define SR_WEL 2 /* Write enable latch */
73 /* meaning of other SR_* bits may differ between vendors */
74 #define SR_BP0 4 /* Block protect 0 */
75 #define SR_BP1 8 /* Block protect 1 */
76 #define SR_BP2 0x10 /* Block protect 2 */
77 #define SR_SRWD 0x80 /* SR write protect */
78
79 /* Define max times to check status register before we give up. */
80 #define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */
81 #define MAX_CMD_SIZE 6
82
83 #define JEDEC_MFR(_jedec_id) ((_jedec_id) >> 16)
84
85 /****************************************************************************/
86
87 struct m25p {
88 struct spi_device *spi;
89 struct mutex lock;
90 struct mtd_info mtd;
91 u16 page_size;
92 u16 addr_width;
93 u8 erase_opcode;
94 u8 read_opcode;
95 u8 program_opcode;
96 u8 *command;
97 bool fast_read;
98 };
99
100 static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
101 {
102 return container_of(mtd, struct m25p, mtd);
103 }
104
105 /****************************************************************************/
106
107 /*
108 * Internal helper functions
109 */
110
111 /*
112 * Read the status register, returning its value in the location
113 * Return the status register value.
114 * Returns negative if error occurred.
115 */
116 static int read_sr(struct m25p *flash)
117 {
118 ssize_t retval;
119 u8 code = OPCODE_RDSR;
120 u8 val;
121
122 retval = spi_write_then_read(flash->spi, &code, 1, &val, 1);
123
124 if (retval < 0) {
125 dev_err(&flash->spi->dev, "error %d reading SR\n",
126 (int) retval);
127 return retval;
128 }
129
130 return val;
131 }
132
133 /*
134 * Write status register 1 byte
135 * Returns negative if error occurred.
136 */
137 static int write_sr(struct m25p *flash, u8 val)
138 {
139 flash->command[0] = OPCODE_WRSR;
140 flash->command[1] = val;
141
142 return spi_write(flash->spi, flash->command, 2);
143 }
144
145 /*
146 * Set write enable latch with Write Enable command.
147 * Returns negative if error occurred.
148 */
149 static inline int write_enable(struct m25p *flash)
150 {
151 u8 code = OPCODE_WREN;
152
153 return spi_write_then_read(flash->spi, &code, 1, NULL, 0);
154 }
155
156 /*
157 * Send write disble instruction to the chip.
158 */
159 static inline int write_disable(struct m25p *flash)
160 {
161 u8 code = OPCODE_WRDI;
162
163 return spi_write_then_read(flash->spi, &code, 1, NULL, 0);
164 }
165
166 /*
167 * Enable/disable 4-byte addressing mode.
168 */
169 static inline int set_4byte(struct m25p *flash, u32 jedec_id, int enable)
170 {
171 int status;
172 bool need_wren = false;
173
174 switch (JEDEC_MFR(jedec_id)) {
175 case CFI_MFR_ST: /* Micron, actually */
176 /* Some Micron need WREN command; all will accept it */
177 need_wren = true;
178 case CFI_MFR_MACRONIX:
179 case 0xEF /* winbond */:
180 if (need_wren)
181 write_enable(flash);
182
183 flash->command[0] = enable ? OPCODE_EN4B : OPCODE_EX4B;
184 status = spi_write(flash->spi, flash->command, 1);
185
186 if (need_wren)
187 write_disable(flash);
188
189 return status;
190 default:
191 /* Spansion style */
192 flash->command[0] = OPCODE_BRWR;
193 flash->command[1] = enable << 7;
194 return spi_write(flash->spi, flash->command, 2);
195 }
196 }
197
198 /*
199 * Service routine to read status register until ready, or timeout occurs.
200 * Returns non-zero if error.
201 */
202 static int wait_till_ready(struct m25p *flash)
203 {
204 unsigned long deadline;
205 int sr;
206
207 deadline = jiffies + MAX_READY_WAIT_JIFFIES;
208
209 do {
210 if ((sr = read_sr(flash)) < 0)
211 break;
212 else if (!(sr & SR_WIP))
213 return 0;
214
215 cond_resched();
216
217 } while (!time_after_eq(jiffies, deadline));
218
219 return 1;
220 }
221
222 /*
223 * Erase the whole flash memory
224 *
225 * Returns 0 if successful, non-zero otherwise.
226 */
227 static int erase_chip(struct m25p *flash)
228 {
229 pr_debug("%s: %s %lldKiB\n", dev_name(&flash->spi->dev), __func__,
230 (long long)(flash->mtd.size >> 10));
231
232 /* Wait until finished previous write command. */
233 if (wait_till_ready(flash))
234 return 1;
235
236 /* Send write enable, then erase commands. */
237 write_enable(flash);
238
239 /* Set up command buffer. */
240 flash->command[0] = OPCODE_CHIP_ERASE;
241
242 spi_write(flash->spi, flash->command, 1);
243
244 return 0;
245 }
246
247 static void m25p_addr2cmd(struct m25p *flash, unsigned int addr, u8 *cmd)
248 {
249 /* opcode is in cmd[0] */
250 cmd[1] = addr >> (flash->addr_width * 8 - 8);
251 cmd[2] = addr >> (flash->addr_width * 8 - 16);
252 cmd[3] = addr >> (flash->addr_width * 8 - 24);
253 cmd[4] = addr >> (flash->addr_width * 8 - 32);
254 }
255
256 static int m25p_cmdsz(struct m25p *flash)
257 {
258 return 1 + flash->addr_width;
259 }
260
261 /*
262 * Erase one sector of flash memory at offset ``offset'' which is any
263 * address within the sector which should be erased.
264 *
265 * Returns 0 if successful, non-zero otherwise.
266 */
267 static int erase_sector(struct m25p *flash, u32 offset)
268 {
269 pr_debug("%s: %s %dKiB at 0x%08x\n", dev_name(&flash->spi->dev),
270 __func__, flash->mtd.erasesize / 1024, offset);
271
272 /* Wait until finished previous write command. */
273 if (wait_till_ready(flash))
274 return 1;
275
276 /* Send write enable, then erase commands. */
277 write_enable(flash);
278
279 /* Set up command buffer. */
280 flash->command[0] = flash->erase_opcode;
281 m25p_addr2cmd(flash, offset, flash->command);
282
283 spi_write(flash->spi, flash->command, m25p_cmdsz(flash));
284
285 return 0;
286 }
287
288 /****************************************************************************/
289
290 /*
291 * MTD implementation
292 */
293
294 /*
295 * Erase an address range on the flash chip. The address range may extend
296 * one or more erase sectors. Return an error is there is a problem erasing.
297 */
298 static int m25p80_erase(struct mtd_info *mtd, struct erase_info *instr)
299 {
300 struct m25p *flash = mtd_to_m25p(mtd);
301 u32 addr,len;
302 uint32_t rem;
303
304 pr_debug("%s: %s at 0x%llx, len %lld\n", dev_name(&flash->spi->dev),
305 __func__, (long long)instr->addr,
306 (long long)instr->len);
307
308 div_u64_rem(instr->len, mtd->erasesize, &rem);
309 if (rem)
310 return -EINVAL;
311
312 addr = instr->addr;
313 len = instr->len;
314
315 mutex_lock(&flash->lock);
316
317 /* whole-chip erase? */
318 if (len == flash->mtd.size) {
319 if (erase_chip(flash)) {
320 instr->state = MTD_ERASE_FAILED;
321 mutex_unlock(&flash->lock);
322 return -EIO;
323 }
324
325 /* REVISIT in some cases we could speed up erasing large regions
326 * by using OPCODE_SE instead of OPCODE_BE_4K. We may have set up
327 * to use "small sector erase", but that's not always optimal.
328 */
329
330 /* "sector"-at-a-time erase */
331 } else {
332 while (len) {
333 if (erase_sector(flash, addr)) {
334 instr->state = MTD_ERASE_FAILED;
335 mutex_unlock(&flash->lock);
336 return -EIO;
337 }
338
339 addr += mtd->erasesize;
340 len -= mtd->erasesize;
341 }
342 }
343
344 mutex_unlock(&flash->lock);
345
346 instr->state = MTD_ERASE_DONE;
347 mtd_erase_callback(instr);
348
349 return 0;
350 }
351
352 /*
353 * Read an address range from the flash chip. The address range
354 * may be any size provided it is within the physical boundaries.
355 */
356 static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
357 size_t *retlen, u_char *buf)
358 {
359 struct m25p *flash = mtd_to_m25p(mtd);
360 struct spi_transfer t[2];
361 struct spi_message m;
362 uint8_t opcode;
363
364 pr_debug("%s: %s from 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
365 __func__, (u32)from, len);
366
367 spi_message_init(&m);
368 memset(t, 0, (sizeof t));
369
370 /* NOTE:
371 * OPCODE_FAST_READ (if available) is faster.
372 * Should add 1 byte DUMMY_BYTE.
373 */
374 t[0].tx_buf = flash->command;
375 t[0].len = m25p_cmdsz(flash) + (flash->fast_read ? 1 : 0);
376 spi_message_add_tail(&t[0], &m);
377
378 t[1].rx_buf = buf;
379 t[1].len = len;
380 spi_message_add_tail(&t[1], &m);
381
382 mutex_lock(&flash->lock);
383
384 /* Wait till previous write/erase is done. */
385 if (wait_till_ready(flash)) {
386 /* REVISIT status return?? */
387 mutex_unlock(&flash->lock);
388 return 1;
389 }
390
391 /* FIXME switch to OPCODE_FAST_READ. It's required for higher
392 * clocks; and at this writing, every chip this driver handles
393 * supports that opcode.
394 */
395
396 /* Set up the write data buffer. */
397 opcode = flash->read_opcode;
398 flash->command[0] = opcode;
399 m25p_addr2cmd(flash, from, flash->command);
400
401 spi_sync(flash->spi, &m);
402
403 *retlen = m.actual_length - m25p_cmdsz(flash) -
404 (flash->fast_read ? 1 : 0);
405
406 mutex_unlock(&flash->lock);
407
408 return 0;
409 }
410
411 /*
412 * Write an address range to the flash chip. Data must be written in
413 * FLASH_PAGESIZE chunks. The address range may be any size provided
414 * it is within the physical boundaries.
415 */
416 static int m25p80_write(struct mtd_info *mtd, loff_t to, size_t len,
417 size_t *retlen, const u_char *buf)
418 {
419 struct m25p *flash = mtd_to_m25p(mtd);
420 u32 page_offset, page_size;
421 struct spi_transfer t[2];
422 struct spi_message m;
423
424 pr_debug("%s: %s to 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
425 __func__, (u32)to, len);
426
427 spi_message_init(&m);
428 memset(t, 0, (sizeof t));
429
430 t[0].tx_buf = flash->command;
431 t[0].len = m25p_cmdsz(flash);
432 spi_message_add_tail(&t[0], &m);
433
434 t[1].tx_buf = buf;
435 spi_message_add_tail(&t[1], &m);
436
437 mutex_lock(&flash->lock);
438
439 /* Wait until finished previous write command. */
440 if (wait_till_ready(flash)) {
441 mutex_unlock(&flash->lock);
442 return 1;
443 }
444
445 write_enable(flash);
446
447 /* Set up the opcode in the write buffer. */
448 flash->command[0] = flash->program_opcode;
449 m25p_addr2cmd(flash, to, flash->command);
450
451 page_offset = to & (flash->page_size - 1);
452
453 /* do all the bytes fit onto one page? */
454 if (page_offset + len <= flash->page_size) {
455 t[1].len = len;
456
457 spi_sync(flash->spi, &m);
458
459 *retlen = m.actual_length - m25p_cmdsz(flash);
460 } else {
461 u32 i;
462
463 /* the size of data remaining on the first page */
464 page_size = flash->page_size - page_offset;
465
466 t[1].len = page_size;
467 spi_sync(flash->spi, &m);
468
469 *retlen = m.actual_length - m25p_cmdsz(flash);
470
471 /* write everything in flash->page_size chunks */
472 for (i = page_size; i < len; i += page_size) {
473 page_size = len - i;
474 if (page_size > flash->page_size)
475 page_size = flash->page_size;
476
477 /* write the next page to flash */
478 m25p_addr2cmd(flash, to + i, flash->command);
479
480 t[1].tx_buf = buf + i;
481 t[1].len = page_size;
482
483 wait_till_ready(flash);
484
485 write_enable(flash);
486
487 spi_sync(flash->spi, &m);
488
489 *retlen += m.actual_length - m25p_cmdsz(flash);
490 }
491 }
492
493 mutex_unlock(&flash->lock);
494
495 return 0;
496 }
497
498 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
499 size_t *retlen, const u_char *buf)
500 {
501 struct m25p *flash = mtd_to_m25p(mtd);
502 struct spi_transfer t[2];
503 struct spi_message m;
504 size_t actual;
505 int cmd_sz, ret;
506
507 pr_debug("%s: %s to 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
508 __func__, (u32)to, len);
509
510 spi_message_init(&m);
511 memset(t, 0, (sizeof t));
512
513 t[0].tx_buf = flash->command;
514 t[0].len = m25p_cmdsz(flash);
515 spi_message_add_tail(&t[0], &m);
516
517 t[1].tx_buf = buf;
518 spi_message_add_tail(&t[1], &m);
519
520 mutex_lock(&flash->lock);
521
522 /* Wait until finished previous write command. */
523 ret = wait_till_ready(flash);
524 if (ret)
525 goto time_out;
526
527 write_enable(flash);
528
529 actual = to % 2;
530 /* Start write from odd address. */
531 if (actual) {
532 flash->command[0] = OPCODE_BP;
533 m25p_addr2cmd(flash, to, flash->command);
534
535 /* write one byte. */
536 t[1].len = 1;
537 spi_sync(flash->spi, &m);
538 ret = wait_till_ready(flash);
539 if (ret)
540 goto time_out;
541 *retlen += m.actual_length - m25p_cmdsz(flash);
542 }
543 to += actual;
544
545 flash->command[0] = OPCODE_AAI_WP;
546 m25p_addr2cmd(flash, to, flash->command);
547
548 /* Write out most of the data here. */
549 cmd_sz = m25p_cmdsz(flash);
550 for (; actual < len - 1; actual += 2) {
551 t[0].len = cmd_sz;
552 /* write two bytes. */
553 t[1].len = 2;
554 t[1].tx_buf = buf + actual;
555
556 spi_sync(flash->spi, &m);
557 ret = wait_till_ready(flash);
558 if (ret)
559 goto time_out;
560 *retlen += m.actual_length - cmd_sz;
561 cmd_sz = 1;
562 to += 2;
563 }
564 write_disable(flash);
565 ret = wait_till_ready(flash);
566 if (ret)
567 goto time_out;
568
569 /* Write out trailing byte if it exists. */
570 if (actual != len) {
571 write_enable(flash);
572 flash->command[0] = OPCODE_BP;
573 m25p_addr2cmd(flash, to, flash->command);
574 t[0].len = m25p_cmdsz(flash);
575 t[1].len = 1;
576 t[1].tx_buf = buf + actual;
577
578 spi_sync(flash->spi, &m);
579 ret = wait_till_ready(flash);
580 if (ret)
581 goto time_out;
582 *retlen += m.actual_length - m25p_cmdsz(flash);
583 write_disable(flash);
584 }
585
586 time_out:
587 mutex_unlock(&flash->lock);
588 return ret;
589 }
590
591 static int m25p80_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
592 {
593 struct m25p *flash = mtd_to_m25p(mtd);
594 uint32_t offset = ofs;
595 uint8_t status_old, status_new;
596 int res = 0;
597
598 mutex_lock(&flash->lock);
599 /* Wait until finished previous command */
600 if (wait_till_ready(flash)) {
601 res = 1;
602 goto err;
603 }
604
605 status_old = read_sr(flash);
606
607 if (offset < flash->mtd.size-(flash->mtd.size/2))
608 status_new = status_old | SR_BP2 | SR_BP1 | SR_BP0;
609 else if (offset < flash->mtd.size-(flash->mtd.size/4))
610 status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
611 else if (offset < flash->mtd.size-(flash->mtd.size/8))
612 status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
613 else if (offset < flash->mtd.size-(flash->mtd.size/16))
614 status_new = (status_old & ~(SR_BP0|SR_BP1)) | SR_BP2;
615 else if (offset < flash->mtd.size-(flash->mtd.size/32))
616 status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
617 else if (offset < flash->mtd.size-(flash->mtd.size/64))
618 status_new = (status_old & ~(SR_BP2|SR_BP0)) | SR_BP1;
619 else
620 status_new = (status_old & ~(SR_BP2|SR_BP1)) | SR_BP0;
621
622 /* Only modify protection if it will not unlock other areas */
623 if ((status_new&(SR_BP2|SR_BP1|SR_BP0)) >
624 (status_old&(SR_BP2|SR_BP1|SR_BP0))) {
625 write_enable(flash);
626 if (write_sr(flash, status_new) < 0) {
627 res = 1;
628 goto err;
629 }
630 }
631
632 err: mutex_unlock(&flash->lock);
633 return res;
634 }
635
636 static int m25p80_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
637 {
638 struct m25p *flash = mtd_to_m25p(mtd);
639 uint32_t offset = ofs;
640 uint8_t status_old, status_new;
641 int res = 0;
642
643 mutex_lock(&flash->lock);
644 /* Wait until finished previous command */
645 if (wait_till_ready(flash)) {
646 res = 1;
647 goto err;
648 }
649
650 status_old = read_sr(flash);
651
652 if (offset+len > flash->mtd.size-(flash->mtd.size/64))
653 status_new = status_old & ~(SR_BP2|SR_BP1|SR_BP0);
654 else if (offset+len > flash->mtd.size-(flash->mtd.size/32))
655 status_new = (status_old & ~(SR_BP2|SR_BP1)) | SR_BP0;
656 else if (offset+len > flash->mtd.size-(flash->mtd.size/16))
657 status_new = (status_old & ~(SR_BP2|SR_BP0)) | SR_BP1;
658 else if (offset+len > flash->mtd.size-(flash->mtd.size/8))
659 status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
660 else if (offset+len > flash->mtd.size-(flash->mtd.size/4))
661 status_new = (status_old & ~(SR_BP0|SR_BP1)) | SR_BP2;
662 else if (offset+len > flash->mtd.size-(flash->mtd.size/2))
663 status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
664 else
665 status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
666
667 /* Only modify protection if it will not lock other areas */
668 if ((status_new&(SR_BP2|SR_BP1|SR_BP0)) <
669 (status_old&(SR_BP2|SR_BP1|SR_BP0))) {
670 write_enable(flash);
671 if (write_sr(flash, status_new) < 0) {
672 res = 1;
673 goto err;
674 }
675 }
676
677 err: mutex_unlock(&flash->lock);
678 return res;
679 }
680
681 /****************************************************************************/
682
683 /*
684 * SPI device driver setup and teardown
685 */
686
687 struct flash_info {
688 /* JEDEC id zero means "no ID" (most older chips); otherwise it has
689 * a high byte of zero plus three data bytes: the manufacturer id,
690 * then a two byte device id.
691 */
692 u32 jedec_id;
693 u16 ext_id;
694
695 /* The size listed here is what works with OPCODE_SE, which isn't
696 * necessarily called a "sector" by the vendor.
697 */
698 unsigned sector_size;
699 u16 n_sectors;
700
701 u16 page_size;
702 u16 addr_width;
703
704 u16 flags;
705 #define SECT_4K 0x01 /* OPCODE_BE_4K works uniformly */
706 #define M25P_NO_ERASE 0x02 /* No erase command needed */
707 #define SST_WRITE 0x04 /* use SST byte programming */
708 #define M25P_NO_FR 0x08 /* Can't do fastread */
709 #define SECT_4K_PMC 0x10 /* OPCODE_BE_4K_PMC works uniformly */
710 };
711
712 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
713 ((kernel_ulong_t)&(struct flash_info) { \
714 .jedec_id = (_jedec_id), \
715 .ext_id = (_ext_id), \
716 .sector_size = (_sector_size), \
717 .n_sectors = (_n_sectors), \
718 .page_size = 256, \
719 .flags = (_flags), \
720 })
721
722 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
723 ((kernel_ulong_t)&(struct flash_info) { \
724 .sector_size = (_sector_size), \
725 .n_sectors = (_n_sectors), \
726 .page_size = (_page_size), \
727 .addr_width = (_addr_width), \
728 .flags = (_flags), \
729 })
730
731 /* NOTE: double check command sets and memory organization when you add
732 * more flash chips. This current list focusses on newer chips, which
733 * have been converging on command sets which including JEDEC ID.
734 */
735 static const struct spi_device_id m25p_ids[] = {
736 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
737 { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
738 { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
739
740 { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
741 { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
742 { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
743
744 { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
745 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
746 { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
747 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
748
749 { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
750
751 /* EON -- en25xxx */
752 { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
753 { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
754 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
755 { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
756 { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
757 { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
758
759 /* Everspin */
760 { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, M25P_NO_ERASE | M25P_NO_FR) },
761 { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, M25P_NO_ERASE | M25P_NO_FR) },
762
763 /* GigaDevice */
764 { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, SECT_4K) },
765 { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) },
766
767 /* Intel/Numonyx -- xxxs33b */
768 { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
769 { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
770 { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
771
772 /* Macronix */
773 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
774 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
775 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
776 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
777 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) },
778 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) },
779 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
780 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
781 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
782 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
783 { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, 0) },
784
785 /* Micron */
786 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, 0) },
787 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, 0) },
788 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, 0) },
789 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K) },
790
791 /* PMC */
792 { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
793 { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
794 { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) },
795
796 /* Spansion -- single (large) sector size only, at least
797 * for the chips listed here (without boot sectors).
798 */
799 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, 0) },
800 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, 0) },
801 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
802 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, 0) },
803 { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, 0) },
804 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
805 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
806 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
807 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) },
808 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) },
809 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
810 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
811 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
812 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
813 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
814 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) },
815 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
816
817 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
818 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
819 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
820 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
821 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
822 { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
823 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
824 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
825 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
826 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
827
828 /* ST Microelectronics -- newer production may have feature updates */
829 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
830 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
831 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
832 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
833 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
834 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
835 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
836 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
837 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
838 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, 0) },
839
840 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
841 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
842 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
843 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
844 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
845 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
846 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
847 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
848 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
849
850 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
851 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
852 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
853
854 { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
855 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
856 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
857
858 { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
859 { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
860 { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
861 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
862
863 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
864 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
865 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
866 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
867 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
868 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
869 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
870 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
871 { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K) },
872 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
873 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
874 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
875 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
876 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
877 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
878 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) },
879
880 /* Catalyst / On Semiconductor -- non-JEDEC */
881 { "cat25c11", CAT25_INFO( 16, 8, 16, 1, M25P_NO_ERASE | M25P_NO_FR) },
882 { "cat25c03", CAT25_INFO( 32, 8, 16, 2, M25P_NO_ERASE | M25P_NO_FR) },
883 { "cat25c09", CAT25_INFO( 128, 8, 32, 2, M25P_NO_ERASE | M25P_NO_FR) },
884 { "cat25c17", CAT25_INFO( 256, 8, 32, 2, M25P_NO_ERASE | M25P_NO_FR) },
885 { "cat25128", CAT25_INFO(2048, 8, 64, 2, M25P_NO_ERASE | M25P_NO_FR) },
886 { },
887 };
888 MODULE_DEVICE_TABLE(spi, m25p_ids);
889
890 static const struct spi_device_id *jedec_probe(struct spi_device *spi)
891 {
892 int tmp;
893 u8 code = OPCODE_RDID;
894 u8 id[5];
895 u32 jedec;
896 u16 ext_jedec;
897 struct flash_info *info;
898
899 /* JEDEC also defines an optional "extended device information"
900 * string for after vendor-specific data, after the three bytes
901 * we use here. Supporting some chips might require using it.
902 */
903 tmp = spi_write_then_read(spi, &code, 1, id, 5);
904 if (tmp < 0) {
905 pr_debug("%s: error %d reading JEDEC ID\n",
906 dev_name(&spi->dev), tmp);
907 return ERR_PTR(tmp);
908 }
909 jedec = id[0];
910 jedec = jedec << 8;
911 jedec |= id[1];
912 jedec = jedec << 8;
913 jedec |= id[2];
914
915 ext_jedec = id[3] << 8 | id[4];
916
917 for (tmp = 0; tmp < ARRAY_SIZE(m25p_ids) - 1; tmp++) {
918 info = (void *)m25p_ids[tmp].driver_data;
919 if (info->jedec_id == jedec) {
920 if (info->ext_id != 0 && info->ext_id != ext_jedec)
921 continue;
922 return &m25p_ids[tmp];
923 }
924 }
925 dev_err(&spi->dev, "unrecognized JEDEC id %06x\n", jedec);
926 return ERR_PTR(-ENODEV);
927 }
928
929
930 /*
931 * board specific setup should have ensured the SPI clock used here
932 * matches what the READ command supports, at least until this driver
933 * understands FAST_READ (for clocks over 25 MHz).
934 */
935 static int m25p_probe(struct spi_device *spi)
936 {
937 const struct spi_device_id *id = spi_get_device_id(spi);
938 struct flash_platform_data *data;
939 struct m25p *flash;
940 struct flash_info *info;
941 unsigned i;
942 struct mtd_part_parser_data ppdata;
943 struct device_node __maybe_unused *np = spi->dev.of_node;
944
945 #ifdef CONFIG_MTD_OF_PARTS
946 if (!of_device_is_available(np))
947 return -ENODEV;
948 #endif
949
950 /* Platform data helps sort out which chip type we have, as
951 * well as how this board partitions it. If we don't have
952 * a chip ID, try the JEDEC id commands; they'll work for most
953 * newer chips, even if we don't recognize the particular chip.
954 */
955 data = dev_get_platdata(&spi->dev);
956 if (data && data->type) {
957 const struct spi_device_id *plat_id;
958
959 for (i = 0; i < ARRAY_SIZE(m25p_ids) - 1; i++) {
960 plat_id = &m25p_ids[i];
961 if (strcmp(data->type, plat_id->name))
962 continue;
963 break;
964 }
965
966 if (i < ARRAY_SIZE(m25p_ids) - 1)
967 id = plat_id;
968 else
969 dev_warn(&spi->dev, "unrecognized id %s\n", data->type);
970 }
971
972 info = (void *)id->driver_data;
973
974 if (info->jedec_id) {
975 const struct spi_device_id *jid;
976
977 jid = jedec_probe(spi);
978 if (IS_ERR(jid)) {
979 return PTR_ERR(jid);
980 } else if (jid != id) {
981 /*
982 * JEDEC knows better, so overwrite platform ID. We
983 * can't trust partitions any longer, but we'll let
984 * mtd apply them anyway, since some partitions may be
985 * marked read-only, and we don't want to lose that
986 * information, even if it's not 100% accurate.
987 */
988 dev_warn(&spi->dev, "found %s, expected %s\n",
989 jid->name, id->name);
990 id = jid;
991 info = (void *)jid->driver_data;
992 }
993 }
994
995 flash = devm_kzalloc(&spi->dev, sizeof(*flash), GFP_KERNEL);
996 if (!flash)
997 return -ENOMEM;
998
999 flash->command = devm_kzalloc(&spi->dev, MAX_CMD_SIZE, GFP_KERNEL);
1000 if (!flash->command)
1001 return -ENOMEM;
1002
1003 flash->spi = spi;
1004 mutex_init(&flash->lock);
1005 spi_set_drvdata(spi, flash);
1006
1007 /*
1008 * Atmel, SST and Intel/Numonyx serial flash tend to power
1009 * up with the software protection bits set
1010 */
1011
1012 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ATMEL ||
1013 JEDEC_MFR(info->jedec_id) == CFI_MFR_INTEL ||
1014 JEDEC_MFR(info->jedec_id) == CFI_MFR_SST) {
1015 write_enable(flash);
1016 write_sr(flash, 0);
1017 }
1018
1019 if (data && data->name)
1020 flash->mtd.name = data->name;
1021 else
1022 flash->mtd.name = dev_name(&spi->dev);
1023
1024 flash->mtd.type = MTD_NORFLASH;
1025 flash->mtd.writesize = 1;
1026 flash->mtd.flags = MTD_CAP_NORFLASH;
1027 flash->mtd.size = info->sector_size * info->n_sectors;
1028 flash->mtd._erase = m25p80_erase;
1029 flash->mtd._read = m25p80_read;
1030
1031 /* flash protection support for STmicro chips */
1032 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ST) {
1033 flash->mtd._lock = m25p80_lock;
1034 flash->mtd._unlock = m25p80_unlock;
1035 }
1036
1037 /* sst flash chips use AAI word program */
1038 if (info->flags & SST_WRITE)
1039 flash->mtd._write = sst_write;
1040 else
1041 flash->mtd._write = m25p80_write;
1042
1043 /* prefer "small sector" erase if possible */
1044 if (info->flags & SECT_4K) {
1045 flash->erase_opcode = OPCODE_BE_4K;
1046 flash->mtd.erasesize = 4096;
1047 } else if (info->flags & SECT_4K_PMC) {
1048 flash->erase_opcode = OPCODE_BE_4K_PMC;
1049 flash->mtd.erasesize = 4096;
1050 } else {
1051 flash->erase_opcode = OPCODE_SE;
1052 flash->mtd.erasesize = info->sector_size;
1053 }
1054
1055 if (info->flags & M25P_NO_ERASE)
1056 flash->mtd.flags |= MTD_NO_ERASE;
1057
1058 ppdata.of_node = spi->dev.of_node;
1059 flash->mtd.dev.parent = &spi->dev;
1060 flash->page_size = info->page_size;
1061 flash->mtd.writebufsize = flash->page_size;
1062
1063 flash->fast_read = false;
1064 if (np && of_property_read_bool(np, "m25p,fast-read"))
1065 flash->fast_read = true;
1066
1067 #ifdef CONFIG_M25PXX_USE_FAST_READ
1068 flash->fast_read = true;
1069 #endif
1070 if (info->flags & M25P_NO_FR)
1071 flash->fast_read = false;
1072
1073 /* Default commands */
1074 if (flash->fast_read)
1075 flash->read_opcode = OPCODE_FAST_READ;
1076 else
1077 flash->read_opcode = OPCODE_NORM_READ;
1078
1079 flash->program_opcode = OPCODE_PP;
1080
1081 if (info->addr_width)
1082 flash->addr_width = info->addr_width;
1083 else if (flash->mtd.size > 0x1000000) {
1084 /* enable 4-byte addressing if the device exceeds 16MiB */
1085 flash->addr_width = 4;
1086 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_AMD) {
1087 /* Dedicated 4-byte command set */
1088 flash->read_opcode = flash->fast_read ?
1089 OPCODE_FAST_READ_4B :
1090 OPCODE_NORM_READ_4B;
1091 flash->program_opcode = OPCODE_PP_4B;
1092 /* No small sector erase for 4-byte command set */
1093 flash->erase_opcode = OPCODE_SE_4B;
1094 flash->mtd.erasesize = info->sector_size;
1095 } else
1096 set_4byte(flash, info->jedec_id, 1);
1097 } else {
1098 flash->addr_width = 3;
1099 }
1100
1101 dev_info(&spi->dev, "%s (%lld Kbytes)\n", id->name,
1102 (long long)flash->mtd.size >> 10);
1103
1104 pr_debug("mtd .name = %s, .size = 0x%llx (%lldMiB) "
1105 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
1106 flash->mtd.name,
1107 (long long)flash->mtd.size, (long long)(flash->mtd.size >> 20),
1108 flash->mtd.erasesize, flash->mtd.erasesize / 1024,
1109 flash->mtd.numeraseregions);
1110
1111 if (flash->mtd.numeraseregions)
1112 for (i = 0; i < flash->mtd.numeraseregions; i++)
1113 pr_debug("mtd.eraseregions[%d] = { .offset = 0x%llx, "
1114 ".erasesize = 0x%.8x (%uKiB), "
1115 ".numblocks = %d }\n",
1116 i, (long long)flash->mtd.eraseregions[i].offset,
1117 flash->mtd.eraseregions[i].erasesize,
1118 flash->mtd.eraseregions[i].erasesize / 1024,
1119 flash->mtd.eraseregions[i].numblocks);
1120
1121
1122 /* partitions should match sector boundaries; and it may be good to
1123 * use readonly partitions for writeprotected sectors (BP2..BP0).
1124 */
1125 return mtd_device_parse_register(&flash->mtd, NULL, &ppdata,
1126 data ? data->parts : NULL,
1127 data ? data->nr_parts : 0);
1128 }
1129
1130
1131 static int m25p_remove(struct spi_device *spi)
1132 {
1133 struct m25p *flash = spi_get_drvdata(spi);
1134
1135 /* Clean up MTD stuff. */
1136 mtd_device_unregister(&flash->mtd);
1137
1138 return 0;
1139 }
1140
1141
1142 static struct spi_driver m25p80_driver = {
1143 .driver = {
1144 .name = "m25p80",
1145 .owner = THIS_MODULE,
1146 },
1147 .id_table = m25p_ids,
1148 .probe = m25p_probe,
1149 .remove = m25p_remove,
1150
1151 /* REVISIT: many of these chips have deep power-down modes, which
1152 * should clearly be entered on suspend() to minimize power use.
1153 * And also when they're otherwise idle...
1154 */
1155 };
1156
1157 module_spi_driver(m25p80_driver);
1158
1159 MODULE_LICENSE("GPL");
1160 MODULE_AUTHOR("Mike Lavender");
1161 MODULE_DESCRIPTION("MTD SPI driver for ST M25Pxx flash chips");
Linux with added FPC-III support