?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 3.12.39
[linux/fpc-iii.git] / drivers / net / wireless / ath / ath9k / mac.c
blob02446801cb3aa4ef1eba7ba6a7dd931491d8ed0d
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "hw.h"
18 #include "hw-ops.h"
19 #include <linux/export.h>
20
21 static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
22 struct ath9k_tx_queue_info *qi)
23 {
24 ath_dbg(ath9k_hw_common(ah), INTERRUPT,
25 "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
26 ah->txok_interrupt_mask, ah->txerr_interrupt_mask,
27 ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask,
28 ah->txurn_interrupt_mask);
29
30 ENABLE_REGWRITE_BUFFER(ah);
31
32 REG_WRITE(ah, AR_IMR_S0,
33 SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK)
34 | SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC));
35 REG_WRITE(ah, AR_IMR_S1,
36 SM(ah->txerr_interrupt_mask, AR_IMR_S1_QCU_TXERR)
37 | SM(ah->txeol_interrupt_mask, AR_IMR_S1_QCU_TXEOL));
38
39 ah->imrs2_reg &= ~AR_IMR_S2_QCU_TXURN;
40 ah->imrs2_reg |= (ah->txurn_interrupt_mask & AR_IMR_S2_QCU_TXURN);
41 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
42
43 REGWRITE_BUFFER_FLUSH(ah);
44 }
45
46 u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q)
47 {
48 return REG_READ(ah, AR_QTXDP(q));
49 }
50 EXPORT_SYMBOL(ath9k_hw_gettxbuf);
51
52 void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp)
53 {
54 REG_WRITE(ah, AR_QTXDP(q), txdp);
55 }
56 EXPORT_SYMBOL(ath9k_hw_puttxbuf);
57
58 void ath9k_hw_txstart(struct ath_hw *ah, u32 q)
59 {
60 ath_dbg(ath9k_hw_common(ah), QUEUE, "Enable TXE on queue: %u\n", q);
61 REG_WRITE(ah, AR_Q_TXE, 1 << q);
62 }
63 EXPORT_SYMBOL(ath9k_hw_txstart);
64
65 u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q)
66 {
67 u32 npend;
68
69 npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
70 if (npend == 0) {
71
72 if (REG_READ(ah, AR_Q_TXE) & (1 << q))
73 npend = 1;
74 }
75
76 return npend;
77 }
78 EXPORT_SYMBOL(ath9k_hw_numtxpending);
79
80 /**
81 * ath9k_hw_updatetxtriglevel - adjusts the frame trigger level
82 *
83 * @ah: atheros hardware struct
84 * @bIncTrigLevel: whether or not the frame trigger level should be updated
85 *
86 * The frame trigger level specifies the minimum number of bytes,
87 * in units of 64 bytes, that must be DMA'ed into the PCU TX FIFO
88 * before the PCU will initiate sending the frame on the air. This can
89 * mean we initiate transmit before a full frame is on the PCU TX FIFO.
90 * Resets to 0x1 (meaning 64 bytes or a full frame, whichever occurs
91 * first)
92 *
93 * Caution must be taken to ensure to set the frame trigger level based
94 * on the DMA request size. For example if the DMA request size is set to
95 * 128 bytes the trigger level cannot exceed 6 * 64 = 384. This is because
96 * there need to be enough space in the tx FIFO for the requested transfer
97 * size. Hence the tx FIFO will stop with 512 - 128 = 384 bytes. If we set
98 * the threshold to a value beyond 6, then the transmit will hang.
99 *
100 * Current dual stream devices have a PCU TX FIFO size of 8 KB.
101 * Current single stream devices have a PCU TX FIFO size of 4 KB, however,
102 * there is a hardware issue which forces us to use 2 KB instead so the
103 * frame trigger level must not exceed 2 KB for these chipsets.
104 */
105 bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
106 {
107 u32 txcfg, curLevel, newLevel;
108
109 if (ah->tx_trig_level >= ah->config.max_txtrig_level)
110 return false;
111
112 ath9k_hw_disable_interrupts(ah);
113
114 txcfg = REG_READ(ah, AR_TXCFG);
115 curLevel = MS(txcfg, AR_FTRIG);
116 newLevel = curLevel;
117 if (bIncTrigLevel) {
118 if (curLevel < ah->config.max_txtrig_level)
119 newLevel++;
120 } else if (curLevel > MIN_TX_FIFO_THRESHOLD)
121 newLevel--;
122 if (newLevel != curLevel)
123 REG_WRITE(ah, AR_TXCFG,
124 (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG));
125
126 ath9k_hw_enable_interrupts(ah);
127
128 ah->tx_trig_level = newLevel;
129
130 return newLevel != curLevel;
131 }
132 EXPORT_SYMBOL(ath9k_hw_updatetxtriglevel);
133
134 void ath9k_hw_abort_tx_dma(struct ath_hw *ah)
135 {
136 int maxdelay = 1000;
137 int i, q;
138
139 if (ah->curchan) {
140 if (IS_CHAN_HALF_RATE(ah->curchan))
141 maxdelay *= 2;
142 else if (IS_CHAN_QUARTER_RATE(ah->curchan))
143 maxdelay *= 4;
144 }
145
146 REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M);
147
148 REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
149 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
150 REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
151
152 for (q = 0; q < AR_NUM_QCU; q++) {
153 for (i = 0; i < maxdelay; i++) {
154 if (i)
155 udelay(5);
156
157 if (!ath9k_hw_numtxpending(ah, q))
158 break;
159 }
160 }
161
162 REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
163 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
164 REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
165
166 REG_WRITE(ah, AR_Q_TXD, 0);
167 }
168 EXPORT_SYMBOL(ath9k_hw_abort_tx_dma);
169
170 bool ath9k_hw_stop_dma_queue(struct ath_hw *ah, u32 q)
171 {
172 #define ATH9K_TX_STOP_DMA_TIMEOUT 1000 /* usec */
173 #define ATH9K_TIME_QUANTUM 100 /* usec */
174 int wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM;
175 int wait;
176
177 REG_WRITE(ah, AR_Q_TXD, 1 << q);
178
179 for (wait = wait_time; wait != 0; wait--) {
180 if (wait != wait_time)
181 udelay(ATH9K_TIME_QUANTUM);
182
183 if (ath9k_hw_numtxpending(ah, q) == 0)
184 break;
185 }
186
187 REG_WRITE(ah, AR_Q_TXD, 0);
188
189 return wait != 0;
190
191 #undef ATH9K_TX_STOP_DMA_TIMEOUT
192 #undef ATH9K_TIME_QUANTUM
193 }
194 EXPORT_SYMBOL(ath9k_hw_stop_dma_queue);
195
196 bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
197 const struct ath9k_tx_queue_info *qinfo)
198 {
199 u32 cw;
200 struct ath_common *common = ath9k_hw_common(ah);
201 struct ath9k_tx_queue_info *qi;
202
203 qi = &ah->txq[q];
204 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
205 ath_dbg(common, QUEUE,
206 "Set TXQ properties, inactive queue: %u\n", q);
207 return false;
208 }
209
210 ath_dbg(common, QUEUE, "Set queue properties for: %u\n", q);
211
212 qi->tqi_ver = qinfo->tqi_ver;
213 qi->tqi_subtype = qinfo->tqi_subtype;
214 qi->tqi_qflags = qinfo->tqi_qflags;
215 qi->tqi_priority = qinfo->tqi_priority;
216 if (qinfo->tqi_aifs != ATH9K_TXQ_USEDEFAULT)
217 qi->tqi_aifs = min(qinfo->tqi_aifs, 255U);
218 else
219 qi->tqi_aifs = INIT_AIFS;
220 if (qinfo->tqi_cwmin != ATH9K_TXQ_USEDEFAULT) {
221 cw = min(qinfo->tqi_cwmin, 1024U);
222 qi->tqi_cwmin = 1;
223 while (qi->tqi_cwmin < cw)
224 qi->tqi_cwmin = (qi->tqi_cwmin << 1) | 1;
225 } else
226 qi->tqi_cwmin = qinfo->tqi_cwmin;
227 if (qinfo->tqi_cwmax != ATH9K_TXQ_USEDEFAULT) {
228 cw = min(qinfo->tqi_cwmax, 1024U);
229 qi->tqi_cwmax = 1;
230 while (qi->tqi_cwmax < cw)
231 qi->tqi_cwmax = (qi->tqi_cwmax << 1) | 1;
232 } else
233 qi->tqi_cwmax = INIT_CWMAX;
234
235 if (qinfo->tqi_shretry != 0)
236 qi->tqi_shretry = min((u32) qinfo->tqi_shretry, 15U);
237 else
238 qi->tqi_shretry = INIT_SH_RETRY;
239 if (qinfo->tqi_lgretry != 0)
240 qi->tqi_lgretry = min((u32) qinfo->tqi_lgretry, 15U);
241 else
242 qi->tqi_lgretry = INIT_LG_RETRY;
243 qi->tqi_cbrPeriod = qinfo->tqi_cbrPeriod;
244 qi->tqi_cbrOverflowLimit = qinfo->tqi_cbrOverflowLimit;
245 qi->tqi_burstTime = qinfo->tqi_burstTime;
246 qi->tqi_readyTime = qinfo->tqi_readyTime;
247
248 switch (qinfo->tqi_subtype) {
249 case ATH9K_WME_UPSD:
250 if (qi->tqi_type == ATH9K_TX_QUEUE_DATA)
251 qi->tqi_intFlags = ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS;
252 break;
253 default:
254 break;
255 }
256
257 return true;
258 }
259 EXPORT_SYMBOL(ath9k_hw_set_txq_props);
260
261 bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
262 struct ath9k_tx_queue_info *qinfo)
263 {
264 struct ath_common *common = ath9k_hw_common(ah);
265 struct ath9k_tx_queue_info *qi;
266
267 qi = &ah->txq[q];
268 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
269 ath_dbg(common, QUEUE,
270 "Get TXQ properties, inactive queue: %u\n", q);
271 return false;
272 }
273
274 qinfo->tqi_qflags = qi->tqi_qflags;
275 qinfo->tqi_ver = qi->tqi_ver;
276 qinfo->tqi_subtype = qi->tqi_subtype;
277 qinfo->tqi_qflags = qi->tqi_qflags;
278 qinfo->tqi_priority = qi->tqi_priority;
279 qinfo->tqi_aifs = qi->tqi_aifs;
280 qinfo->tqi_cwmin = qi->tqi_cwmin;
281 qinfo->tqi_cwmax = qi->tqi_cwmax;
282 qinfo->tqi_shretry = qi->tqi_shretry;
283 qinfo->tqi_lgretry = qi->tqi_lgretry;
284 qinfo->tqi_cbrPeriod = qi->tqi_cbrPeriod;
285 qinfo->tqi_cbrOverflowLimit = qi->tqi_cbrOverflowLimit;
286 qinfo->tqi_burstTime = qi->tqi_burstTime;
287 qinfo->tqi_readyTime = qi->tqi_readyTime;
288
289 return true;
290 }
291 EXPORT_SYMBOL(ath9k_hw_get_txq_props);
292
293 int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
294 const struct ath9k_tx_queue_info *qinfo)
295 {
296 struct ath_common *common = ath9k_hw_common(ah);
297 struct ath9k_tx_queue_info *qi;
298 int q;
299
300 switch (type) {
301 case ATH9K_TX_QUEUE_BEACON:
302 q = ATH9K_NUM_TX_QUEUES - 1;
303 break;
304 case ATH9K_TX_QUEUE_CAB:
305 q = ATH9K_NUM_TX_QUEUES - 2;
306 break;
307 case ATH9K_TX_QUEUE_PSPOLL:
308 q = 1;
309 break;
310 case ATH9K_TX_QUEUE_UAPSD:
311 q = ATH9K_NUM_TX_QUEUES - 3;
312 break;
313 case ATH9K_TX_QUEUE_DATA:
314 q = qinfo->tqi_subtype;
315 break;
316 default:
317 ath_err(common, "Invalid TX queue type: %u\n", type);
318 return -1;
319 }
320
321 ath_dbg(common, QUEUE, "Setup TX queue: %u\n", q);
322
323 qi = &ah->txq[q];
324 if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
325 ath_err(common, "TX queue: %u already active\n", q);
326 return -1;
327 }
328 memset(qi, 0, sizeof(struct ath9k_tx_queue_info));
329 qi->tqi_type = type;
330 qi->tqi_physCompBuf = qinfo->tqi_physCompBuf;
331 (void) ath9k_hw_set_txq_props(ah, q, qinfo);
332
333 return q;
334 }
335 EXPORT_SYMBOL(ath9k_hw_setuptxqueue);
336
337 static void ath9k_hw_clear_queue_interrupts(struct ath_hw *ah, u32 q)
338 {
339 ah->txok_interrupt_mask &= ~(1 << q);
340 ah->txerr_interrupt_mask &= ~(1 << q);
341 ah->txdesc_interrupt_mask &= ~(1 << q);
342 ah->txeol_interrupt_mask &= ~(1 << q);
343 ah->txurn_interrupt_mask &= ~(1 << q);
344 }
345
346 bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
347 {
348 struct ath_common *common = ath9k_hw_common(ah);
349 struct ath9k_tx_queue_info *qi;
350
351 qi = &ah->txq[q];
352 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
353 ath_dbg(common, QUEUE, "Release TXQ, inactive queue: %u\n", q);
354 return false;
355 }
356
357 ath_dbg(common, QUEUE, "Release TX queue: %u\n", q);
358
359 qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
360 ath9k_hw_clear_queue_interrupts(ah, q);
361 ath9k_hw_set_txq_interrupts(ah, qi);
362
363 return true;
364 }
365 EXPORT_SYMBOL(ath9k_hw_releasetxqueue);
366
367 bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
368 {
369 struct ath_common *common = ath9k_hw_common(ah);
370 struct ath9k_channel *chan = ah->curchan;
371 struct ath9k_tx_queue_info *qi;
372 u32 cwMin, chanCwMin, value;
373
374 qi = &ah->txq[q];
375 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
376 ath_dbg(common, QUEUE, "Reset TXQ, inactive queue: %u\n", q);
377 return true;
378 }
379
380 ath_dbg(common, QUEUE, "Reset TX queue: %u\n", q);
381
382 if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
383 if (chan && IS_CHAN_B(chan))
384 chanCwMin = INIT_CWMIN_11B;
385 else
386 chanCwMin = INIT_CWMIN;
387
388 for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1);
389 } else
390 cwMin = qi->tqi_cwmin;
391
392 ENABLE_REGWRITE_BUFFER(ah);
393
394 REG_WRITE(ah, AR_DLCL_IFS(q),
395 SM(cwMin, AR_D_LCL_IFS_CWMIN) |
396 SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) |
397 SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
398
399 REG_WRITE(ah, AR_DRETRY_LIMIT(q),
400 SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) |
401 SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) |
402 SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH));
403
404 REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
405
406 if (AR_SREV_9340(ah) && !AR_SREV_9340_13_OR_LATER(ah))
407 REG_WRITE(ah, AR_DMISC(q),
408 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x1);
409 else
410 REG_WRITE(ah, AR_DMISC(q),
411 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2);
412
413 if (qi->tqi_cbrPeriod) {
414 REG_WRITE(ah, AR_QCBRCFG(q),
415 SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) |
416 SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_OVF_THRESH));
417 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_FSP_CBR |
418 (qi->tqi_cbrOverflowLimit ?
419 AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0));
420 }
421 if (qi->tqi_readyTime && (qi->tqi_type != ATH9K_TX_QUEUE_CAB)) {
422 REG_WRITE(ah, AR_QRDYTIMECFG(q),
423 SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) |
424 AR_Q_RDYTIMECFG_EN);
425 }
426
427 REG_WRITE(ah, AR_DCHNTIME(q),
428 SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
429 (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
430
431 if (qi->tqi_burstTime
432 && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE))
433 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_RDYTIME_EXP_POLICY);
434
435 if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE)
436 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS);
437
438 REGWRITE_BUFFER_FLUSH(ah);
439
440 if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE)
441 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_FRAG_BKOFF_EN);
442
443 switch (qi->tqi_type) {
444 case ATH9K_TX_QUEUE_BEACON:
445 ENABLE_REGWRITE_BUFFER(ah);
446
447 REG_SET_BIT(ah, AR_QMISC(q),
448 AR_Q_MISC_FSP_DBA_GATED
449 | AR_Q_MISC_BEACON_USE
450 | AR_Q_MISC_CBR_INCR_DIS1);
451
452 REG_SET_BIT(ah, AR_DMISC(q),
453 (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
454 AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
455 | AR_D_MISC_BEACON_USE
456 | AR_D_MISC_POST_FR_BKOFF_DIS);
457
458 REGWRITE_BUFFER_FLUSH(ah);
459
460 /*
461 * cwmin and cwmax should be 0 for beacon queue
462 * but not for IBSS as we would create an imbalance
463 * on beaconing fairness for participating nodes.
464 */
465 if (AR_SREV_9300_20_OR_LATER(ah) &&
466 ah->opmode != NL80211_IFTYPE_ADHOC) {
467 REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN)
468 | SM(0, AR_D_LCL_IFS_CWMAX)
469 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
470 }
471 break;
472 case ATH9K_TX_QUEUE_CAB:
473 ENABLE_REGWRITE_BUFFER(ah);
474
475 REG_SET_BIT(ah, AR_QMISC(q),
476 AR_Q_MISC_FSP_DBA_GATED
477 | AR_Q_MISC_CBR_INCR_DIS1
478 | AR_Q_MISC_CBR_INCR_DIS0);
479 value = (qi->tqi_readyTime -
480 (ah->config.sw_beacon_response_time -
481 ah->config.dma_beacon_response_time) -
482 ah->config.additional_swba_backoff) * 1024;
483 REG_WRITE(ah, AR_QRDYTIMECFG(q),
484 value | AR_Q_RDYTIMECFG_EN);
485 REG_SET_BIT(ah, AR_DMISC(q),
486 (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
487 AR_D_MISC_ARB_LOCKOUT_CNTRL_S));
488
489 REGWRITE_BUFFER_FLUSH(ah);
490
491 break;
492 case ATH9K_TX_QUEUE_PSPOLL:
493 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_CBR_INCR_DIS1);
494 break;
495 case ATH9K_TX_QUEUE_UAPSD:
496 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS);
497 break;
498 default:
499 break;
500 }
501
502 if (qi->tqi_intFlags & ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS) {
503 REG_SET_BIT(ah, AR_DMISC(q),
504 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
505 AR_D_MISC_ARB_LOCKOUT_CNTRL) |
506 AR_D_MISC_POST_FR_BKOFF_DIS);
507 }
508
509 if (AR_SREV_9300_20_OR_LATER(ah))
510 REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN);
511
512 ath9k_hw_clear_queue_interrupts(ah, q);
513 if (qi->tqi_qflags & TXQ_FLAG_TXINT_ENABLE) {
514 ah->txok_interrupt_mask |= 1 << q;
515 ah->txerr_interrupt_mask |= 1 << q;
516 }
517 if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE)
518 ah->txdesc_interrupt_mask |= 1 << q;
519 if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE)
520 ah->txeol_interrupt_mask |= 1 << q;
521 if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE)
522 ah->txurn_interrupt_mask |= 1 << q;
523 ath9k_hw_set_txq_interrupts(ah, qi);
524
525 return true;
526 }
527 EXPORT_SYMBOL(ath9k_hw_resettxqueue);
528
529 int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
530 struct ath_rx_status *rs)
531 {
532 struct ar5416_desc ads;
533 struct ar5416_desc *adsp = AR5416DESC(ds);
534 u32 phyerr;
535
536 if ((adsp->ds_rxstatus8 & AR_RxDone) == 0)
537 return -EINPROGRESS;
538
539 ads.u.rx = adsp->u.rx;
540
541 rs->rs_status = 0;
542 rs->rs_flags = 0;
543 rs->flag = 0;
544
545 rs->rs_datalen = ads.ds_rxstatus1 & AR_DataLen;
546 rs->rs_tstamp = ads.AR_RcvTimestamp;
547
548 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr) {
549 rs->rs_rssi = ATH9K_RSSI_BAD;
550 rs->rs_rssi_ctl0 = ATH9K_RSSI_BAD;
551 rs->rs_rssi_ctl1 = ATH9K_RSSI_BAD;
552 rs->rs_rssi_ctl2 = ATH9K_RSSI_BAD;
553 rs->rs_rssi_ext0 = ATH9K_RSSI_BAD;
554 rs->rs_rssi_ext1 = ATH9K_RSSI_BAD;
555 rs->rs_rssi_ext2 = ATH9K_RSSI_BAD;
556 } else {
557 rs->rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined);
558 rs->rs_rssi_ctl0 = MS(ads.ds_rxstatus0,
559 AR_RxRSSIAnt00);
560 rs->rs_rssi_ctl1 = MS(ads.ds_rxstatus0,
561 AR_RxRSSIAnt01);
562 rs->rs_rssi_ctl2 = MS(ads.ds_rxstatus0,
563 AR_RxRSSIAnt02);
564 rs->rs_rssi_ext0 = MS(ads.ds_rxstatus4,
565 AR_RxRSSIAnt10);
566 rs->rs_rssi_ext1 = MS(ads.ds_rxstatus4,
567 AR_RxRSSIAnt11);
568 rs->rs_rssi_ext2 = MS(ads.ds_rxstatus4,
569 AR_RxRSSIAnt12);
570 }
571 if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
572 rs->rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
573 else
574 rs->rs_keyix = ATH9K_RXKEYIX_INVALID;
575
576 rs->rs_rate = MS(ads.ds_rxstatus0, AR_RxRate);
577 rs->rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;
578
579 rs->rs_firstaggr = (ads.ds_rxstatus8 & AR_RxFirstAggr) ? 1 : 0;
580 rs->rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
581 rs->rs_moreaggr = (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
582 rs->rs_antenna = MS(ads.ds_rxstatus3, AR_RxAntenna);
583
584 /* directly mapped flags for ieee80211_rx_status */
585 rs->flag |=
586 (ads.ds_rxstatus3 & AR_GI) ? RX_FLAG_SHORT_GI : 0;
587 rs->flag |=
588 (ads.ds_rxstatus3 & AR_2040) ? RX_FLAG_40MHZ : 0;
589 if (AR_SREV_9280_20_OR_LATER(ah))
590 rs->flag |=
591 (ads.ds_rxstatus3 & AR_STBC) ?
592 /* we can only Nss=1 STBC */
593 (1 << RX_FLAG_STBC_SHIFT) : 0;
594
595 if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
596 rs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
597 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
598 rs->rs_flags |= ATH9K_RX_DELIM_CRC_POST;
599 if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
600 rs->rs_flags |= ATH9K_RX_DECRYPT_BUSY;
601
602 if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
603 /*
604 * Treat these errors as mutually exclusive to avoid spurious
605 * extra error reports from the hardware. If a CRC error is
606 * reported, then decryption and MIC errors are irrelevant,
607 * the frame is going to be dropped either way
608 */
609 if (ads.ds_rxstatus8 & AR_PHYErr) {
610 rs->rs_status |= ATH9K_RXERR_PHY;
611 phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
612 rs->rs_phyerr = phyerr;
613 } else if (ads.ds_rxstatus8 & AR_CRCErr)
614 rs->rs_status |= ATH9K_RXERR_CRC;
615 else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
616 rs->rs_status |= ATH9K_RXERR_DECRYPT;
617 else if (ads.ds_rxstatus8 & AR_MichaelErr)
618 rs->rs_status |= ATH9K_RXERR_MIC;
619 } else {
620 if (ads.ds_rxstatus8 &
621 (AR_CRCErr | AR_PHYErr | AR_DecryptCRCErr | AR_MichaelErr))
622 rs->rs_status |= ATH9K_RXERR_CORRUPT_DESC;
623
624 /* Only up to MCS16 supported, everything above is invalid */
625 if (rs->rs_rate >= 0x90)
626 rs->rs_status |= ATH9K_RXERR_CORRUPT_DESC;
627 }
628
629 if (ads.ds_rxstatus8 & AR_KeyMiss)
630 rs->rs_status |= ATH9K_RXERR_KEYMISS;
631
632 return 0;
633 }
634 EXPORT_SYMBOL(ath9k_hw_rxprocdesc);
635
636 /*
637 * This can stop or re-enables RX.
638 *
639 * If bool is set this will kill any frame which is currently being
640 * transferred between the MAC and baseband and also prevent any new
641 * frames from getting started.
642 */
643 bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set)
644 {
645 u32 reg;
646
647 if (set) {
648 REG_SET_BIT(ah, AR_DIAG_SW,
649 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
650
651 if (!ath9k_hw_wait(ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE,
652 0, AH_WAIT_TIMEOUT)) {
653 REG_CLR_BIT(ah, AR_DIAG_SW,
654 (AR_DIAG_RX_DIS |
655 AR_DIAG_RX_ABORT));
656
657 reg = REG_READ(ah, AR_OBS_BUS_1);
658 ath_err(ath9k_hw_common(ah),
659 "RX failed to go idle in 10 ms RXSM=0x%x\n",
660 reg);
661
662 return false;
663 }
664 } else {
665 REG_CLR_BIT(ah, AR_DIAG_SW,
666 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
667 }
668
669 return true;
670 }
671 EXPORT_SYMBOL(ath9k_hw_setrxabort);
672
673 void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp)
674 {
675 REG_WRITE(ah, AR_RXDP, rxdp);
676 }
677 EXPORT_SYMBOL(ath9k_hw_putrxbuf);
678
679 void ath9k_hw_startpcureceive(struct ath_hw *ah, bool is_scanning)
680 {
681 ath9k_enable_mib_counters(ah);
682
683 ath9k_ani_reset(ah, is_scanning);
684
685 REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
686 }
687 EXPORT_SYMBOL(ath9k_hw_startpcureceive);
688
689 void ath9k_hw_abortpcurecv(struct ath_hw *ah)
690 {
691 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_ABORT | AR_DIAG_RX_DIS);
692
693 ath9k_hw_disable_mib_counters(ah);
694 }
695 EXPORT_SYMBOL(ath9k_hw_abortpcurecv);
696
697 bool ath9k_hw_stopdmarecv(struct ath_hw *ah, bool *reset)
698 {
699 #define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */
700 struct ath_common *common = ath9k_hw_common(ah);
701 u32 mac_status, last_mac_status = 0;
702 int i;
703
704 /* Enable access to the DMA observation bus */
705 REG_WRITE(ah, AR_MACMISC,
706 ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) |
707 (AR_MACMISC_MISC_OBS_BUS_1 <<
708 AR_MACMISC_MISC_OBS_BUS_MSB_S)));
709
710 REG_WRITE(ah, AR_CR, AR_CR_RXD);
711
712 /* Wait for rx enable bit to go low */
713 for (i = AH_RX_STOP_DMA_TIMEOUT / AH_TIME_QUANTUM; i != 0; i--) {
714 if ((REG_READ(ah, AR_CR) & AR_CR_RXE) == 0)
715 break;
716
717 if (!AR_SREV_9300_20_OR_LATER(ah)) {
718 mac_status = REG_READ(ah, AR_DMADBG_7) & 0x7f0;
719 if (mac_status == 0x1c0 && mac_status == last_mac_status) {
720 *reset = true;
721 break;
722 }
723
724 last_mac_status = mac_status;
725 }
726
727 udelay(AH_TIME_QUANTUM);
728 }
729
730 if (i == 0) {
731 ath_err(common,
732 "DMA failed to stop in %d ms AR_CR=0x%08x AR_DIAG_SW=0x%08x DMADBG_7=0x%08x\n",
733 AH_RX_STOP_DMA_TIMEOUT / 1000,
734 REG_READ(ah, AR_CR),
735 REG_READ(ah, AR_DIAG_SW),
736 REG_READ(ah, AR_DMADBG_7));
737 return false;
738 } else {
739 return true;
740 }
741
742 #undef AH_RX_STOP_DMA_TIMEOUT
743 }
744 EXPORT_SYMBOL(ath9k_hw_stopdmarecv);
745
746 int ath9k_hw_beaconq_setup(struct ath_hw *ah)
747 {
748 struct ath9k_tx_queue_info qi;
749
750 memset(&qi, 0, sizeof(qi));
751 qi.tqi_aifs = 1;
752 qi.tqi_cwmin = 0;
753 qi.tqi_cwmax = 0;
754
755 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
756 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
757
758 return ath9k_hw_setuptxqueue(ah, ATH9K_TX_QUEUE_BEACON, &qi);
759 }
760 EXPORT_SYMBOL(ath9k_hw_beaconq_setup);
761
762 bool ath9k_hw_intrpend(struct ath_hw *ah)
763 {
764 u32 host_isr;
765
766 if (AR_SREV_9100(ah))
767 return true;
768
769 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
770
771 if (((host_isr & AR_INTR_MAC_IRQ) ||
772 (host_isr & AR_INTR_ASYNC_MASK_MCI)) &&
773 (host_isr != AR_INTR_SPURIOUS))
774 return true;
775
776 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
777 if ((host_isr & AR_INTR_SYNC_DEFAULT)
778 && (host_isr != AR_INTR_SPURIOUS))
779 return true;
780
781 return false;
782 }
783 EXPORT_SYMBOL(ath9k_hw_intrpend);
784
785 void ath9k_hw_kill_interrupts(struct ath_hw *ah)
786 {
787 struct ath_common *common = ath9k_hw_common(ah);
788
789 ath_dbg(common, INTERRUPT, "disable IER\n");
790 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
791 (void) REG_READ(ah, AR_IER);
792 if (!AR_SREV_9100(ah)) {
793 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
794 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
795
796 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
797 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
798 }
799 }
800 EXPORT_SYMBOL(ath9k_hw_kill_interrupts);
801
802 void ath9k_hw_disable_interrupts(struct ath_hw *ah)
803 {
804 if (!(ah->imask & ATH9K_INT_GLOBAL))
805 atomic_set(&ah->intr_ref_cnt, -1);
806 else
807 atomic_dec(&ah->intr_ref_cnt);
808
809 ath9k_hw_kill_interrupts(ah);
810 }
811 EXPORT_SYMBOL(ath9k_hw_disable_interrupts);
812
813 void ath9k_hw_enable_interrupts(struct ath_hw *ah)
814 {
815 struct ath_common *common = ath9k_hw_common(ah);
816 u32 sync_default = AR_INTR_SYNC_DEFAULT;
817 u32 async_mask;
818
819 if (!(ah->imask & ATH9K_INT_GLOBAL))
820 return;
821
822 if (!atomic_inc_and_test(&ah->intr_ref_cnt)) {
823 ath_dbg(common, INTERRUPT, "Do not enable IER ref count %d\n",
824 atomic_read(&ah->intr_ref_cnt));
825 return;
826 }
827
828 if (AR_SREV_9340(ah) || AR_SREV_9550(ah))
829 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
830
831 async_mask = AR_INTR_MAC_IRQ;
832
833 if (ah->imask & ATH9K_INT_MCI)
834 async_mask |= AR_INTR_ASYNC_MASK_MCI;
835
836 ath_dbg(common, INTERRUPT, "enable IER\n");
837 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
838 if (!AR_SREV_9100(ah)) {
839 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, async_mask);
840 REG_WRITE(ah, AR_INTR_ASYNC_MASK, async_mask);
841
842 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
843 REG_WRITE(ah, AR_INTR_SYNC_MASK, sync_default);
844 }
845 ath_dbg(common, INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
846 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
847 }
848 EXPORT_SYMBOL(ath9k_hw_enable_interrupts);
849
850 void ath9k_hw_set_interrupts(struct ath_hw *ah)
851 {
852 enum ath9k_int ints = ah->imask;
853 u32 mask, mask2;
854 struct ath9k_hw_capabilities *pCap = &ah->caps;
855 struct ath_common *common = ath9k_hw_common(ah);
856
857 if (!(ints & ATH9K_INT_GLOBAL))
858 ath9k_hw_disable_interrupts(ah);
859
860 ath_dbg(common, INTERRUPT, "New interrupt mask 0x%x\n", ints);
861
862 mask = ints & ATH9K_INT_COMMON;
863 mask2 = 0;
864
865 if (ints & ATH9K_INT_TX) {
866 if (ah->config.tx_intr_mitigation)
867 mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM;
868 else {
869 if (ah->txok_interrupt_mask)
870 mask |= AR_IMR_TXOK;
871 if (ah->txdesc_interrupt_mask)
872 mask |= AR_IMR_TXDESC;
873 }
874 if (ah->txerr_interrupt_mask)
875 mask |= AR_IMR_TXERR;
876 if (ah->txeol_interrupt_mask)
877 mask |= AR_IMR_TXEOL;
878 }
879 if (ints & ATH9K_INT_RX) {
880 if (AR_SREV_9300_20_OR_LATER(ah)) {
881 mask |= AR_IMR_RXERR | AR_IMR_RXOK_HP;
882 if (ah->config.rx_intr_mitigation) {
883 mask &= ~AR_IMR_RXOK_LP;
884 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
885 } else {
886 mask |= AR_IMR_RXOK_LP;
887 }
888 } else {
889 if (ah->config.rx_intr_mitigation)
890 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
891 else
892 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
893 }
894 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
895 mask |= AR_IMR_GENTMR;
896 }
897
898 if (ints & ATH9K_INT_GENTIMER)
899 mask |= AR_IMR_GENTMR;
900
901 if (ints & (ATH9K_INT_BMISC)) {
902 mask |= AR_IMR_BCNMISC;
903 if (ints & ATH9K_INT_TIM)
904 mask2 |= AR_IMR_S2_TIM;
905 if (ints & ATH9K_INT_DTIM)
906 mask2 |= AR_IMR_S2_DTIM;
907 if (ints & ATH9K_INT_DTIMSYNC)
908 mask2 |= AR_IMR_S2_DTIMSYNC;
909 if (ints & ATH9K_INT_CABEND)
910 mask2 |= AR_IMR_S2_CABEND;
911 if (ints & ATH9K_INT_TSFOOR)
912 mask2 |= AR_IMR_S2_TSFOOR;
913 }
914
915 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
916 mask |= AR_IMR_BCNMISC;
917 if (ints & ATH9K_INT_GTT)
918 mask2 |= AR_IMR_S2_GTT;
919 if (ints & ATH9K_INT_CST)
920 mask2 |= AR_IMR_S2_CST;
921 }
922
923 ath_dbg(common, INTERRUPT, "new IMR 0x%x\n", mask);
924 REG_WRITE(ah, AR_IMR, mask);
925 ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
926 AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
927 AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
928 ah->imrs2_reg |= mask2;
929 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
930
931 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
932 if (ints & ATH9K_INT_TIM_TIMER)
933 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
934 else
935 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
936 }
937
938 return;
939 }
940 EXPORT_SYMBOL(ath9k_hw_set_interrupts);
Linux with added FPC-III support