?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 3.12.39
[linux/fpc-iii.git] / drivers / spi / spi-omap2-mcspi.c
blob5f19cc975b27cc752f342fc53fb2604234eadc27
1 /*
2 * OMAP2 McSPI controller driver
3 *
4 * Copyright (C) 2005, 2006 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
6 * Juha Yrj�l� <juha.yrjola@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24 #include <linux/kernel.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/module.h>
28 #include <linux/device.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/dmaengine.h>
32 #include <linux/omap-dma.h>
33 #include <linux/platform_device.h>
34 #include <linux/err.h>
35 #include <linux/clk.h>
36 #include <linux/io.h>
37 #include <linux/slab.h>
38 #include <linux/pm_runtime.h>
39 #include <linux/of.h>
40 #include <linux/of_device.h>
41 #include <linux/gcd.h>
42
43 #include <linux/spi/spi.h>
44
45 #include <linux/platform_data/spi-omap2-mcspi.h>
46
47 #define OMAP2_MCSPI_MAX_FREQ 48000000
48 #define OMAP2_MCSPI_MAX_FIFODEPTH 64
49 #define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF
50 #define SPI_AUTOSUSPEND_TIMEOUT 2000
51
52 #define OMAP2_MCSPI_REVISION 0x00
53 #define OMAP2_MCSPI_SYSSTATUS 0x14
54 #define OMAP2_MCSPI_IRQSTATUS 0x18
55 #define OMAP2_MCSPI_IRQENABLE 0x1c
56 #define OMAP2_MCSPI_WAKEUPENABLE 0x20
57 #define OMAP2_MCSPI_SYST 0x24
58 #define OMAP2_MCSPI_MODULCTRL 0x28
59 #define OMAP2_MCSPI_XFERLEVEL 0x7c
60
61 /* per-channel banks, 0x14 bytes each, first is: */
62 #define OMAP2_MCSPI_CHCONF0 0x2c
63 #define OMAP2_MCSPI_CHSTAT0 0x30
64 #define OMAP2_MCSPI_CHCTRL0 0x34
65 #define OMAP2_MCSPI_TX0 0x38
66 #define OMAP2_MCSPI_RX0 0x3c
67
68 /* per-register bitmasks: */
69 #define OMAP2_MCSPI_IRQSTATUS_EOW BIT(17)
70
71 #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
72 #define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
73 #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
74
75 #define OMAP2_MCSPI_CHCONF_PHA BIT(0)
76 #define OMAP2_MCSPI_CHCONF_POL BIT(1)
77 #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
78 #define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
79 #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
80 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
81 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
82 #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
83 #define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
84 #define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
85 #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
86 #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
87 #define OMAP2_MCSPI_CHCONF_IS BIT(18)
88 #define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
89 #define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
90 #define OMAP2_MCSPI_CHCONF_FFET BIT(27)
91 #define OMAP2_MCSPI_CHCONF_FFER BIT(28)
92
93 #define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
94 #define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
95 #define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
96 #define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3)
97
98 #define OMAP2_MCSPI_CHCTRL_EN BIT(0)
99
100 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
101
102 /* We have 2 DMA channels per CS, one for RX and one for TX */
103 struct omap2_mcspi_dma {
104 struct dma_chan *dma_tx;
105 struct dma_chan *dma_rx;
106
107 int dma_tx_sync_dev;
108 int dma_rx_sync_dev;
109
110 struct completion dma_tx_completion;
111 struct completion dma_rx_completion;
112
113 char dma_rx_ch_name[14];
114 char dma_tx_ch_name[14];
115 };
116
117 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
118 * cache operations; better heuristics consider wordsize and bitrate.
119 */
120 #define DMA_MIN_BYTES 160
121
122
123 /*
124 * Used for context save and restore, structure members to be updated whenever
125 * corresponding registers are modified.
126 */
127 struct omap2_mcspi_regs {
128 u32 modulctrl;
129 u32 wakeupenable;
130 struct list_head cs;
131 };
132
133 struct omap2_mcspi {
134 struct spi_master *master;
135 /* Virtual base address of the controller */
136 void __iomem *base;
137 unsigned long phys;
138 /* SPI1 has 4 channels, while SPI2 has 2 */
139 struct omap2_mcspi_dma *dma_channels;
140 struct device *dev;
141 struct omap2_mcspi_regs ctx;
142 int fifo_depth;
143 unsigned int pin_dir:1;
144 };
145
146 struct omap2_mcspi_cs {
147 void __iomem *base;
148 unsigned long phys;
149 int word_len;
150 struct list_head node;
151 /* Context save and restore shadow register */
152 u32 chconf0;
153 };
154
155 static inline void mcspi_write_reg(struct spi_master *master,
156 int idx, u32 val)
157 {
158 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
159
160 __raw_writel(val, mcspi->base + idx);
161 }
162
163 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
164 {
165 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
166
167 return __raw_readl(mcspi->base + idx);
168 }
169
170 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
171 int idx, u32 val)
172 {
173 struct omap2_mcspi_cs *cs = spi->controller_state;
174
175 __raw_writel(val, cs->base + idx);
176 }
177
178 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
179 {
180 struct omap2_mcspi_cs *cs = spi->controller_state;
181
182 return __raw_readl(cs->base + idx);
183 }
184
185 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
186 {
187 struct omap2_mcspi_cs *cs = spi->controller_state;
188
189 return cs->chconf0;
190 }
191
192 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
193 {
194 struct omap2_mcspi_cs *cs = spi->controller_state;
195
196 cs->chconf0 = val;
197 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
198 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
199 }
200
201 static inline int mcspi_bytes_per_word(int word_len)
202 {
203 if (word_len <= 8)
204 return 1;
205 else if (word_len <= 16)
206 return 2;
207 else /* word_len <= 32 */
208 return 4;
209 }
210
211 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
212 int is_read, int enable)
213 {
214 u32 l, rw;
215
216 l = mcspi_cached_chconf0(spi);
217
218 if (is_read) /* 1 is read, 0 write */
219 rw = OMAP2_MCSPI_CHCONF_DMAR;
220 else
221 rw = OMAP2_MCSPI_CHCONF_DMAW;
222
223 if (enable)
224 l |= rw;
225 else
226 l &= ~rw;
227
228 mcspi_write_chconf0(spi, l);
229 }
230
231 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
232 {
233 u32 l;
234
235 l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
236 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
237 /* Flash post-writes */
238 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
239 }
240
241 static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
242 {
243 u32 l;
244
245 l = mcspi_cached_chconf0(spi);
246 if (cs_active)
247 l |= OMAP2_MCSPI_CHCONF_FORCE;
248 else
249 l &= ~OMAP2_MCSPI_CHCONF_FORCE;
250
251 mcspi_write_chconf0(spi, l);
252 }
253
254 static void omap2_mcspi_set_master_mode(struct spi_master *master)
255 {
256 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
257 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
258 u32 l;
259
260 /*
261 * Setup when switching from (reset default) slave mode
262 * to single-channel master mode
263 */
264 l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
265 l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS);
266 l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
267 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
268
269 ctx->modulctrl = l;
270 }
271
272 static void omap2_mcspi_set_fifo(const struct spi_device *spi,
273 struct spi_transfer *t, int enable)
274 {
275 struct spi_master *master = spi->master;
276 struct omap2_mcspi_cs *cs = spi->controller_state;
277 struct omap2_mcspi *mcspi;
278 unsigned int wcnt;
279 int fifo_depth, bytes_per_word;
280 u32 chconf, xferlevel;
281
282 mcspi = spi_master_get_devdata(master);
283
284 chconf = mcspi_cached_chconf0(spi);
285 if (enable) {
286 bytes_per_word = mcspi_bytes_per_word(cs->word_len);
287 if (t->len % bytes_per_word != 0)
288 goto disable_fifo;
289
290 fifo_depth = gcd(t->len, OMAP2_MCSPI_MAX_FIFODEPTH);
291 if (fifo_depth < 2 || fifo_depth % bytes_per_word != 0)
292 goto disable_fifo;
293
294 wcnt = t->len / bytes_per_word;
295 if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT)
296 goto disable_fifo;
297
298 xferlevel = wcnt << 16;
299 if (t->rx_buf != NULL) {
300 chconf |= OMAP2_MCSPI_CHCONF_FFER;
301 xferlevel |= (fifo_depth - 1) << 8;
302 } else {
303 chconf |= OMAP2_MCSPI_CHCONF_FFET;
304 xferlevel |= fifo_depth - 1;
305 }
306
307 mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel);
308 mcspi_write_chconf0(spi, chconf);
309 mcspi->fifo_depth = fifo_depth;
310
311 return;
312 }
313
314 disable_fifo:
315 if (t->rx_buf != NULL)
316 chconf &= ~OMAP2_MCSPI_CHCONF_FFER;
317
318 if (t->tx_buf != NULL)
319 chconf &= ~OMAP2_MCSPI_CHCONF_FFET;
320
321 mcspi_write_chconf0(spi, chconf);
322 mcspi->fifo_depth = 0;
323 }
324
325 static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
326 {
327 struct spi_master *spi_cntrl = mcspi->master;
328 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
329 struct omap2_mcspi_cs *cs;
330
331 /* McSPI: context restore */
332 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
333 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
334
335 list_for_each_entry(cs, &ctx->cs, node)
336 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
337 }
338
339 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
340 {
341 unsigned long timeout;
342
343 timeout = jiffies + msecs_to_jiffies(1000);
344 while (!(__raw_readl(reg) & bit)) {
345 if (time_after(jiffies, timeout)) {
346 if (!(__raw_readl(reg) & bit))
347 return -ETIMEDOUT;
348 else
349 return 0;
350 }
351 cpu_relax();
352 }
353 return 0;
354 }
355
356 static void omap2_mcspi_rx_callback(void *data)
357 {
358 struct spi_device *spi = data;
359 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
360 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
361
362 /* We must disable the DMA RX request */
363 omap2_mcspi_set_dma_req(spi, 1, 0);
364
365 complete(&mcspi_dma->dma_rx_completion);
366 }
367
368 static void omap2_mcspi_tx_callback(void *data)
369 {
370 struct spi_device *spi = data;
371 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
372 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
373
374 /* We must disable the DMA TX request */
375 omap2_mcspi_set_dma_req(spi, 0, 0);
376
377 complete(&mcspi_dma->dma_tx_completion);
378 }
379
380 static void omap2_mcspi_tx_dma(struct spi_device *spi,
381 struct spi_transfer *xfer,
382 struct dma_slave_config cfg)
383 {
384 struct omap2_mcspi *mcspi;
385 struct omap2_mcspi_dma *mcspi_dma;
386 unsigned int count;
387
388 mcspi = spi_master_get_devdata(spi->master);
389 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
390 count = xfer->len;
391
392 if (mcspi_dma->dma_tx) {
393 struct dma_async_tx_descriptor *tx;
394 struct scatterlist sg;
395
396 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
397
398 sg_init_table(&sg, 1);
399 sg_dma_address(&sg) = xfer->tx_dma;
400 sg_dma_len(&sg) = xfer->len;
401
402 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1,
403 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
404 if (tx) {
405 tx->callback = omap2_mcspi_tx_callback;
406 tx->callback_param = spi;
407 dmaengine_submit(tx);
408 } else {
409 /* FIXME: fall back to PIO? */
410 }
411 }
412 dma_async_issue_pending(mcspi_dma->dma_tx);
413 omap2_mcspi_set_dma_req(spi, 0, 1);
414
415 }
416
417 static unsigned
418 omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
419 struct dma_slave_config cfg,
420 unsigned es)
421 {
422 struct omap2_mcspi *mcspi;
423 struct omap2_mcspi_dma *mcspi_dma;
424 unsigned int count, dma_count;
425 u32 l;
426 int elements = 0;
427 int word_len, element_count;
428 struct omap2_mcspi_cs *cs = spi->controller_state;
429 mcspi = spi_master_get_devdata(spi->master);
430 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
431 count = xfer->len;
432 dma_count = xfer->len;
433
434 if (mcspi->fifo_depth == 0)
435 dma_count -= es;
436
437 word_len = cs->word_len;
438 l = mcspi_cached_chconf0(spi);
439
440 if (word_len <= 8)
441 element_count = count;
442 else if (word_len <= 16)
443 element_count = count >> 1;
444 else /* word_len <= 32 */
445 element_count = count >> 2;
446
447 if (mcspi_dma->dma_rx) {
448 struct dma_async_tx_descriptor *tx;
449 struct scatterlist sg;
450
451 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
452
453 if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0)
454 dma_count -= es;
455
456 sg_init_table(&sg, 1);
457 sg_dma_address(&sg) = xfer->rx_dma;
458 sg_dma_len(&sg) = dma_count;
459
460 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1,
461 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT |
462 DMA_CTRL_ACK);
463 if (tx) {
464 tx->callback = omap2_mcspi_rx_callback;
465 tx->callback_param = spi;
466 dmaengine_submit(tx);
467 } else {
468 /* FIXME: fall back to PIO? */
469 }
470 }
471
472 dma_async_issue_pending(mcspi_dma->dma_rx);
473 omap2_mcspi_set_dma_req(spi, 1, 1);
474
475 wait_for_completion(&mcspi_dma->dma_rx_completion);
476 dma_unmap_single(mcspi->dev, xfer->rx_dma, count,
477 DMA_FROM_DEVICE);
478
479 if (mcspi->fifo_depth > 0)
480 return count;
481
482 omap2_mcspi_set_enable(spi, 0);
483
484 elements = element_count - 1;
485
486 if (l & OMAP2_MCSPI_CHCONF_TURBO) {
487 elements--;
488
489 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
490 & OMAP2_MCSPI_CHSTAT_RXS)) {
491 u32 w;
492
493 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
494 if (word_len <= 8)
495 ((u8 *)xfer->rx_buf)[elements++] = w;
496 else if (word_len <= 16)
497 ((u16 *)xfer->rx_buf)[elements++] = w;
498 else /* word_len <= 32 */
499 ((u32 *)xfer->rx_buf)[elements++] = w;
500 } else {
501 int bytes_per_word = mcspi_bytes_per_word(word_len);
502 dev_err(&spi->dev, "DMA RX penultimate word empty");
503 count -= (bytes_per_word << 1);
504 omap2_mcspi_set_enable(spi, 1);
505 return count;
506 }
507 }
508 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
509 & OMAP2_MCSPI_CHSTAT_RXS)) {
510 u32 w;
511
512 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
513 if (word_len <= 8)
514 ((u8 *)xfer->rx_buf)[elements] = w;
515 else if (word_len <= 16)
516 ((u16 *)xfer->rx_buf)[elements] = w;
517 else /* word_len <= 32 */
518 ((u32 *)xfer->rx_buf)[elements] = w;
519 } else {
520 dev_err(&spi->dev, "DMA RX last word empty");
521 count -= mcspi_bytes_per_word(word_len);
522 }
523 omap2_mcspi_set_enable(spi, 1);
524 return count;
525 }
526
527 static unsigned
528 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
529 {
530 struct omap2_mcspi *mcspi;
531 struct omap2_mcspi_cs *cs = spi->controller_state;
532 struct omap2_mcspi_dma *mcspi_dma;
533 unsigned int count;
534 u32 l;
535 u8 *rx;
536 const u8 *tx;
537 struct dma_slave_config cfg;
538 enum dma_slave_buswidth width;
539 unsigned es;
540 u32 burst;
541 void __iomem *chstat_reg;
542 void __iomem *irqstat_reg;
543 int wait_res;
544
545 mcspi = spi_master_get_devdata(spi->master);
546 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
547 l = mcspi_cached_chconf0(spi);
548
549
550 if (cs->word_len <= 8) {
551 width = DMA_SLAVE_BUSWIDTH_1_BYTE;
552 es = 1;
553 } else if (cs->word_len <= 16) {
554 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
555 es = 2;
556 } else {
557 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
558 es = 4;
559 }
560
561 count = xfer->len;
562 burst = 1;
563
564 if (mcspi->fifo_depth > 0) {
565 if (count > mcspi->fifo_depth)
566 burst = mcspi->fifo_depth / es;
567 else
568 burst = count / es;
569 }
570
571 memset(&cfg, 0, sizeof(cfg));
572 cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
573 cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
574 cfg.src_addr_width = width;
575 cfg.dst_addr_width = width;
576 cfg.src_maxburst = burst;
577 cfg.dst_maxburst = burst;
578
579 rx = xfer->rx_buf;
580 tx = xfer->tx_buf;
581
582 if (tx != NULL)
583 omap2_mcspi_tx_dma(spi, xfer, cfg);
584
585 if (rx != NULL)
586 count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
587
588 if (tx != NULL) {
589 wait_for_completion(&mcspi_dma->dma_tx_completion);
590 dma_unmap_single(mcspi->dev, xfer->tx_dma, xfer->len,
591 DMA_TO_DEVICE);
592
593 if (mcspi->fifo_depth > 0) {
594 irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS;
595
596 if (mcspi_wait_for_reg_bit(irqstat_reg,
597 OMAP2_MCSPI_IRQSTATUS_EOW) < 0)
598 dev_err(&spi->dev, "EOW timed out\n");
599
600 mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS,
601 OMAP2_MCSPI_IRQSTATUS_EOW);
602 }
603
604 /* for TX_ONLY mode, be sure all words have shifted out */
605 if (rx == NULL) {
606 chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
607 if (mcspi->fifo_depth > 0) {
608 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
609 OMAP2_MCSPI_CHSTAT_TXFFE);
610 if (wait_res < 0)
611 dev_err(&spi->dev, "TXFFE timed out\n");
612 } else {
613 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
614 OMAP2_MCSPI_CHSTAT_TXS);
615 if (wait_res < 0)
616 dev_err(&spi->dev, "TXS timed out\n");
617 }
618 if (wait_res >= 0 &&
619 (mcspi_wait_for_reg_bit(chstat_reg,
620 OMAP2_MCSPI_CHSTAT_EOT) < 0))
621 dev_err(&spi->dev, "EOT timed out\n");
622 }
623 }
624 return count;
625 }
626
627 static unsigned
628 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
629 {
630 struct omap2_mcspi *mcspi;
631 struct omap2_mcspi_cs *cs = spi->controller_state;
632 unsigned int count, c;
633 u32 l;
634 void __iomem *base = cs->base;
635 void __iomem *tx_reg;
636 void __iomem *rx_reg;
637 void __iomem *chstat_reg;
638 int word_len;
639
640 mcspi = spi_master_get_devdata(spi->master);
641 count = xfer->len;
642 c = count;
643 word_len = cs->word_len;
644
645 l = mcspi_cached_chconf0(spi);
646
647 /* We store the pre-calculated register addresses on stack to speed
648 * up the transfer loop. */
649 tx_reg = base + OMAP2_MCSPI_TX0;
650 rx_reg = base + OMAP2_MCSPI_RX0;
651 chstat_reg = base + OMAP2_MCSPI_CHSTAT0;
652
653 if (c < (word_len>>3))
654 return 0;
655
656 if (word_len <= 8) {
657 u8 *rx;
658 const u8 *tx;
659
660 rx = xfer->rx_buf;
661 tx = xfer->tx_buf;
662
663 do {
664 c -= 1;
665 if (tx != NULL) {
666 if (mcspi_wait_for_reg_bit(chstat_reg,
667 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
668 dev_err(&spi->dev, "TXS timed out\n");
669 goto out;
670 }
671 dev_vdbg(&spi->dev, "write-%d %02x\n",
672 word_len, *tx);
673 __raw_writel(*tx++, tx_reg);
674 }
675 if (rx != NULL) {
676 if (mcspi_wait_for_reg_bit(chstat_reg,
677 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
678 dev_err(&spi->dev, "RXS timed out\n");
679 goto out;
680 }
681
682 if (c == 1 && tx == NULL &&
683 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
684 omap2_mcspi_set_enable(spi, 0);
685 *rx++ = __raw_readl(rx_reg);
686 dev_vdbg(&spi->dev, "read-%d %02x\n",
687 word_len, *(rx - 1));
688 if (mcspi_wait_for_reg_bit(chstat_reg,
689 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
690 dev_err(&spi->dev,
691 "RXS timed out\n");
692 goto out;
693 }
694 c = 0;
695 } else if (c == 0 && tx == NULL) {
696 omap2_mcspi_set_enable(spi, 0);
697 }
698
699 *rx++ = __raw_readl(rx_reg);
700 dev_vdbg(&spi->dev, "read-%d %02x\n",
701 word_len, *(rx - 1));
702 }
703 } while (c);
704 } else if (word_len <= 16) {
705 u16 *rx;
706 const u16 *tx;
707
708 rx = xfer->rx_buf;
709 tx = xfer->tx_buf;
710 do {
711 c -= 2;
712 if (tx != NULL) {
713 if (mcspi_wait_for_reg_bit(chstat_reg,
714 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
715 dev_err(&spi->dev, "TXS timed out\n");
716 goto out;
717 }
718 dev_vdbg(&spi->dev, "write-%d %04x\n",
719 word_len, *tx);
720 __raw_writel(*tx++, tx_reg);
721 }
722 if (rx != NULL) {
723 if (mcspi_wait_for_reg_bit(chstat_reg,
724 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
725 dev_err(&spi->dev, "RXS timed out\n");
726 goto out;
727 }
728
729 if (c == 2 && tx == NULL &&
730 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
731 omap2_mcspi_set_enable(spi, 0);
732 *rx++ = __raw_readl(rx_reg);
733 dev_vdbg(&spi->dev, "read-%d %04x\n",
734 word_len, *(rx - 1));
735 if (mcspi_wait_for_reg_bit(chstat_reg,
736 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
737 dev_err(&spi->dev,
738 "RXS timed out\n");
739 goto out;
740 }
741 c = 0;
742 } else if (c == 0 && tx == NULL) {
743 omap2_mcspi_set_enable(spi, 0);
744 }
745
746 *rx++ = __raw_readl(rx_reg);
747 dev_vdbg(&spi->dev, "read-%d %04x\n",
748 word_len, *(rx - 1));
749 }
750 } while (c >= 2);
751 } else if (word_len <= 32) {
752 u32 *rx;
753 const u32 *tx;
754
755 rx = xfer->rx_buf;
756 tx = xfer->tx_buf;
757 do {
758 c -= 4;
759 if (tx != NULL) {
760 if (mcspi_wait_for_reg_bit(chstat_reg,
761 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
762 dev_err(&spi->dev, "TXS timed out\n");
763 goto out;
764 }
765 dev_vdbg(&spi->dev, "write-%d %08x\n",
766 word_len, *tx);
767 __raw_writel(*tx++, tx_reg);
768 }
769 if (rx != NULL) {
770 if (mcspi_wait_for_reg_bit(chstat_reg,
771 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
772 dev_err(&spi->dev, "RXS timed out\n");
773 goto out;
774 }
775
776 if (c == 4 && tx == NULL &&
777 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
778 omap2_mcspi_set_enable(spi, 0);
779 *rx++ = __raw_readl(rx_reg);
780 dev_vdbg(&spi->dev, "read-%d %08x\n",
781 word_len, *(rx - 1));
782 if (mcspi_wait_for_reg_bit(chstat_reg,
783 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
784 dev_err(&spi->dev,
785 "RXS timed out\n");
786 goto out;
787 }
788 c = 0;
789 } else if (c == 0 && tx == NULL) {
790 omap2_mcspi_set_enable(spi, 0);
791 }
792
793 *rx++ = __raw_readl(rx_reg);
794 dev_vdbg(&spi->dev, "read-%d %08x\n",
795 word_len, *(rx - 1));
796 }
797 } while (c >= 4);
798 }
799
800 /* for TX_ONLY mode, be sure all words have shifted out */
801 if (xfer->rx_buf == NULL) {
802 if (mcspi_wait_for_reg_bit(chstat_reg,
803 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
804 dev_err(&spi->dev, "TXS timed out\n");
805 } else if (mcspi_wait_for_reg_bit(chstat_reg,
806 OMAP2_MCSPI_CHSTAT_EOT) < 0)
807 dev_err(&spi->dev, "EOT timed out\n");
808
809 /* disable chan to purge rx datas received in TX_ONLY transfer,
810 * otherwise these rx datas will affect the direct following
811 * RX_ONLY transfer.
812 */
813 omap2_mcspi_set_enable(spi, 0);
814 }
815 out:
816 omap2_mcspi_set_enable(spi, 1);
817 return count - c;
818 }
819
820 static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
821 {
822 u32 div;
823
824 for (div = 0; div < 15; div++)
825 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
826 return div;
827
828 return 15;
829 }
830
831 /* called only when no transfer is active to this device */
832 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
833 struct spi_transfer *t)
834 {
835 struct omap2_mcspi_cs *cs = spi->controller_state;
836 struct omap2_mcspi *mcspi;
837 struct spi_master *spi_cntrl;
838 u32 l = 0, div = 0;
839 u8 word_len = spi->bits_per_word;
840 u32 speed_hz = spi->max_speed_hz;
841
842 mcspi = spi_master_get_devdata(spi->master);
843 spi_cntrl = mcspi->master;
844
845 if (t != NULL && t->bits_per_word)
846 word_len = t->bits_per_word;
847
848 cs->word_len = word_len;
849
850 if (t && t->speed_hz)
851 speed_hz = t->speed_hz;
852
853 speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
854 div = omap2_mcspi_calc_divisor(speed_hz);
855
856 l = mcspi_cached_chconf0(spi);
857
858 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
859 * REVISIT: this controller could support SPI_3WIRE mode.
860 */
861 if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
862 l &= ~OMAP2_MCSPI_CHCONF_IS;
863 l &= ~OMAP2_MCSPI_CHCONF_DPE1;
864 l |= OMAP2_MCSPI_CHCONF_DPE0;
865 } else {
866 l |= OMAP2_MCSPI_CHCONF_IS;
867 l |= OMAP2_MCSPI_CHCONF_DPE1;
868 l &= ~OMAP2_MCSPI_CHCONF_DPE0;
869 }
870
871 /* wordlength */
872 l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
873 l |= (word_len - 1) << 7;
874
875 /* set chipselect polarity; manage with FORCE */
876 if (!(spi->mode & SPI_CS_HIGH))
877 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */
878 else
879 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
880
881 /* set clock divisor */
882 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
883 l |= div << 2;
884
885 /* set SPI mode 0..3 */
886 if (spi->mode & SPI_CPOL)
887 l |= OMAP2_MCSPI_CHCONF_POL;
888 else
889 l &= ~OMAP2_MCSPI_CHCONF_POL;
890 if (spi->mode & SPI_CPHA)
891 l |= OMAP2_MCSPI_CHCONF_PHA;
892 else
893 l &= ~OMAP2_MCSPI_CHCONF_PHA;
894
895 mcspi_write_chconf0(spi, l);
896
897 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
898 OMAP2_MCSPI_MAX_FREQ >> div,
899 (spi->mode & SPI_CPHA) ? "trailing" : "leading",
900 (spi->mode & SPI_CPOL) ? "inverted" : "normal");
901
902 return 0;
903 }
904
905 /*
906 * Note that we currently allow DMA only if we get a channel
907 * for both rx and tx. Otherwise we'll do PIO for both rx and tx.
908 */
909 static int omap2_mcspi_request_dma(struct spi_device *spi)
910 {
911 struct spi_master *master = spi->master;
912 struct omap2_mcspi *mcspi;
913 struct omap2_mcspi_dma *mcspi_dma;
914 dma_cap_mask_t mask;
915 unsigned sig;
916
917 mcspi = spi_master_get_devdata(master);
918 mcspi_dma = mcspi->dma_channels + spi->chip_select;
919
920 init_completion(&mcspi_dma->dma_rx_completion);
921 init_completion(&mcspi_dma->dma_tx_completion);
922
923 dma_cap_zero(mask);
924 dma_cap_set(DMA_SLAVE, mask);
925 sig = mcspi_dma->dma_rx_sync_dev;
926
927 mcspi_dma->dma_rx =
928 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
929 &sig, &master->dev,
930 mcspi_dma->dma_rx_ch_name);
931 if (!mcspi_dma->dma_rx)
932 goto no_dma;
933
934 sig = mcspi_dma->dma_tx_sync_dev;
935 mcspi_dma->dma_tx =
936 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
937 &sig, &master->dev,
938 mcspi_dma->dma_tx_ch_name);
939
940 if (!mcspi_dma->dma_tx) {
941 dma_release_channel(mcspi_dma->dma_rx);
942 mcspi_dma->dma_rx = NULL;
943 goto no_dma;
944 }
945
946 return 0;
947
948 no_dma:
949 dev_warn(&spi->dev, "not using DMA for McSPI\n");
950 return -EAGAIN;
951 }
952
953 static int omap2_mcspi_setup(struct spi_device *spi)
954 {
955 int ret;
956 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
957 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
958 struct omap2_mcspi_dma *mcspi_dma;
959 struct omap2_mcspi_cs *cs = spi->controller_state;
960
961 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
962
963 if (!cs) {
964 cs = kzalloc(sizeof *cs, GFP_KERNEL);
965 if (!cs)
966 return -ENOMEM;
967 cs->base = mcspi->base + spi->chip_select * 0x14;
968 cs->phys = mcspi->phys + spi->chip_select * 0x14;
969 cs->chconf0 = 0;
970 spi->controller_state = cs;
971 /* Link this to context save list */
972 list_add_tail(&cs->node, &ctx->cs);
973 }
974
975 if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) {
976 ret = omap2_mcspi_request_dma(spi);
977 if (ret < 0 && ret != -EAGAIN)
978 return ret;
979 }
980
981 ret = pm_runtime_get_sync(mcspi->dev);
982 if (ret < 0)
983 return ret;
984
985 ret = omap2_mcspi_setup_transfer(spi, NULL);
986 pm_runtime_mark_last_busy(mcspi->dev);
987 pm_runtime_put_autosuspend(mcspi->dev);
988
989 return ret;
990 }
991
992 static void omap2_mcspi_cleanup(struct spi_device *spi)
993 {
994 struct omap2_mcspi *mcspi;
995 struct omap2_mcspi_dma *mcspi_dma;
996 struct omap2_mcspi_cs *cs;
997
998 mcspi = spi_master_get_devdata(spi->master);
999
1000 if (spi->controller_state) {
1001 /* Unlink controller state from context save list */
1002 cs = spi->controller_state;
1003 list_del(&cs->node);
1004
1005 kfree(cs);
1006 }
1007
1008 if (spi->chip_select < spi->master->num_chipselect) {
1009 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
1010
1011 if (mcspi_dma->dma_rx) {
1012 dma_release_channel(mcspi_dma->dma_rx);
1013 mcspi_dma->dma_rx = NULL;
1014 }
1015 if (mcspi_dma->dma_tx) {
1016 dma_release_channel(mcspi_dma->dma_tx);
1017 mcspi_dma->dma_tx = NULL;
1018 }
1019 }
1020 }
1021
1022 static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m)
1023 {
1024
1025 /* We only enable one channel at a time -- the one whose message is
1026 * -- although this controller would gladly
1027 * arbitrate among multiple channels. This corresponds to "single
1028 * channel" master mode. As a side effect, we need to manage the
1029 * chipselect with the FORCE bit ... CS != channel enable.
1030 */
1031
1032 struct spi_device *spi;
1033 struct spi_transfer *t = NULL;
1034 struct spi_master *master;
1035 struct omap2_mcspi_dma *mcspi_dma;
1036 int cs_active = 0;
1037 struct omap2_mcspi_cs *cs;
1038 struct omap2_mcspi_device_config *cd;
1039 int par_override = 0;
1040 int status = 0;
1041 u32 chconf;
1042
1043 spi = m->spi;
1044 master = spi->master;
1045 mcspi_dma = mcspi->dma_channels + spi->chip_select;
1046 cs = spi->controller_state;
1047 cd = spi->controller_data;
1048
1049 omap2_mcspi_set_enable(spi, 0);
1050 list_for_each_entry(t, &m->transfers, transfer_list) {
1051 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
1052 status = -EINVAL;
1053 break;
1054 }
1055 if (par_override || t->speed_hz || t->bits_per_word) {
1056 par_override = 1;
1057 status = omap2_mcspi_setup_transfer(spi, t);
1058 if (status < 0)
1059 break;
1060 if (!t->speed_hz && !t->bits_per_word)
1061 par_override = 0;
1062 }
1063 if (cd && cd->cs_per_word) {
1064 chconf = mcspi->ctx.modulctrl;
1065 chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE;
1066 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1067 mcspi->ctx.modulctrl =
1068 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1069 }
1070
1071
1072 if (!cs_active) {
1073 omap2_mcspi_force_cs(spi, 1);
1074 cs_active = 1;
1075 }
1076
1077 chconf = mcspi_cached_chconf0(spi);
1078 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
1079 chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
1080
1081 if (t->tx_buf == NULL)
1082 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
1083 else if (t->rx_buf == NULL)
1084 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
1085
1086 if (cd && cd->turbo_mode && t->tx_buf == NULL) {
1087 /* Turbo mode is for more than one word */
1088 if (t->len > ((cs->word_len + 7) >> 3))
1089 chconf |= OMAP2_MCSPI_CHCONF_TURBO;
1090 }
1091
1092 mcspi_write_chconf0(spi, chconf);
1093
1094 if (t->len) {
1095 unsigned count;
1096
1097 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1098 (m->is_dma_mapped || t->len >= DMA_MIN_BYTES))
1099 omap2_mcspi_set_fifo(spi, t, 1);
1100
1101 omap2_mcspi_set_enable(spi, 1);
1102
1103 /* RX_ONLY mode needs dummy data in TX reg */
1104 if (t->tx_buf == NULL)
1105 __raw_writel(0, cs->base
1106 + OMAP2_MCSPI_TX0);
1107
1108 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1109 (m->is_dma_mapped || t->len >= DMA_MIN_BYTES))
1110 count = omap2_mcspi_txrx_dma(spi, t);
1111 else
1112 count = omap2_mcspi_txrx_pio(spi, t);
1113 m->actual_length += count;
1114
1115 if (count != t->len) {
1116 status = -EIO;
1117 break;
1118 }
1119 }
1120
1121 if (t->delay_usecs)
1122 udelay(t->delay_usecs);
1123
1124 /* ignore the "leave it on after last xfer" hint */
1125 if (t->cs_change) {
1126 omap2_mcspi_force_cs(spi, 0);
1127 cs_active = 0;
1128 }
1129
1130 omap2_mcspi_set_enable(spi, 0);
1131
1132 if (mcspi->fifo_depth > 0)
1133 omap2_mcspi_set_fifo(spi, t, 0);
1134 }
1135 /* Restore defaults if they were overriden */
1136 if (par_override) {
1137 par_override = 0;
1138 status = omap2_mcspi_setup_transfer(spi, NULL);
1139 }
1140
1141 if (cs_active)
1142 omap2_mcspi_force_cs(spi, 0);
1143
1144 if (cd && cd->cs_per_word) {
1145 chconf = mcspi->ctx.modulctrl;
1146 chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE;
1147 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1148 mcspi->ctx.modulctrl =
1149 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1150 }
1151
1152 omap2_mcspi_set_enable(spi, 0);
1153
1154 if (mcspi->fifo_depth > 0 && t)
1155 omap2_mcspi_set_fifo(spi, t, 0);
1156
1157 m->status = status;
1158 }
1159
1160 static int omap2_mcspi_transfer_one_message(struct spi_master *master,
1161 struct spi_message *m)
1162 {
1163 struct spi_device *spi;
1164 struct omap2_mcspi *mcspi;
1165 struct omap2_mcspi_dma *mcspi_dma;
1166 struct spi_transfer *t;
1167
1168 spi = m->spi;
1169 mcspi = spi_master_get_devdata(master);
1170 mcspi_dma = mcspi->dma_channels + spi->chip_select;
1171 m->actual_length = 0;
1172 m->status = 0;
1173
1174 /* reject invalid messages and transfers */
1175 if (list_empty(&m->transfers))
1176 return -EINVAL;
1177 list_for_each_entry(t, &m->transfers, transfer_list) {
1178 const void *tx_buf = t->tx_buf;
1179 void *rx_buf = t->rx_buf;
1180 unsigned len = t->len;
1181
1182 if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
1183 || (len && !(rx_buf || tx_buf))) {
1184 dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
1185 t->speed_hz,
1186 len,
1187 tx_buf ? "tx" : "",
1188 rx_buf ? "rx" : "",
1189 t->bits_per_word);
1190 return -EINVAL;
1191 }
1192 if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) {
1193 dev_dbg(mcspi->dev, "speed_hz %d below minimum %d Hz\n",
1194 t->speed_hz,
1195 OMAP2_MCSPI_MAX_FREQ >> 15);
1196 return -EINVAL;
1197 }
1198
1199 if (m->is_dma_mapped || len < DMA_MIN_BYTES)
1200 continue;
1201
1202 if (mcspi_dma->dma_tx && tx_buf != NULL) {
1203 t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf,
1204 len, DMA_TO_DEVICE);
1205 if (dma_mapping_error(mcspi->dev, t->tx_dma)) {
1206 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
1207 'T', len);
1208 return -EINVAL;
1209 }
1210 }
1211 if (mcspi_dma->dma_rx && rx_buf != NULL) {
1212 t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len,
1213 DMA_FROM_DEVICE);
1214 if (dma_mapping_error(mcspi->dev, t->rx_dma)) {
1215 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
1216 'R', len);
1217 if (tx_buf != NULL)
1218 dma_unmap_single(mcspi->dev, t->tx_dma,
1219 len, DMA_TO_DEVICE);
1220 return -EINVAL;
1221 }
1222 }
1223 }
1224
1225 omap2_mcspi_work(mcspi, m);
1226 spi_finalize_current_message(master);
1227 return 0;
1228 }
1229
1230 static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
1231 {
1232 struct spi_master *master = mcspi->master;
1233 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1234 int ret = 0;
1235
1236 ret = pm_runtime_get_sync(mcspi->dev);
1237 if (ret < 0)
1238 return ret;
1239
1240 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
1241 OMAP2_MCSPI_WAKEUPENABLE_WKEN);
1242 ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1243
1244 omap2_mcspi_set_master_mode(master);
1245 pm_runtime_mark_last_busy(mcspi->dev);
1246 pm_runtime_put_autosuspend(mcspi->dev);
1247 return 0;
1248 }
1249
1250 static int omap_mcspi_runtime_resume(struct device *dev)
1251 {
1252 struct omap2_mcspi *mcspi;
1253 struct spi_master *master;
1254
1255 master = dev_get_drvdata(dev);
1256 mcspi = spi_master_get_devdata(master);
1257 omap2_mcspi_restore_ctx(mcspi);
1258
1259 return 0;
1260 }
1261
1262 static struct omap2_mcspi_platform_config omap2_pdata = {
1263 .regs_offset = 0,
1264 };
1265
1266 static struct omap2_mcspi_platform_config omap4_pdata = {
1267 .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1268 };
1269
1270 static const struct of_device_id omap_mcspi_of_match[] = {
1271 {
1272 .compatible = "ti,omap2-mcspi",
1273 .data = &omap2_pdata,
1274 },
1275 {
1276 .compatible = "ti,omap4-mcspi",
1277 .data = &omap4_pdata,
1278 },
1279 { },
1280 };
1281 MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
1282
1283 static int omap2_mcspi_probe(struct platform_device *pdev)
1284 {
1285 struct spi_master *master;
1286 const struct omap2_mcspi_platform_config *pdata;
1287 struct omap2_mcspi *mcspi;
1288 struct resource *r;
1289 int status = 0, i;
1290 u32 regs_offset = 0;
1291 static int bus_num = 1;
1292 struct device_node *node = pdev->dev.of_node;
1293 const struct of_device_id *match;
1294
1295 master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1296 if (master == NULL) {
1297 dev_dbg(&pdev->dev, "master allocation failed\n");
1298 return -ENOMEM;
1299 }
1300
1301 /* the spi->mode bits understood by this driver: */
1302 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1303 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1304 master->setup = omap2_mcspi_setup;
1305 master->auto_runtime_pm = true;
1306 master->transfer_one_message = omap2_mcspi_transfer_one_message;
1307 master->cleanup = omap2_mcspi_cleanup;
1308 master->dev.of_node = node;
1309
1310 platform_set_drvdata(pdev, master);
1311
1312 mcspi = spi_master_get_devdata(master);
1313 mcspi->master = master;
1314
1315 match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1316 if (match) {
1317 u32 num_cs = 1; /* default number of chipselect */
1318 pdata = match->data;
1319
1320 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1321 master->num_chipselect = num_cs;
1322 master->bus_num = bus_num++;
1323 if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL))
1324 mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
1325 } else {
1326 pdata = dev_get_platdata(&pdev->dev);
1327 master->num_chipselect = pdata->num_cs;
1328 if (pdev->id != -1)
1329 master->bus_num = pdev->id;
1330 mcspi->pin_dir = pdata->pin_dir;
1331 }
1332 regs_offset = pdata->regs_offset;
1333
1334 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1335 if (r == NULL) {
1336 status = -ENODEV;
1337 goto free_master;
1338 }
1339
1340 r->start += regs_offset;
1341 r->end += regs_offset;
1342 mcspi->phys = r->start;
1343
1344 mcspi->base = devm_ioremap_resource(&pdev->dev, r);
1345 if (IS_ERR(mcspi->base)) {
1346 status = PTR_ERR(mcspi->base);
1347 goto free_master;
1348 }
1349
1350 mcspi->dev = &pdev->dev;
1351
1352 INIT_LIST_HEAD(&mcspi->ctx.cs);
1353
1354 mcspi->dma_channels = kcalloc(master->num_chipselect,
1355 sizeof(struct omap2_mcspi_dma),
1356 GFP_KERNEL);
1357
1358 if (mcspi->dma_channels == NULL)
1359 goto free_master;
1360
1361 for (i = 0; i < master->num_chipselect; i++) {
1362 char *dma_rx_ch_name = mcspi->dma_channels[i].dma_rx_ch_name;
1363 char *dma_tx_ch_name = mcspi->dma_channels[i].dma_tx_ch_name;
1364 struct resource *dma_res;
1365
1366 sprintf(dma_rx_ch_name, "rx%d", i);
1367 if (!pdev->dev.of_node) {
1368 dma_res =
1369 platform_get_resource_byname(pdev,
1370 IORESOURCE_DMA,
1371 dma_rx_ch_name);
1372 if (!dma_res) {
1373 dev_dbg(&pdev->dev,
1374 "cannot get DMA RX channel\n");
1375 status = -ENODEV;
1376 break;
1377 }
1378
1379 mcspi->dma_channels[i].dma_rx_sync_dev =
1380 dma_res->start;
1381 }
1382 sprintf(dma_tx_ch_name, "tx%d", i);
1383 if (!pdev->dev.of_node) {
1384 dma_res =
1385 platform_get_resource_byname(pdev,
1386 IORESOURCE_DMA,
1387 dma_tx_ch_name);
1388 if (!dma_res) {
1389 dev_dbg(&pdev->dev,
1390 "cannot get DMA TX channel\n");
1391 status = -ENODEV;
1392 break;
1393 }
1394
1395 mcspi->dma_channels[i].dma_tx_sync_dev =
1396 dma_res->start;
1397 }
1398 }
1399
1400 if (status < 0)
1401 goto dma_chnl_free;
1402
1403 pm_runtime_use_autosuspend(&pdev->dev);
1404 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1405 pm_runtime_enable(&pdev->dev);
1406
1407 status = omap2_mcspi_master_setup(mcspi);
1408 if (status < 0)
1409 goto disable_pm;
1410
1411 status = spi_register_master(master);
1412 if (status < 0)
1413 goto disable_pm;
1414
1415 return status;
1416
1417 disable_pm:
1418 pm_runtime_disable(&pdev->dev);
1419 dma_chnl_free:
1420 kfree(mcspi->dma_channels);
1421 free_master:
1422 spi_master_put(master);
1423 return status;
1424 }
1425
1426 static int omap2_mcspi_remove(struct platform_device *pdev)
1427 {
1428 struct spi_master *master;
1429 struct omap2_mcspi *mcspi;
1430 struct omap2_mcspi_dma *dma_channels;
1431
1432 master = platform_get_drvdata(pdev);
1433 mcspi = spi_master_get_devdata(master);
1434 dma_channels = mcspi->dma_channels;
1435
1436 pm_runtime_put_sync(mcspi->dev);
1437 pm_runtime_disable(&pdev->dev);
1438
1439 spi_unregister_master(master);
1440 kfree(dma_channels);
1441
1442 return 0;
1443 }
1444
1445 /* work with hotplug and coldplug */
1446 MODULE_ALIAS("platform:omap2_mcspi");
1447
1448 #ifdef CONFIG_SUSPEND
1449 /*
1450 * When SPI wake up from off-mode, CS is in activate state. If it was in
1451 * unactive state when driver was suspend, then force it to unactive state at
1452 * wake up.
1453 */
1454 static int omap2_mcspi_resume(struct device *dev)
1455 {
1456 struct spi_master *master = dev_get_drvdata(dev);
1457 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1458 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1459 struct omap2_mcspi_cs *cs;
1460
1461 pm_runtime_get_sync(mcspi->dev);
1462 list_for_each_entry(cs, &ctx->cs, node) {
1463 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
1464 /*
1465 * We need to toggle CS state for OMAP take this
1466 * change in account.
1467 */
1468 cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
1469 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1470 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1471 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1472 }
1473 }
1474 pm_runtime_mark_last_busy(mcspi->dev);
1475 pm_runtime_put_autosuspend(mcspi->dev);
1476 return 0;
1477 }
1478 #else
1479 #define omap2_mcspi_resume NULL
1480 #endif
1481
1482 static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1483 .resume = omap2_mcspi_resume,
1484 .runtime_resume = omap_mcspi_runtime_resume,
1485 };
1486
1487 static struct platform_driver omap2_mcspi_driver = {
1488 .driver = {
1489 .name = "omap2_mcspi",
1490 .owner = THIS_MODULE,
1491 .pm = &omap2_mcspi_pm_ops,
1492 .of_match_table = omap_mcspi_of_match,
1493 },
1494 .probe = omap2_mcspi_probe,
1495 .remove = omap2_mcspi_remove,
1496 };
1497
1498 module_platform_driver(omap2_mcspi_driver);
1499 MODULE_LICENSE("GPL");
Linux with added FPC-III support