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Linux 3.12.39
[linux/fpc-iii.git] / drivers / tty / serial / atmel_serial.c
blobebdc00f184a142754a95627d204a6538aacae857
1 /*
2 * Driver for Atmel AT91 / AT32 Serial ports
3 * Copyright (C) 2003 Rick Bronson
4 *
5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * DMA support added by Chip Coldwell.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25 #include <linux/module.h>
26 #include <linux/tty.h>
27 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/init.h>
30 #include <linux/serial.h>
31 #include <linux/clk.h>
32 #include <linux/console.h>
33 #include <linux/sysrq.h>
34 #include <linux/tty_flip.h>
35 #include <linux/platform_device.h>
36 #include <linux/of.h>
37 #include <linux/of_device.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/atmel_pdc.h>
40 #include <linux/atmel_serial.h>
41 #include <linux/uaccess.h>
42 #include <linux/platform_data/atmel.h>
43 #include <linux/timer.h>
44
45 #include <asm/io.h>
46 #include <asm/ioctls.h>
47
48 #ifdef CONFIG_ARM
49 #include <mach/cpu.h>
50 #include <asm/gpio.h>
51 #endif
52
53 #define PDC_BUFFER_SIZE 512
54 /* Revisit: We should calculate this based on the actual port settings */
55 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
56
57 #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
58 #define SUPPORT_SYSRQ
59 #endif
60
61 #include <linux/serial_core.h>
62
63 static void atmel_start_rx(struct uart_port *port);
64 static void atmel_stop_rx(struct uart_port *port);
65
66 #ifdef CONFIG_SERIAL_ATMEL_TTYAT
67
68 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
69 * should coexist with the 8250 driver, such as if we have an external 16C550
70 * UART. */
71 #define SERIAL_ATMEL_MAJOR 204
72 #define MINOR_START 154
73 #define ATMEL_DEVICENAME "ttyAT"
74
75 #else
76
77 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
78 * name, but it is legally reserved for the 8250 driver. */
79 #define SERIAL_ATMEL_MAJOR TTY_MAJOR
80 #define MINOR_START 64
81 #define ATMEL_DEVICENAME "ttyS"
82
83 #endif
84
85 #define ATMEL_ISR_PASS_LIMIT 256
86
87 /* UART registers. CR is write-only, hence no GET macro */
88 #define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR)
89 #define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR)
90 #define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR)
91 #define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER)
92 #define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR)
93 #define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR)
94 #define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR)
95 #define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR)
96 #define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR)
97 #define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR)
98 #define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR)
99 #define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR)
100 #define UART_PUT_TTGR(port, v) __raw_writel(v, (port)->membase + ATMEL_US_TTGR)
101 #define UART_GET_IP_NAME(port) __raw_readl((port)->membase + ATMEL_US_NAME)
102
103 /* PDC registers */
104 #define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR)
105 #define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR)
106
107 #define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR)
108 #define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR)
109 #define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR)
110 #define UART_PUT_RNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNPR)
111 #define UART_PUT_RNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNCR)
112
113 #define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR)
114 #define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR)
115 #define UART_GET_TCR(port) __raw_readl((port)->membase + ATMEL_PDC_TCR)
116
117 static int (*atmel_open_hook)(struct uart_port *);
118 static void (*atmel_close_hook)(struct uart_port *);
119
120 struct atmel_dma_buffer {
121 unsigned char *buf;
122 dma_addr_t dma_addr;
123 unsigned int dma_size;
124 unsigned int ofs;
125 };
126
127 struct atmel_uart_char {
128 u16 status;
129 u16 ch;
130 };
131
132 #define ATMEL_SERIAL_RINGSIZE 1024
133
134 /*
135 * We wrap our port structure around the generic uart_port.
136 */
137 struct atmel_uart_port {
138 struct uart_port uart; /* uart */
139 struct clk *clk; /* uart clock */
140 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
141 u32 backup_imr; /* IMR saved during suspend */
142 int break_active; /* break being received */
143
144 bool use_dma_rx; /* enable DMA receiver */
145 bool use_pdc_rx; /* enable PDC receiver */
146 short pdc_rx_idx; /* current PDC RX buffer */
147 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
148
149 bool use_dma_tx; /* enable DMA transmitter */
150 bool use_pdc_tx; /* enable PDC transmitter */
151 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
152
153 spinlock_t lock_tx; /* port lock */
154 spinlock_t lock_rx; /* port lock */
155 struct dma_chan *chan_tx;
156 struct dma_chan *chan_rx;
157 struct dma_async_tx_descriptor *desc_tx;
158 struct dma_async_tx_descriptor *desc_rx;
159 dma_cookie_t cookie_tx;
160 dma_cookie_t cookie_rx;
161 struct scatterlist sg_tx;
162 struct scatterlist sg_rx;
163 struct tasklet_struct tasklet;
164 unsigned int irq_status;
165 unsigned int irq_status_prev;
166
167 struct circ_buf rx_ring;
168
169 struct serial_rs485 rs485; /* rs485 settings */
170 unsigned int tx_done_mask;
171 bool is_usart; /* usart or uart */
172 struct timer_list uart_timer; /* uart timer */
173 int (*prepare_rx)(struct uart_port *port);
174 int (*prepare_tx)(struct uart_port *port);
175 void (*schedule_rx)(struct uart_port *port);
176 void (*schedule_tx)(struct uart_port *port);
177 void (*release_rx)(struct uart_port *port);
178 void (*release_tx)(struct uart_port *port);
179 };
180
181 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
182 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
183
184 #ifdef SUPPORT_SYSRQ
185 static struct console atmel_console;
186 #endif
187
188 #if defined(CONFIG_OF)
189 static const struct of_device_id atmel_serial_dt_ids[] = {
190 { .compatible = "atmel,at91rm9200-usart" },
191 { .compatible = "atmel,at91sam9260-usart" },
192 { /* sentinel */ }
193 };
194
195 MODULE_DEVICE_TABLE(of, atmel_serial_dt_ids);
196 #endif
197
198 static inline struct atmel_uart_port *
199 to_atmel_uart_port(struct uart_port *uart)
200 {
201 return container_of(uart, struct atmel_uart_port, uart);
202 }
203
204 #ifdef CONFIG_SERIAL_ATMEL_PDC
205 static bool atmel_use_pdc_rx(struct uart_port *port)
206 {
207 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
208
209 return atmel_port->use_pdc_rx;
210 }
211
212 static bool atmel_use_pdc_tx(struct uart_port *port)
213 {
214 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
215
216 return atmel_port->use_pdc_tx;
217 }
218 #else
219 static bool atmel_use_pdc_rx(struct uart_port *port)
220 {
221 return false;
222 }
223
224 static bool atmel_use_pdc_tx(struct uart_port *port)
225 {
226 return false;
227 }
228 #endif
229
230 static bool atmel_use_dma_tx(struct uart_port *port)
231 {
232 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
233
234 return atmel_port->use_dma_tx;
235 }
236
237 static bool atmel_use_dma_rx(struct uart_port *port)
238 {
239 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
240
241 return atmel_port->use_dma_rx;
242 }
243
244 /* Enable or disable the rs485 support */
245 void atmel_config_rs485(struct uart_port *port, struct serial_rs485 *rs485conf)
246 {
247 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
248 unsigned int mode;
249 unsigned long flags;
250
251 spin_lock_irqsave(&port->lock, flags);
252
253 /* Disable interrupts */
254 UART_PUT_IDR(port, atmel_port->tx_done_mask);
255
256 mode = UART_GET_MR(port);
257
258 /* Resetting serial mode to RS232 (0x0) */
259 mode &= ~ATMEL_US_USMODE;
260
261 atmel_port->rs485 = *rs485conf;
262
263 if (rs485conf->flags & SER_RS485_ENABLED) {
264 dev_dbg(port->dev, "Setting UART to RS485\n");
265 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
266 if ((rs485conf->delay_rts_after_send) > 0)
267 UART_PUT_TTGR(port, rs485conf->delay_rts_after_send);
268 mode |= ATMEL_US_USMODE_RS485;
269 } else {
270 dev_dbg(port->dev, "Setting UART to RS232\n");
271 if (atmel_use_pdc_tx(port))
272 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
273 ATMEL_US_TXBUFE;
274 else
275 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
276 }
277 UART_PUT_MR(port, mode);
278
279 /* Enable interrupts */
280 UART_PUT_IER(port, atmel_port->tx_done_mask);
281
282 spin_unlock_irqrestore(&port->lock, flags);
283
284 }
285
286 /*
287 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
288 */
289 static u_int atmel_tx_empty(struct uart_port *port)
290 {
291 return (UART_GET_CSR(port) & ATMEL_US_TXEMPTY) ? TIOCSER_TEMT : 0;
292 }
293
294 /*
295 * Set state of the modem control output lines
296 */
297 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
298 {
299 unsigned int control = 0;
300 unsigned int mode;
301 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
302
303 #ifdef CONFIG_ARCH_AT91RM9200
304 if (cpu_is_at91rm9200()) {
305 /*
306 * AT91RM9200 Errata #39: RTS0 is not internally connected
307 * to PA21. We need to drive the pin manually.
308 */
309 if (port->mapbase == AT91RM9200_BASE_US0) {
310 if (mctrl & TIOCM_RTS)
311 at91_set_gpio_value(AT91_PIN_PA21, 0);
312 else
313 at91_set_gpio_value(AT91_PIN_PA21, 1);
314 }
315 }
316 #endif
317
318 if (mctrl & TIOCM_RTS)
319 control |= ATMEL_US_RTSEN;
320 else
321 control |= ATMEL_US_RTSDIS;
322
323 if (mctrl & TIOCM_DTR)
324 control |= ATMEL_US_DTREN;
325 else
326 control |= ATMEL_US_DTRDIS;
327
328 UART_PUT_CR(port, control);
329
330 /* Local loopback mode? */
331 mode = UART_GET_MR(port) & ~ATMEL_US_CHMODE;
332 if (mctrl & TIOCM_LOOP)
333 mode |= ATMEL_US_CHMODE_LOC_LOOP;
334 else
335 mode |= ATMEL_US_CHMODE_NORMAL;
336
337 /* Resetting serial mode to RS232 (0x0) */
338 mode &= ~ATMEL_US_USMODE;
339
340 if (atmel_port->rs485.flags & SER_RS485_ENABLED) {
341 dev_dbg(port->dev, "Setting UART to RS485\n");
342 if ((atmel_port->rs485.delay_rts_after_send) > 0)
343 UART_PUT_TTGR(port,
344 atmel_port->rs485.delay_rts_after_send);
345 mode |= ATMEL_US_USMODE_RS485;
346 } else {
347 dev_dbg(port->dev, "Setting UART to RS232\n");
348 }
349 UART_PUT_MR(port, mode);
350 }
351
352 /*
353 * Get state of the modem control input lines
354 */
355 static u_int atmel_get_mctrl(struct uart_port *port)
356 {
357 unsigned int status, ret = 0;
358
359 status = UART_GET_CSR(port);
360
361 /*
362 * The control signals are active low.
363 */
364 if (!(status & ATMEL_US_DCD))
365 ret |= TIOCM_CD;
366 if (!(status & ATMEL_US_CTS))
367 ret |= TIOCM_CTS;
368 if (!(status & ATMEL_US_DSR))
369 ret |= TIOCM_DSR;
370 if (!(status & ATMEL_US_RI))
371 ret |= TIOCM_RI;
372
373 return ret;
374 }
375
376 /*
377 * Stop transmitting.
378 */
379 static void atmel_stop_tx(struct uart_port *port)
380 {
381 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
382
383 if (atmel_use_pdc_tx(port)) {
384 /* disable PDC transmit */
385 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
386 }
387 /* Disable interrupts */
388 UART_PUT_IDR(port, atmel_port->tx_done_mask);
389
390 if ((atmel_port->rs485.flags & SER_RS485_ENABLED) &&
391 !(atmel_port->rs485.flags & SER_RS485_RX_DURING_TX))
392 atmel_start_rx(port);
393 }
394
395 /*
396 * Start transmitting.
397 */
398 static void atmel_start_tx(struct uart_port *port)
399 {
400 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
401
402 if (atmel_use_pdc_tx(port)) {
403 if (UART_GET_PTSR(port) & ATMEL_PDC_TXTEN)
404 /* The transmitter is already running. Yes, we
405 really need this.*/
406 return;
407
408 if ((atmel_port->rs485.flags & SER_RS485_ENABLED) &&
409 !(atmel_port->rs485.flags & SER_RS485_RX_DURING_TX))
410 atmel_stop_rx(port);
411
412 /* re-enable PDC transmit */
413 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
414 }
415 /* Enable interrupts */
416 UART_PUT_IER(port, atmel_port->tx_done_mask);
417 }
418
419 /*
420 * start receiving - port is in process of being opened.
421 */
422 static void atmel_start_rx(struct uart_port *port)
423 {
424 UART_PUT_CR(port, ATMEL_US_RSTSTA); /* reset status and receiver */
425
426 UART_PUT_CR(port, ATMEL_US_RXEN);
427
428 if (atmel_use_pdc_rx(port)) {
429 /* enable PDC controller */
430 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
431 port->read_status_mask);
432 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN);
433 } else {
434 UART_PUT_IER(port, ATMEL_US_RXRDY);
435 }
436 }
437
438 /*
439 * Stop receiving - port is in process of being closed.
440 */
441 static void atmel_stop_rx(struct uart_port *port)
442 {
443 UART_PUT_CR(port, ATMEL_US_RXDIS);
444
445 if (atmel_use_pdc_rx(port)) {
446 /* disable PDC receive */
447 UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS);
448 UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
449 port->read_status_mask);
450 } else {
451 UART_PUT_IDR(port, ATMEL_US_RXRDY);
452 }
453 }
454
455 /*
456 * Enable modem status interrupts
457 */
458 static void atmel_enable_ms(struct uart_port *port)
459 {
460 UART_PUT_IER(port, ATMEL_US_RIIC | ATMEL_US_DSRIC
461 | ATMEL_US_DCDIC | ATMEL_US_CTSIC);
462 }
463
464 /*
465 * Control the transmission of a break signal
466 */
467 static void atmel_break_ctl(struct uart_port *port, int break_state)
468 {
469 if (break_state != 0)
470 UART_PUT_CR(port, ATMEL_US_STTBRK); /* start break */
471 else
472 UART_PUT_CR(port, ATMEL_US_STPBRK); /* stop break */
473 }
474
475 /*
476 * Stores the incoming character in the ring buffer
477 */
478 static void
479 atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
480 unsigned int ch)
481 {
482 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
483 struct circ_buf *ring = &atmel_port->rx_ring;
484 struct atmel_uart_char *c;
485
486 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
487 /* Buffer overflow, ignore char */
488 return;
489
490 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
491 c->status = status;
492 c->ch = ch;
493
494 /* Make sure the character is stored before we update head. */
495 smp_wmb();
496
497 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
498 }
499
500 /*
501 * Deal with parity, framing and overrun errors.
502 */
503 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
504 {
505 /* clear error */
506 UART_PUT_CR(port, ATMEL_US_RSTSTA);
507
508 if (status & ATMEL_US_RXBRK) {
509 /* ignore side-effect */
510 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
511 port->icount.brk++;
512 }
513 if (status & ATMEL_US_PARE)
514 port->icount.parity++;
515 if (status & ATMEL_US_FRAME)
516 port->icount.frame++;
517 if (status & ATMEL_US_OVRE)
518 port->icount.overrun++;
519 }
520
521 /*
522 * Characters received (called from interrupt handler)
523 */
524 static void atmel_rx_chars(struct uart_port *port)
525 {
526 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
527 unsigned int status, ch;
528
529 status = UART_GET_CSR(port);
530 while (status & ATMEL_US_RXRDY) {
531 ch = UART_GET_CHAR(port);
532
533 /*
534 * note that the error handling code is
535 * out of the main execution path
536 */
537 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
538 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
539 || atmel_port->break_active)) {
540
541 /* clear error */
542 UART_PUT_CR(port, ATMEL_US_RSTSTA);
543
544 if (status & ATMEL_US_RXBRK
545 && !atmel_port->break_active) {
546 atmel_port->break_active = 1;
547 UART_PUT_IER(port, ATMEL_US_RXBRK);
548 } else {
549 /*
550 * This is either the end-of-break
551 * condition or we've received at
552 * least one character without RXBRK
553 * being set. In both cases, the next
554 * RXBRK will indicate start-of-break.
555 */
556 UART_PUT_IDR(port, ATMEL_US_RXBRK);
557 status &= ~ATMEL_US_RXBRK;
558 atmel_port->break_active = 0;
559 }
560 }
561
562 atmel_buffer_rx_char(port, status, ch);
563 status = UART_GET_CSR(port);
564 }
565
566 tasklet_schedule(&atmel_port->tasklet);
567 }
568
569 /*
570 * Transmit characters (called from tasklet with TXRDY interrupt
571 * disabled)
572 */
573 static void atmel_tx_chars(struct uart_port *port)
574 {
575 struct circ_buf *xmit = &port->state->xmit;
576 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
577
578 if (port->x_char && UART_GET_CSR(port) & atmel_port->tx_done_mask) {
579 UART_PUT_CHAR(port, port->x_char);
580 port->icount.tx++;
581 port->x_char = 0;
582 }
583 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
584 return;
585
586 while (UART_GET_CSR(port) & atmel_port->tx_done_mask) {
587 UART_PUT_CHAR(port, xmit->buf[xmit->tail]);
588 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
589 port->icount.tx++;
590 if (uart_circ_empty(xmit))
591 break;
592 }
593
594 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
595 uart_write_wakeup(port);
596
597 if (!uart_circ_empty(xmit))
598 /* Enable interrupts */
599 UART_PUT_IER(port, atmel_port->tx_done_mask);
600 }
601
602 static void atmel_complete_tx_dma(void *arg)
603 {
604 struct atmel_uart_port *atmel_port = arg;
605 struct uart_port *port = &atmel_port->uart;
606 struct circ_buf *xmit = &port->state->xmit;
607 struct dma_chan *chan = atmel_port->chan_tx;
608 unsigned long flags;
609
610 spin_lock_irqsave(&port->lock, flags);
611
612 if (chan)
613 dmaengine_terminate_all(chan);
614 xmit->tail += sg_dma_len(&atmel_port->sg_tx);
615 xmit->tail &= UART_XMIT_SIZE - 1;
616
617 port->icount.tx += sg_dma_len(&atmel_port->sg_tx);
618
619 spin_lock_irq(&atmel_port->lock_tx);
620 async_tx_ack(atmel_port->desc_tx);
621 atmel_port->cookie_tx = -EINVAL;
622 atmel_port->desc_tx = NULL;
623 spin_unlock_irq(&atmel_port->lock_tx);
624
625 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
626 uart_write_wakeup(port);
627
628 /* Do we really need this? */
629 if (!uart_circ_empty(xmit))
630 tasklet_schedule(&atmel_port->tasklet);
631
632 spin_unlock_irqrestore(&port->lock, flags);
633 }
634
635 static void atmel_release_tx_dma(struct uart_port *port)
636 {
637 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
638 struct dma_chan *chan = atmel_port->chan_tx;
639
640 if (chan) {
641 dmaengine_terminate_all(chan);
642 dma_release_channel(chan);
643 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
644 DMA_MEM_TO_DEV);
645 }
646
647 atmel_port->desc_tx = NULL;
648 atmel_port->chan_tx = NULL;
649 atmel_port->cookie_tx = -EINVAL;
650 }
651
652 /*
653 * Called from tasklet with TXRDY interrupt is disabled.
654 */
655 static void atmel_tx_dma(struct uart_port *port)
656 {
657 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
658 struct circ_buf *xmit = &port->state->xmit;
659 struct dma_chan *chan = atmel_port->chan_tx;
660 struct dma_async_tx_descriptor *desc;
661 struct scatterlist *sg = &atmel_port->sg_tx;
662
663 /* Make sure we have an idle channel */
664 if (atmel_port->desc_tx != NULL)
665 return;
666
667 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
668 /*
669 * DMA is idle now.
670 * Port xmit buffer is already mapped,
671 * and it is one page... Just adjust
672 * offsets and lengths. Since it is a circular buffer,
673 * we have to transmit till the end, and then the rest.
674 * Take the port lock to get a
675 * consistent xmit buffer state.
676 */
677 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
678 sg_dma_address(sg) = (sg_dma_address(sg) &
679 ~(UART_XMIT_SIZE - 1))
680 + sg->offset;
681 sg_dma_len(sg) = CIRC_CNT_TO_END(xmit->head,
682 xmit->tail,
683 UART_XMIT_SIZE);
684 BUG_ON(!sg_dma_len(sg));
685
686 desc = dmaengine_prep_slave_sg(chan,
687 sg,
688 1,
689 DMA_MEM_TO_DEV,
690 DMA_PREP_INTERRUPT |
691 DMA_CTRL_ACK);
692 if (!desc) {
693 dev_err(port->dev, "Failed to send via dma!\n");
694 return;
695 }
696
697 dma_sync_sg_for_device(port->dev, sg, 1, DMA_MEM_TO_DEV);
698
699 atmel_port->desc_tx = desc;
700 desc->callback = atmel_complete_tx_dma;
701 desc->callback_param = atmel_port;
702 atmel_port->cookie_tx = dmaengine_submit(desc);
703
704 } else {
705 if (atmel_port->rs485.flags & SER_RS485_ENABLED) {
706 /* DMA done, stop TX, start RX for RS485 */
707 atmel_start_rx(port);
708 }
709 }
710
711 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
712 uart_write_wakeup(port);
713 }
714
715 static int atmel_prepare_tx_dma(struct uart_port *port)
716 {
717 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
718 dma_cap_mask_t mask;
719 struct dma_slave_config config;
720 int ret, nent;
721
722 dma_cap_zero(mask);
723 dma_cap_set(DMA_SLAVE, mask);
724
725 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx");
726 if (atmel_port->chan_tx == NULL)
727 goto chan_err;
728 dev_info(port->dev, "using %s for tx DMA transfers\n",
729 dma_chan_name(atmel_port->chan_tx));
730
731 spin_lock_init(&atmel_port->lock_tx);
732 sg_init_table(&atmel_port->sg_tx, 1);
733 /* UART circular tx buffer is an aligned page. */
734 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
735 sg_set_page(&atmel_port->sg_tx,
736 virt_to_page(port->state->xmit.buf),
737 UART_XMIT_SIZE,
738 (int)port->state->xmit.buf & ~PAGE_MASK);
739 nent = dma_map_sg(port->dev,
740 &atmel_port->sg_tx,
741 1,
742 DMA_MEM_TO_DEV);
743
744 if (!nent) {
745 dev_dbg(port->dev, "need to release resource of dma\n");
746 goto chan_err;
747 } else {
748 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
749 sg_dma_len(&atmel_port->sg_tx),
750 port->state->xmit.buf,
751 sg_dma_address(&atmel_port->sg_tx));
752 }
753
754 /* Configure the slave DMA */
755 memset(&config, 0, sizeof(config));
756 config.direction = DMA_MEM_TO_DEV;
757 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
758 config.dst_addr = port->mapbase + ATMEL_US_THR;
759
760 ret = dmaengine_device_control(atmel_port->chan_tx,
761 DMA_SLAVE_CONFIG,
762 (unsigned long)&config);
763 if (ret) {
764 dev_err(port->dev, "DMA tx slave configuration failed\n");
765 goto chan_err;
766 }
767
768 return 0;
769
770 chan_err:
771 dev_err(port->dev, "TX channel not available, switch to pio\n");
772 atmel_port->use_dma_tx = 0;
773 if (atmel_port->chan_tx)
774 atmel_release_tx_dma(port);
775 return -EINVAL;
776 }
777
778 static void atmel_flip_buffer_rx_dma(struct uart_port *port,
779 char *buf, size_t count)
780 {
781 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
782 struct tty_port *tport = &port->state->port;
783
784 dma_sync_sg_for_cpu(port->dev,
785 &atmel_port->sg_rx,
786 1,
787 DMA_DEV_TO_MEM);
788
789 tty_insert_flip_string(tport, buf, count);
790
791 dma_sync_sg_for_device(port->dev,
792 &atmel_port->sg_rx,
793 1,
794 DMA_DEV_TO_MEM);
795 /*
796 * Drop the lock here since it might end up calling
797 * uart_start(), which takes the lock.
798 */
799 spin_unlock(&port->lock);
800 tty_flip_buffer_push(tport);
801 spin_lock(&port->lock);
802 }
803
804 static void atmel_complete_rx_dma(void *arg)
805 {
806 struct uart_port *port = arg;
807 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
808
809 tasklet_schedule(&atmel_port->tasklet);
810 }
811
812 static void atmel_release_rx_dma(struct uart_port *port)
813 {
814 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
815 struct dma_chan *chan = atmel_port->chan_rx;
816
817 if (chan) {
818 dmaengine_terminate_all(chan);
819 dma_release_channel(chan);
820 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
821 DMA_DEV_TO_MEM);
822 }
823
824 atmel_port->desc_rx = NULL;
825 atmel_port->chan_rx = NULL;
826 atmel_port->cookie_rx = -EINVAL;
827 }
828
829 static void atmel_rx_from_dma(struct uart_port *port)
830 {
831 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
832 struct circ_buf *ring = &atmel_port->rx_ring;
833 struct dma_chan *chan = atmel_port->chan_rx;
834 struct dma_tx_state state;
835 enum dma_status dmastat;
836 size_t pending, count;
837
838
839 /* Reset the UART timeout early so that we don't miss one */
840 UART_PUT_CR(port, ATMEL_US_STTTO);
841 dmastat = dmaengine_tx_status(chan,
842 atmel_port->cookie_rx,
843 &state);
844 /* Restart a new tasklet if DMA status is error */
845 if (dmastat == DMA_ERROR) {
846 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
847 UART_PUT_IER(port, ATMEL_US_TIMEOUT);
848 tasklet_schedule(&atmel_port->tasklet);
849 return;
850 }
851 /* current transfer size should no larger than dma buffer */
852 pending = sg_dma_len(&atmel_port->sg_rx) - state.residue;
853 BUG_ON(pending > sg_dma_len(&atmel_port->sg_rx));
854
855 /*
856 * This will take the chars we have so far,
857 * ring->head will record the transfer size, only new bytes come
858 * will insert into the framework.
859 */
860 if (pending > ring->head) {
861 count = pending - ring->head;
862
863 atmel_flip_buffer_rx_dma(port, ring->buf + ring->head, count);
864
865 ring->head += count;
866 if (ring->head == sg_dma_len(&atmel_port->sg_rx))
867 ring->head = 0;
868
869 port->icount.rx += count;
870 }
871
872 UART_PUT_IER(port, ATMEL_US_TIMEOUT);
873 }
874
875 static int atmel_prepare_rx_dma(struct uart_port *port)
876 {
877 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
878 struct dma_async_tx_descriptor *desc;
879 dma_cap_mask_t mask;
880 struct dma_slave_config config;
881 struct circ_buf *ring;
882 int ret, nent;
883
884 ring = &atmel_port->rx_ring;
885
886 dma_cap_zero(mask);
887 dma_cap_set(DMA_CYCLIC, mask);
888
889 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx");
890 if (atmel_port->chan_rx == NULL)
891 goto chan_err;
892 dev_info(port->dev, "using %s for rx DMA transfers\n",
893 dma_chan_name(atmel_port->chan_rx));
894
895 spin_lock_init(&atmel_port->lock_rx);
896 sg_init_table(&atmel_port->sg_rx, 1);
897 /* UART circular rx buffer is an aligned page. */
898 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
899 sg_set_page(&atmel_port->sg_rx,
900 virt_to_page(ring->buf),
901 ATMEL_SERIAL_RINGSIZE,
902 (int)ring->buf & ~PAGE_MASK);
903 nent = dma_map_sg(port->dev,
904 &atmel_port->sg_rx,
905 1,
906 DMA_DEV_TO_MEM);
907
908 if (!nent) {
909 dev_dbg(port->dev, "need to release resource of dma\n");
910 goto chan_err;
911 } else {
912 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
913 sg_dma_len(&atmel_port->sg_rx),
914 ring->buf,
915 sg_dma_address(&atmel_port->sg_rx));
916 }
917
918 /* Configure the slave DMA */
919 memset(&config, 0, sizeof(config));
920 config.direction = DMA_DEV_TO_MEM;
921 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
922 config.src_addr = port->mapbase + ATMEL_US_RHR;
923
924 ret = dmaengine_device_control(atmel_port->chan_rx,
925 DMA_SLAVE_CONFIG,
926 (unsigned long)&config);
927 if (ret) {
928 dev_err(port->dev, "DMA rx slave configuration failed\n");
929 goto chan_err;
930 }
931 /*
932 * Prepare a cyclic dma transfer, assign 2 descriptors,
933 * each one is half ring buffer size
934 */
935 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
936 sg_dma_address(&atmel_port->sg_rx),
937 sg_dma_len(&atmel_port->sg_rx),
938 sg_dma_len(&atmel_port->sg_rx)/2,
939 DMA_DEV_TO_MEM,
940 DMA_PREP_INTERRUPT);
941 desc->callback = atmel_complete_rx_dma;
942 desc->callback_param = port;
943 atmel_port->desc_rx = desc;
944 atmel_port->cookie_rx = dmaengine_submit(desc);
945
946 return 0;
947
948 chan_err:
949 dev_err(port->dev, "RX channel not available, switch to pio\n");
950 atmel_port->use_dma_rx = 0;
951 if (atmel_port->chan_rx)
952 atmel_release_rx_dma(port);
953 return -EINVAL;
954 }
955
956 static void atmel_uart_timer_callback(unsigned long data)
957 {
958 struct uart_port *port = (void *)data;
959 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
960
961 tasklet_schedule(&atmel_port->tasklet);
962 mod_timer(&atmel_port->uart_timer, jiffies + uart_poll_timeout(port));
963 }
964
965 /*
966 * receive interrupt handler.
967 */
968 static void
969 atmel_handle_receive(struct uart_port *port, unsigned int pending)
970 {
971 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
972
973 if (atmel_use_pdc_rx(port)) {
974 /*
975 * PDC receive. Just schedule the tasklet and let it
976 * figure out the details.
977 *
978 * TODO: We're not handling error flags correctly at
979 * the moment.
980 */
981 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
982 UART_PUT_IDR(port, (ATMEL_US_ENDRX
983 | ATMEL_US_TIMEOUT));
984 tasklet_schedule(&atmel_port->tasklet);
985 }
986
987 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
988 ATMEL_US_FRAME | ATMEL_US_PARE))
989 atmel_pdc_rxerr(port, pending);
990 }
991
992 if (atmel_use_dma_rx(port)) {
993 if (pending & ATMEL_US_TIMEOUT) {
994 UART_PUT_IDR(port, ATMEL_US_TIMEOUT);
995 tasklet_schedule(&atmel_port->tasklet);
996 }
997 }
998
999 /* Interrupt receive */
1000 if (pending & ATMEL_US_RXRDY)
1001 atmel_rx_chars(port);
1002 else if (pending & ATMEL_US_RXBRK) {
1003 /*
1004 * End of break detected. If it came along with a
1005 * character, atmel_rx_chars will handle it.
1006 */
1007 UART_PUT_CR(port, ATMEL_US_RSTSTA);
1008 UART_PUT_IDR(port, ATMEL_US_RXBRK);
1009 atmel_port->break_active = 0;
1010 }
1011 }
1012
1013 /*
1014 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
1015 */
1016 static void
1017 atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1018 {
1019 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1020
1021 if (pending & atmel_port->tx_done_mask) {
1022 /* Either PDC or interrupt transmission */
1023 UART_PUT_IDR(port, atmel_port->tx_done_mask);
1024 tasklet_schedule(&atmel_port->tasklet);
1025 }
1026 }
1027
1028 /*
1029 * status flags interrupt handler.
1030 */
1031 static void
1032 atmel_handle_status(struct uart_port *port, unsigned int pending,
1033 unsigned int status)
1034 {
1035 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1036
1037 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1038 | ATMEL_US_CTSIC)) {
1039 atmel_port->irq_status = status;
1040 tasklet_schedule(&atmel_port->tasklet);
1041 }
1042 }
1043
1044 /*
1045 * Interrupt handler
1046 */
1047 static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1048 {
1049 struct uart_port *port = dev_id;
1050 unsigned int status, pending, pass_counter = 0;
1051
1052 do {
1053 status = UART_GET_CSR(port);
1054 pending = status & UART_GET_IMR(port);
1055 if (!pending)
1056 break;
1057
1058 atmel_handle_receive(port, pending);
1059 atmel_handle_status(port, pending, status);
1060 atmel_handle_transmit(port, pending);
1061 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
1062
1063 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
1064 }
1065
1066 static void atmel_release_tx_pdc(struct uart_port *port)
1067 {
1068 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1069 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1070
1071 dma_unmap_single(port->dev,
1072 pdc->dma_addr,
1073 pdc->dma_size,
1074 DMA_TO_DEVICE);
1075 }
1076
1077 /*
1078 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1079 */
1080 static void atmel_tx_pdc(struct uart_port *port)
1081 {
1082 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1083 struct circ_buf *xmit = &port->state->xmit;
1084 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1085 int count;
1086
1087 /* nothing left to transmit? */
1088 if (UART_GET_TCR(port))
1089 return;
1090
1091 xmit->tail += pdc->ofs;
1092 xmit->tail &= UART_XMIT_SIZE - 1;
1093
1094 port->icount.tx += pdc->ofs;
1095 pdc->ofs = 0;
1096
1097 /* more to transmit - setup next transfer */
1098
1099 /* disable PDC transmit */
1100 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
1101
1102 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
1103 dma_sync_single_for_device(port->dev,
1104 pdc->dma_addr,
1105 pdc->dma_size,
1106 DMA_TO_DEVICE);
1107
1108 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1109 pdc->ofs = count;
1110
1111 UART_PUT_TPR(port, pdc->dma_addr + xmit->tail);
1112 UART_PUT_TCR(port, count);
1113 /* re-enable PDC transmit */
1114 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
1115 /* Enable interrupts */
1116 UART_PUT_IER(port, atmel_port->tx_done_mask);
1117 } else {
1118 if ((atmel_port->rs485.flags & SER_RS485_ENABLED) &&
1119 !(atmel_port->rs485.flags & SER_RS485_RX_DURING_TX)) {
1120 /* DMA done, stop TX, start RX for RS485 */
1121 atmel_start_rx(port);
1122 }
1123 }
1124
1125 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1126 uart_write_wakeup(port);
1127 }
1128
1129 static int atmel_prepare_tx_pdc(struct uart_port *port)
1130 {
1131 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1132 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1133 struct circ_buf *xmit = &port->state->xmit;
1134
1135 pdc->buf = xmit->buf;
1136 pdc->dma_addr = dma_map_single(port->dev,
1137 pdc->buf,
1138 UART_XMIT_SIZE,
1139 DMA_TO_DEVICE);
1140 pdc->dma_size = UART_XMIT_SIZE;
1141 pdc->ofs = 0;
1142
1143 return 0;
1144 }
1145
1146 static void atmel_rx_from_ring(struct uart_port *port)
1147 {
1148 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1149 struct circ_buf *ring = &atmel_port->rx_ring;
1150 unsigned int flg;
1151 unsigned int status;
1152
1153 while (ring->head != ring->tail) {
1154 struct atmel_uart_char c;
1155
1156 /* Make sure c is loaded after head. */
1157 smp_rmb();
1158
1159 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1160
1161 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1162
1163 port->icount.rx++;
1164 status = c.status;
1165 flg = TTY_NORMAL;
1166
1167 /*
1168 * note that the error handling code is
1169 * out of the main execution path
1170 */
1171 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1172 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1173 if (status & ATMEL_US_RXBRK) {
1174 /* ignore side-effect */
1175 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1176
1177 port->icount.brk++;
1178 if (uart_handle_break(port))
1179 continue;
1180 }
1181 if (status & ATMEL_US_PARE)
1182 port->icount.parity++;
1183 if (status & ATMEL_US_FRAME)
1184 port->icount.frame++;
1185 if (status & ATMEL_US_OVRE)
1186 port->icount.overrun++;
1187
1188 status &= port->read_status_mask;
1189
1190 if (status & ATMEL_US_RXBRK)
1191 flg = TTY_BREAK;
1192 else if (status & ATMEL_US_PARE)
1193 flg = TTY_PARITY;
1194 else if (status & ATMEL_US_FRAME)
1195 flg = TTY_FRAME;
1196 }
1197
1198
1199 if (uart_handle_sysrq_char(port, c.ch))
1200 continue;
1201
1202 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1203 }
1204
1205 /*
1206 * Drop the lock here since it might end up calling
1207 * uart_start(), which takes the lock.
1208 */
1209 spin_unlock(&port->lock);
1210 tty_flip_buffer_push(&port->state->port);
1211 spin_lock(&port->lock);
1212 }
1213
1214 static void atmel_release_rx_pdc(struct uart_port *port)
1215 {
1216 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1217 int i;
1218
1219 for (i = 0; i < 2; i++) {
1220 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1221
1222 dma_unmap_single(port->dev,
1223 pdc->dma_addr,
1224 pdc->dma_size,
1225 DMA_FROM_DEVICE);
1226 kfree(pdc->buf);
1227 }
1228 }
1229
1230 static void atmel_rx_from_pdc(struct uart_port *port)
1231 {
1232 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1233 struct tty_port *tport = &port->state->port;
1234 struct atmel_dma_buffer *pdc;
1235 int rx_idx = atmel_port->pdc_rx_idx;
1236 unsigned int head;
1237 unsigned int tail;
1238 unsigned int count;
1239
1240 do {
1241 /* Reset the UART timeout early so that we don't miss one */
1242 UART_PUT_CR(port, ATMEL_US_STTTO);
1243
1244 pdc = &atmel_port->pdc_rx[rx_idx];
1245 head = UART_GET_RPR(port) - pdc->dma_addr;
1246 tail = pdc->ofs;
1247
1248 /* If the PDC has switched buffers, RPR won't contain
1249 * any address within the current buffer. Since head
1250 * is unsigned, we just need a one-way comparison to
1251 * find out.
1252 *
1253 * In this case, we just need to consume the entire
1254 * buffer and resubmit it for DMA. This will clear the
1255 * ENDRX bit as well, so that we can safely re-enable
1256 * all interrupts below.
1257 */
1258 head = min(head, pdc->dma_size);
1259
1260 if (likely(head != tail)) {
1261 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1262 pdc->dma_size, DMA_FROM_DEVICE);
1263
1264 /*
1265 * head will only wrap around when we recycle
1266 * the DMA buffer, and when that happens, we
1267 * explicitly set tail to 0. So head will
1268 * always be greater than tail.
1269 */
1270 count = head - tail;
1271
1272 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1273 count);
1274
1275 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1276 pdc->dma_size, DMA_FROM_DEVICE);
1277
1278 port->icount.rx += count;
1279 pdc->ofs = head;
1280 }
1281
1282 /*
1283 * If the current buffer is full, we need to check if
1284 * the next one contains any additional data.
1285 */
1286 if (head >= pdc->dma_size) {
1287 pdc->ofs = 0;
1288 UART_PUT_RNPR(port, pdc->dma_addr);
1289 UART_PUT_RNCR(port, pdc->dma_size);
1290
1291 rx_idx = !rx_idx;
1292 atmel_port->pdc_rx_idx = rx_idx;
1293 }
1294 } while (head >= pdc->dma_size);
1295
1296 /*
1297 * Drop the lock here since it might end up calling
1298 * uart_start(), which takes the lock.
1299 */
1300 spin_unlock(&port->lock);
1301 tty_flip_buffer_push(tport);
1302 spin_lock(&port->lock);
1303
1304 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1305 }
1306
1307 static int atmel_prepare_rx_pdc(struct uart_port *port)
1308 {
1309 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1310 int i;
1311
1312 for (i = 0; i < 2; i++) {
1313 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1314
1315 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1316 if (pdc->buf == NULL) {
1317 if (i != 0) {
1318 dma_unmap_single(port->dev,
1319 atmel_port->pdc_rx[0].dma_addr,
1320 PDC_BUFFER_SIZE,
1321 DMA_FROM_DEVICE);
1322 kfree(atmel_port->pdc_rx[0].buf);
1323 }
1324 atmel_port->use_pdc_rx = 0;
1325 return -ENOMEM;
1326 }
1327 pdc->dma_addr = dma_map_single(port->dev,
1328 pdc->buf,
1329 PDC_BUFFER_SIZE,
1330 DMA_FROM_DEVICE);
1331 pdc->dma_size = PDC_BUFFER_SIZE;
1332 pdc->ofs = 0;
1333 }
1334
1335 atmel_port->pdc_rx_idx = 0;
1336
1337 UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr);
1338 UART_PUT_RCR(port, PDC_BUFFER_SIZE);
1339
1340 UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr);
1341 UART_PUT_RNCR(port, PDC_BUFFER_SIZE);
1342
1343 return 0;
1344 }
1345
1346 /*
1347 * tasklet handling tty stuff outside the interrupt handler.
1348 */
1349 static void atmel_tasklet_func(unsigned long data)
1350 {
1351 struct uart_port *port = (struct uart_port *)data;
1352 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1353 unsigned int status;
1354 unsigned int status_change;
1355
1356 /* The interrupt handler does not take the lock */
1357 spin_lock(&port->lock);
1358
1359 atmel_port->schedule_tx(port);
1360
1361 status = atmel_port->irq_status;
1362 status_change = status ^ atmel_port->irq_status_prev;
1363
1364 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1365 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1366 /* TODO: All reads to CSR will clear these interrupts! */
1367 if (status_change & ATMEL_US_RI)
1368 port->icount.rng++;
1369 if (status_change & ATMEL_US_DSR)
1370 port->icount.dsr++;
1371 if (status_change & ATMEL_US_DCD)
1372 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1373 if (status_change & ATMEL_US_CTS)
1374 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1375
1376 wake_up_interruptible(&port->state->port.delta_msr_wait);
1377
1378 atmel_port->irq_status_prev = status;
1379 }
1380
1381 atmel_port->schedule_rx(port);
1382
1383 spin_unlock(&port->lock);
1384 }
1385
1386 static int atmel_init_property(struct atmel_uart_port *atmel_port,
1387 struct platform_device *pdev)
1388 {
1389 struct device_node *np = pdev->dev.of_node;
1390 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1391
1392 if (np) {
1393 /* DMA/PDC usage specification */
1394 if (of_get_property(np, "atmel,use-dma-rx", NULL)) {
1395 if (of_get_property(np, "dmas", NULL)) {
1396 atmel_port->use_dma_rx = true;
1397 atmel_port->use_pdc_rx = false;
1398 } else {
1399 atmel_port->use_dma_rx = false;
1400 atmel_port->use_pdc_rx = true;
1401 }
1402 } else {
1403 atmel_port->use_dma_rx = false;
1404 atmel_port->use_pdc_rx = false;
1405 }
1406
1407 if (of_get_property(np, "atmel,use-dma-tx", NULL)) {
1408 if (of_get_property(np, "dmas", NULL)) {
1409 atmel_port->use_dma_tx = true;
1410 atmel_port->use_pdc_tx = false;
1411 } else {
1412 atmel_port->use_dma_tx = false;
1413 atmel_port->use_pdc_tx = true;
1414 }
1415 } else {
1416 atmel_port->use_dma_tx = false;
1417 atmel_port->use_pdc_tx = false;
1418 }
1419
1420 } else {
1421 atmel_port->use_pdc_rx = pdata->use_dma_rx;
1422 atmel_port->use_pdc_tx = pdata->use_dma_tx;
1423 atmel_port->use_dma_rx = false;
1424 atmel_port->use_dma_tx = false;
1425 }
1426
1427 return 0;
1428 }
1429
1430 static void atmel_init_rs485(struct atmel_uart_port *atmel_port,
1431 struct platform_device *pdev)
1432 {
1433 struct device_node *np = pdev->dev.of_node;
1434 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1435
1436 if (np) {
1437 u32 rs485_delay[2];
1438 /* rs485 properties */
1439 if (of_property_read_u32_array(np, "rs485-rts-delay",
1440 rs485_delay, 2) == 0) {
1441 struct serial_rs485 *rs485conf = &atmel_port->rs485;
1442
1443 rs485conf->delay_rts_before_send = rs485_delay[0];
1444 rs485conf->delay_rts_after_send = rs485_delay[1];
1445 rs485conf->flags = 0;
1446
1447 if (of_get_property(np, "rs485-rx-during-tx", NULL))
1448 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1449
1450 if (of_get_property(np, "linux,rs485-enabled-at-boot-time",
1451 NULL))
1452 rs485conf->flags |= SER_RS485_ENABLED;
1453 }
1454 } else {
1455 atmel_port->rs485 = pdata->rs485;
1456 }
1457
1458 }
1459
1460 static void atmel_set_ops(struct uart_port *port)
1461 {
1462 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1463
1464 if (atmel_use_dma_rx(port)) {
1465 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1466 atmel_port->schedule_rx = &atmel_rx_from_dma;
1467 atmel_port->release_rx = &atmel_release_rx_dma;
1468 } else if (atmel_use_pdc_rx(port)) {
1469 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1470 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1471 atmel_port->release_rx = &atmel_release_rx_pdc;
1472 } else {
1473 atmel_port->prepare_rx = NULL;
1474 atmel_port->schedule_rx = &atmel_rx_from_ring;
1475 atmel_port->release_rx = NULL;
1476 }
1477
1478 if (atmel_use_dma_tx(port)) {
1479 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1480 atmel_port->schedule_tx = &atmel_tx_dma;
1481 atmel_port->release_tx = &atmel_release_tx_dma;
1482 } else if (atmel_use_pdc_tx(port)) {
1483 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1484 atmel_port->schedule_tx = &atmel_tx_pdc;
1485 atmel_port->release_tx = &atmel_release_tx_pdc;
1486 } else {
1487 atmel_port->prepare_tx = NULL;
1488 atmel_port->schedule_tx = &atmel_tx_chars;
1489 atmel_port->release_tx = NULL;
1490 }
1491 }
1492
1493 /*
1494 * Get ip name usart or uart
1495 */
1496 static void atmel_get_ip_name(struct uart_port *port)
1497 {
1498 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1499 int name = UART_GET_IP_NAME(port);
1500 int usart, uart;
1501 /* usart and uart ascii */
1502 usart = 0x55534152;
1503 uart = 0x44424755;
1504
1505 atmel_port->is_usart = false;
1506
1507 if (name == usart) {
1508 dev_dbg(port->dev, "This is usart\n");
1509 atmel_port->is_usart = true;
1510 } else if (name == uart) {
1511 dev_dbg(port->dev, "This is uart\n");
1512 atmel_port->is_usart = false;
1513 } else {
1514 dev_err(port->dev, "Not supported ip name, set to uart\n");
1515 }
1516 }
1517
1518 /*
1519 * Perform initialization and enable port for reception
1520 */
1521 static int atmel_startup(struct uart_port *port)
1522 {
1523 struct platform_device *pdev = to_platform_device(port->dev);
1524 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1525 struct tty_struct *tty = port->state->port.tty;
1526 int retval;
1527
1528 /*
1529 * Ensure that no interrupts are enabled otherwise when
1530 * request_irq() is called we could get stuck trying to
1531 * handle an unexpected interrupt
1532 */
1533 UART_PUT_IDR(port, -1);
1534
1535 /*
1536 * Allocate the IRQ
1537 */
1538 retval = request_irq(port->irq, atmel_interrupt, IRQF_SHARED,
1539 tty ? tty->name : "atmel_serial", port);
1540 if (retval) {
1541 printk("atmel_serial: atmel_startup - Can't get irq\n");
1542 return retval;
1543 }
1544
1545 /*
1546 * Initialize DMA (if necessary)
1547 */
1548 atmel_init_property(atmel_port, pdev);
1549
1550 if (atmel_port->prepare_rx) {
1551 retval = atmel_port->prepare_rx(port);
1552 if (retval < 0)
1553 atmel_set_ops(port);
1554 }
1555
1556 if (atmel_port->prepare_tx) {
1557 retval = atmel_port->prepare_tx(port);
1558 if (retval < 0)
1559 atmel_set_ops(port);
1560 }
1561 /*
1562 * If there is a specific "open" function (to register
1563 * control line interrupts)
1564 */
1565 if (atmel_open_hook) {
1566 retval = atmel_open_hook(port);
1567 if (retval) {
1568 free_irq(port->irq, port);
1569 return retval;
1570 }
1571 }
1572
1573 /* Save current CSR for comparison in atmel_tasklet_func() */
1574 atmel_port->irq_status_prev = UART_GET_CSR(port);
1575 atmel_port->irq_status = atmel_port->irq_status_prev;
1576
1577 /*
1578 * Finally, enable the serial port
1579 */
1580 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1581 /* enable xmit & rcvr */
1582 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
1583
1584 setup_timer(&atmel_port->uart_timer,
1585 atmel_uart_timer_callback,
1586 (unsigned long)port);
1587
1588 if (atmel_use_pdc_rx(port)) {
1589 /* set UART timeout */
1590 if (!atmel_port->is_usart) {
1591 mod_timer(&atmel_port->uart_timer,
1592 jiffies + uart_poll_timeout(port));
1593 /* set USART timeout */
1594 } else {
1595 UART_PUT_RTOR(port, PDC_RX_TIMEOUT);
1596 UART_PUT_CR(port, ATMEL_US_STTTO);
1597
1598 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1599 }
1600 /* enable PDC controller */
1601 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN);
1602 } else if (atmel_use_dma_rx(port)) {
1603 /* set UART timeout */
1604 if (!atmel_port->is_usart) {
1605 mod_timer(&atmel_port->uart_timer,
1606 jiffies + uart_poll_timeout(port));
1607 /* set USART timeout */
1608 } else {
1609 UART_PUT_RTOR(port, PDC_RX_TIMEOUT);
1610 UART_PUT_CR(port, ATMEL_US_STTTO);
1611
1612 UART_PUT_IER(port, ATMEL_US_TIMEOUT);
1613 }
1614 } else {
1615 /* enable receive only */
1616 UART_PUT_IER(port, ATMEL_US_RXRDY);
1617 }
1618
1619 return 0;
1620 }
1621
1622 /*
1623 * Disable the port
1624 */
1625 static void atmel_shutdown(struct uart_port *port)
1626 {
1627 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1628
1629 /*
1630 * Prevent any tasklets being scheduled during
1631 * cleanup
1632 */
1633 del_timer_sync(&atmel_port->uart_timer);
1634
1635 /*
1636 * Clear out any scheduled tasklets before
1637 * we destroy the buffers
1638 */
1639 tasklet_kill(&atmel_port->tasklet);
1640
1641 /*
1642 * Ensure everything is stopped and
1643 * disable all interrupts, port and break condition.
1644 */
1645 atmel_stop_rx(port);
1646 atmel_stop_tx(port);
1647
1648 UART_PUT_CR(port, ATMEL_US_RSTSTA);
1649 UART_PUT_IDR(port, -1);
1650
1651
1652 /*
1653 * Shut-down the DMA.
1654 */
1655 if (atmel_port->release_rx)
1656 atmel_port->release_rx(port);
1657 if (atmel_port->release_tx)
1658 atmel_port->release_tx(port);
1659
1660 /*
1661 * Reset ring buffer pointers
1662 */
1663 atmel_port->rx_ring.head = 0;
1664 atmel_port->rx_ring.tail = 0;
1665
1666 /*
1667 * Free the interrupt
1668 */
1669 free_irq(port->irq, port);
1670
1671 /*
1672 * If there is a specific "close" function (to unregister
1673 * control line interrupts)
1674 */
1675 if (atmel_close_hook)
1676 atmel_close_hook(port);
1677 }
1678
1679 /*
1680 * Flush any TX data submitted for DMA. Called when the TX circular
1681 * buffer is reset.
1682 */
1683 static void atmel_flush_buffer(struct uart_port *port)
1684 {
1685 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1686
1687 if (atmel_use_pdc_tx(port)) {
1688 UART_PUT_TCR(port, 0);
1689 atmel_port->pdc_tx.ofs = 0;
1690 }
1691 }
1692
1693 /*
1694 * Power / Clock management.
1695 */
1696 static void atmel_serial_pm(struct uart_port *port, unsigned int state,
1697 unsigned int oldstate)
1698 {
1699 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1700
1701 switch (state) {
1702 case 0:
1703 /*
1704 * Enable the peripheral clock for this serial port.
1705 * This is called on uart_open() or a resume event.
1706 */
1707 clk_prepare_enable(atmel_port->clk);
1708
1709 /* re-enable interrupts if we disabled some on suspend */
1710 UART_PUT_IER(port, atmel_port->backup_imr);
1711 break;
1712 case 3:
1713 /* Back up the interrupt mask and disable all interrupts */
1714 atmel_port->backup_imr = UART_GET_IMR(port);
1715 UART_PUT_IDR(port, -1);
1716
1717 /*
1718 * Disable the peripheral clock for this serial port.
1719 * This is called on uart_close() or a suspend event.
1720 */
1721 clk_disable_unprepare(atmel_port->clk);
1722 break;
1723 default:
1724 printk(KERN_ERR "atmel_serial: unknown pm %d\n", state);
1725 }
1726 }
1727
1728 /*
1729 * Change the port parameters
1730 */
1731 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
1732 struct ktermios *old)
1733 {
1734 unsigned long flags;
1735 unsigned int mode, imr, quot, baud;
1736 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1737
1738 /* Get current mode register */
1739 mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL
1740 | ATMEL_US_NBSTOP | ATMEL_US_PAR
1741 | ATMEL_US_USMODE);
1742
1743 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1744 quot = uart_get_divisor(port, baud);
1745
1746 if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */
1747 quot /= 8;
1748 mode |= ATMEL_US_USCLKS_MCK_DIV8;
1749 }
1750
1751 /* byte size */
1752 switch (termios->c_cflag & CSIZE) {
1753 case CS5:
1754 mode |= ATMEL_US_CHRL_5;
1755 break;
1756 case CS6:
1757 mode |= ATMEL_US_CHRL_6;
1758 break;
1759 case CS7:
1760 mode |= ATMEL_US_CHRL_7;
1761 break;
1762 default:
1763 mode |= ATMEL_US_CHRL_8;
1764 break;
1765 }
1766
1767 /* stop bits */
1768 if (termios->c_cflag & CSTOPB)
1769 mode |= ATMEL_US_NBSTOP_2;
1770
1771 /* parity */
1772 if (termios->c_cflag & PARENB) {
1773 /* Mark or Space parity */
1774 if (termios->c_cflag & CMSPAR) {
1775 if (termios->c_cflag & PARODD)
1776 mode |= ATMEL_US_PAR_MARK;
1777 else
1778 mode |= ATMEL_US_PAR_SPACE;
1779 } else if (termios->c_cflag & PARODD)
1780 mode |= ATMEL_US_PAR_ODD;
1781 else
1782 mode |= ATMEL_US_PAR_EVEN;
1783 } else
1784 mode |= ATMEL_US_PAR_NONE;
1785
1786 /* hardware handshake (RTS/CTS) */
1787 if (termios->c_cflag & CRTSCTS)
1788 mode |= ATMEL_US_USMODE_HWHS;
1789 else
1790 mode |= ATMEL_US_USMODE_NORMAL;
1791
1792 spin_lock_irqsave(&port->lock, flags);
1793
1794 port->read_status_mask = ATMEL_US_OVRE;
1795 if (termios->c_iflag & INPCK)
1796 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1797 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1798 port->read_status_mask |= ATMEL_US_RXBRK;
1799
1800 if (atmel_use_pdc_rx(port))
1801 /* need to enable error interrupts */
1802 UART_PUT_IER(port, port->read_status_mask);
1803
1804 /*
1805 * Characters to ignore
1806 */
1807 port->ignore_status_mask = 0;
1808 if (termios->c_iflag & IGNPAR)
1809 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1810 if (termios->c_iflag & IGNBRK) {
1811 port->ignore_status_mask |= ATMEL_US_RXBRK;
1812 /*
1813 * If we're ignoring parity and break indicators,
1814 * ignore overruns too (for real raw support).
1815 */
1816 if (termios->c_iflag & IGNPAR)
1817 port->ignore_status_mask |= ATMEL_US_OVRE;
1818 }
1819 /* TODO: Ignore all characters if CREAD is set.*/
1820
1821 /* update the per-port timeout */
1822 uart_update_timeout(port, termios->c_cflag, baud);
1823
1824 /*
1825 * save/disable interrupts. The tty layer will ensure that the
1826 * transmitter is empty if requested by the caller, so there's
1827 * no need to wait for it here.
1828 */
1829 imr = UART_GET_IMR(port);
1830 UART_PUT_IDR(port, -1);
1831
1832 /* disable receiver and transmitter */
1833 UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
1834
1835 /* Resetting serial mode to RS232 (0x0) */
1836 mode &= ~ATMEL_US_USMODE;
1837
1838 if (atmel_port->rs485.flags & SER_RS485_ENABLED) {
1839 dev_dbg(port->dev, "Setting UART to RS485\n");
1840 if ((atmel_port->rs485.delay_rts_after_send) > 0)
1841 UART_PUT_TTGR(port,
1842 atmel_port->rs485.delay_rts_after_send);
1843 mode |= ATMEL_US_USMODE_RS485;
1844 } else {
1845 dev_dbg(port->dev, "Setting UART to RS232\n");
1846 }
1847
1848 /* set the parity, stop bits and data size */
1849 UART_PUT_MR(port, mode);
1850
1851 /* set the baud rate */
1852 UART_PUT_BRGR(port, quot);
1853 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1854 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
1855
1856 /* restore interrupts */
1857 UART_PUT_IER(port, imr);
1858
1859 /* CTS flow-control and modem-status interrupts */
1860 if (UART_ENABLE_MS(port, termios->c_cflag))
1861 port->ops->enable_ms(port);
1862
1863 spin_unlock_irqrestore(&port->lock, flags);
1864 }
1865
1866 static void atmel_set_ldisc(struct uart_port *port, int new)
1867 {
1868 if (new == N_PPS) {
1869 port->flags |= UPF_HARDPPS_CD;
1870 atmel_enable_ms(port);
1871 } else {
1872 port->flags &= ~UPF_HARDPPS_CD;
1873 }
1874 }
1875
1876 /*
1877 * Return string describing the specified port
1878 */
1879 static const char *atmel_type(struct uart_port *port)
1880 {
1881 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
1882 }
1883
1884 /*
1885 * Release the memory region(s) being used by 'port'.
1886 */
1887 static void atmel_release_port(struct uart_port *port)
1888 {
1889 struct platform_device *pdev = to_platform_device(port->dev);
1890 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
1891
1892 release_mem_region(port->mapbase, size);
1893
1894 if (port->flags & UPF_IOREMAP) {
1895 iounmap(port->membase);
1896 port->membase = NULL;
1897 }
1898 }
1899
1900 /*
1901 * Request the memory region(s) being used by 'port'.
1902 */
1903 static int atmel_request_port(struct uart_port *port)
1904 {
1905 struct platform_device *pdev = to_platform_device(port->dev);
1906 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
1907
1908 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
1909 return -EBUSY;
1910
1911 if (port->flags & UPF_IOREMAP) {
1912 port->membase = ioremap(port->mapbase, size);
1913 if (port->membase == NULL) {
1914 release_mem_region(port->mapbase, size);
1915 return -ENOMEM;
1916 }
1917 }
1918
1919 return 0;
1920 }
1921
1922 /*
1923 * Configure/autoconfigure the port.
1924 */
1925 static void atmel_config_port(struct uart_port *port, int flags)
1926 {
1927 if (flags & UART_CONFIG_TYPE) {
1928 port->type = PORT_ATMEL;
1929 atmel_request_port(port);
1930 }
1931 }
1932
1933 /*
1934 * Verify the new serial_struct (for TIOCSSERIAL).
1935 */
1936 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
1937 {
1938 int ret = 0;
1939 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
1940 ret = -EINVAL;
1941 if (port->irq != ser->irq)
1942 ret = -EINVAL;
1943 if (ser->io_type != SERIAL_IO_MEM)
1944 ret = -EINVAL;
1945 if (port->uartclk / 16 != ser->baud_base)
1946 ret = -EINVAL;
1947 if ((void *)port->mapbase != ser->iomem_base)
1948 ret = -EINVAL;
1949 if (port->iobase != ser->port)
1950 ret = -EINVAL;
1951 if (ser->hub6 != 0)
1952 ret = -EINVAL;
1953 return ret;
1954 }
1955
1956 #ifdef CONFIG_CONSOLE_POLL
1957 static int atmel_poll_get_char(struct uart_port *port)
1958 {
1959 while (!(UART_GET_CSR(port) & ATMEL_US_RXRDY))
1960 cpu_relax();
1961
1962 return UART_GET_CHAR(port);
1963 }
1964
1965 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
1966 {
1967 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY))
1968 cpu_relax();
1969
1970 UART_PUT_CHAR(port, ch);
1971 }
1972 #endif
1973
1974 static int
1975 atmel_ioctl(struct uart_port *port, unsigned int cmd, unsigned long arg)
1976 {
1977 struct serial_rs485 rs485conf;
1978
1979 switch (cmd) {
1980 case TIOCSRS485:
1981 if (copy_from_user(&rs485conf, (struct serial_rs485 *) arg,
1982 sizeof(rs485conf)))
1983 return -EFAULT;
1984
1985 atmel_config_rs485(port, &rs485conf);
1986 break;
1987
1988 case TIOCGRS485:
1989 if (copy_to_user((struct serial_rs485 *) arg,
1990 &(to_atmel_uart_port(port)->rs485),
1991 sizeof(rs485conf)))
1992 return -EFAULT;
1993 break;
1994
1995 default:
1996 return -ENOIOCTLCMD;
1997 }
1998 return 0;
1999 }
2000
2001
2002
2003 static struct uart_ops atmel_pops = {
2004 .tx_empty = atmel_tx_empty,
2005 .set_mctrl = atmel_set_mctrl,
2006 .get_mctrl = atmel_get_mctrl,
2007 .stop_tx = atmel_stop_tx,
2008 .start_tx = atmel_start_tx,
2009 .stop_rx = atmel_stop_rx,
2010 .enable_ms = atmel_enable_ms,
2011 .break_ctl = atmel_break_ctl,
2012 .startup = atmel_startup,
2013 .shutdown = atmel_shutdown,
2014 .flush_buffer = atmel_flush_buffer,
2015 .set_termios = atmel_set_termios,
2016 .set_ldisc = atmel_set_ldisc,
2017 .type = atmel_type,
2018 .release_port = atmel_release_port,
2019 .request_port = atmel_request_port,
2020 .config_port = atmel_config_port,
2021 .verify_port = atmel_verify_port,
2022 .pm = atmel_serial_pm,
2023 .ioctl = atmel_ioctl,
2024 #ifdef CONFIG_CONSOLE_POLL
2025 .poll_get_char = atmel_poll_get_char,
2026 .poll_put_char = atmel_poll_put_char,
2027 #endif
2028 };
2029
2030 /*
2031 * Configure the port from the platform device resource info.
2032 */
2033 static int atmel_init_port(struct atmel_uart_port *atmel_port,
2034 struct platform_device *pdev)
2035 {
2036 int ret;
2037 struct uart_port *port = &atmel_port->uart;
2038 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2039
2040 if (!atmel_init_property(atmel_port, pdev))
2041 atmel_set_ops(port);
2042
2043 atmel_init_rs485(atmel_port, pdev);
2044
2045 port->iotype = UPIO_MEM;
2046 port->flags = UPF_BOOT_AUTOCONF;
2047 port->ops = &atmel_pops;
2048 port->fifosize = 1;
2049 port->dev = &pdev->dev;
2050 port->mapbase = pdev->resource[0].start;
2051 port->irq = pdev->resource[1].start;
2052
2053 tasklet_init(&atmel_port->tasklet, atmel_tasklet_func,
2054 (unsigned long)port);
2055
2056 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2057
2058 if (pdata && pdata->regs) {
2059 /* Already mapped by setup code */
2060 port->membase = pdata->regs;
2061 } else {
2062 port->flags |= UPF_IOREMAP;
2063 port->membase = NULL;
2064 }
2065
2066 /* for console, the clock could already be configured */
2067 if (!atmel_port->clk) {
2068 atmel_port->clk = clk_get(&pdev->dev, "usart");
2069 if (IS_ERR(atmel_port->clk)) {
2070 ret = PTR_ERR(atmel_port->clk);
2071 atmel_port->clk = NULL;
2072 return ret;
2073 }
2074 ret = clk_prepare_enable(atmel_port->clk);
2075 if (ret) {
2076 clk_put(atmel_port->clk);
2077 atmel_port->clk = NULL;
2078 return ret;
2079 }
2080 port->uartclk = clk_get_rate(atmel_port->clk);
2081 clk_disable_unprepare(atmel_port->clk);
2082 /* only enable clock when USART is in use */
2083 }
2084
2085 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */
2086 if (atmel_port->rs485.flags & SER_RS485_ENABLED)
2087 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2088 else if (atmel_use_pdc_tx(port)) {
2089 port->fifosize = PDC_BUFFER_SIZE;
2090 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2091 } else {
2092 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2093 }
2094
2095 return 0;
2096 }
2097
2098 struct platform_device *atmel_default_console_device; /* the serial console device */
2099
2100 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2101 static void atmel_console_putchar(struct uart_port *port, int ch)
2102 {
2103 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY))
2104 cpu_relax();
2105 UART_PUT_CHAR(port, ch);
2106 }
2107
2108 /*
2109 * Interrupts are disabled on entering
2110 */
2111 static void atmel_console_write(struct console *co, const char *s, u_int count)
2112 {
2113 struct uart_port *port = &atmel_ports[co->index].uart;
2114 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2115 unsigned int status, imr;
2116 unsigned int pdc_tx;
2117
2118 /*
2119 * First, save IMR and then disable interrupts
2120 */
2121 imr = UART_GET_IMR(port);
2122 UART_PUT_IDR(port, ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2123
2124 /* Store PDC transmit status and disable it */
2125 pdc_tx = UART_GET_PTSR(port) & ATMEL_PDC_TXTEN;
2126 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
2127
2128 uart_console_write(port, s, count, atmel_console_putchar);
2129
2130 /*
2131 * Finally, wait for transmitter to become empty
2132 * and restore IMR
2133 */
2134 do {
2135 status = UART_GET_CSR(port);
2136 } while (!(status & ATMEL_US_TXRDY));
2137
2138 /* Restore PDC transmit status */
2139 if (pdc_tx)
2140 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
2141
2142 /* set interrupts back the way they were */
2143 UART_PUT_IER(port, imr);
2144 }
2145
2146 /*
2147 * If the port was already initialised (eg, by a boot loader),
2148 * try to determine the current setup.
2149 */
2150 static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2151 int *parity, int *bits)
2152 {
2153 unsigned int mr, quot;
2154
2155 /*
2156 * If the baud rate generator isn't running, the port wasn't
2157 * initialized by the boot loader.
2158 */
2159 quot = UART_GET_BRGR(port) & ATMEL_US_CD;
2160 if (!quot)
2161 return;
2162
2163 mr = UART_GET_MR(port) & ATMEL_US_CHRL;
2164 if (mr == ATMEL_US_CHRL_8)
2165 *bits = 8;
2166 else
2167 *bits = 7;
2168
2169 mr = UART_GET_MR(port) & ATMEL_US_PAR;
2170 if (mr == ATMEL_US_PAR_EVEN)
2171 *parity = 'e';
2172 else if (mr == ATMEL_US_PAR_ODD)
2173 *parity = 'o';
2174
2175 /*
2176 * The serial core only rounds down when matching this to a
2177 * supported baud rate. Make sure we don't end up slightly
2178 * lower than one of those, as it would make us fall through
2179 * to a much lower baud rate than we really want.
2180 */
2181 *baud = port->uartclk / (16 * (quot - 1));
2182 }
2183
2184 static int __init atmel_console_setup(struct console *co, char *options)
2185 {
2186 int ret;
2187 struct uart_port *port = &atmel_ports[co->index].uart;
2188 int baud = 115200;
2189 int bits = 8;
2190 int parity = 'n';
2191 int flow = 'n';
2192
2193 if (port->membase == NULL) {
2194 /* Port not initialized yet - delay setup */
2195 return -ENODEV;
2196 }
2197
2198 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2199 if (ret)
2200 return ret;
2201
2202 UART_PUT_IDR(port, -1);
2203 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2204 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
2205
2206 if (options)
2207 uart_parse_options(options, &baud, &parity, &bits, &flow);
2208 else
2209 atmel_console_get_options(port, &baud, &parity, &bits);
2210
2211 return uart_set_options(port, co, baud, parity, bits, flow);
2212 }
2213
2214 static struct uart_driver atmel_uart;
2215
2216 static struct console atmel_console = {
2217 .name = ATMEL_DEVICENAME,
2218 .write = atmel_console_write,
2219 .device = uart_console_device,
2220 .setup = atmel_console_setup,
2221 .flags = CON_PRINTBUFFER,
2222 .index = -1,
2223 .data = &atmel_uart,
2224 };
2225
2226 #define ATMEL_CONSOLE_DEVICE (&atmel_console)
2227
2228 /*
2229 * Early console initialization (before VM subsystem initialized).
2230 */
2231 static int __init atmel_console_init(void)
2232 {
2233 int ret;
2234 if (atmel_default_console_device) {
2235 struct atmel_uart_data *pdata =
2236 dev_get_platdata(&atmel_default_console_device->dev);
2237 int id = pdata->num;
2238 struct atmel_uart_port *port = &atmel_ports[id];
2239
2240 port->backup_imr = 0;
2241 port->uart.line = id;
2242
2243 add_preferred_console(ATMEL_DEVICENAME, id, NULL);
2244 ret = atmel_init_port(port, atmel_default_console_device);
2245 if (ret)
2246 return ret;
2247 register_console(&atmel_console);
2248 }
2249
2250 return 0;
2251 }
2252
2253 console_initcall(atmel_console_init);
2254
2255 /*
2256 * Late console initialization.
2257 */
2258 static int __init atmel_late_console_init(void)
2259 {
2260 if (atmel_default_console_device
2261 && !(atmel_console.flags & CON_ENABLED))
2262 register_console(&atmel_console);
2263
2264 return 0;
2265 }
2266
2267 core_initcall(atmel_late_console_init);
2268
2269 static inline bool atmel_is_console_port(struct uart_port *port)
2270 {
2271 return port->cons && port->cons->index == port->line;
2272 }
2273
2274 #else
2275 #define ATMEL_CONSOLE_DEVICE NULL
2276
2277 static inline bool atmel_is_console_port(struct uart_port *port)
2278 {
2279 return false;
2280 }
2281 #endif
2282
2283 static struct uart_driver atmel_uart = {
2284 .owner = THIS_MODULE,
2285 .driver_name = "atmel_serial",
2286 .dev_name = ATMEL_DEVICENAME,
2287 .major = SERIAL_ATMEL_MAJOR,
2288 .minor = MINOR_START,
2289 .nr = ATMEL_MAX_UART,
2290 .cons = ATMEL_CONSOLE_DEVICE,
2291 };
2292
2293 #ifdef CONFIG_PM
2294 static bool atmel_serial_clk_will_stop(void)
2295 {
2296 #ifdef CONFIG_ARCH_AT91
2297 return at91_suspend_entering_slow_clock();
2298 #else
2299 return false;
2300 #endif
2301 }
2302
2303 static int atmel_serial_suspend(struct platform_device *pdev,
2304 pm_message_t state)
2305 {
2306 struct uart_port *port = platform_get_drvdata(pdev);
2307 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2308
2309 if (atmel_is_console_port(port) && console_suspend_enabled) {
2310 /* Drain the TX shifter */
2311 while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY))
2312 cpu_relax();
2313 }
2314
2315 /* we can not wake up if we're running on slow clock */
2316 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2317 if (atmel_serial_clk_will_stop())
2318 device_set_wakeup_enable(&pdev->dev, 0);
2319
2320 uart_suspend_port(&atmel_uart, port);
2321
2322 return 0;
2323 }
2324
2325 static int atmel_serial_resume(struct platform_device *pdev)
2326 {
2327 struct uart_port *port = platform_get_drvdata(pdev);
2328 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2329
2330 uart_resume_port(&atmel_uart, port);
2331 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
2332
2333 return 0;
2334 }
2335 #else
2336 #define atmel_serial_suspend NULL
2337 #define atmel_serial_resume NULL
2338 #endif
2339
2340 static int atmel_serial_probe(struct platform_device *pdev)
2341 {
2342 struct atmel_uart_port *port;
2343 struct device_node *np = pdev->dev.of_node;
2344 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2345 void *data;
2346 int ret = -ENODEV;
2347
2348 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2349
2350 if (np)
2351 ret = of_alias_get_id(np, "serial");
2352 else
2353 if (pdata)
2354 ret = pdata->num;
2355
2356 if (ret < 0)
2357 /* port id not found in platform data nor device-tree aliases:
2358 * auto-enumerate it */
2359 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
2360
2361 if (ret >= ATMEL_MAX_UART) {
2362 ret = -ENODEV;
2363 goto err;
2364 }
2365
2366 if (test_and_set_bit(ret, atmel_ports_in_use)) {
2367 /* port already in use */
2368 ret = -EBUSY;
2369 goto err;
2370 }
2371
2372 port = &atmel_ports[ret];
2373 port->backup_imr = 0;
2374 port->uart.line = ret;
2375
2376 ret = atmel_init_port(port, pdev);
2377 if (ret)
2378 goto err_clear_bit;
2379
2380 if (!atmel_use_pdc_rx(&port->uart)) {
2381 ret = -ENOMEM;
2382 data = kmalloc(sizeof(struct atmel_uart_char)
2383 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
2384 if (!data)
2385 goto err_alloc_ring;
2386 port->rx_ring.buf = data;
2387 }
2388
2389 ret = uart_add_one_port(&atmel_uart, &port->uart);
2390 if (ret)
2391 goto err_add_port;
2392
2393 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2394 if (atmel_is_console_port(&port->uart)
2395 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2396 /*
2397 * The serial core enabled the clock for us, so undo
2398 * the clk_prepare_enable() in atmel_console_setup()
2399 */
2400 clk_disable_unprepare(port->clk);
2401 }
2402 #endif
2403
2404 device_init_wakeup(&pdev->dev, 1);
2405 platform_set_drvdata(pdev, port);
2406
2407 if (port->rs485.flags & SER_RS485_ENABLED) {
2408 UART_PUT_MR(&port->uart, ATMEL_US_USMODE_NORMAL);
2409 UART_PUT_CR(&port->uart, ATMEL_US_RTSEN);
2410 }
2411
2412 /*
2413 * Get port name of usart or uart
2414 */
2415 atmel_get_ip_name(&port->uart);
2416
2417 return 0;
2418
2419 err_add_port:
2420 kfree(port->rx_ring.buf);
2421 port->rx_ring.buf = NULL;
2422 err_alloc_ring:
2423 if (!atmel_is_console_port(&port->uart)) {
2424 clk_put(port->clk);
2425 port->clk = NULL;
2426 }
2427 err_clear_bit:
2428 clear_bit(port->uart.line, atmel_ports_in_use);
2429 err:
2430 return ret;
2431 }
2432
2433 static int atmel_serial_remove(struct platform_device *pdev)
2434 {
2435 struct uart_port *port = platform_get_drvdata(pdev);
2436 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2437 int ret = 0;
2438
2439 tasklet_kill(&atmel_port->tasklet);
2440
2441 device_init_wakeup(&pdev->dev, 0);
2442
2443 ret = uart_remove_one_port(&atmel_uart, port);
2444
2445 kfree(atmel_port->rx_ring.buf);
2446
2447 /* "port" is allocated statically, so we shouldn't free it */
2448
2449 clear_bit(port->line, atmel_ports_in_use);
2450
2451 clk_put(atmel_port->clk);
2452
2453 return ret;
2454 }
2455
2456 static struct platform_driver atmel_serial_driver = {
2457 .probe = atmel_serial_probe,
2458 .remove = atmel_serial_remove,
2459 .suspend = atmel_serial_suspend,
2460 .resume = atmel_serial_resume,
2461 .driver = {
2462 .name = "atmel_usart",
2463 .owner = THIS_MODULE,
2464 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
2465 },
2466 };
2467
2468 static int __init atmel_serial_init(void)
2469 {
2470 int ret;
2471
2472 ret = uart_register_driver(&atmel_uart);
2473 if (ret)
2474 return ret;
2475
2476 ret = platform_driver_register(&atmel_serial_driver);
2477 if (ret)
2478 uart_unregister_driver(&atmel_uart);
2479
2480 return ret;
2481 }
2482
2483 static void __exit atmel_serial_exit(void)
2484 {
2485 platform_driver_unregister(&atmel_serial_driver);
2486 uart_unregister_driver(&atmel_uart);
2487 }
2488
2489 module_init(atmel_serial_init);
2490 module_exit(atmel_serial_exit);
2491
2492 MODULE_AUTHOR("Rick Bronson");
2493 MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver");
2494 MODULE_LICENSE("GPL");
2495 MODULE_ALIAS("platform:atmel_usart");
Linux with added FPC-III support