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Linux 3.12.39
[linux/fpc-iii.git] / drivers / tty / serial / samsung.c
blob6b0adfbfacafb55487e5cd9d29ed36e4d869db37
1 /*
2 * Driver core for Samsung SoC onboard UARTs.
3 *
4 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 /* Hote on 2410 error handling
13 *
14 * The s3c2410 manual has a love/hate affair with the contents of the
15 * UERSTAT register in the UART blocks, and keeps marking some of the
16 * error bits as reserved. Having checked with the s3c2410x01,
17 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
18 * feature from the latter versions of the manual.
19 *
20 * If it becomes aparrent that latter versions of the 2410 remove these
21 * bits, then action will have to be taken to differentiate the versions
22 * and change the policy on BREAK
23 *
24 * BJD, 04-Nov-2004
25 */
26
27 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
28 #define SUPPORT_SYSRQ
29 #endif
30
31 #include <linux/module.h>
32 #include <linux/ioport.h>
33 #include <linux/io.h>
34 #include <linux/platform_device.h>
35 #include <linux/init.h>
36 #include <linux/sysrq.h>
37 #include <linux/console.h>
38 #include <linux/tty.h>
39 #include <linux/tty_flip.h>
40 #include <linux/serial_core.h>
41 #include <linux/serial.h>
42 #include <linux/serial_s3c.h>
43 #include <linux/delay.h>
44 #include <linux/clk.h>
45 #include <linux/cpufreq.h>
46 #include <linux/of.h>
47
48 #include <asm/irq.h>
49
50 #ifdef CONFIG_SAMSUNG_CLOCK
51 #include <plat/clock.h>
52 #endif
53
54 #include "samsung.h"
55
56 /* UART name and device definitions */
57
58 #define S3C24XX_SERIAL_NAME "ttySAC"
59 #define S3C24XX_SERIAL_MAJOR 204
60 #define S3C24XX_SERIAL_MINOR 64
61
62 /* macros to change one thing to another */
63
64 #define tx_enabled(port) ((port)->unused[0])
65 #define rx_enabled(port) ((port)->unused[1])
66
67 /* flag to ignore all characters coming in */
68 #define RXSTAT_DUMMY_READ (0x10000000)
69
70 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
71 {
72 return container_of(port, struct s3c24xx_uart_port, port);
73 }
74
75 /* translate a port to the device name */
76
77 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
78 {
79 return to_platform_device(port->dev)->name;
80 }
81
82 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
83 {
84 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
85 }
86
87 /*
88 * s3c64xx and later SoC's include the interrupt mask and status registers in
89 * the controller itself, unlike the s3c24xx SoC's which have these registers
90 * in the interrupt controller. Check if the port type is s3c64xx or higher.
91 */
92 static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
93 {
94 return to_ourport(port)->info->type == PORT_S3C6400;
95 }
96
97 static void s3c24xx_serial_rx_enable(struct uart_port *port)
98 {
99 unsigned long flags;
100 unsigned int ucon, ufcon;
101 int count = 10000;
102
103 spin_lock_irqsave(&port->lock, flags);
104
105 while (--count && !s3c24xx_serial_txempty_nofifo(port))
106 udelay(100);
107
108 ufcon = rd_regl(port, S3C2410_UFCON);
109 ufcon |= S3C2410_UFCON_RESETRX;
110 wr_regl(port, S3C2410_UFCON, ufcon);
111
112 ucon = rd_regl(port, S3C2410_UCON);
113 ucon |= S3C2410_UCON_RXIRQMODE;
114 wr_regl(port, S3C2410_UCON, ucon);
115
116 rx_enabled(port) = 1;
117 spin_unlock_irqrestore(&port->lock, flags);
118 }
119
120 static void s3c24xx_serial_rx_disable(struct uart_port *port)
121 {
122 unsigned long flags;
123 unsigned int ucon;
124
125 spin_lock_irqsave(&port->lock, flags);
126
127 ucon = rd_regl(port, S3C2410_UCON);
128 ucon &= ~S3C2410_UCON_RXIRQMODE;
129 wr_regl(port, S3C2410_UCON, ucon);
130
131 rx_enabled(port) = 0;
132 spin_unlock_irqrestore(&port->lock, flags);
133 }
134
135 static void s3c24xx_serial_stop_tx(struct uart_port *port)
136 {
137 struct s3c24xx_uart_port *ourport = to_ourport(port);
138
139 if (tx_enabled(port)) {
140 if (s3c24xx_serial_has_interrupt_mask(port))
141 __set_bit(S3C64XX_UINTM_TXD,
142 portaddrl(port, S3C64XX_UINTM));
143 else
144 disable_irq_nosync(ourport->tx_irq);
145 tx_enabled(port) = 0;
146 if (port->flags & UPF_CONS_FLOW)
147 s3c24xx_serial_rx_enable(port);
148 }
149 }
150
151 static void s3c24xx_serial_start_tx(struct uart_port *port)
152 {
153 struct s3c24xx_uart_port *ourport = to_ourport(port);
154
155 if (!tx_enabled(port)) {
156 if (port->flags & UPF_CONS_FLOW)
157 s3c24xx_serial_rx_disable(port);
158
159 if (s3c24xx_serial_has_interrupt_mask(port))
160 __clear_bit(S3C64XX_UINTM_TXD,
161 portaddrl(port, S3C64XX_UINTM));
162 else
163 enable_irq(ourport->tx_irq);
164 tx_enabled(port) = 1;
165 }
166 }
167
168 static void s3c24xx_serial_stop_rx(struct uart_port *port)
169 {
170 struct s3c24xx_uart_port *ourport = to_ourport(port);
171
172 if (rx_enabled(port)) {
173 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
174 if (s3c24xx_serial_has_interrupt_mask(port))
175 __set_bit(S3C64XX_UINTM_RXD,
176 portaddrl(port, S3C64XX_UINTM));
177 else
178 disable_irq_nosync(ourport->rx_irq);
179 rx_enabled(port) = 0;
180 }
181 }
182
183 static void s3c24xx_serial_enable_ms(struct uart_port *port)
184 {
185 }
186
187 static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port)
188 {
189 return to_ourport(port)->info;
190 }
191
192 static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port)
193 {
194 struct s3c24xx_uart_port *ourport;
195
196 if (port->dev == NULL)
197 return NULL;
198
199 ourport = container_of(port, struct s3c24xx_uart_port, port);
200 return ourport->cfg;
201 }
202
203 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
204 unsigned long ufstat)
205 {
206 struct s3c24xx_uart_info *info = ourport->info;
207
208 if (ufstat & info->rx_fifofull)
209 return ourport->port.fifosize;
210
211 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
212 }
213
214
215 /* ? - where has parity gone?? */
216 #define S3C2410_UERSTAT_PARITY (0x1000)
217
218 static irqreturn_t
219 s3c24xx_serial_rx_chars(int irq, void *dev_id)
220 {
221 struct s3c24xx_uart_port *ourport = dev_id;
222 struct uart_port *port = &ourport->port;
223 unsigned int ufcon, ch, flag, ufstat, uerstat;
224 unsigned long flags;
225 int max_count = 64;
226
227 spin_lock_irqsave(&port->lock, flags);
228
229 while (max_count-- > 0) {
230 ufcon = rd_regl(port, S3C2410_UFCON);
231 ufstat = rd_regl(port, S3C2410_UFSTAT);
232
233 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
234 break;
235
236 uerstat = rd_regl(port, S3C2410_UERSTAT);
237 ch = rd_regb(port, S3C2410_URXH);
238
239 if (port->flags & UPF_CONS_FLOW) {
240 int txe = s3c24xx_serial_txempty_nofifo(port);
241
242 if (rx_enabled(port)) {
243 if (!txe) {
244 rx_enabled(port) = 0;
245 continue;
246 }
247 } else {
248 if (txe) {
249 ufcon |= S3C2410_UFCON_RESETRX;
250 wr_regl(port, S3C2410_UFCON, ufcon);
251 rx_enabled(port) = 1;
252 spin_unlock_irqrestore(&port->lock,
253 flags);
254 goto out;
255 }
256 continue;
257 }
258 }
259
260 /* insert the character into the buffer */
261
262 flag = TTY_NORMAL;
263 port->icount.rx++;
264
265 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
266 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
267 ch, uerstat);
268
269 /* check for break */
270 if (uerstat & S3C2410_UERSTAT_BREAK) {
271 dbg("break!\n");
272 port->icount.brk++;
273 if (uart_handle_break(port))
274 goto ignore_char;
275 }
276
277 if (uerstat & S3C2410_UERSTAT_FRAME)
278 port->icount.frame++;
279 if (uerstat & S3C2410_UERSTAT_OVERRUN)
280 port->icount.overrun++;
281
282 uerstat &= port->read_status_mask;
283
284 if (uerstat & S3C2410_UERSTAT_BREAK)
285 flag = TTY_BREAK;
286 else if (uerstat & S3C2410_UERSTAT_PARITY)
287 flag = TTY_PARITY;
288 else if (uerstat & (S3C2410_UERSTAT_FRAME |
289 S3C2410_UERSTAT_OVERRUN))
290 flag = TTY_FRAME;
291 }
292
293 if (uart_handle_sysrq_char(port, ch))
294 goto ignore_char;
295
296 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
297 ch, flag);
298
299 ignore_char:
300 continue;
301 }
302
303 spin_unlock_irqrestore(&port->lock, flags);
304 tty_flip_buffer_push(&port->state->port);
305
306 out:
307 return IRQ_HANDLED;
308 }
309
310 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
311 {
312 struct s3c24xx_uart_port *ourport = id;
313 struct uart_port *port = &ourport->port;
314 struct circ_buf *xmit = &port->state->xmit;
315 unsigned long flags;
316 int count = 256;
317
318 spin_lock_irqsave(&port->lock, flags);
319
320 if (port->x_char) {
321 wr_regb(port, S3C2410_UTXH, port->x_char);
322 port->icount.tx++;
323 port->x_char = 0;
324 goto out;
325 }
326
327 /* if there isn't anything more to transmit, or the uart is now
328 * stopped, disable the uart and exit
329 */
330
331 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
332 s3c24xx_serial_stop_tx(port);
333 goto out;
334 }
335
336 /* try and drain the buffer... */
337
338 while (!uart_circ_empty(xmit) && count-- > 0) {
339 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
340 break;
341
342 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
343 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
344 port->icount.tx++;
345 }
346
347 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
348 spin_unlock(&port->lock);
349 uart_write_wakeup(port);
350 spin_lock(&port->lock);
351 }
352
353 if (uart_circ_empty(xmit))
354 s3c24xx_serial_stop_tx(port);
355
356 out:
357 spin_unlock_irqrestore(&port->lock, flags);
358 return IRQ_HANDLED;
359 }
360
361 /* interrupt handler for s3c64xx and later SoC's.*/
362 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
363 {
364 struct s3c24xx_uart_port *ourport = id;
365 struct uart_port *port = &ourport->port;
366 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
367 irqreturn_t ret = IRQ_HANDLED;
368
369 if (pend & S3C64XX_UINTM_RXD_MSK) {
370 ret = s3c24xx_serial_rx_chars(irq, id);
371 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
372 }
373 if (pend & S3C64XX_UINTM_TXD_MSK) {
374 ret = s3c24xx_serial_tx_chars(irq, id);
375 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
376 }
377 return ret;
378 }
379
380 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
381 {
382 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
383 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
384 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
385
386 if (ufcon & S3C2410_UFCON_FIFOMODE) {
387 if ((ufstat & info->tx_fifomask) != 0 ||
388 (ufstat & info->tx_fifofull))
389 return 0;
390
391 return 1;
392 }
393
394 return s3c24xx_serial_txempty_nofifo(port);
395 }
396
397 /* no modem control lines */
398 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
399 {
400 unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
401
402 if (umstat & S3C2410_UMSTAT_CTS)
403 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
404 else
405 return TIOCM_CAR | TIOCM_DSR;
406 }
407
408 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
409 {
410 /* todo - possibly remove AFC and do manual CTS */
411 }
412
413 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
414 {
415 unsigned long flags;
416 unsigned int ucon;
417
418 spin_lock_irqsave(&port->lock, flags);
419
420 ucon = rd_regl(port, S3C2410_UCON);
421
422 if (break_state)
423 ucon |= S3C2410_UCON_SBREAK;
424 else
425 ucon &= ~S3C2410_UCON_SBREAK;
426
427 wr_regl(port, S3C2410_UCON, ucon);
428
429 spin_unlock_irqrestore(&port->lock, flags);
430 }
431
432 static void s3c24xx_serial_shutdown(struct uart_port *port)
433 {
434 struct s3c24xx_uart_port *ourport = to_ourport(port);
435
436 if (ourport->tx_claimed) {
437 if (!s3c24xx_serial_has_interrupt_mask(port))
438 free_irq(ourport->tx_irq, ourport);
439 tx_enabled(port) = 0;
440 ourport->tx_claimed = 0;
441 }
442
443 if (ourport->rx_claimed) {
444 if (!s3c24xx_serial_has_interrupt_mask(port))
445 free_irq(ourport->rx_irq, ourport);
446 ourport->rx_claimed = 0;
447 rx_enabled(port) = 0;
448 }
449
450 /* Clear pending interrupts and mask all interrupts */
451 if (s3c24xx_serial_has_interrupt_mask(port)) {
452 free_irq(port->irq, ourport);
453
454 wr_regl(port, S3C64XX_UINTP, 0xf);
455 wr_regl(port, S3C64XX_UINTM, 0xf);
456 }
457 }
458
459 static int s3c24xx_serial_startup(struct uart_port *port)
460 {
461 struct s3c24xx_uart_port *ourport = to_ourport(port);
462 int ret;
463
464 dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n",
465 port->mapbase, port->membase);
466
467 rx_enabled(port) = 1;
468
469 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
470 s3c24xx_serial_portname(port), ourport);
471
472 if (ret != 0) {
473 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
474 return ret;
475 }
476
477 ourport->rx_claimed = 1;
478
479 dbg("requesting tx irq...\n");
480
481 tx_enabled(port) = 1;
482
483 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
484 s3c24xx_serial_portname(port), ourport);
485
486 if (ret) {
487 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
488 goto err;
489 }
490
491 ourport->tx_claimed = 1;
492
493 dbg("s3c24xx_serial_startup ok\n");
494
495 /* the port reset code should have done the correct
496 * register setup for the port controls */
497
498 return ret;
499
500 err:
501 s3c24xx_serial_shutdown(port);
502 return ret;
503 }
504
505 static int s3c64xx_serial_startup(struct uart_port *port)
506 {
507 struct s3c24xx_uart_port *ourport = to_ourport(port);
508 int ret;
509
510 dbg("s3c64xx_serial_startup: port=%p (%08lx,%p)\n",
511 port->mapbase, port->membase);
512
513 wr_regl(port, S3C64XX_UINTM, 0xf);
514
515 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
516 s3c24xx_serial_portname(port), ourport);
517 if (ret) {
518 dev_err(port->dev, "cannot get irq %d\n", port->irq);
519 return ret;
520 }
521
522 /* For compatibility with s3c24xx Soc's */
523 rx_enabled(port) = 1;
524 ourport->rx_claimed = 1;
525 tx_enabled(port) = 0;
526 ourport->tx_claimed = 1;
527
528 /* Enable Rx Interrupt */
529 __clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM));
530 dbg("s3c64xx_serial_startup ok\n");
531 return ret;
532 }
533
534 /* power power management control */
535
536 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
537 unsigned int old)
538 {
539 struct s3c24xx_uart_port *ourport = to_ourport(port);
540 int timeout = 10000;
541
542 ourport->pm_level = level;
543
544 switch (level) {
545 case 3:
546 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
547 udelay(100);
548
549 if (!IS_ERR(ourport->baudclk))
550 clk_disable_unprepare(ourport->baudclk);
551
552 clk_disable_unprepare(ourport->clk);
553 break;
554
555 case 0:
556 clk_prepare_enable(ourport->clk);
557
558 if (!IS_ERR(ourport->baudclk))
559 clk_prepare_enable(ourport->baudclk);
560
561 break;
562 default:
563 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
564 }
565 }
566
567 /* baud rate calculation
568 *
569 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
570 * of different sources, including the peripheral clock ("pclk") and an
571 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
572 * with a programmable extra divisor.
573 *
574 * The following code goes through the clock sources, and calculates the
575 * baud clocks (and the resultant actual baud rates) and then tries to
576 * pick the closest one and select that.
577 *
578 */
579
580 #define MAX_CLK_NAME_LENGTH 15
581
582 static inline int s3c24xx_serial_getsource(struct uart_port *port)
583 {
584 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
585 unsigned int ucon;
586
587 if (info->num_clks == 1)
588 return 0;
589
590 ucon = rd_regl(port, S3C2410_UCON);
591 ucon &= info->clksel_mask;
592 return ucon >> info->clksel_shift;
593 }
594
595 static void s3c24xx_serial_setsource(struct uart_port *port,
596 unsigned int clk_sel)
597 {
598 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
599 unsigned int ucon;
600
601 if (info->num_clks == 1)
602 return;
603
604 ucon = rd_regl(port, S3C2410_UCON);
605 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
606 return;
607
608 ucon &= ~info->clksel_mask;
609 ucon |= clk_sel << info->clksel_shift;
610 wr_regl(port, S3C2410_UCON, ucon);
611 }
612
613 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
614 unsigned int req_baud, struct clk **best_clk,
615 unsigned int *clk_num)
616 {
617 struct s3c24xx_uart_info *info = ourport->info;
618 struct clk *clk;
619 unsigned long rate;
620 unsigned int cnt, baud, quot, clk_sel, best_quot = 0;
621 char clkname[MAX_CLK_NAME_LENGTH];
622 int calc_deviation, deviation = (1 << 30) - 1;
623
624 clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
625 ourport->info->def_clk_sel;
626 for (cnt = 0; cnt < info->num_clks; cnt++) {
627 if (!(clk_sel & (1 << cnt)))
628 continue;
629
630 sprintf(clkname, "clk_uart_baud%d", cnt);
631 clk = clk_get(ourport->port.dev, clkname);
632 if (IS_ERR(clk))
633 continue;
634
635 rate = clk_get_rate(clk);
636 if (!rate)
637 continue;
638
639 if (ourport->info->has_divslot) {
640 unsigned long div = rate / req_baud;
641
642 /* The UDIVSLOT register on the newer UARTs allows us to
643 * get a divisor adjustment of 1/16th on the baud clock.
644 *
645 * We don't keep the UDIVSLOT value (the 16ths we
646 * calculated by not multiplying the baud by 16) as it
647 * is easy enough to recalculate.
648 */
649
650 quot = div / 16;
651 baud = rate / div;
652 } else {
653 quot = (rate + (8 * req_baud)) / (16 * req_baud);
654 baud = rate / (quot * 16);
655 }
656 quot--;
657
658 calc_deviation = req_baud - baud;
659 if (calc_deviation < 0)
660 calc_deviation = -calc_deviation;
661
662 if (calc_deviation < deviation) {
663 *best_clk = clk;
664 best_quot = quot;
665 *clk_num = cnt;
666 deviation = calc_deviation;
667 }
668 }
669
670 return best_quot;
671 }
672
673 /* udivslot_table[]
674 *
675 * This table takes the fractional value of the baud divisor and gives
676 * the recommended setting for the UDIVSLOT register.
677 */
678 static u16 udivslot_table[16] = {
679 [0] = 0x0000,
680 [1] = 0x0080,
681 [2] = 0x0808,
682 [3] = 0x0888,
683 [4] = 0x2222,
684 [5] = 0x4924,
685 [6] = 0x4A52,
686 [7] = 0x54AA,
687 [8] = 0x5555,
688 [9] = 0xD555,
689 [10] = 0xD5D5,
690 [11] = 0xDDD5,
691 [12] = 0xDDDD,
692 [13] = 0xDFDD,
693 [14] = 0xDFDF,
694 [15] = 0xFFDF,
695 };
696
697 static void s3c24xx_serial_set_termios(struct uart_port *port,
698 struct ktermios *termios,
699 struct ktermios *old)
700 {
701 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
702 struct s3c24xx_uart_port *ourport = to_ourport(port);
703 struct clk *clk = ERR_PTR(-EINVAL);
704 unsigned long flags;
705 unsigned int baud, quot, clk_sel = 0;
706 unsigned int ulcon;
707 unsigned int umcon;
708 unsigned int udivslot = 0;
709
710 /*
711 * We don't support modem control lines.
712 */
713 termios->c_cflag &= ~(HUPCL | CMSPAR);
714 termios->c_cflag |= CLOCAL;
715
716 /*
717 * Ask the core to calculate the divisor for us.
718 */
719
720 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
721 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
722 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
723 quot = port->custom_divisor;
724 if (IS_ERR(clk))
725 return;
726
727 /* check to see if we need to change clock source */
728
729 if (ourport->baudclk != clk) {
730 s3c24xx_serial_setsource(port, clk_sel);
731
732 if (!IS_ERR(ourport->baudclk)) {
733 clk_disable_unprepare(ourport->baudclk);
734 ourport->baudclk = ERR_PTR(-EINVAL);
735 }
736
737 clk_prepare_enable(clk);
738
739 ourport->baudclk = clk;
740 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
741 }
742
743 if (ourport->info->has_divslot) {
744 unsigned int div = ourport->baudclk_rate / baud;
745
746 if (cfg->has_fracval) {
747 udivslot = (div & 15);
748 dbg("fracval = %04x\n", udivslot);
749 } else {
750 udivslot = udivslot_table[div & 15];
751 dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
752 }
753 }
754
755 switch (termios->c_cflag & CSIZE) {
756 case CS5:
757 dbg("config: 5bits/char\n");
758 ulcon = S3C2410_LCON_CS5;
759 break;
760 case CS6:
761 dbg("config: 6bits/char\n");
762 ulcon = S3C2410_LCON_CS6;
763 break;
764 case CS7:
765 dbg("config: 7bits/char\n");
766 ulcon = S3C2410_LCON_CS7;
767 break;
768 case CS8:
769 default:
770 dbg("config: 8bits/char\n");
771 ulcon = S3C2410_LCON_CS8;
772 break;
773 }
774
775 /* preserve original lcon IR settings */
776 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
777
778 if (termios->c_cflag & CSTOPB)
779 ulcon |= S3C2410_LCON_STOPB;
780
781 umcon = (termios->c_cflag & CRTSCTS) ? S3C2410_UMCOM_AFC : 0;
782
783 if (termios->c_cflag & PARENB) {
784 if (termios->c_cflag & PARODD)
785 ulcon |= S3C2410_LCON_PODD;
786 else
787 ulcon |= S3C2410_LCON_PEVEN;
788 } else {
789 ulcon |= S3C2410_LCON_PNONE;
790 }
791
792 spin_lock_irqsave(&port->lock, flags);
793
794 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
795 ulcon, quot, udivslot);
796
797 wr_regl(port, S3C2410_ULCON, ulcon);
798 wr_regl(port, S3C2410_UBRDIV, quot);
799 wr_regl(port, S3C2410_UMCON, umcon);
800
801 if (ourport->info->has_divslot)
802 wr_regl(port, S3C2443_DIVSLOT, udivslot);
803
804 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
805 rd_regl(port, S3C2410_ULCON),
806 rd_regl(port, S3C2410_UCON),
807 rd_regl(port, S3C2410_UFCON));
808
809 /*
810 * Update the per-port timeout.
811 */
812 uart_update_timeout(port, termios->c_cflag, baud);
813
814 /*
815 * Which character status flags are we interested in?
816 */
817 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
818 if (termios->c_iflag & INPCK)
819 port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY;
820
821 /*
822 * Which character status flags should we ignore?
823 */
824 port->ignore_status_mask = 0;
825 if (termios->c_iflag & IGNPAR)
826 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
827 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
828 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
829
830 /*
831 * Ignore all characters if CREAD is not set.
832 */
833 if ((termios->c_cflag & CREAD) == 0)
834 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
835
836 spin_unlock_irqrestore(&port->lock, flags);
837 }
838
839 static const char *s3c24xx_serial_type(struct uart_port *port)
840 {
841 switch (port->type) {
842 case PORT_S3C2410:
843 return "S3C2410";
844 case PORT_S3C2440:
845 return "S3C2440";
846 case PORT_S3C2412:
847 return "S3C2412";
848 case PORT_S3C6400:
849 return "S3C6400/10";
850 default:
851 return NULL;
852 }
853 }
854
855 #define MAP_SIZE (0x100)
856
857 static void s3c24xx_serial_release_port(struct uart_port *port)
858 {
859 release_mem_region(port->mapbase, MAP_SIZE);
860 }
861
862 static int s3c24xx_serial_request_port(struct uart_port *port)
863 {
864 const char *name = s3c24xx_serial_portname(port);
865 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
866 }
867
868 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
869 {
870 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
871
872 if (flags & UART_CONFIG_TYPE &&
873 s3c24xx_serial_request_port(port) == 0)
874 port->type = info->type;
875 }
876
877 /*
878 * verify the new serial_struct (for TIOCSSERIAL).
879 */
880 static int
881 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
882 {
883 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
884
885 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
886 return -EINVAL;
887
888 return 0;
889 }
890
891
892 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
893
894 static struct console s3c24xx_serial_console;
895
896 static int __init s3c24xx_serial_console_init(void)
897 {
898 register_console(&s3c24xx_serial_console);
899 return 0;
900 }
901 console_initcall(s3c24xx_serial_console_init);
902
903 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
904 #else
905 #define S3C24XX_SERIAL_CONSOLE NULL
906 #endif
907
908 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
909 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
910 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
911 unsigned char c);
912 #endif
913
914 static struct uart_ops s3c24xx_serial_ops = {
915 .pm = s3c24xx_serial_pm,
916 .tx_empty = s3c24xx_serial_tx_empty,
917 .get_mctrl = s3c24xx_serial_get_mctrl,
918 .set_mctrl = s3c24xx_serial_set_mctrl,
919 .stop_tx = s3c24xx_serial_stop_tx,
920 .start_tx = s3c24xx_serial_start_tx,
921 .stop_rx = s3c24xx_serial_stop_rx,
922 .enable_ms = s3c24xx_serial_enable_ms,
923 .break_ctl = s3c24xx_serial_break_ctl,
924 .startup = s3c24xx_serial_startup,
925 .shutdown = s3c24xx_serial_shutdown,
926 .set_termios = s3c24xx_serial_set_termios,
927 .type = s3c24xx_serial_type,
928 .release_port = s3c24xx_serial_release_port,
929 .request_port = s3c24xx_serial_request_port,
930 .config_port = s3c24xx_serial_config_port,
931 .verify_port = s3c24xx_serial_verify_port,
932 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
933 .poll_get_char = s3c24xx_serial_get_poll_char,
934 .poll_put_char = s3c24xx_serial_put_poll_char,
935 #endif
936 };
937
938 static struct uart_driver s3c24xx_uart_drv = {
939 .owner = THIS_MODULE,
940 .driver_name = "s3c2410_serial",
941 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
942 .cons = S3C24XX_SERIAL_CONSOLE,
943 .dev_name = S3C24XX_SERIAL_NAME,
944 .major = S3C24XX_SERIAL_MAJOR,
945 .minor = S3C24XX_SERIAL_MINOR,
946 };
947
948 static struct s3c24xx_uart_port s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
949 [0] = {
950 .port = {
951 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock),
952 .iotype = UPIO_MEM,
953 .uartclk = 0,
954 .fifosize = 16,
955 .ops = &s3c24xx_serial_ops,
956 .flags = UPF_BOOT_AUTOCONF,
957 .line = 0,
958 }
959 },
960 [1] = {
961 .port = {
962 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[1].port.lock),
963 .iotype = UPIO_MEM,
964 .uartclk = 0,
965 .fifosize = 16,
966 .ops = &s3c24xx_serial_ops,
967 .flags = UPF_BOOT_AUTOCONF,
968 .line = 1,
969 }
970 },
971 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
972
973 [2] = {
974 .port = {
975 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[2].port.lock),
976 .iotype = UPIO_MEM,
977 .uartclk = 0,
978 .fifosize = 16,
979 .ops = &s3c24xx_serial_ops,
980 .flags = UPF_BOOT_AUTOCONF,
981 .line = 2,
982 }
983 },
984 #endif
985 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
986 [3] = {
987 .port = {
988 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[3].port.lock),
989 .iotype = UPIO_MEM,
990 .uartclk = 0,
991 .fifosize = 16,
992 .ops = &s3c24xx_serial_ops,
993 .flags = UPF_BOOT_AUTOCONF,
994 .line = 3,
995 }
996 }
997 #endif
998 };
999
1000 /* s3c24xx_serial_resetport
1001 *
1002 * reset the fifos and other the settings.
1003 */
1004
1005 static void s3c24xx_serial_resetport(struct uart_port *port,
1006 struct s3c2410_uartcfg *cfg)
1007 {
1008 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1009 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1010 unsigned int ucon_mask;
1011
1012 ucon_mask = info->clksel_mask;
1013 if (info->type == PORT_S3C2440)
1014 ucon_mask |= S3C2440_UCON0_DIVMASK;
1015
1016 ucon &= ucon_mask;
1017 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1018
1019 /* reset both fifos */
1020 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1021 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1022
1023 /* some delay is required after fifo reset */
1024 udelay(1);
1025 }
1026
1027
1028 #ifdef CONFIG_CPU_FREQ
1029
1030 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1031 unsigned long val, void *data)
1032 {
1033 struct s3c24xx_uart_port *port;
1034 struct uart_port *uport;
1035
1036 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1037 uport = &port->port;
1038
1039 /* check to see if port is enabled */
1040
1041 if (port->pm_level != 0)
1042 return 0;
1043
1044 /* try and work out if the baudrate is changing, we can detect
1045 * a change in rate, but we do not have support for detecting
1046 * a disturbance in the clock-rate over the change.
1047 */
1048
1049 if (IS_ERR(port->baudclk))
1050 goto exit;
1051
1052 if (port->baudclk_rate == clk_get_rate(port->baudclk))
1053 goto exit;
1054
1055 if (val == CPUFREQ_PRECHANGE) {
1056 /* we should really shut the port down whilst the
1057 * frequency change is in progress. */
1058
1059 } else if (val == CPUFREQ_POSTCHANGE) {
1060 struct ktermios *termios;
1061 struct tty_struct *tty;
1062
1063 if (uport->state == NULL)
1064 goto exit;
1065
1066 tty = uport->state->port.tty;
1067
1068 if (tty == NULL)
1069 goto exit;
1070
1071 termios = &tty->termios;
1072
1073 if (termios == NULL) {
1074 dev_warn(uport->dev, "%s: no termios?\n", __func__);
1075 goto exit;
1076 }
1077
1078 s3c24xx_serial_set_termios(uport, termios, NULL);
1079 }
1080
1081 exit:
1082 return 0;
1083 }
1084
1085 static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1086 {
1087 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1088
1089 return cpufreq_register_notifier(&port->freq_transition,
1090 CPUFREQ_TRANSITION_NOTIFIER);
1091 }
1092
1093 static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1094 {
1095 cpufreq_unregister_notifier(&port->freq_transition,
1096 CPUFREQ_TRANSITION_NOTIFIER);
1097 }
1098
1099 #else
1100 static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1101 {
1102 return 0;
1103 }
1104
1105 static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1106 {
1107 }
1108 #endif
1109
1110 /* s3c24xx_serial_init_port
1111 *
1112 * initialise a single serial port from the platform device given
1113 */
1114
1115 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1116 struct platform_device *platdev)
1117 {
1118 struct uart_port *port = &ourport->port;
1119 struct s3c2410_uartcfg *cfg = ourport->cfg;
1120 struct resource *res;
1121 int ret;
1122
1123 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1124
1125 if (platdev == NULL)
1126 return -ENODEV;
1127
1128 if (port->mapbase != 0)
1129 return 0;
1130
1131 /* setup info for port */
1132 port->dev = &platdev->dev;
1133
1134 /* Startup sequence is different for s3c64xx and higher SoC's */
1135 if (s3c24xx_serial_has_interrupt_mask(port))
1136 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1137
1138 port->uartclk = 1;
1139
1140 if (cfg->uart_flags & UPF_CONS_FLOW) {
1141 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1142 port->flags |= UPF_CONS_FLOW;
1143 }
1144
1145 /* sort our the physical and virtual addresses for each UART */
1146
1147 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1148 if (res == NULL) {
1149 dev_err(port->dev, "failed to find memory resource for uart\n");
1150 return -EINVAL;
1151 }
1152
1153 dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
1154
1155 port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1156 if (!port->membase) {
1157 dev_err(port->dev, "failed to remap controller address\n");
1158 return -EBUSY;
1159 }
1160
1161 port->mapbase = res->start;
1162 ret = platform_get_irq(platdev, 0);
1163 if (ret < 0)
1164 port->irq = 0;
1165 else {
1166 port->irq = ret;
1167 ourport->rx_irq = ret;
1168 ourport->tx_irq = ret + 1;
1169 }
1170
1171 ret = platform_get_irq(platdev, 1);
1172 if (ret > 0)
1173 ourport->tx_irq = ret;
1174
1175 ourport->clk = clk_get(&platdev->dev, "uart");
1176 if (IS_ERR(ourport->clk)) {
1177 pr_err("%s: Controller clock not found\n",
1178 dev_name(&platdev->dev));
1179 return PTR_ERR(ourport->clk);
1180 }
1181
1182 ret = clk_prepare_enable(ourport->clk);
1183 if (ret) {
1184 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1185 clk_put(ourport->clk);
1186 return ret;
1187 }
1188
1189 /* Keep all interrupts masked and cleared */
1190 if (s3c24xx_serial_has_interrupt_mask(port)) {
1191 wr_regl(port, S3C64XX_UINTM, 0xf);
1192 wr_regl(port, S3C64XX_UINTP, 0xf);
1193 wr_regl(port, S3C64XX_UINTSP, 0xf);
1194 }
1195
1196 dbg("port: map=%08x, mem=%08x, irq=%d (%d,%d), clock=%ld\n",
1197 port->mapbase, port->membase, port->irq,
1198 ourport->rx_irq, ourport->tx_irq, port->uartclk);
1199
1200 /* reset the fifos (and setup the uart) */
1201 s3c24xx_serial_resetport(port, cfg);
1202 clk_disable_unprepare(ourport->clk);
1203 return 0;
1204 }
1205
1206 #ifdef CONFIG_SAMSUNG_CLOCK
1207 static ssize_t s3c24xx_serial_show_clksrc(struct device *dev,
1208 struct device_attribute *attr,
1209 char *buf)
1210 {
1211 struct uart_port *port = s3c24xx_dev_to_port(dev);
1212 struct s3c24xx_uart_port *ourport = to_ourport(port);
1213
1214 if (IS_ERR(ourport->baudclk))
1215 return -EINVAL;
1216
1217 return snprintf(buf, PAGE_SIZE, "* %s\n",
1218 ourport->baudclk->name ?: "(null)");
1219 }
1220
1221 static DEVICE_ATTR(clock_source, S_IRUGO, s3c24xx_serial_show_clksrc, NULL);
1222 #endif
1223
1224 /* Device driver serial port probe */
1225
1226 static const struct of_device_id s3c24xx_uart_dt_match[];
1227 static int probe_index;
1228
1229 static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1230 struct platform_device *pdev)
1231 {
1232 #ifdef CONFIG_OF
1233 if (pdev->dev.of_node) {
1234 const struct of_device_id *match;
1235 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1236 return (struct s3c24xx_serial_drv_data *)match->data;
1237 }
1238 #endif
1239 return (struct s3c24xx_serial_drv_data *)
1240 platform_get_device_id(pdev)->driver_data;
1241 }
1242
1243 static int s3c24xx_serial_probe(struct platform_device *pdev)
1244 {
1245 struct s3c24xx_uart_port *ourport;
1246 int ret;
1247
1248 dbg("s3c24xx_serial_probe(%p) %d\n", pdev, probe_index);
1249
1250 ourport = &s3c24xx_serial_ports[probe_index];
1251
1252 ourport->drv_data = s3c24xx_get_driver_data(pdev);
1253 if (!ourport->drv_data) {
1254 dev_err(&pdev->dev, "could not find driver data\n");
1255 return -ENODEV;
1256 }
1257
1258 ourport->baudclk = ERR_PTR(-EINVAL);
1259 ourport->info = ourport->drv_data->info;
1260 ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
1261 (struct s3c2410_uartcfg *)dev_get_platdata(&pdev->dev) :
1262 ourport->drv_data->def_cfg;
1263
1264 ourport->port.fifosize = (ourport->info->fifosize) ?
1265 ourport->info->fifosize :
1266 ourport->drv_data->fifosize[probe_index];
1267
1268 probe_index++;
1269
1270 dbg("%s: initialising port %p...\n", __func__, ourport);
1271
1272 ret = s3c24xx_serial_init_port(ourport, pdev);
1273 if (ret < 0)
1274 goto probe_err;
1275
1276 dbg("%s: adding port\n", __func__);
1277 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1278 platform_set_drvdata(pdev, &ourport->port);
1279
1280 #ifdef CONFIG_SAMSUNG_CLOCK
1281 ret = device_create_file(&pdev->dev, &dev_attr_clock_source);
1282 if (ret < 0)
1283 dev_err(&pdev->dev, "failed to add clock source attr.\n");
1284 #endif
1285
1286 ret = s3c24xx_serial_cpufreq_register(ourport);
1287 if (ret < 0)
1288 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
1289
1290 return 0;
1291
1292 probe_err:
1293 return ret;
1294 }
1295
1296 static int s3c24xx_serial_remove(struct platform_device *dev)
1297 {
1298 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1299
1300 if (port) {
1301 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
1302 #ifdef CONFIG_SAMSUNG_CLOCK
1303 device_remove_file(&dev->dev, &dev_attr_clock_source);
1304 #endif
1305 uart_remove_one_port(&s3c24xx_uart_drv, port);
1306 }
1307
1308 return 0;
1309 }
1310
1311 /* UART power management code */
1312 #ifdef CONFIG_PM_SLEEP
1313 static int s3c24xx_serial_suspend(struct device *dev)
1314 {
1315 struct uart_port *port = s3c24xx_dev_to_port(dev);
1316
1317 if (port)
1318 uart_suspend_port(&s3c24xx_uart_drv, port);
1319
1320 return 0;
1321 }
1322
1323 static int s3c24xx_serial_resume(struct device *dev)
1324 {
1325 struct uart_port *port = s3c24xx_dev_to_port(dev);
1326 struct s3c24xx_uart_port *ourport = to_ourport(port);
1327
1328 if (port) {
1329 clk_prepare_enable(ourport->clk);
1330 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1331 clk_disable_unprepare(ourport->clk);
1332
1333 uart_resume_port(&s3c24xx_uart_drv, port);
1334 }
1335
1336 return 0;
1337 }
1338
1339 static int s3c24xx_serial_resume_noirq(struct device *dev)
1340 {
1341 struct uart_port *port = s3c24xx_dev_to_port(dev);
1342
1343 if (port) {
1344 /* restore IRQ mask */
1345 if (s3c24xx_serial_has_interrupt_mask(port)) {
1346 unsigned int uintm = 0xf;
1347 if (tx_enabled(port))
1348 uintm &= ~S3C64XX_UINTM_TXD_MSK;
1349 if (rx_enabled(port))
1350 uintm &= ~S3C64XX_UINTM_RXD_MSK;
1351 wr_regl(port, S3C64XX_UINTM, uintm);
1352 }
1353 }
1354
1355 return 0;
1356 }
1357
1358 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1359 .suspend = s3c24xx_serial_suspend,
1360 .resume = s3c24xx_serial_resume,
1361 .resume_noirq = s3c24xx_serial_resume_noirq,
1362 };
1363 #define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1364
1365 #else /* !CONFIG_PM_SLEEP */
1366
1367 #define SERIAL_SAMSUNG_PM_OPS NULL
1368 #endif /* CONFIG_PM_SLEEP */
1369
1370 /* Console code */
1371
1372 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1373
1374 static struct uart_port *cons_uart;
1375
1376 static int
1377 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1378 {
1379 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1380 unsigned long ufstat, utrstat;
1381
1382 if (ufcon & S3C2410_UFCON_FIFOMODE) {
1383 /* fifo mode - check amount of data in fifo registers... */
1384
1385 ufstat = rd_regl(port, S3C2410_UFSTAT);
1386 return (ufstat & info->tx_fifofull) ? 0 : 1;
1387 }
1388
1389 /* in non-fifo mode, we go and use the tx buffer empty */
1390
1391 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1392 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1393 }
1394
1395 static bool
1396 s3c24xx_port_configured(unsigned int ucon)
1397 {
1398 /* consider the serial port configured if the tx/rx mode set */
1399 return (ucon & 0xf) != 0;
1400 }
1401
1402 #ifdef CONFIG_CONSOLE_POLL
1403 /*
1404 * Console polling routines for writing and reading from the uart while
1405 * in an interrupt or debug context.
1406 */
1407
1408 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
1409 {
1410 struct s3c24xx_uart_port *ourport = to_ourport(port);
1411 unsigned int ufstat;
1412
1413 ufstat = rd_regl(port, S3C2410_UFSTAT);
1414 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
1415 return NO_POLL_CHAR;
1416
1417 return rd_regb(port, S3C2410_URXH);
1418 }
1419
1420 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1421 unsigned char c)
1422 {
1423 unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
1424 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
1425
1426 /* not possible to xmit on unconfigured port */
1427 if (!s3c24xx_port_configured(ucon))
1428 return;
1429
1430 while (!s3c24xx_serial_console_txrdy(port, ufcon))
1431 cpu_relax();
1432 wr_regb(cons_uart, S3C2410_UTXH, c);
1433 }
1434
1435 #endif /* CONFIG_CONSOLE_POLL */
1436
1437 static void
1438 s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
1439 {
1440 unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
1441 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
1442
1443 /* not possible to xmit on unconfigured port */
1444 if (!s3c24xx_port_configured(ucon))
1445 return;
1446
1447 while (!s3c24xx_serial_console_txrdy(port, ufcon))
1448 barrier();
1449 wr_regb(cons_uart, S3C2410_UTXH, ch);
1450 }
1451
1452 static void
1453 s3c24xx_serial_console_write(struct console *co, const char *s,
1454 unsigned int count)
1455 {
1456 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
1457 }
1458
1459 static void __init
1460 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
1461 int *parity, int *bits)
1462 {
1463 struct clk *clk;
1464 unsigned int ulcon;
1465 unsigned int ucon;
1466 unsigned int ubrdiv;
1467 unsigned long rate;
1468 unsigned int clk_sel;
1469 char clk_name[MAX_CLK_NAME_LENGTH];
1470
1471 ulcon = rd_regl(port, S3C2410_ULCON);
1472 ucon = rd_regl(port, S3C2410_UCON);
1473 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
1474
1475 dbg("s3c24xx_serial_get_options: port=%p\n"
1476 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1477 port, ulcon, ucon, ubrdiv);
1478
1479 if (s3c24xx_port_configured(ucon)) {
1480 switch (ulcon & S3C2410_LCON_CSMASK) {
1481 case S3C2410_LCON_CS5:
1482 *bits = 5;
1483 break;
1484 case S3C2410_LCON_CS6:
1485 *bits = 6;
1486 break;
1487 case S3C2410_LCON_CS7:
1488 *bits = 7;
1489 break;
1490 default:
1491 case S3C2410_LCON_CS8:
1492 *bits = 8;
1493 break;
1494 }
1495
1496 switch (ulcon & S3C2410_LCON_PMASK) {
1497 case S3C2410_LCON_PEVEN:
1498 *parity = 'e';
1499 break;
1500
1501 case S3C2410_LCON_PODD:
1502 *parity = 'o';
1503 break;
1504
1505 case S3C2410_LCON_PNONE:
1506 default:
1507 *parity = 'n';
1508 }
1509
1510 /* now calculate the baud rate */
1511
1512 clk_sel = s3c24xx_serial_getsource(port);
1513 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
1514
1515 clk = clk_get(port->dev, clk_name);
1516 if (!IS_ERR(clk))
1517 rate = clk_get_rate(clk);
1518 else
1519 rate = 1;
1520
1521 *baud = rate / (16 * (ubrdiv + 1));
1522 dbg("calculated baud %d\n", *baud);
1523 }
1524
1525 }
1526
1527 static int __init
1528 s3c24xx_serial_console_setup(struct console *co, char *options)
1529 {
1530 struct uart_port *port;
1531 int baud = 9600;
1532 int bits = 8;
1533 int parity = 'n';
1534 int flow = 'n';
1535
1536 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1537 co, co->index, options);
1538
1539 /* is this a valid port */
1540
1541 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
1542 co->index = 0;
1543
1544 port = &s3c24xx_serial_ports[co->index].port;
1545
1546 /* is the port configured? */
1547
1548 if (port->mapbase == 0x0)
1549 return -ENODEV;
1550
1551 cons_uart = port;
1552
1553 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
1554
1555 /*
1556 * Check whether an invalid uart number has been specified, and
1557 * if so, search for the first available port that does have
1558 * console support.
1559 */
1560 if (options)
1561 uart_parse_options(options, &baud, &parity, &bits, &flow);
1562 else
1563 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
1564
1565 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
1566
1567 return uart_set_options(port, co, baud, parity, bits, flow);
1568 }
1569
1570 static struct console s3c24xx_serial_console = {
1571 .name = S3C24XX_SERIAL_NAME,
1572 .device = uart_console_device,
1573 .flags = CON_PRINTBUFFER,
1574 .index = -1,
1575 .write = s3c24xx_serial_console_write,
1576 .setup = s3c24xx_serial_console_setup,
1577 .data = &s3c24xx_uart_drv,
1578 };
1579 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
1580
1581 #ifdef CONFIG_CPU_S3C2410
1582 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
1583 .info = &(struct s3c24xx_uart_info) {
1584 .name = "Samsung S3C2410 UART",
1585 .type = PORT_S3C2410,
1586 .fifosize = 16,
1587 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1588 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1589 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1590 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1591 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1592 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1593 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1594 .num_clks = 2,
1595 .clksel_mask = S3C2410_UCON_CLKMASK,
1596 .clksel_shift = S3C2410_UCON_CLKSHIFT,
1597 },
1598 .def_cfg = &(struct s3c2410_uartcfg) {
1599 .ucon = S3C2410_UCON_DEFAULT,
1600 .ufcon = S3C2410_UFCON_DEFAULT,
1601 },
1602 };
1603 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
1604 #else
1605 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1606 #endif
1607
1608 #ifdef CONFIG_CPU_S3C2412
1609 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
1610 .info = &(struct s3c24xx_uart_info) {
1611 .name = "Samsung S3C2412 UART",
1612 .type = PORT_S3C2412,
1613 .fifosize = 64,
1614 .has_divslot = 1,
1615 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1616 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1617 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1618 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1619 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1620 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1621 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1622 .num_clks = 4,
1623 .clksel_mask = S3C2412_UCON_CLKMASK,
1624 .clksel_shift = S3C2412_UCON_CLKSHIFT,
1625 },
1626 .def_cfg = &(struct s3c2410_uartcfg) {
1627 .ucon = S3C2410_UCON_DEFAULT,
1628 .ufcon = S3C2410_UFCON_DEFAULT,
1629 },
1630 };
1631 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
1632 #else
1633 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1634 #endif
1635
1636 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
1637 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
1638 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
1639 .info = &(struct s3c24xx_uart_info) {
1640 .name = "Samsung S3C2440 UART",
1641 .type = PORT_S3C2440,
1642 .fifosize = 64,
1643 .has_divslot = 1,
1644 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1645 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1646 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1647 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1648 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1649 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1650 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1651 .num_clks = 4,
1652 .clksel_mask = S3C2412_UCON_CLKMASK,
1653 .clksel_shift = S3C2412_UCON_CLKSHIFT,
1654 },
1655 .def_cfg = &(struct s3c2410_uartcfg) {
1656 .ucon = S3C2410_UCON_DEFAULT,
1657 .ufcon = S3C2410_UFCON_DEFAULT,
1658 },
1659 };
1660 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
1661 #else
1662 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1663 #endif
1664
1665 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) || \
1666 defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450) || \
1667 defined(CONFIG_CPU_S5PC100)
1668 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
1669 .info = &(struct s3c24xx_uart_info) {
1670 .name = "Samsung S3C6400 UART",
1671 .type = PORT_S3C6400,
1672 .fifosize = 64,
1673 .has_divslot = 1,
1674 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1675 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1676 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1677 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1678 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1679 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1680 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1681 .num_clks = 4,
1682 .clksel_mask = S3C6400_UCON_CLKMASK,
1683 .clksel_shift = S3C6400_UCON_CLKSHIFT,
1684 },
1685 .def_cfg = &(struct s3c2410_uartcfg) {
1686 .ucon = S3C2410_UCON_DEFAULT,
1687 .ufcon = S3C2410_UFCON_DEFAULT,
1688 },
1689 };
1690 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
1691 #else
1692 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1693 #endif
1694
1695 #ifdef CONFIG_CPU_S5PV210
1696 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
1697 .info = &(struct s3c24xx_uart_info) {
1698 .name = "Samsung S5PV210 UART",
1699 .type = PORT_S3C6400,
1700 .has_divslot = 1,
1701 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
1702 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
1703 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
1704 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
1705 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
1706 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
1707 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1708 .num_clks = 2,
1709 .clksel_mask = S5PV210_UCON_CLKMASK,
1710 .clksel_shift = S5PV210_UCON_CLKSHIFT,
1711 },
1712 .def_cfg = &(struct s3c2410_uartcfg) {
1713 .ucon = S5PV210_UCON_DEFAULT,
1714 .ufcon = S5PV210_UFCON_DEFAULT,
1715 },
1716 .fifosize = { 256, 64, 16, 16 },
1717 };
1718 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
1719 #else
1720 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1721 #endif
1722
1723 #if defined(CONFIG_ARCH_EXYNOS)
1724 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
1725 .info = &(struct s3c24xx_uart_info) {
1726 .name = "Samsung Exynos4 UART",
1727 .type = PORT_S3C6400,
1728 .has_divslot = 1,
1729 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
1730 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
1731 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
1732 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
1733 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
1734 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
1735 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1736 .num_clks = 1,
1737 .clksel_mask = 0,
1738 .clksel_shift = 0,
1739 },
1740 .def_cfg = &(struct s3c2410_uartcfg) {
1741 .ucon = S5PV210_UCON_DEFAULT,
1742 .ufcon = S5PV210_UFCON_DEFAULT,
1743 .has_fracval = 1,
1744 },
1745 .fifosize = { 256, 64, 16, 16 },
1746 };
1747 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
1748 #else
1749 #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1750 #endif
1751
1752 static struct platform_device_id s3c24xx_serial_driver_ids[] = {
1753 {
1754 .name = "s3c2410-uart",
1755 .driver_data = S3C2410_SERIAL_DRV_DATA,
1756 }, {
1757 .name = "s3c2412-uart",
1758 .driver_data = S3C2412_SERIAL_DRV_DATA,
1759 }, {
1760 .name = "s3c2440-uart",
1761 .driver_data = S3C2440_SERIAL_DRV_DATA,
1762 }, {
1763 .name = "s3c6400-uart",
1764 .driver_data = S3C6400_SERIAL_DRV_DATA,
1765 }, {
1766 .name = "s5pv210-uart",
1767 .driver_data = S5PV210_SERIAL_DRV_DATA,
1768 }, {
1769 .name = "exynos4210-uart",
1770 .driver_data = EXYNOS4210_SERIAL_DRV_DATA,
1771 },
1772 { },
1773 };
1774 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
1775
1776 #ifdef CONFIG_OF
1777 static const struct of_device_id s3c24xx_uart_dt_match[] = {
1778 { .compatible = "samsung,s3c2410-uart",
1779 .data = (void *)S3C2410_SERIAL_DRV_DATA },
1780 { .compatible = "samsung,s3c2412-uart",
1781 .data = (void *)S3C2412_SERIAL_DRV_DATA },
1782 { .compatible = "samsung,s3c2440-uart",
1783 .data = (void *)S3C2440_SERIAL_DRV_DATA },
1784 { .compatible = "samsung,s3c6400-uart",
1785 .data = (void *)S3C6400_SERIAL_DRV_DATA },
1786 { .compatible = "samsung,s5pv210-uart",
1787 .data = (void *)S5PV210_SERIAL_DRV_DATA },
1788 { .compatible = "samsung,exynos4210-uart",
1789 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
1790 {},
1791 };
1792 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
1793 #endif
1794
1795 static struct platform_driver samsung_serial_driver = {
1796 .probe = s3c24xx_serial_probe,
1797 .remove = s3c24xx_serial_remove,
1798 .id_table = s3c24xx_serial_driver_ids,
1799 .driver = {
1800 .name = "samsung-uart",
1801 .owner = THIS_MODULE,
1802 .pm = SERIAL_SAMSUNG_PM_OPS,
1803 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
1804 },
1805 };
1806
1807 /* module initialisation code */
1808
1809 static int __init s3c24xx_serial_modinit(void)
1810 {
1811 int ret;
1812
1813 ret = uart_register_driver(&s3c24xx_uart_drv);
1814 if (ret < 0) {
1815 pr_err("Failed to register Samsung UART driver\n");
1816 return ret;
1817 }
1818
1819 ret = platform_driver_register(&samsung_serial_driver);
1820 if (ret < 0) {
1821 pr_err("Failed to register platform driver\n");
1822 uart_unregister_driver(&s3c24xx_uart_drv);
1823 }
1824
1825 return ret;
1826 }
1827
1828 static void __exit s3c24xx_serial_modexit(void)
1829 {
1830 platform_driver_unregister(&samsung_serial_driver);
1831 uart_unregister_driver(&s3c24xx_uart_drv);
1832 }
1833
1834 module_init(s3c24xx_serial_modinit);
1835 module_exit(s3c24xx_serial_modexit);
1836
1837 MODULE_ALIAS("platform:samsung-uart");
1838 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
1839 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1840 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support