drivers/net/spider_net.h

   1 /*
   2  * Network device driver for Cell Processor-Based Blade
   3  *
   4  * (C) Copyright IBM Corp. 2005
   5  *
   6  * Authors : Utz Bacher <utz.bacher@de.ibm.com>
   7  *           Jens Osterkamp <Jens.Osterkamp@de.ibm.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2, or (at your option)
  12  * any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22  */
  23
  24 #ifndef _SPIDER_NET_H
  25 #define _SPIDER_NET_H
  26
  27 #include "sungem_phy.h"
  28
  29 extern int spider_net_stop(struct net_device *netdev);
  30 extern int spider_net_open(struct net_device *netdev);
  31
  32 extern struct ethtool_ops spider_net_ethtool_ops;
  33
  34 extern char spider_net_driver_name[];
  35
  36 #define SPIDER_NET_MAX_MTU                      2308
  37 #define SPIDER_NET_MIN_MTU                      64
  38
  39 #define SPIDER_NET_RXBUF_ALIGN                  128
  40
  41 #define SPIDER_NET_RX_DESCRIPTORS_DEFAULT       64
  42 #define SPIDER_NET_RX_DESCRIPTORS_MIN           16
  43 #define SPIDER_NET_RX_DESCRIPTORS_MAX           256
  44
  45 #define SPIDER_NET_TX_DESCRIPTORS_DEFAULT       64
  46 #define SPIDER_NET_TX_DESCRIPTORS_MIN           16
  47 #define SPIDER_NET_TX_DESCRIPTORS_MAX           256
  48
  49 #define SPIDER_NET_RX_CSUM_DEFAULT              1
  50
  51 #define SPIDER_NET_WATCHDOG_TIMEOUT 5*HZ
  52 #define SPIDER_NET_NAPI_WEIGHT 64
  53
  54 #define SPIDER_NET_FIRMWARE_LEN         1024
  55 #define SPIDER_NET_FIRMWARE_NAME        "spider_fw.bin"
  56
  57 /** spider_net SMMIO registers */
  58 #define SPIDER_NET_GHIINT0STS           0x00000000
  59 #define SPIDER_NET_GHIINT1STS           0x00000004
  60 #define SPIDER_NET_GHIINT2STS           0x00000008
  61 #define SPIDER_NET_GHIINT0MSK           0x00000010
  62 #define SPIDER_NET_GHIINT1MSK           0x00000014
  63 #define SPIDER_NET_GHIINT2MSK           0x00000018
  64
  65 #define SPIDER_NET_GRESUMINTNUM         0x00000020
  66 #define SPIDER_NET_GREINTNUM            0x00000024
  67
  68 #define SPIDER_NET_GFFRMNUM             0x00000028
  69 #define SPIDER_NET_GFAFRMNUM            0x0000002c
  70 #define SPIDER_NET_GFBFRMNUM            0x00000030
  71 #define SPIDER_NET_GFCFRMNUM            0x00000034
  72 #define SPIDER_NET_GFDFRMNUM            0x00000038
  73
  74 /* clear them (don't use it) */
  75 #define SPIDER_NET_GFREECNNUM           0x0000003c
  76 #define SPIDER_NET_GONETIMENUM          0x00000040
  77
  78 #define SPIDER_NET_GTOUTFRMNUM          0x00000044
  79
  80 #define SPIDER_NET_GTXMDSET             0x00000050
  81 #define SPIDER_NET_GPCCTRL              0x00000054
  82 #define SPIDER_NET_GRXMDSET             0x00000058
  83 #define SPIDER_NET_GIPSECINIT           0x0000005c
  84 #define SPIDER_NET_GFTRESTRT            0x00000060
  85 #define SPIDER_NET_GRXDMAEN             0x00000064
  86 #define SPIDER_NET_GMRWOLCTRL           0x00000068
  87 #define SPIDER_NET_GPCWOPCMD            0x0000006c
  88 #define SPIDER_NET_GPCROPCMD            0x00000070
  89 #define SPIDER_NET_GTTFRMCNT            0x00000078
  90 #define SPIDER_NET_GTESTMD              0x0000007c
  91
  92 #define SPIDER_NET_GSINIT               0x00000080
  93 #define SPIDER_NET_GSnPRGADR            0x00000084
  94 #define SPIDER_NET_GSnPRGDAT            0x00000088
  95
  96 #define SPIDER_NET_GMACOPEMD            0x00000100
  97 #define SPIDER_NET_GMACLENLMT           0x00000108
  98 #define SPIDER_NET_GMACINTEN            0x00000118
  99 #define SPIDER_NET_GMACPHYCTRL          0x00000120
 100
 101 #define SPIDER_NET_GMACAPAUSE           0x00000154
 102 #define SPIDER_NET_GMACTXPAUSE          0x00000164
 103
 104 #define SPIDER_NET_GMACMODE             0x000001b0
 105 #define SPIDER_NET_GMACBSTLMT           0x000001b4
 106
 107 #define SPIDER_NET_GMACUNIMACU          0x000001c0
 108 #define SPIDER_NET_GMACUNIMACL          0x000001c8
 109
 110 #define SPIDER_NET_GMRMHFILnR           0x00000400
 111 #define SPIDER_NET_MULTICAST_HASHES     256
 112
 113 #define SPIDER_NET_GMRUAFILnR           0x00000500
 114 #define SPIDER_NET_GMRUA0FIL15R         0x00000578
 115
 116 /* RX DMA controller registers, all 0x00000a.. are for DMA controller A,
 117  * 0x00000b.. for DMA controller B, etc. */
 118 #define SPIDER_NET_GDADCHA              0x00000a00
 119 #define SPIDER_NET_GDADMACCNTR          0x00000a04
 120 #define SPIDER_NET_GDACTDPA             0x00000a08
 121 #define SPIDER_NET_GDACTDCNT            0x00000a0c
 122 #define SPIDER_NET_GDACDBADDR           0x00000a20
 123 #define SPIDER_NET_GDACDBSIZE           0x00000a24
 124 #define SPIDER_NET_GDACNEXTDA           0x00000a28
 125 #define SPIDER_NET_GDACCOMST            0x00000a2c
 126 #define SPIDER_NET_GDAWBCOMST           0x00000a30
 127 #define SPIDER_NET_GDAWBRSIZE           0x00000a34
 128 #define SPIDER_NET_GDAWBVSIZE           0x00000a38
 129 #define SPIDER_NET_GDAWBTRST            0x00000a3c
 130 #define SPIDER_NET_GDAWBTRERR           0x00000a40
 131
 132 /* TX DMA controller registers */
 133 #define SPIDER_NET_GDTDCHA              0x00000e00
 134 #define SPIDER_NET_GDTDMACCNTR          0x00000e04
 135 #define SPIDER_NET_GDTCDPA              0x00000e08
 136 #define SPIDER_NET_GDTDMASEL            0x00000e14
 137
 138 #define SPIDER_NET_ECMODE               0x00000f00
 139 /* clock and reset control register */
 140 #define SPIDER_NET_CKRCTRL              0x00000ff0
 141
 142 /** SCONFIG registers */
 143 #define SPIDER_NET_SCONFIG_IOACTE       0x00002810
 144
 145 /** hardcoded register values */
 146 #define SPIDER_NET_INT0_MASK_VALUE      0x3f7fe3ff
 147 #define SPIDER_NET_INT1_MASK_VALUE      0xffffffff
 148 /* no MAC aborts -> auto retransmission */
 149 #define SPIDER_NET_INT2_MASK_VALUE      0xfffffff1
 150
 151 /* clear counter when interrupt sources are cleared
 152 #define SPIDER_NET_FRAMENUM_VALUE       0x0001f001 */
 153 /* we rely on flagged descriptor interrupts */
 154 #define SPIDER_NET_FRAMENUM_VALUE       0x00000000
 155 /* set this first, then the FRAMENUM_VALUE */
 156 #define SPIDER_NET_GFXFRAMES_VALUE      0x00000000
 157
 158 #define SPIDER_NET_STOP_SEQ_VALUE       0x00000000
 159 #define SPIDER_NET_RUN_SEQ_VALUE        0x0000007e
 160
 161 #define SPIDER_NET_PHY_CTRL_VALUE       0x00040040
 162 /* #define SPIDER_NET_PHY_CTRL_VALUE    0x01070080*/
 163 #define SPIDER_NET_RXMODE_VALUE         0x00000011
 164 /* auto retransmission in case of MAC aborts */
 165 #define SPIDER_NET_TXMODE_VALUE         0x00010000
 166 #define SPIDER_NET_RESTART_VALUE        0x00000000
 167 #define SPIDER_NET_WOL_VALUE            0x00001111
 168 #if 0
 169 #define SPIDER_NET_WOL_VALUE            0x00000000
 170 #endif
 171 #define SPIDER_NET_IPSECINIT_VALUE      0x00f000f8
 172
 173 /* pause frames: automatic, no upper retransmission count */
 174 /* outside loopback mode: ETOMOD signal dont matter, not connected */
 175 #define SPIDER_NET_OPMODE_VALUE         0x00000063
 176 /*#define SPIDER_NET_OPMODE_VALUE               0x001b0062*/
 177 #define SPIDER_NET_LENLMT_VALUE         0x00000908
 178
 179 #define SPIDER_NET_MACAPAUSE_VALUE      0x00000800 /* about 1 ms */
 180 #define SPIDER_NET_TXPAUSE_VALUE        0x00000000
 181
 182 #define SPIDER_NET_MACMODE_VALUE        0x00000001
 183 #define SPIDER_NET_BURSTLMT_VALUE       0x00000200 /* about 16 us */
 184
 185 /* 1(0)                                 enable r/tx dma
 186  *  0000000                             fixed to 0
 187  *
 188  *         000000                       fixed to 0
 189  *               0(1)                   en/disable descr writeback on force end
 190  *                0(1)                  force end
 191  *
 192  *                 000000               fixed to 0
 193  *                       00             burst alignment: 128 bytes
 194  *
 195  *                         00000        fixed to 0
 196  *                              0       descr writeback size 32 bytes
 197  *                               0(1)   descr chain end interrupt enable
 198  *                                0(1)  descr status writeback enable */
 199
 200 /* to set RX_DMA_EN */
 201 #define SPIDER_NET_DMA_RX_VALUE         0x80000000
 202 #define SPIDER_NET_DMA_RX_FEND_VALUE    0x00030003
 203 /* to set TX_DMA_EN */
 204 #define SPIDER_NET_DMA_TX_VALUE         0x80000000
 205 #define SPIDER_NET_DMA_TX_FEND_VALUE    0x00030003
 206
 207 /* SPIDER_NET_UA_DESCR_VALUE is OR'ed with the unicast address */
 208 #define SPIDER_NET_UA_DESCR_VALUE       0x00080000
 209 #define SPIDER_NET_PROMISC_VALUE        0x00080000
 210 #define SPIDER_NET_NONPROMISC_VALUE     0x00000000
 211
 212 #define SPIDER_NET_DMASEL_VALUE         0x00000001
 213
 214 #define SPIDER_NET_ECMODE_VALUE         0x00000000
 215
 216 #define SPIDER_NET_CKRCTRL_RUN_VALUE    0x1fff010f
 217 #define SPIDER_NET_CKRCTRL_STOP_VALUE   0x0000010f
 218
 219 #define SPIDER_NET_SBIMSTATE_VALUE      0x00000000
 220 #define SPIDER_NET_SBTMSTATE_VALUE      0x00000000
 221
 222 /* SPIDER_NET_GHIINT0STS bits, in reverse order so that they can be used
 223  * with 1 << SPIDER_NET_... */
 224 enum spider_net_int0_status {
 225         SPIDER_NET_GPHYINT = 0,
 226         SPIDER_NET_GMAC2INT,
 227         SPIDER_NET_GMAC1INT,
 228         SPIDER_NET_GIPSINT,
 229         SPIDER_NET_GFIFOINT,
 230         SPIDER_NET_GDMACINT,
 231         SPIDER_NET_GSYSINT,
 232         SPIDER_NET_GPWOPCMPINT,
 233         SPIDER_NET_GPROPCMPINT,
 234         SPIDER_NET_GPWFFINT,
 235         SPIDER_NET_GRMDADRINT,
 236         SPIDER_NET_GRMARPINT,
 237         SPIDER_NET_GRMMPINT,
 238         SPIDER_NET_GDTDEN0INT,
 239         SPIDER_NET_GDDDEN0INT,
 240         SPIDER_NET_GDCDEN0INT,
 241         SPIDER_NET_GDBDEN0INT,
 242         SPIDER_NET_GDADEN0INT,
 243         SPIDER_NET_GDTFDCINT,
 244         SPIDER_NET_GDDFDCINT,
 245         SPIDER_NET_GDCFDCINT,
 246         SPIDER_NET_GDBFDCINT,
 247         SPIDER_NET_GDAFDCINT,
 248         SPIDER_NET_GTTEDINT,
 249         SPIDER_NET_GDTDCEINT,
 250         SPIDER_NET_GRFDNMINT,
 251         SPIDER_NET_GRFCNMINT,
 252         SPIDER_NET_GRFBNMINT,
 253         SPIDER_NET_GRFANMINT,
 254         SPIDER_NET_GRFNMINT,
 255         SPIDER_NET_G1TMCNTINT,
 256         SPIDER_NET_GFREECNTINT
 257 };
 258 /* GHIINT1STS bits */
 259 enum spider_net_int1_status {
 260         SPIDER_NET_GTMFLLINT = 0,
 261         SPIDER_NET_GRMFLLINT,
 262         SPIDER_NET_GTMSHTINT,
 263         SPIDER_NET_GDTINVDINT,
 264         SPIDER_NET_GRFDFLLINT,
 265         SPIDER_NET_GDDDCEINT,
 266         SPIDER_NET_GDDINVDINT,
 267         SPIDER_NET_GRFCFLLINT,
 268         SPIDER_NET_GDCDCEINT,
 269         SPIDER_NET_GDCINVDINT,
 270         SPIDER_NET_GRFBFLLINT,
 271         SPIDER_NET_GDBDCEINT,
 272         SPIDER_NET_GDBINVDINT,
 273         SPIDER_NET_GRFAFLLINT,
 274         SPIDER_NET_GDADCEINT,
 275         SPIDER_NET_GDAINVDINT,
 276         SPIDER_NET_GDTRSERINT,
 277         SPIDER_NET_GDDRSERINT,
 278         SPIDER_NET_GDCRSERINT,
 279         SPIDER_NET_GDBRSERINT,
 280         SPIDER_NET_GDARSERINT,
 281         SPIDER_NET_GDSERINT,
 282         SPIDER_NET_GDTPTERINT,
 283         SPIDER_NET_GDDPTERINT,
 284         SPIDER_NET_GDCPTERINT,
 285         SPIDER_NET_GDBPTERINT,
 286         SPIDER_NET_GDAPTERINT
 287 };
 288 /* GHIINT2STS bits */
 289 enum spider_net_int2_status {
 290         SPIDER_NET_GPROPERINT = 0,
 291         SPIDER_NET_GMCTCRSNGINT,
 292         SPIDER_NET_GMCTLCOLINT,
 293         SPIDER_NET_GMCTTMOTINT,
 294         SPIDER_NET_GMCRCAERINT,
 295         SPIDER_NET_GMCRCALERINT,
 296         SPIDER_NET_GMCRALNERINT,
 297         SPIDER_NET_GMCROVRINT,
 298         SPIDER_NET_GMCRRNTINT,
 299         SPIDER_NET_GMCRRXERINT,
 300         SPIDER_NET_GTITCSERINT,
 301         SPIDER_NET_GTIFMTERINT,
 302         SPIDER_NET_GTIPKTRVKINT,
 303         SPIDER_NET_GTISPINGINT,
 304         SPIDER_NET_GTISADNGINT,
 305         SPIDER_NET_GTISPDNGINT,
 306         SPIDER_NET_GRIFMTERINT,
 307         SPIDER_NET_GRIPKTRVKINT,
 308         SPIDER_NET_GRISPINGINT,
 309         SPIDER_NET_GRISADNGINT,
 310         SPIDER_NET_GRISPDNGINT
 311 };
 312
 313 #define SPIDER_NET_TXINT        ( (1 << SPIDER_NET_GTTEDINT) | \
 314                                   (1 << SPIDER_NET_GDTDCEINT) | \
 315                                   (1 << SPIDER_NET_GDTFDCINT) )
 316
 317 /* we rely on flagged descriptor interrupts*/
 318 #define SPIDER_NET_RXINT        ( (1 << SPIDER_NET_GDAFDCINT) | \
 319                                   (1 << SPIDER_NET_GRMFLLINT) )
 320
 321 #define SPIDER_NET_GPREXEC              0x80000000
 322 #define SPIDER_NET_GPRDAT_MASK          0x0000ffff
 323
 324 /* descriptor bits
 325  *
 326  * 1010                                 descriptor ready
 327  *     0                                descr in middle of chain
 328  *      000                             fixed to 0
 329  *
 330  *         0                            no interrupt on completion
 331  *          000                         fixed to 0
 332  *             1                        no ipsec processing
 333  *              1                       last descriptor for this frame
 334  *               00                     no checksum
 335  *               10                     tcp checksum
 336  *               11                     udp checksum
 337  *
 338  *                 00                   fixed to 0
 339  *                   0                  fixed to 0
 340  *                    0                 no interrupt on response errors
 341  *                     0                no interrupt on invalid descr
 342  *                      0               no interrupt on dma process termination
 343  *                       0              no interrupt on descr chain end
 344  *                        0             no interrupt on descr complete
 345  *
 346  *                         000          fixed to 0
 347  *                            0         response error interrupt status
 348  *                             0        invalid descr status
 349  *                              0       dma termination status
 350  *                               0      descr chain end status
 351  *                                0     descr complete status */
 352 #define SPIDER_NET_DMAC_CMDSTAT_NOCS    0xa00c0000
 353 #define SPIDER_NET_DMAC_CMDSTAT_TCPCS   0xa00e0000
 354 #define SPIDER_NET_DMAC_CMDSTAT_UDPCS   0xa00f0000
 355 #define SPIDER_NET_DESCR_IND_PROC_SHIFT 28
 356 #define SPIDER_NET_DESCR_IND_PROC_MASKO 0x0fffffff
 357
 358 /* descr ready, descr is in middle of chain, get interrupt on completion */
 359 #define SPIDER_NET_DMAC_RX_CARDOWNED    0xa0800000
 360
 361 /* multicast is no problem */
 362 #define SPIDER_NET_DATA_ERROR_MASK      0xffffbfff
 363
 364 enum spider_net_descr_status {
 365         SPIDER_NET_DESCR_COMPLETE               = 0x00, /* used in rx and tx */
 366         SPIDER_NET_DESCR_RESPONSE_ERROR         = 0x01, /* used in rx and tx */
 367         SPIDER_NET_DESCR_PROTECTION_ERROR       = 0x02, /* used in rx and tx */
 368         SPIDER_NET_DESCR_FRAME_END              = 0x04, /* used in rx */
 369         SPIDER_NET_DESCR_FORCE_END              = 0x05, /* used in rx and tx */
 370         SPIDER_NET_DESCR_CARDOWNED              = 0x0a, /* used in rx and tx */
 371         SPIDER_NET_DESCR_NOT_IN_USE /* any other value */
 372 };
 373
 374 struct spider_net_descr {
 375         /* as defined by the hardware */
 376         dma_addr_t buf_addr;
 377         u32 buf_size;
 378         dma_addr_t next_descr_addr;
 379         u32 dmac_cmd_status;
 380         u32 result_size;
 381         u32 valid_size; /* all zeroes for tx */
 382         u32 data_status;
 383         u32 data_error; /* all zeroes for tx */
 384
 385         /* used in the driver */
 386         struct sk_buff *skb;
 387         dma_addr_t bus_addr;
 388         struct spider_net_descr *next;
 389         struct spider_net_descr *prev;
 390 } __attribute__((aligned(32)));
 391
 392 struct spider_net_descr_chain {
 393         /* we walk from tail to head */
 394         struct spider_net_descr *head;
 395         struct spider_net_descr *tail;
 396 };
 397
 398 /* descriptor data_status bits */
 399 #define SPIDER_NET_RXIPCHK              29
 400 #define SPIDER_NET_TCPUDPIPCHK          28
 401 #define SPIDER_NET_DATA_STATUS_CHK_MASK (1 << SPIDER_NET_RXIPCHK | \
 402                                          1 << SPIDER_NET_TCPUDPIPCHK)
 403
 404 #define SPIDER_NET_VLAN_PACKET          21
 405
 406 /* descriptor data_error bits */
 407 #define SPIDER_NET_RXIPCHKERR           27
 408 #define SPIDER_NET_RXTCPCHKERR          26
 409 #define SPIDER_NET_DATA_ERROR_CHK_MASK  (1 << SPIDER_NET_RXIPCHKERR | \
 410                                          1 << SPIDER_NET_RXTCPCHKERR)
 411
 412 /* the cases we don't pass the packet to the stack */
 413 #define SPIDER_NET_DESTROY_RX_FLAGS     0x70138000
 414
 415 #define SPIDER_NET_DESCR_SIZE           32
 416
 417 /* this will be bigger some time */
 418 struct spider_net_options {
 419         int rx_csum; /* for rx: if 0 ip_summed=NONE,
 420                         if 1 and hw has verified, ip_summed=UNNECESSARY */
 421 };
 422
 423 #define SPIDER_NET_DEFAULT_MSG          ( NETIF_MSG_DRV | \
 424                                           NETIF_MSG_PROBE | \
 425                                           NETIF_MSG_LINK | \
 426                                           NETIF_MSG_TIMER | \
 427                                           NETIF_MSG_IFDOWN | \
 428                                           NETIF_MSG_IFUP | \
 429                                           NETIF_MSG_RX_ERR | \
 430                                           NETIF_MSG_TX_ERR | \
 431                                           NETIF_MSG_TX_QUEUED | \
 432                                           NETIF_MSG_INTR | \
 433                                           NETIF_MSG_TX_DONE | \
 434                                           NETIF_MSG_RX_STATUS | \
 435                                           NETIF_MSG_PKTDATA | \
 436                                           NETIF_MSG_HW | \
 437                                           NETIF_MSG_WOL )
 438
 439 struct spider_net_card {
 440         struct net_device *netdev;
 441         struct pci_dev *pdev;
 442         struct mii_phy phy;
 443
 444         void __iomem *regs;
 445
 446         struct spider_net_descr_chain tx_chain;
 447         struct spider_net_descr_chain rx_chain;
 448         spinlock_t chain_lock;
 449
 450         struct net_device_stats netdev_stats;
 451
 452         struct spider_net_options options;
 453
 454         spinlock_t intmask_lock;
 455
 456         struct work_struct tx_timeout_task;
 457         atomic_t tx_timeout_task_counter;
 458         wait_queue_head_t waitq;
 459
 460         /* for ethtool */
 461         int msg_enable;
 462
 463         struct spider_net_descr descr[0];
 464 };
 465
 466 #define pr_err(fmt,arg...) \
 467         printk(KERN_ERR fmt ,##arg)
 468
 469 #endif