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ARM: fix put_user() for gcc-8
[linux/fpc-iii.git] / drivers / irqchip / irq-gic-v3.c
blob9ab424b9b28198aa9b0603d0f76561891a54eab1
1 /*
2 * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18 #include <linux/cpu.h>
19 #include <linux/cpu_pm.h>
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/of.h>
23 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
25 #include <linux/percpu.h>
26 #include <linux/slab.h>
27
28 #include <linux/irqchip.h>
29 #include <linux/irqchip/arm-gic-v3.h>
30
31 #include <asm/cputype.h>
32 #include <asm/exception.h>
33 #include <asm/smp_plat.h>
34 #include <asm/virt.h>
35
36 #include "irq-gic-common.h"
37
38 struct redist_region {
39 void __iomem *redist_base;
40 phys_addr_t phys_base;
41 };
42
43 struct gic_chip_data {
44 void __iomem *dist_base;
45 struct redist_region *redist_regions;
46 struct rdists rdists;
47 struct irq_domain *domain;
48 u64 redist_stride;
49 u32 nr_redist_regions;
50 unsigned int irq_nr;
51 };
52
53 static struct gic_chip_data gic_data __read_mostly;
54 static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE;
55
56 #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist))
57 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
58 #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K)
59
60 /* Our default, arbitrary priority value. Linux only uses one anyway. */
61 #define DEFAULT_PMR_VALUE 0xf0
62
63 static inline unsigned int gic_irq(struct irq_data *d)
64 {
65 return d->hwirq;
66 }
67
68 static inline int gic_irq_in_rdist(struct irq_data *d)
69 {
70 return gic_irq(d) < 32;
71 }
72
73 static inline void __iomem *gic_dist_base(struct irq_data *d)
74 {
75 if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */
76 return gic_data_rdist_sgi_base();
77
78 if (d->hwirq <= 1023) /* SPI -> dist_base */
79 return gic_data.dist_base;
80
81 return NULL;
82 }
83
84 static void gic_do_wait_for_rwp(void __iomem *base)
85 {
86 u32 count = 1000000; /* 1s! */
87
88 while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) {
89 count--;
90 if (!count) {
91 pr_err_ratelimited("RWP timeout, gone fishing\n");
92 return;
93 }
94 cpu_relax();
95 udelay(1);
96 };
97 }
98
99 /* Wait for completion of a distributor change */
100 static void gic_dist_wait_for_rwp(void)
101 {
102 gic_do_wait_for_rwp(gic_data.dist_base);
103 }
104
105 /* Wait for completion of a redistributor change */
106 static void gic_redist_wait_for_rwp(void)
107 {
108 gic_do_wait_for_rwp(gic_data_rdist_rd_base());
109 }
110
111 #ifdef CONFIG_ARM64
112 static DEFINE_STATIC_KEY_FALSE(is_cavium_thunderx);
113
114 static u64 __maybe_unused gic_read_iar(void)
115 {
116 if (static_branch_unlikely(&is_cavium_thunderx))
117 return gic_read_iar_cavium_thunderx();
118 else
119 return gic_read_iar_common();
120 }
121 #endif
122
123 static void gic_enable_redist(bool enable)
124 {
125 void __iomem *rbase;
126 u32 count = 1000000; /* 1s! */
127 u32 val;
128
129 rbase = gic_data_rdist_rd_base();
130
131 val = readl_relaxed(rbase + GICR_WAKER);
132 if (enable)
133 /* Wake up this CPU redistributor */
134 val &= ~GICR_WAKER_ProcessorSleep;
135 else
136 val |= GICR_WAKER_ProcessorSleep;
137 writel_relaxed(val, rbase + GICR_WAKER);
138
139 if (!enable) { /* Check that GICR_WAKER is writeable */
140 val = readl_relaxed(rbase + GICR_WAKER);
141 if (!(val & GICR_WAKER_ProcessorSleep))
142 return; /* No PM support in this redistributor */
143 }
144
145 while (--count) {
146 val = readl_relaxed(rbase + GICR_WAKER);
147 if (enable ^ (val & GICR_WAKER_ChildrenAsleep))
148 break;
149 cpu_relax();
150 udelay(1);
151 };
152 if (!count)
153 pr_err_ratelimited("redistributor failed to %s...\n",
154 enable ? "wakeup" : "sleep");
155 }
156
157 /*
158 * Routines to disable, enable, EOI and route interrupts
159 */
160 static int gic_peek_irq(struct irq_data *d, u32 offset)
161 {
162 u32 mask = 1 << (gic_irq(d) % 32);
163 void __iomem *base;
164
165 if (gic_irq_in_rdist(d))
166 base = gic_data_rdist_sgi_base();
167 else
168 base = gic_data.dist_base;
169
170 return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask);
171 }
172
173 static void gic_poke_irq(struct irq_data *d, u32 offset)
174 {
175 u32 mask = 1 << (gic_irq(d) % 32);
176 void (*rwp_wait)(void);
177 void __iomem *base;
178
179 if (gic_irq_in_rdist(d)) {
180 base = gic_data_rdist_sgi_base();
181 rwp_wait = gic_redist_wait_for_rwp;
182 } else {
183 base = gic_data.dist_base;
184 rwp_wait = gic_dist_wait_for_rwp;
185 }
186
187 writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4);
188 rwp_wait();
189 }
190
191 static void gic_mask_irq(struct irq_data *d)
192 {
193 gic_poke_irq(d, GICD_ICENABLER);
194 }
195
196 static void gic_eoimode1_mask_irq(struct irq_data *d)
197 {
198 gic_mask_irq(d);
199 /*
200 * When masking a forwarded interrupt, make sure it is
201 * deactivated as well.
202 *
203 * This ensures that an interrupt that is getting
204 * disabled/masked will not get "stuck", because there is
205 * noone to deactivate it (guest is being terminated).
206 */
207 if (irqd_is_forwarded_to_vcpu(d))
208 gic_poke_irq(d, GICD_ICACTIVER);
209 }
210
211 static void gic_unmask_irq(struct irq_data *d)
212 {
213 gic_poke_irq(d, GICD_ISENABLER);
214 }
215
216 static int gic_irq_set_irqchip_state(struct irq_data *d,
217 enum irqchip_irq_state which, bool val)
218 {
219 u32 reg;
220
221 if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */
222 return -EINVAL;
223
224 switch (which) {
225 case IRQCHIP_STATE_PENDING:
226 reg = val ? GICD_ISPENDR : GICD_ICPENDR;
227 break;
228
229 case IRQCHIP_STATE_ACTIVE:
230 reg = val ? GICD_ISACTIVER : GICD_ICACTIVER;
231 break;
232
233 case IRQCHIP_STATE_MASKED:
234 reg = val ? GICD_ICENABLER : GICD_ISENABLER;
235 break;
236
237 default:
238 return -EINVAL;
239 }
240
241 gic_poke_irq(d, reg);
242 return 0;
243 }
244
245 static int gic_irq_get_irqchip_state(struct irq_data *d,
246 enum irqchip_irq_state which, bool *val)
247 {
248 if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */
249 return -EINVAL;
250
251 switch (which) {
252 case IRQCHIP_STATE_PENDING:
253 *val = gic_peek_irq(d, GICD_ISPENDR);
254 break;
255
256 case IRQCHIP_STATE_ACTIVE:
257 *val = gic_peek_irq(d, GICD_ISACTIVER);
258 break;
259
260 case IRQCHIP_STATE_MASKED:
261 *val = !gic_peek_irq(d, GICD_ISENABLER);
262 break;
263
264 default:
265 return -EINVAL;
266 }
267
268 return 0;
269 }
270
271 static void gic_eoi_irq(struct irq_data *d)
272 {
273 gic_write_eoir(gic_irq(d));
274 }
275
276 static void gic_eoimode1_eoi_irq(struct irq_data *d)
277 {
278 /*
279 * No need to deactivate an LPI, or an interrupt that
280 * is is getting forwarded to a vcpu.
281 */
282 if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d))
283 return;
284 gic_write_dir(gic_irq(d));
285 }
286
287 static int gic_set_type(struct irq_data *d, unsigned int type)
288 {
289 unsigned int irq = gic_irq(d);
290 void (*rwp_wait)(void);
291 void __iomem *base;
292
293 /* Interrupt configuration for SGIs can't be changed */
294 if (irq < 16)
295 return -EINVAL;
296
297 /* SPIs have restrictions on the supported types */
298 if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
299 type != IRQ_TYPE_EDGE_RISING)
300 return -EINVAL;
301
302 if (gic_irq_in_rdist(d)) {
303 base = gic_data_rdist_sgi_base();
304 rwp_wait = gic_redist_wait_for_rwp;
305 } else {
306 base = gic_data.dist_base;
307 rwp_wait = gic_dist_wait_for_rwp;
308 }
309
310 return gic_configure_irq(irq, type, base, rwp_wait);
311 }
312
313 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
314 {
315 if (vcpu)
316 irqd_set_forwarded_to_vcpu(d);
317 else
318 irqd_clr_forwarded_to_vcpu(d);
319 return 0;
320 }
321
322 static u64 gic_mpidr_to_affinity(unsigned long mpidr)
323 {
324 u64 aff;
325
326 aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 |
327 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
328 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
329 MPIDR_AFFINITY_LEVEL(mpidr, 0));
330
331 return aff;
332 }
333
334 static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
335 {
336 u32 irqnr;
337
338 do {
339 irqnr = gic_read_iar();
340
341 if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) {
342 int err;
343
344 if (static_key_true(&supports_deactivate))
345 gic_write_eoir(irqnr);
346
347 err = handle_domain_irq(gic_data.domain, irqnr, regs);
348 if (err) {
349 WARN_ONCE(true, "Unexpected interrupt received!\n");
350 if (static_key_true(&supports_deactivate)) {
351 if (irqnr < 8192)
352 gic_write_dir(irqnr);
353 } else {
354 gic_write_eoir(irqnr);
355 }
356 }
357 continue;
358 }
359 if (irqnr < 16) {
360 gic_write_eoir(irqnr);
361 if (static_key_true(&supports_deactivate))
362 gic_write_dir(irqnr);
363 #ifdef CONFIG_SMP
364 /*
365 * Unlike GICv2, we don't need an smp_rmb() here.
366 * The control dependency from gic_read_iar to
367 * the ISB in gic_write_eoir is enough to ensure
368 * that any shared data read by handle_IPI will
369 * be read after the ACK.
370 */
371 handle_IPI(irqnr, regs);
372 #else
373 WARN_ONCE(true, "Unexpected SGI received!\n");
374 #endif
375 continue;
376 }
377 } while (irqnr != ICC_IAR1_EL1_SPURIOUS);
378 }
379
380 static void __init gic_dist_init(void)
381 {
382 unsigned int i;
383 u64 affinity;
384 void __iomem *base = gic_data.dist_base;
385
386 /* Disable the distributor */
387 writel_relaxed(0, base + GICD_CTLR);
388 gic_dist_wait_for_rwp();
389
390 /*
391 * Configure SPIs as non-secure Group-1. This will only matter
392 * if the GIC only has a single security state. This will not
393 * do the right thing if the kernel is running in secure mode,
394 * but that's not the intended use case anyway.
395 */
396 for (i = 32; i < gic_data.irq_nr; i += 32)
397 writel_relaxed(~0, base + GICD_IGROUPR + i / 8);
398
399 gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp);
400
401 /* Enable distributor with ARE, Group1 */
402 writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1,
403 base + GICD_CTLR);
404
405 /*
406 * Set all global interrupts to the boot CPU only. ARE must be
407 * enabled.
408 */
409 affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id()));
410 for (i = 32; i < gic_data.irq_nr; i++)
411 gic_write_irouter(affinity, base + GICD_IROUTER + i * 8);
412 }
413
414 static int gic_populate_rdist(void)
415 {
416 unsigned long mpidr = cpu_logical_map(smp_processor_id());
417 u64 typer;
418 u32 aff;
419 int i;
420
421 /*
422 * Convert affinity to a 32bit value that can be matched to
423 * GICR_TYPER bits [63:32].
424 */
425 aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 |
426 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
427 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
428 MPIDR_AFFINITY_LEVEL(mpidr, 0));
429
430 for (i = 0; i < gic_data.nr_redist_regions; i++) {
431 void __iomem *ptr = gic_data.redist_regions[i].redist_base;
432 u32 reg;
433
434 reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK;
435 if (reg != GIC_PIDR2_ARCH_GICv3 &&
436 reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */
437 pr_warn("No redistributor present @%p\n", ptr);
438 break;
439 }
440
441 do {
442 typer = gic_read_typer(ptr + GICR_TYPER);
443 if ((typer >> 32) == aff) {
444 u64 offset = ptr - gic_data.redist_regions[i].redist_base;
445 gic_data_rdist_rd_base() = ptr;
446 gic_data_rdist()->phys_base = gic_data.redist_regions[i].phys_base + offset;
447 pr_info("CPU%d: found redistributor %lx region %d:%pa\n",
448 smp_processor_id(), mpidr, i,
449 &gic_data_rdist()->phys_base);
450 return 0;
451 }
452
453 if (gic_data.redist_stride) {
454 ptr += gic_data.redist_stride;
455 } else {
456 ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */
457 if (typer & GICR_TYPER_VLPIS)
458 ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */
459 }
460 } while (!(typer & GICR_TYPER_LAST));
461 }
462
463 /* We couldn't even deal with ourselves... */
464 WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n",
465 smp_processor_id(), mpidr);
466 return -ENODEV;
467 }
468
469 static void gic_cpu_sys_reg_init(void)
470 {
471 /*
472 * Need to check that the SRE bit has actually been set. If
473 * not, it means that SRE is disabled at EL2. We're going to
474 * die painfully, and there is nothing we can do about it.
475 *
476 * Kindly inform the luser.
477 */
478 if (!gic_enable_sre())
479 pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");
480
481 /* Set priority mask register */
482 gic_write_pmr(DEFAULT_PMR_VALUE);
483
484 if (static_key_true(&supports_deactivate)) {
485 /* EOI drops priority only (mode 1) */
486 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop);
487 } else {
488 /* EOI deactivates interrupt too (mode 0) */
489 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir);
490 }
491
492 /* ... and let's hit the road... */
493 gic_write_grpen1(1);
494 }
495
496 static int gic_dist_supports_lpis(void)
497 {
498 return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS);
499 }
500
501 static void gic_cpu_init(void)
502 {
503 void __iomem *rbase;
504
505 /* Register ourselves with the rest of the world */
506 if (gic_populate_rdist())
507 return;
508
509 gic_enable_redist(true);
510
511 rbase = gic_data_rdist_sgi_base();
512
513 /* Configure SGIs/PPIs as non-secure Group-1 */
514 writel_relaxed(~0, rbase + GICR_IGROUPR0);
515
516 gic_cpu_config(rbase, gic_redist_wait_for_rwp);
517
518 /* Give LPIs a spin */
519 if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
520 its_cpu_init();
521
522 /* initialise system registers */
523 gic_cpu_sys_reg_init();
524 }
525
526 #ifdef CONFIG_SMP
527 static int gic_secondary_init(struct notifier_block *nfb,
528 unsigned long action, void *hcpu)
529 {
530 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
531 gic_cpu_init();
532 return NOTIFY_OK;
533 }
534
535 /*
536 * Notifier for enabling the GIC CPU interface. Set an arbitrarily high
537 * priority because the GIC needs to be up before the ARM generic timers.
538 */
539 static struct notifier_block gic_cpu_notifier = {
540 .notifier_call = gic_secondary_init,
541 .priority = 100,
542 };
543
544 static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask,
545 unsigned long cluster_id)
546 {
547 int next_cpu, cpu = *base_cpu;
548 unsigned long mpidr = cpu_logical_map(cpu);
549 u16 tlist = 0;
550
551 while (cpu < nr_cpu_ids) {
552 /*
553 * If we ever get a cluster of more than 16 CPUs, just
554 * scream and skip that CPU.
555 */
556 if (WARN_ON((mpidr & 0xff) >= 16))
557 goto out;
558
559 tlist |= 1 << (mpidr & 0xf);
560
561 next_cpu = cpumask_next(cpu, mask);
562 if (next_cpu >= nr_cpu_ids)
563 goto out;
564 cpu = next_cpu;
565
566 mpidr = cpu_logical_map(cpu);
567
568 if (cluster_id != (mpidr & ~0xffUL)) {
569 cpu--;
570 goto out;
571 }
572 }
573 out:
574 *base_cpu = cpu;
575 return tlist;
576 }
577
578 #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \
579 (MPIDR_AFFINITY_LEVEL(cluster_id, level) \
580 << ICC_SGI1R_AFFINITY_## level ##_SHIFT)
581
582 static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq)
583 {
584 u64 val;
585
586 val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) |
587 MPIDR_TO_SGI_AFFINITY(cluster_id, 2) |
588 irq << ICC_SGI1R_SGI_ID_SHIFT |
589 MPIDR_TO_SGI_AFFINITY(cluster_id, 1) |
590 tlist << ICC_SGI1R_TARGET_LIST_SHIFT);
591
592 pr_devel("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val);
593 gic_write_sgi1r(val);
594 }
595
596 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
597 {
598 int cpu;
599
600 if (WARN_ON(irq >= 16))
601 return;
602
603 /*
604 * Ensure that stores to Normal memory are visible to the
605 * other CPUs before issuing the IPI.
606 */
607 wmb();
608
609 for_each_cpu(cpu, mask) {
610 unsigned long cluster_id = cpu_logical_map(cpu) & ~0xffUL;
611 u16 tlist;
612
613 tlist = gic_compute_target_list(&cpu, mask, cluster_id);
614 gic_send_sgi(cluster_id, tlist, irq);
615 }
616
617 /* Force the above writes to ICC_SGI1R_EL1 to be executed */
618 isb();
619 }
620
621 static void gic_smp_init(void)
622 {
623 set_smp_cross_call(gic_raise_softirq);
624 register_cpu_notifier(&gic_cpu_notifier);
625 }
626
627 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
628 bool force)
629 {
630 unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
631 void __iomem *reg;
632 int enabled;
633 u64 val;
634
635 if (cpu >= nr_cpu_ids)
636 return -EINVAL;
637
638 if (gic_irq_in_rdist(d))
639 return -EINVAL;
640
641 /* If interrupt was enabled, disable it first */
642 enabled = gic_peek_irq(d, GICD_ISENABLER);
643 if (enabled)
644 gic_mask_irq(d);
645
646 reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8);
647 val = gic_mpidr_to_affinity(cpu_logical_map(cpu));
648
649 gic_write_irouter(val, reg);
650
651 /*
652 * If the interrupt was enabled, enabled it again. Otherwise,
653 * just wait for the distributor to have digested our changes.
654 */
655 if (enabled)
656 gic_unmask_irq(d);
657 else
658 gic_dist_wait_for_rwp();
659
660 return IRQ_SET_MASK_OK;
661 }
662 #else
663 #define gic_set_affinity NULL
664 #define gic_smp_init() do { } while(0)
665 #endif
666
667 #ifdef CONFIG_CPU_PM
668 static int gic_cpu_pm_notifier(struct notifier_block *self,
669 unsigned long cmd, void *v)
670 {
671 if (cmd == CPU_PM_EXIT) {
672 gic_enable_redist(true);
673 gic_cpu_sys_reg_init();
674 } else if (cmd == CPU_PM_ENTER) {
675 gic_write_grpen1(0);
676 gic_enable_redist(false);
677 }
678 return NOTIFY_OK;
679 }
680
681 static struct notifier_block gic_cpu_pm_notifier_block = {
682 .notifier_call = gic_cpu_pm_notifier,
683 };
684
685 static void gic_cpu_pm_init(void)
686 {
687 cpu_pm_register_notifier(&gic_cpu_pm_notifier_block);
688 }
689
690 #else
691 static inline void gic_cpu_pm_init(void) { }
692 #endif /* CONFIG_CPU_PM */
693
694 static struct irq_chip gic_chip = {
695 .name = "GICv3",
696 .irq_mask = gic_mask_irq,
697 .irq_unmask = gic_unmask_irq,
698 .irq_eoi = gic_eoi_irq,
699 .irq_set_type = gic_set_type,
700 .irq_set_affinity = gic_set_affinity,
701 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
702 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
703 .flags = IRQCHIP_SET_TYPE_MASKED,
704 };
705
706 static struct irq_chip gic_eoimode1_chip = {
707 .name = "GICv3",
708 .irq_mask = gic_eoimode1_mask_irq,
709 .irq_unmask = gic_unmask_irq,
710 .irq_eoi = gic_eoimode1_eoi_irq,
711 .irq_set_type = gic_set_type,
712 .irq_set_affinity = gic_set_affinity,
713 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
714 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
715 .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity,
716 .flags = IRQCHIP_SET_TYPE_MASKED,
717 };
718
719 #define GIC_ID_NR (1U << gic_data.rdists.id_bits)
720
721 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
722 irq_hw_number_t hw)
723 {
724 struct irq_chip *chip = &gic_chip;
725
726 if (static_key_true(&supports_deactivate))
727 chip = &gic_eoimode1_chip;
728
729 /* SGIs are private to the core kernel */
730 if (hw < 16)
731 return -EPERM;
732 /* Nothing here */
733 if (hw >= gic_data.irq_nr && hw < 8192)
734 return -EPERM;
735 /* Off limits */
736 if (hw >= GIC_ID_NR)
737 return -EPERM;
738
739 /* PPIs */
740 if (hw < 32) {
741 irq_set_percpu_devid(irq);
742 irq_domain_set_info(d, irq, hw, chip, d->host_data,
743 handle_percpu_devid_irq, NULL, NULL);
744 irq_set_status_flags(irq, IRQ_NOAUTOEN);
745 }
746 /* SPIs */
747 if (hw >= 32 && hw < gic_data.irq_nr) {
748 irq_domain_set_info(d, irq, hw, chip, d->host_data,
749 handle_fasteoi_irq, NULL, NULL);
750 irq_set_probe(irq);
751 }
752 /* LPIs */
753 if (hw >= 8192 && hw < GIC_ID_NR) {
754 if (!gic_dist_supports_lpis())
755 return -EPERM;
756 irq_domain_set_info(d, irq, hw, chip, d->host_data,
757 handle_fasteoi_irq, NULL, NULL);
758 }
759
760 return 0;
761 }
762
763 static int gic_irq_domain_translate(struct irq_domain *d,
764 struct irq_fwspec *fwspec,
765 unsigned long *hwirq,
766 unsigned int *type)
767 {
768 if (is_of_node(fwspec->fwnode)) {
769 if (fwspec->param_count < 3)
770 return -EINVAL;
771
772 switch (fwspec->param[0]) {
773 case 0: /* SPI */
774 *hwirq = fwspec->param[1] + 32;
775 break;
776 case 1: /* PPI */
777 *hwirq = fwspec->param[1] + 16;
778 break;
779 case GIC_IRQ_TYPE_LPI: /* LPI */
780 *hwirq = fwspec->param[1];
781 break;
782 default:
783 return -EINVAL;
784 }
785
786 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
787 return 0;
788 }
789
790 return -EINVAL;
791 }
792
793 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
794 unsigned int nr_irqs, void *arg)
795 {
796 int i, ret;
797 irq_hw_number_t hwirq;
798 unsigned int type = IRQ_TYPE_NONE;
799 struct irq_fwspec *fwspec = arg;
800
801 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type);
802 if (ret)
803 return ret;
804
805 for (i = 0; i < nr_irqs; i++)
806 gic_irq_domain_map(domain, virq + i, hwirq + i);
807
808 return 0;
809 }
810
811 static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq,
812 unsigned int nr_irqs)
813 {
814 int i;
815
816 for (i = 0; i < nr_irqs; i++) {
817 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
818 irq_set_handler(virq + i, NULL);
819 irq_domain_reset_irq_data(d);
820 }
821 }
822
823 static const struct irq_domain_ops gic_irq_domain_ops = {
824 .translate = gic_irq_domain_translate,
825 .alloc = gic_irq_domain_alloc,
826 .free = gic_irq_domain_free,
827 };
828
829 static void gicv3_enable_quirks(void)
830 {
831 #ifdef CONFIG_ARM64
832 if (cpus_have_cap(ARM64_WORKAROUND_CAVIUM_23154))
833 static_branch_enable(&is_cavium_thunderx);
834 #endif
835 }
836
837 static int __init gic_of_init(struct device_node *node, struct device_node *parent)
838 {
839 void __iomem *dist_base;
840 struct redist_region *rdist_regs;
841 u64 redist_stride;
842 u32 nr_redist_regions;
843 u32 typer;
844 u32 reg;
845 int gic_irqs;
846 int err;
847 int i;
848
849 dist_base = of_iomap(node, 0);
850 if (!dist_base) {
851 pr_err("%s: unable to map gic dist registers\n",
852 node->full_name);
853 return -ENXIO;
854 }
855
856 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
857 if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) {
858 pr_err("%s: no distributor detected, giving up\n",
859 node->full_name);
860 err = -ENODEV;
861 goto out_unmap_dist;
862 }
863
864 if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions))
865 nr_redist_regions = 1;
866
867 rdist_regs = kzalloc(sizeof(*rdist_regs) * nr_redist_regions, GFP_KERNEL);
868 if (!rdist_regs) {
869 err = -ENOMEM;
870 goto out_unmap_dist;
871 }
872
873 for (i = 0; i < nr_redist_regions; i++) {
874 struct resource res;
875 int ret;
876
877 ret = of_address_to_resource(node, 1 + i, &res);
878 rdist_regs[i].redist_base = of_iomap(node, 1 + i);
879 if (ret || !rdist_regs[i].redist_base) {
880 pr_err("%s: couldn't map region %d\n",
881 node->full_name, i);
882 err = -ENODEV;
883 goto out_unmap_rdist;
884 }
885 rdist_regs[i].phys_base = res.start;
886 }
887
888 if (of_property_read_u64(node, "redistributor-stride", &redist_stride))
889 redist_stride = 0;
890
891 if (!is_hyp_mode_available())
892 static_key_slow_dec(&supports_deactivate);
893
894 if (static_key_true(&supports_deactivate))
895 pr_info("GIC: Using split EOI/Deactivate mode\n");
896
897 gic_data.dist_base = dist_base;
898 gic_data.redist_regions = rdist_regs;
899 gic_data.nr_redist_regions = nr_redist_regions;
900 gic_data.redist_stride = redist_stride;
901
902 gicv3_enable_quirks();
903
904 /*
905 * Find out how many interrupts are supported.
906 * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI)
907 */
908 typer = readl_relaxed(gic_data.dist_base + GICD_TYPER);
909 gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer);
910 gic_irqs = GICD_TYPER_IRQS(typer);
911 if (gic_irqs > 1020)
912 gic_irqs = 1020;
913 gic_data.irq_nr = gic_irqs;
914
915 gic_data.domain = irq_domain_add_tree(node, &gic_irq_domain_ops,
916 &gic_data);
917 gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist));
918
919 if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) {
920 err = -ENOMEM;
921 goto out_free;
922 }
923
924 set_handle_irq(gic_handle_irq);
925
926 if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
927 its_init(node, &gic_data.rdists, gic_data.domain);
928
929 gic_smp_init();
930 gic_dist_init();
931 gic_cpu_init();
932 gic_cpu_pm_init();
933
934 return 0;
935
936 out_free:
937 if (gic_data.domain)
938 irq_domain_remove(gic_data.domain);
939 free_percpu(gic_data.rdists.rdist);
940 out_unmap_rdist:
941 for (i = 0; i < nr_redist_regions; i++)
942 if (rdist_regs[i].redist_base)
943 iounmap(rdist_regs[i].redist_base);
944 kfree(rdist_regs);
945 out_unmap_dist:
946 iounmap(dist_base);
947 return err;
948 }
949
950 IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
Linux with added FPC-III support