drivers/pci/setup-res.c

   1 /*
   2  *      drivers/pci/setup-res.c
   3  *
   4  * Extruded from code written by
   5  *      Dave Rusling (david.rusling@reo.mts.dec.com)
   6  *      David Mosberger (davidm@cs.arizona.edu)
   7  *      David Miller (davem@redhat.com)
   8  *
   9  * Support routines for initializing a PCI subsystem.
  10  */
  11
  12 /* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */
  13
  14 /*
  15  * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
  16  *           Resource sorting
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/export.h>
  21 #include <linux/pci.h>
  22 #include <linux/errno.h>
  23 #include <linux/ioport.h>
  24 #include <linux/cache.h>
  25 #include <linux/slab.h>
  26 #include "pci.h"
  27
  28 static void pci_std_update_resource(struct pci_dev *dev, int resno)
  29 {
  30         struct pci_bus_region region;
  31         bool disable;
  32         u16 cmd;
  33         u32 new, check, mask;
  34         int reg;
  35         struct resource *res = dev->resource + resno;
  36
  37         /* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */
  38         if (dev->is_virtfn)
  39                 return;
  40
  41         /*
  42          * Ignore resources for unimplemented BARs and unused resource slots
  43          * for 64 bit BARs.
  44          */
  45         if (!res->flags)
  46                 return;
  47
  48         if (res->flags & IORESOURCE_UNSET)
  49                 return;
  50
  51         /*
  52          * Ignore non-moveable resources.  This might be legacy resources for
  53          * which no functional BAR register exists or another important
  54          * system resource we shouldn't move around.
  55          */
  56         if (res->flags & IORESOURCE_PCI_FIXED)
  57                 return;
  58
  59         pcibios_resource_to_bus(dev->bus, &region, res);
  60         new = region.start;
  61
  62         if (res->flags & IORESOURCE_IO) {
  63                 mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
  64                 new |= res->flags & ~PCI_BASE_ADDRESS_IO_MASK;
  65         } else if (resno == PCI_ROM_RESOURCE) {
  66                 mask = PCI_ROM_ADDRESS_MASK;
  67         } else {
  68                 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
  69                 new |= res->flags & ~PCI_BASE_ADDRESS_MEM_MASK;
  70         }
  71
  72         if (resno < PCI_ROM_RESOURCE) {
  73                 reg = PCI_BASE_ADDRESS_0 + 4 * resno;
  74         } else if (resno == PCI_ROM_RESOURCE) {
  75
  76                 /*
  77                  * Apparently some Matrox devices have ROM BARs that read
  78                  * as zero when disabled, so don't update ROM BARs unless
  79                  * they're enabled.  See https://lkml.org/lkml/2005/8/30/138.
  80                  */
  81                 if (!(res->flags & IORESOURCE_ROM_ENABLE))
  82                         return;
  83
  84                 reg = dev->rom_base_reg;
  85                 new |= PCI_ROM_ADDRESS_ENABLE;
  86         } else
  87                 return;
  88
  89         /*
  90          * We can't update a 64-bit BAR atomically, so when possible,
  91          * disable decoding so that a half-updated BAR won't conflict
  92          * with another device.
  93          */
  94         disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on;
  95         if (disable) {
  96                 pci_read_config_word(dev, PCI_COMMAND, &cmd);
  97                 pci_write_config_word(dev, PCI_COMMAND,
  98                                       cmd & ~PCI_COMMAND_MEMORY);
  99         }
 100
 101         pci_write_config_dword(dev, reg, new);
 102         pci_read_config_dword(dev, reg, &check);
 103
 104         if ((new ^ check) & mask) {
 105                 dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
 106                         resno, new, check);
 107         }
 108
 109         if (res->flags & IORESOURCE_MEM_64) {
 110                 new = region.start >> 16 >> 16;
 111                 pci_write_config_dword(dev, reg + 4, new);
 112                 pci_read_config_dword(dev, reg + 4, &check);
 113                 if (check != new) {
 114                         dev_err(&dev->dev, "BAR %d: error updating (high %#08x != %#08x)\n",
 115                                 resno, new, check);
 116                 }
 117         }
 118
 119         if (disable)
 120                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 121 }
 122
 123 void pci_update_resource(struct pci_dev *dev, int resno)
 124 {
 125         if (resno <= PCI_ROM_RESOURCE)
 126                 pci_std_update_resource(dev, resno);
 127 #ifdef CONFIG_PCI_IOV
 128         else if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
 129                 pci_iov_update_resource(dev, resno);
 130 #endif
 131 }
 132
 133 int pci_claim_resource(struct pci_dev *dev, int resource)
 134 {
 135         struct resource *res = &dev->resource[resource];
 136         struct resource *root, *conflict;
 137
 138         if (res->flags & IORESOURCE_UNSET) {
 139                 dev_info(&dev->dev, "can't claim BAR %d %pR: no address assigned\n",
 140                          resource, res);
 141                 return -EINVAL;
 142         }
 143
 144         root = pci_find_parent_resource(dev, res);
 145         if (!root) {
 146                 dev_info(&dev->dev, "can't claim BAR %d %pR: no compatible bridge window\n",
 147                          resource, res);
 148                 res->flags |= IORESOURCE_UNSET;
 149                 return -EINVAL;
 150         }
 151
 152         conflict = request_resource_conflict(root, res);
 153         if (conflict) {
 154                 dev_info(&dev->dev, "can't claim BAR %d %pR: address conflict with %s %pR\n",
 155                          resource, res, conflict->name, conflict);
 156                 res->flags |= IORESOURCE_UNSET;
 157                 return -EBUSY;
 158         }
 159
 160         return 0;
 161 }
 162 EXPORT_SYMBOL(pci_claim_resource);
 163
 164 void pci_disable_bridge_window(struct pci_dev *dev)
 165 {
 166         dev_info(&dev->dev, "disabling bridge mem windows\n");
 167
 168         /* MMIO Base/Limit */
 169         pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
 170
 171         /* Prefetchable MMIO Base/Limit */
 172         pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
 173         pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
 174         pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
 175 }
 176
 177 /*
 178  * Generic function that returns a value indicating that the device's
 179  * original BIOS BAR address was not saved and so is not available for
 180  * reinstatement.
 181  *
 182  * Can be over-ridden by architecture specific code that implements
 183  * reinstatement functionality rather than leaving it disabled when
 184  * normal allocation attempts fail.
 185  */
 186 resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
 187 {
 188         return 0;
 189 }
 190
 191 static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
 192                 int resno, resource_size_t size)
 193 {
 194         struct resource *root, *conflict;
 195         resource_size_t fw_addr, start, end;
 196
 197         fw_addr = pcibios_retrieve_fw_addr(dev, resno);
 198         if (!fw_addr)
 199                 return -ENOMEM;
 200
 201         start = res->start;
 202         end = res->end;
 203         res->start = fw_addr;
 204         res->end = res->start + size - 1;
 205         res->flags &= ~IORESOURCE_UNSET;
 206
 207         root = pci_find_parent_resource(dev, res);
 208         if (!root) {
 209                 if (res->flags & IORESOURCE_IO)
 210                         root = &ioport_resource;
 211                 else
 212                         root = &iomem_resource;
 213         }
 214
 215         dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n",
 216                  resno, res);
 217         conflict = request_resource_conflict(root, res);
 218         if (conflict) {
 219                 dev_info(&dev->dev, "BAR %d: %pR conflicts with %s %pR\n",
 220                          resno, res, conflict->name, conflict);
 221                 res->start = start;
 222                 res->end = end;
 223                 res->flags |= IORESOURCE_UNSET;
 224                 return -EBUSY;
 225         }
 226         return 0;
 227 }
 228
 229 static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
 230                 int resno, resource_size_t size, resource_size_t align)
 231 {
 232         struct resource *res = dev->resource + resno;
 233         resource_size_t min;
 234         int ret;
 235
 236         min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
 237
 238         /*
 239          * First, try exact prefetching match.  Even if a 64-bit
 240          * prefetchable bridge window is below 4GB, we can't put a 32-bit
 241          * prefetchable resource in it because pbus_size_mem() assumes a
 242          * 64-bit window will contain no 32-bit resources.  If we assign
 243          * things differently than they were sized, not everything will fit.
 244          */
 245         ret = pci_bus_alloc_resource(bus, res, size, align, min,
 246                                      IORESOURCE_PREFETCH | IORESOURCE_MEM_64,
 247                                      pcibios_align_resource, dev);
 248         if (ret == 0)
 249                 return 0;
 250
 251         /*
 252          * If the prefetchable window is only 32 bits wide, we can put
 253          * 64-bit prefetchable resources in it.
 254          */
 255         if ((res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) ==
 256              (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) {
 257                 ret = pci_bus_alloc_resource(bus, res, size, align, min,
 258                                              IORESOURCE_PREFETCH,
 259                                              pcibios_align_resource, dev);
 260                 if (ret == 0)
 261                         return 0;
 262         }
 263
 264         /*
 265          * If we didn't find a better match, we can put any memory resource
 266          * in a non-prefetchable window.  If this resource is 32 bits and
 267          * non-prefetchable, the first call already tried the only possibility
 268          * so we don't need to try again.
 269          */
 270         if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64))
 271                 ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
 272                                              pcibios_align_resource, dev);
 273
 274         return ret;
 275 }
 276
 277 static int _pci_assign_resource(struct pci_dev *dev, int resno,
 278                                 resource_size_t size, resource_size_t min_align)
 279 {
 280         struct pci_bus *bus;
 281         int ret;
 282
 283         bus = dev->bus;
 284         while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
 285                 if (!bus->parent || !bus->self->transparent)
 286                         break;
 287                 bus = bus->parent;
 288         }
 289
 290         return ret;
 291 }
 292
 293 int pci_assign_resource(struct pci_dev *dev, int resno)
 294 {
 295         struct resource *res = dev->resource + resno;
 296         resource_size_t align, size;
 297         int ret;
 298
 299         res->flags |= IORESOURCE_UNSET;
 300         align = pci_resource_alignment(dev, res);
 301         if (!align) {
 302                 dev_info(&dev->dev, "BAR %d: can't assign %pR (bogus alignment)\n",
 303                          resno, res);
 304                 return -EINVAL;
 305         }
 306
 307         size = resource_size(res);
 308         ret = _pci_assign_resource(dev, resno, size, align);
 309
 310         /*
 311          * If we failed to assign anything, let's try the address
 312          * where firmware left it.  That at least has a chance of
 313          * working, which is better than just leaving it disabled.
 314          */
 315         if (ret < 0) {
 316                 dev_info(&dev->dev, "BAR %d: no space for %pR\n", resno, res);
 317                 ret = pci_revert_fw_address(res, dev, resno, size);
 318         }
 319
 320         if (ret < 0) {
 321                 dev_info(&dev->dev, "BAR %d: failed to assign %pR\n", resno,
 322                          res);
 323                 return ret;
 324         }
 325
 326         res->flags &= ~IORESOURCE_UNSET;
 327         res->flags &= ~IORESOURCE_STARTALIGN;
 328         dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
 329         if (resno < PCI_BRIDGE_RESOURCES)
 330                 pci_update_resource(dev, resno);
 331
 332         return 0;
 333 }
 334 EXPORT_SYMBOL(pci_assign_resource);
 335
 336 int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
 337                         resource_size_t min_align)
 338 {
 339         struct resource *res = dev->resource + resno;
 340         unsigned long flags;
 341         resource_size_t new_size;
 342         int ret;
 343
 344         flags = res->flags;
 345         res->flags |= IORESOURCE_UNSET;
 346         if (!res->parent) {
 347                 dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resource %pR\n",
 348                          resno, res);
 349                 return -EINVAL;
 350         }
 351
 352         /* already aligned with min_align */
 353         new_size = resource_size(res) + addsize;
 354         ret = _pci_assign_resource(dev, resno, new_size, min_align);
 355         if (ret) {
 356                 res->flags = flags;
 357                 dev_info(&dev->dev, "BAR %d: %pR (failed to expand by %#llx)\n",
 358                          resno, res, (unsigned long long) addsize);
 359                 return ret;
 360         }
 361
 362         res->flags &= ~IORESOURCE_UNSET;
 363         res->flags &= ~IORESOURCE_STARTALIGN;
 364         dev_info(&dev->dev, "BAR %d: reassigned %pR (expanded by %#llx)\n",
 365                  resno, res, (unsigned long long) addsize);
 366         if (resno < PCI_BRIDGE_RESOURCES)
 367                 pci_update_resource(dev, resno);
 368
 369         return 0;
 370 }
 371
 372 int pci_enable_resources(struct pci_dev *dev, int mask)
 373 {
 374         u16 cmd, old_cmd;
 375         int i;
 376         struct resource *r;
 377
 378         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 379         old_cmd = cmd;
 380
 381         for (i = 0; i < PCI_NUM_RESOURCES; i++) {
 382                 if (!(mask & (1 << i)))
 383                         continue;
 384
 385                 r = &dev->resource[i];
 386
 387                 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
 388                         continue;
 389                 if ((i == PCI_ROM_RESOURCE) &&
 390                                 (!(r->flags & IORESOURCE_ROM_ENABLE)))
 391                         continue;
 392
 393                 if (r->flags & IORESOURCE_UNSET) {
 394                         dev_err(&dev->dev, "can't enable device: BAR %d %pR not assigned\n",
 395                                 i, r);
 396                         return -EINVAL;
 397                 }
 398
 399                 if (!r->parent) {
 400                         dev_err(&dev->dev, "can't enable device: BAR %d %pR not claimed\n",
 401                                 i, r);
 402                         return -EINVAL;
 403                 }
 404
 405                 if (r->flags & IORESOURCE_IO)
 406                         cmd |= PCI_COMMAND_IO;
 407                 if (r->flags & IORESOURCE_MEM)
 408                         cmd |= PCI_COMMAND_MEMORY;
 409         }
 410
 411         if (cmd != old_cmd) {
 412                 dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
 413                          old_cmd, cmd);
 414                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 415         }
 416         return 0;
 417 }