drivers/rtc/rtc-snvs.c

   1 /*
   2  * Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/io.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/of.h>
  17 #include <linux/of_device.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/rtc.h>
  20 #include <linux/clk.h>
  21 #include <linux/mfd/syscon.h>
  22 #include <linux/regmap.h>
  23
  24 #define SNVS_LPREGISTER_OFFSET  0x34
  25
  26 /* These register offsets are relative to LP (Low Power) range */
  27 #define SNVS_LPCR               0x04
  28 #define SNVS_LPSR               0x18
  29 #define SNVS_LPSRTCMR           0x1c
  30 #define SNVS_LPSRTCLR           0x20
  31 #define SNVS_LPTAR              0x24
  32 #define SNVS_LPPGDR             0x30
  33
  34 #define SNVS_LPCR_SRTC_ENV      (1 << 0)
  35 #define SNVS_LPCR_LPTA_EN       (1 << 1)
  36 #define SNVS_LPCR_LPWUI_EN      (1 << 3)
  37 #define SNVS_LPSR_LPTA          (1 << 0)
  38
  39 #define SNVS_LPPGDR_INIT        0x41736166
  40 #define CNTR_TO_SECS_SH         15
  41
  42 struct snvs_rtc_data {
  43         struct rtc_device *rtc;
  44         struct regmap *regmap;
  45         int offset;
  46         int irq;
  47         struct clk *clk;
  48 };
  49
  50 static u32 rtc_read_lp_counter(struct snvs_rtc_data *data)
  51 {
  52         u64 read1, read2;
  53         u32 val;
  54
  55         do {
  56                 regmap_read(data->regmap, data->offset + SNVS_LPSRTCMR, &val);
  57                 read1 = val;
  58                 read1 <<= 32;
  59                 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &val);
  60                 read1 |= val;
  61
  62                 regmap_read(data->regmap, data->offset + SNVS_LPSRTCMR, &val);
  63                 read2 = val;
  64                 read2 <<= 32;
  65                 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &val);
  66                 read2 |= val;
  67         } while (read1 != read2);
  68
  69         /* Convert 47-bit counter to 32-bit raw second count */
  70         return (u32) (read1 >> CNTR_TO_SECS_SH);
  71 }
  72
  73 static void rtc_write_sync_lp(struct snvs_rtc_data *data)
  74 {
  75         u32 count1, count2, count3;
  76         int i;
  77
  78         /* Wait for 3 CKIL cycles */
  79         for (i = 0; i < 3; i++) {
  80                 do {
  81                         regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
  82                         regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count2);
  83                 } while (count1 != count2);
  84
  85                 /* Now wait until counter value changes */
  86                 do {
  87                         do {
  88                                 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count2);
  89                                 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count3);
  90                         } while (count2 != count3);
  91                 } while (count3 == count1);
  92         }
  93 }
  94
  95 static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable)
  96 {
  97         int timeout = 1000;
  98         u32 lpcr;
  99
 100         regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_SRTC_ENV,
 101                            enable ? SNVS_LPCR_SRTC_ENV : 0);
 102
 103         while (--timeout) {
 104                 regmap_read(data->regmap, data->offset + SNVS_LPCR, &lpcr);
 105
 106                 if (enable) {
 107                         if (lpcr & SNVS_LPCR_SRTC_ENV)
 108                                 break;
 109                 } else {
 110                         if (!(lpcr & SNVS_LPCR_SRTC_ENV))
 111                                 break;
 112                 }
 113         }
 114
 115         if (!timeout)
 116                 return -ETIMEDOUT;
 117
 118         return 0;
 119 }
 120
 121 static int snvs_rtc_read_time(struct device *dev, struct rtc_time *tm)
 122 {
 123         struct snvs_rtc_data *data = dev_get_drvdata(dev);
 124         unsigned long time = rtc_read_lp_counter(data);
 125
 126         rtc_time_to_tm(time, tm);
 127
 128         return 0;
 129 }
 130
 131 static int snvs_rtc_set_time(struct device *dev, struct rtc_time *tm)
 132 {
 133         struct snvs_rtc_data *data = dev_get_drvdata(dev);
 134         unsigned long time;
 135         int ret;
 136
 137         rtc_tm_to_time(tm, &time);
 138
 139         /* Disable RTC first */
 140         ret = snvs_rtc_enable(data, false);
 141         if (ret)
 142                 return ret;
 143
 144         /* Write 32-bit time to 47-bit timer, leaving 15 LSBs blank */
 145         regmap_write(data->regmap, data->offset + SNVS_LPSRTCLR, time << CNTR_TO_SECS_SH);
 146         regmap_write(data->regmap, data->offset + SNVS_LPSRTCMR, time >> (32 - CNTR_TO_SECS_SH));
 147
 148         /* Enable RTC again */
 149         ret = snvs_rtc_enable(data, true);
 150
 151         return ret;
 152 }
 153
 154 static int snvs_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 155 {
 156         struct snvs_rtc_data *data = dev_get_drvdata(dev);
 157         u32 lptar, lpsr;
 158
 159         regmap_read(data->regmap, data->offset + SNVS_LPTAR, &lptar);
 160         rtc_time_to_tm(lptar, &alrm->time);
 161
 162         regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
 163         alrm->pending = (lpsr & SNVS_LPSR_LPTA) ? 1 : 0;
 164
 165         return 0;
 166 }
 167
 168 static int snvs_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
 169 {
 170         struct snvs_rtc_data *data = dev_get_drvdata(dev);
 171
 172         regmap_update_bits(data->regmap, data->offset + SNVS_LPCR,
 173                            (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN),
 174                            enable ? (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN) : 0);
 175
 176         rtc_write_sync_lp(data);
 177
 178         return 0;
 179 }
 180
 181 static int snvs_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 182 {
 183         struct snvs_rtc_data *data = dev_get_drvdata(dev);
 184         struct rtc_time *alrm_tm = &alrm->time;
 185         unsigned long time;
 186
 187         rtc_tm_to_time(alrm_tm, &time);
 188
 189         regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_LPTA_EN, 0);
 190         regmap_write(data->regmap, data->offset + SNVS_LPTAR, time);
 191
 192         /* Clear alarm interrupt status bit */
 193         regmap_write(data->regmap, data->offset + SNVS_LPSR, SNVS_LPSR_LPTA);
 194
 195         return snvs_rtc_alarm_irq_enable(dev, alrm->enabled);
 196 }
 197
 198 static const struct rtc_class_ops snvs_rtc_ops = {
 199         .read_time = snvs_rtc_read_time,
 200         .set_time = snvs_rtc_set_time,
 201         .read_alarm = snvs_rtc_read_alarm,
 202         .set_alarm = snvs_rtc_set_alarm,
 203         .alarm_irq_enable = snvs_rtc_alarm_irq_enable,
 204 };
 205
 206 static irqreturn_t snvs_rtc_irq_handler(int irq, void *dev_id)
 207 {
 208         struct device *dev = dev_id;
 209         struct snvs_rtc_data *data = dev_get_drvdata(dev);
 210         u32 lpsr;
 211         u32 events = 0;
 212
 213         regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
 214
 215         if (lpsr & SNVS_LPSR_LPTA) {
 216                 events |= (RTC_AF | RTC_IRQF);
 217
 218                 /* RTC alarm should be one-shot */
 219                 snvs_rtc_alarm_irq_enable(dev, 0);
 220
 221                 rtc_update_irq(data->rtc, 1, events);
 222         }
 223
 224         /* clear interrupt status */
 225         regmap_write(data->regmap, data->offset + SNVS_LPSR, lpsr);
 226
 227         return events ? IRQ_HANDLED : IRQ_NONE;
 228 }
 229
 230 static const struct regmap_config snvs_rtc_config = {
 231         .reg_bits = 32,
 232         .val_bits = 32,
 233         .reg_stride = 4,
 234 };
 235
 236 static int snvs_rtc_probe(struct platform_device *pdev)
 237 {
 238         struct snvs_rtc_data *data;
 239         struct resource *res;
 240         int ret;
 241         void __iomem *mmio;
 242
 243         data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
 244         if (!data)
 245                 return -ENOMEM;
 246
 247         data->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "regmap");
 248
 249         if (IS_ERR(data->regmap)) {
 250                 dev_warn(&pdev->dev, "snvs rtc: you use old dts file, please update it\n");
 251                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 252
 253                 mmio = devm_ioremap_resource(&pdev->dev, res);
 254                 if (IS_ERR(mmio))
 255                         return PTR_ERR(mmio);
 256
 257                 data->regmap = devm_regmap_init_mmio(&pdev->dev, mmio, &snvs_rtc_config);
 258         } else {
 259                 data->offset = SNVS_LPREGISTER_OFFSET;
 260                 of_property_read_u32(pdev->dev.of_node, "offset", &data->offset);
 261         }
 262
 263         if (IS_ERR(data->regmap)) {
 264                 dev_err(&pdev->dev, "Can't find snvs syscon\n");
 265                 return -ENODEV;
 266         }
 267
 268         data->irq = platform_get_irq(pdev, 0);
 269         if (data->irq < 0)
 270                 return data->irq;
 271
 272         data->clk = devm_clk_get(&pdev->dev, "snvs-rtc");
 273         if (IS_ERR(data->clk)) {
 274                 data->clk = NULL;
 275         } else {
 276                 ret = clk_prepare_enable(data->clk);
 277                 if (ret) {
 278                         dev_err(&pdev->dev,
 279                                 "Could not prepare or enable the snvs clock\n");
 280                         return ret;
 281                 }
 282         }
 283
 284         platform_set_drvdata(pdev, data);
 285
 286         /* Initialize glitch detect */
 287         regmap_write(data->regmap, data->offset + SNVS_LPPGDR, SNVS_LPPGDR_INIT);
 288
 289         /* Clear interrupt status */
 290         regmap_write(data->regmap, data->offset + SNVS_LPSR, 0xffffffff);
 291
 292         /* Enable RTC */
 293         ret = snvs_rtc_enable(data, true);
 294         if (ret) {
 295                 dev_err(&pdev->dev, "failed to enable rtc %d\n", ret);
 296                 goto error_rtc_device_register;
 297         }
 298
 299         device_init_wakeup(&pdev->dev, true);
 300
 301         ret = devm_request_irq(&pdev->dev, data->irq, snvs_rtc_irq_handler,
 302                                IRQF_SHARED, "rtc alarm", &pdev->dev);
 303         if (ret) {
 304                 dev_err(&pdev->dev, "failed to request irq %d: %d\n",
 305                         data->irq, ret);
 306                 goto error_rtc_device_register;
 307         }
 308
 309         data->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
 310                                         &snvs_rtc_ops, THIS_MODULE);
 311         if (IS_ERR(data->rtc)) {
 312                 ret = PTR_ERR(data->rtc);
 313                 dev_err(&pdev->dev, "failed to register rtc: %d\n", ret);
 314                 goto error_rtc_device_register;
 315         }
 316
 317         return 0;
 318
 319 error_rtc_device_register:
 320         if (data->clk)
 321                 clk_disable_unprepare(data->clk);
 322
 323         return ret;
 324 }
 325
 326 #ifdef CONFIG_PM_SLEEP
 327 static int snvs_rtc_suspend(struct device *dev)
 328 {
 329         struct snvs_rtc_data *data = dev_get_drvdata(dev);
 330
 331         if (device_may_wakeup(dev))
 332                 enable_irq_wake(data->irq);
 333
 334         return 0;
 335 }
 336
 337 static int snvs_rtc_suspend_noirq(struct device *dev)
 338 {
 339         struct snvs_rtc_data *data = dev_get_drvdata(dev);
 340
 341         if (data->clk)
 342                 clk_disable_unprepare(data->clk);
 343
 344         return 0;
 345 }
 346
 347 static int snvs_rtc_resume(struct device *dev)
 348 {
 349         struct snvs_rtc_data *data = dev_get_drvdata(dev);
 350
 351         if (device_may_wakeup(dev))
 352                 return disable_irq_wake(data->irq);
 353
 354         return 0;
 355 }
 356
 357 static int snvs_rtc_resume_noirq(struct device *dev)
 358 {
 359         struct snvs_rtc_data *data = dev_get_drvdata(dev);
 360
 361         if (data->clk)
 362                 return clk_prepare_enable(data->clk);
 363
 364         return 0;
 365 }
 366
 367 static const struct dev_pm_ops snvs_rtc_pm_ops = {
 368         .suspend = snvs_rtc_suspend,
 369         .suspend_noirq = snvs_rtc_suspend_noirq,
 370         .resume = snvs_rtc_resume,
 371         .resume_noirq = snvs_rtc_resume_noirq,
 372 };
 373
 374 #define SNVS_RTC_PM_OPS (&snvs_rtc_pm_ops)
 375
 376 #else
 377
 378 #define SNVS_RTC_PM_OPS NULL
 379
 380 #endif
 381
 382 static const struct of_device_id snvs_dt_ids[] = {
 383         { .compatible = "fsl,sec-v4.0-mon-rtc-lp", },
 384         { /* sentinel */ }
 385 };
 386 MODULE_DEVICE_TABLE(of, snvs_dt_ids);
 387
 388 static struct platform_driver snvs_rtc_driver = {
 389         .driver = {
 390                 .name   = "snvs_rtc",
 391                 .pm     = SNVS_RTC_PM_OPS,
 392                 .of_match_table = snvs_dt_ids,
 393         },
 394         .probe          = snvs_rtc_probe,
 395 };
 396 module_platform_driver(snvs_rtc_driver);
 397
 398 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
 399 MODULE_DESCRIPTION("Freescale SNVS RTC Driver");
 400 MODULE_LICENSE("GPL");