drivers/iio/counter/104-quad-8.c

   1 /*
   2  * IIO driver for the ACCES 104-QUAD-8
   3  * Copyright (C) 2016 William Breathitt Gray
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License, version 2, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * General Public License for more details.
  13  *
  14  * This driver supports the ACCES 104-QUAD-8 and ACCES 104-QUAD-4.
  15  */
  16 #include <linux/bitops.h>
  17 #include <linux/device.h>
  18 #include <linux/errno.h>
  19 #include <linux/iio/iio.h>
  20 #include <linux/iio/types.h>
  21 #include <linux/io.h>
  22 #include <linux/ioport.h>
  23 #include <linux/isa.h>
  24 #include <linux/kernel.h>
  25 #include <linux/module.h>
  26 #include <linux/moduleparam.h>
  27 #include <linux/types.h>
  28
  29 #define QUAD8_EXTENT 32
  30
  31 static unsigned int base[max_num_isa_dev(QUAD8_EXTENT)];
  32 static unsigned int num_quad8;
  33 module_param_array(base, uint, &num_quad8, 0);
  34 MODULE_PARM_DESC(base, "ACCES 104-QUAD-8 base addresses");
  35
  36 #define QUAD8_NUM_COUNTERS 8
  37
  38 /**
  39  * struct quad8_iio - IIO device private data structure
  40  * @preset:             array of preset values
  41  * @count_mode:         array of count mode configurations
  42  * @quadrature_mode:    array of quadrature mode configurations
  43  * @quadrature_scale:   array of quadrature mode scale configurations
  44  * @ab_enable:          array of A and B inputs enable configurations
  45  * @preset_enable:      array of set_to_preset_on_index attribute configurations
  46  * @synchronous_mode:   array of index function synchronous mode configurations
  47  * @index_polarity:     array of index function polarity configurations
  48  * @base:               base port address of the IIO device
  49  */
  50 struct quad8_iio {
  51         unsigned int preset[QUAD8_NUM_COUNTERS];
  52         unsigned int count_mode[QUAD8_NUM_COUNTERS];
  53         unsigned int quadrature_mode[QUAD8_NUM_COUNTERS];
  54         unsigned int quadrature_scale[QUAD8_NUM_COUNTERS];
  55         unsigned int ab_enable[QUAD8_NUM_COUNTERS];
  56         unsigned int preset_enable[QUAD8_NUM_COUNTERS];
  57         unsigned int synchronous_mode[QUAD8_NUM_COUNTERS];
  58         unsigned int index_polarity[QUAD8_NUM_COUNTERS];
  59         unsigned int base;
  60 };
  61
  62 static int quad8_read_raw(struct iio_dev *indio_dev,
  63         struct iio_chan_spec const *chan, int *val, int *val2, long mask)
  64 {
  65         struct quad8_iio *const priv = iio_priv(indio_dev);
  66         const int base_offset = priv->base + 2 * chan->channel;
  67         unsigned int flags;
  68         unsigned int borrow;
  69         unsigned int carry;
  70         int i;
  71
  72         switch (mask) {
  73         case IIO_CHAN_INFO_RAW:
  74                 if (chan->type == IIO_INDEX) {
  75                         *val = !!(inb(priv->base + 0x16) & BIT(chan->channel));
  76                         return IIO_VAL_INT;
  77                 }
  78
  79                 flags = inb(base_offset + 1);
  80                 borrow = flags & BIT(0);
  81                 carry = !!(flags & BIT(1));
  82
  83                 /* Borrow XOR Carry effectively doubles count range */
  84                 *val = (borrow ^ carry) << 24;
  85
  86                 /* Reset Byte Pointer; transfer Counter to Output Latch */
  87                 outb(0x11, base_offset + 1);
  88
  89                 for (i = 0; i < 3; i++)
  90                         *val |= (unsigned int)inb(base_offset) << (8 * i);
  91
  92                 return IIO_VAL_INT;
  93         case IIO_CHAN_INFO_ENABLE:
  94                 *val = priv->ab_enable[chan->channel];
  95                 return IIO_VAL_INT;
  96         case IIO_CHAN_INFO_SCALE:
  97                 *val = 1;
  98                 *val2 = priv->quadrature_scale[chan->channel];
  99                 return IIO_VAL_FRACTIONAL_LOG2;
 100         }
 101
 102         return -EINVAL;
 103 }
 104
 105 static int quad8_write_raw(struct iio_dev *indio_dev,
 106         struct iio_chan_spec const *chan, int val, int val2, long mask)
 107 {
 108         struct quad8_iio *const priv = iio_priv(indio_dev);
 109         const int base_offset = priv->base + 2 * chan->channel;
 110         int i;
 111         unsigned int ior_cfg;
 112
 113         switch (mask) {
 114         case IIO_CHAN_INFO_RAW:
 115                 if (chan->type == IIO_INDEX)
 116                         return -EINVAL;
 117
 118                 /* Only 24-bit values are supported */
 119                 if ((unsigned int)val > 0xFFFFFF)
 120                         return -EINVAL;
 121
 122                 /* Reset Byte Pointer */
 123                 outb(0x01, base_offset + 1);
 124
 125                 /* Counter can only be set via Preset Register */
 126                 for (i = 0; i < 3; i++)
 127                         outb(val >> (8 * i), base_offset);
 128
 129                 /* Transfer Preset Register to Counter */
 130                 outb(0x08, base_offset + 1);
 131
 132                 /* Reset Byte Pointer */
 133                 outb(0x01, base_offset + 1);
 134
 135                 /* Set Preset Register back to original value */
 136                 val = priv->preset[chan->channel];
 137                 for (i = 0; i < 3; i++)
 138                         outb(val >> (8 * i), base_offset);
 139
 140                 /* Reset Borrow, Carry, Compare, and Sign flags */
 141                 outb(0x02, base_offset + 1);
 142                 /* Reset Error flag */
 143                 outb(0x06, base_offset + 1);
 144
 145                 return 0;
 146         case IIO_CHAN_INFO_ENABLE:
 147                 /* only boolean values accepted */
 148                 if (val < 0 || val > 1)
 149                         return -EINVAL;
 150
 151                 priv->ab_enable[chan->channel] = val;
 152
 153                 ior_cfg = val | priv->preset_enable[chan->channel] << 1;
 154
 155                 /* Load I/O control configuration */
 156                 outb(0x40 | ior_cfg, base_offset + 1);
 157
 158                 return 0;
 159         case IIO_CHAN_INFO_SCALE:
 160                 /* Quadrature scaling only available in quadrature mode */
 161                 if (!priv->quadrature_mode[chan->channel] && (val2 || val != 1))
 162                         return -EINVAL;
 163
 164                 /* Only three gain states (1, 0.5, 0.25) */
 165                 if (val == 1 && !val2)
 166                         priv->quadrature_scale[chan->channel] = 0;
 167                 else if (!val)
 168                         switch (val2) {
 169                         case 500000:
 170                                 priv->quadrature_scale[chan->channel] = 1;
 171                                 break;
 172                         case 250000:
 173                                 priv->quadrature_scale[chan->channel] = 2;
 174                                 break;
 175                         default:
 176                                 return -EINVAL;
 177                         }
 178                 else
 179                         return -EINVAL;
 180
 181                 return 0;
 182         }
 183
 184         return -EINVAL;
 185 }
 186
 187 static const struct iio_info quad8_info = {
 188         .driver_module = THIS_MODULE,
 189         .read_raw = quad8_read_raw,
 190         .write_raw = quad8_write_raw
 191 };
 192
 193 static ssize_t quad8_read_preset(struct iio_dev *indio_dev, uintptr_t private,
 194         const struct iio_chan_spec *chan, char *buf)
 195 {
 196         const struct quad8_iio *const priv = iio_priv(indio_dev);
 197
 198         return snprintf(buf, PAGE_SIZE, "%u\n", priv->preset[chan->channel]);
 199 }
 200
 201 static ssize_t quad8_write_preset(struct iio_dev *indio_dev, uintptr_t private,
 202         const struct iio_chan_spec *chan, const char *buf, size_t len)
 203 {
 204         struct quad8_iio *const priv = iio_priv(indio_dev);
 205         const int base_offset = priv->base + 2 * chan->channel;
 206         unsigned int preset;
 207         int ret;
 208         int i;
 209
 210         ret = kstrtouint(buf, 0, &preset);
 211         if (ret)
 212                 return ret;
 213
 214         /* Only 24-bit values are supported */
 215         if (preset > 0xFFFFFF)
 216                 return -EINVAL;
 217
 218         priv->preset[chan->channel] = preset;
 219
 220         /* Reset Byte Pointer */
 221         outb(0x01, base_offset + 1);
 222
 223         /* Set Preset Register */
 224         for (i = 0; i < 3; i++)
 225                 outb(preset >> (8 * i), base_offset);
 226
 227         return len;
 228 }
 229
 230 static ssize_t quad8_read_set_to_preset_on_index(struct iio_dev *indio_dev,
 231         uintptr_t private, const struct iio_chan_spec *chan, char *buf)
 232 {
 233         const struct quad8_iio *const priv = iio_priv(indio_dev);
 234
 235         return snprintf(buf, PAGE_SIZE, "%u\n",
 236                 !priv->preset_enable[chan->channel]);
 237 }
 238
 239 static ssize_t quad8_write_set_to_preset_on_index(struct iio_dev *indio_dev,
 240         uintptr_t private, const struct iio_chan_spec *chan, const char *buf,
 241         size_t len)
 242 {
 243         struct quad8_iio *const priv = iio_priv(indio_dev);
 244         const int base_offset = priv->base + 2 * chan->channel + 1;
 245         bool preset_enable;
 246         int ret;
 247         unsigned int ior_cfg;
 248
 249         ret = kstrtobool(buf, &preset_enable);
 250         if (ret)
 251                 return ret;
 252
 253         /* Preset enable is active low in Input/Output Control register */
 254         preset_enable = !preset_enable;
 255
 256         priv->preset_enable[chan->channel] = preset_enable;
 257
 258         ior_cfg = priv->ab_enable[chan->channel] |
 259                 (unsigned int)preset_enable << 1;
 260
 261         /* Load I/O control configuration to Input / Output Control Register */
 262         outb(0x40 | ior_cfg, base_offset);
 263
 264         return len;
 265 }
 266
 267 static const char *const quad8_noise_error_states[] = {
 268         "No excessive noise is present at the count inputs",
 269         "Excessive noise is present at the count inputs"
 270 };
 271
 272 static int quad8_get_noise_error(struct iio_dev *indio_dev,
 273         const struct iio_chan_spec *chan)
 274 {
 275         struct quad8_iio *const priv = iio_priv(indio_dev);
 276         const int base_offset = priv->base + 2 * chan->channel + 1;
 277
 278         return !!(inb(base_offset) & BIT(4));
 279 }
 280
 281 static const struct iio_enum quad8_noise_error_enum = {
 282         .items = quad8_noise_error_states,
 283         .num_items = ARRAY_SIZE(quad8_noise_error_states),
 284         .get = quad8_get_noise_error
 285 };
 286
 287 static const char *const quad8_count_direction_states[] = {
 288         "down",
 289         "up"
 290 };
 291
 292 static int quad8_get_count_direction(struct iio_dev *indio_dev,
 293         const struct iio_chan_spec *chan)
 294 {
 295         struct quad8_iio *const priv = iio_priv(indio_dev);
 296         const int base_offset = priv->base + 2 * chan->channel + 1;
 297
 298         return !!(inb(base_offset) & BIT(5));
 299 }
 300
 301 static const struct iio_enum quad8_count_direction_enum = {
 302         .items = quad8_count_direction_states,
 303         .num_items = ARRAY_SIZE(quad8_count_direction_states),
 304         .get = quad8_get_count_direction
 305 };
 306
 307 static const char *const quad8_count_modes[] = {
 308         "normal",
 309         "range limit",
 310         "non-recycle",
 311         "modulo-n"
 312 };
 313
 314 static int quad8_set_count_mode(struct iio_dev *indio_dev,
 315         const struct iio_chan_spec *chan, unsigned int count_mode)
 316 {
 317         struct quad8_iio *const priv = iio_priv(indio_dev);
 318         unsigned int mode_cfg = count_mode << 1;
 319         const int base_offset = priv->base + 2 * chan->channel + 1;
 320
 321         priv->count_mode[chan->channel] = count_mode;
 322
 323         /* Add quadrature mode configuration */
 324         if (priv->quadrature_mode[chan->channel])
 325                 mode_cfg |= (priv->quadrature_scale[chan->channel] + 1) << 3;
 326
 327         /* Load mode configuration to Counter Mode Register */
 328         outb(0x20 | mode_cfg, base_offset);
 329
 330         return 0;
 331 }
 332
 333 static int quad8_get_count_mode(struct iio_dev *indio_dev,
 334         const struct iio_chan_spec *chan)
 335 {
 336         const struct quad8_iio *const priv = iio_priv(indio_dev);
 337
 338         return priv->count_mode[chan->channel];
 339 }
 340
 341 static const struct iio_enum quad8_count_mode_enum = {
 342         .items = quad8_count_modes,
 343         .num_items = ARRAY_SIZE(quad8_count_modes),
 344         .set = quad8_set_count_mode,
 345         .get = quad8_get_count_mode
 346 };
 347
 348 static const char *const quad8_synchronous_modes[] = {
 349         "non-synchronous",
 350         "synchronous"
 351 };
 352
 353 static int quad8_set_synchronous_mode(struct iio_dev *indio_dev,
 354         const struct iio_chan_spec *chan, unsigned int synchronous_mode)
 355 {
 356         struct quad8_iio *const priv = iio_priv(indio_dev);
 357         const unsigned int idr_cfg = synchronous_mode |
 358                 priv->index_polarity[chan->channel] << 1;
 359         const int base_offset = priv->base + 2 * chan->channel + 1;
 360
 361         /* Index function must be non-synchronous in non-quadrature mode */
 362         if (synchronous_mode && !priv->quadrature_mode[chan->channel])
 363                 return -EINVAL;
 364
 365         priv->synchronous_mode[chan->channel] = synchronous_mode;
 366
 367         /* Load Index Control configuration to Index Control Register */
 368         outb(0x60 | idr_cfg, base_offset);
 369
 370         return 0;
 371 }
 372
 373 static int quad8_get_synchronous_mode(struct iio_dev *indio_dev,
 374         const struct iio_chan_spec *chan)
 375 {
 376         const struct quad8_iio *const priv = iio_priv(indio_dev);
 377
 378         return priv->synchronous_mode[chan->channel];
 379 }
 380
 381 static const struct iio_enum quad8_synchronous_mode_enum = {
 382         .items = quad8_synchronous_modes,
 383         .num_items = ARRAY_SIZE(quad8_synchronous_modes),
 384         .set = quad8_set_synchronous_mode,
 385         .get = quad8_get_synchronous_mode
 386 };
 387
 388 static const char *const quad8_quadrature_modes[] = {
 389         "non-quadrature",
 390         "quadrature"
 391 };
 392
 393 static int quad8_set_quadrature_mode(struct iio_dev *indio_dev,
 394         const struct iio_chan_spec *chan, unsigned int quadrature_mode)
 395 {
 396         struct quad8_iio *const priv = iio_priv(indio_dev);
 397         unsigned int mode_cfg = priv->count_mode[chan->channel] << 1;
 398         const int base_offset = priv->base + 2 * chan->channel + 1;
 399
 400         if (quadrature_mode)
 401                 mode_cfg |= (priv->quadrature_scale[chan->channel] + 1) << 3;
 402         else {
 403                 /* Quadrature scaling only available in quadrature mode */
 404                 priv->quadrature_scale[chan->channel] = 0;
 405
 406                 /* Synchronous function not supported in non-quadrature mode */
 407                 if (priv->synchronous_mode[chan->channel])
 408                         quad8_set_synchronous_mode(indio_dev, chan, 0);
 409         }
 410
 411         priv->quadrature_mode[chan->channel] = quadrature_mode;
 412
 413         /* Load mode configuration to Counter Mode Register */
 414         outb(0x20 | mode_cfg, base_offset);
 415
 416         return 0;
 417 }
 418
 419 static int quad8_get_quadrature_mode(struct iio_dev *indio_dev,
 420         const struct iio_chan_spec *chan)
 421 {
 422         const struct quad8_iio *const priv = iio_priv(indio_dev);
 423
 424         return priv->quadrature_mode[chan->channel];
 425 }
 426
 427 static const struct iio_enum quad8_quadrature_mode_enum = {
 428         .items = quad8_quadrature_modes,
 429         .num_items = ARRAY_SIZE(quad8_quadrature_modes),
 430         .set = quad8_set_quadrature_mode,
 431         .get = quad8_get_quadrature_mode
 432 };
 433
 434 static const char *const quad8_index_polarity_modes[] = {
 435         "negative",
 436         "positive"
 437 };
 438
 439 static int quad8_set_index_polarity(struct iio_dev *indio_dev,
 440         const struct iio_chan_spec *chan, unsigned int index_polarity)
 441 {
 442         struct quad8_iio *const priv = iio_priv(indio_dev);
 443         const unsigned int idr_cfg = priv->synchronous_mode[chan->channel] |
 444                 index_polarity << 1;
 445         const int base_offset = priv->base + 2 * chan->channel + 1;
 446
 447         priv->index_polarity[chan->channel] = index_polarity;
 448
 449         /* Load Index Control configuration to Index Control Register */
 450         outb(0x60 | idr_cfg, base_offset);
 451
 452         return 0;
 453 }
 454
 455 static int quad8_get_index_polarity(struct iio_dev *indio_dev,
 456         const struct iio_chan_spec *chan)
 457 {
 458         const struct quad8_iio *const priv = iio_priv(indio_dev);
 459
 460         return priv->index_polarity[chan->channel];
 461 }
 462
 463 static const struct iio_enum quad8_index_polarity_enum = {
 464         .items = quad8_index_polarity_modes,
 465         .num_items = ARRAY_SIZE(quad8_index_polarity_modes),
 466         .set = quad8_set_index_polarity,
 467         .get = quad8_get_index_polarity
 468 };
 469
 470 static const struct iio_chan_spec_ext_info quad8_count_ext_info[] = {
 471         {
 472                 .name = "preset",
 473                 .shared = IIO_SEPARATE,
 474                 .read = quad8_read_preset,
 475                 .write = quad8_write_preset
 476         },
 477         {
 478                 .name = "set_to_preset_on_index",
 479                 .shared = IIO_SEPARATE,
 480                 .read = quad8_read_set_to_preset_on_index,
 481                 .write = quad8_write_set_to_preset_on_index
 482         },
 483         IIO_ENUM("noise_error", IIO_SEPARATE, &quad8_noise_error_enum),
 484         IIO_ENUM_AVAILABLE("noise_error", &quad8_noise_error_enum),
 485         IIO_ENUM("count_direction", IIO_SEPARATE, &quad8_count_direction_enum),
 486         IIO_ENUM_AVAILABLE("count_direction", &quad8_count_direction_enum),
 487         IIO_ENUM("count_mode", IIO_SEPARATE, &quad8_count_mode_enum),
 488         IIO_ENUM_AVAILABLE("count_mode", &quad8_count_mode_enum),
 489         IIO_ENUM("quadrature_mode", IIO_SEPARATE, &quad8_quadrature_mode_enum),
 490         IIO_ENUM_AVAILABLE("quadrature_mode", &quad8_quadrature_mode_enum),
 491         {}
 492 };
 493
 494 static const struct iio_chan_spec_ext_info quad8_index_ext_info[] = {
 495         IIO_ENUM("synchronous_mode", IIO_SEPARATE,
 496                 &quad8_synchronous_mode_enum),
 497         IIO_ENUM_AVAILABLE("synchronous_mode", &quad8_synchronous_mode_enum),
 498         IIO_ENUM("index_polarity", IIO_SEPARATE, &quad8_index_polarity_enum),
 499         IIO_ENUM_AVAILABLE("index_polarity", &quad8_index_polarity_enum),
 500         {}
 501 };
 502
 503 #define QUAD8_COUNT_CHAN(_chan) {                                       \
 504         .type = IIO_COUNT,                                              \
 505         .channel = (_chan),                                             \
 506         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |                  \
 507                 BIT(IIO_CHAN_INFO_ENABLE) | BIT(IIO_CHAN_INFO_SCALE),   \
 508         .ext_info = quad8_count_ext_info,                               \
 509         .indexed = 1                                                    \
 510 }
 511
 512 #define QUAD8_INDEX_CHAN(_chan) {                       \
 513         .type = IIO_INDEX,                              \
 514         .channel = (_chan),                             \
 515         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),   \
 516         .ext_info = quad8_index_ext_info,               \
 517         .indexed = 1                                    \
 518 }
 519
 520 static const struct iio_chan_spec quad8_channels[] = {
 521         QUAD8_COUNT_CHAN(0), QUAD8_INDEX_CHAN(0),
 522         QUAD8_COUNT_CHAN(1), QUAD8_INDEX_CHAN(1),
 523         QUAD8_COUNT_CHAN(2), QUAD8_INDEX_CHAN(2),
 524         QUAD8_COUNT_CHAN(3), QUAD8_INDEX_CHAN(3),
 525         QUAD8_COUNT_CHAN(4), QUAD8_INDEX_CHAN(4),
 526         QUAD8_COUNT_CHAN(5), QUAD8_INDEX_CHAN(5),
 527         QUAD8_COUNT_CHAN(6), QUAD8_INDEX_CHAN(6),
 528         QUAD8_COUNT_CHAN(7), QUAD8_INDEX_CHAN(7)
 529 };
 530
 531 static int quad8_probe(struct device *dev, unsigned int id)
 532 {
 533         struct iio_dev *indio_dev;
 534         struct quad8_iio *priv;
 535         int i, j;
 536         unsigned int base_offset;
 537
 538         indio_dev = devm_iio_device_alloc(dev, sizeof(*priv));
 539         if (!indio_dev)
 540                 return -ENOMEM;
 541
 542         if (!devm_request_region(dev, base[id], QUAD8_EXTENT,
 543                 dev_name(dev))) {
 544                 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
 545                         base[id], base[id] + QUAD8_EXTENT);
 546                 return -EBUSY;
 547         }
 548
 549         indio_dev->info = &quad8_info;
 550         indio_dev->modes = INDIO_DIRECT_MODE;
 551         indio_dev->num_channels = ARRAY_SIZE(quad8_channels);
 552         indio_dev->channels = quad8_channels;
 553         indio_dev->name = dev_name(dev);
 554         indio_dev->dev.parent = dev;
 555
 556         priv = iio_priv(indio_dev);
 557         priv->base = base[id];
 558
 559         /* Reset all counters and disable interrupt function */
 560         outb(0x01, base[id] + 0x11);
 561         /* Set initial configuration for all counters */
 562         for (i = 0; i < QUAD8_NUM_COUNTERS; i++) {
 563                 base_offset = base[id] + 2 * i;
 564                 /* Reset Byte Pointer */
 565                 outb(0x01, base_offset + 1);
 566                 /* Reset Preset Register */
 567                 for (j = 0; j < 3; j++)
 568                         outb(0x00, base_offset);
 569                 /* Reset Borrow, Carry, Compare, and Sign flags */
 570                 outb(0x04, base_offset + 1);
 571                 /* Reset Error flag */
 572                 outb(0x06, base_offset + 1);
 573                 /* Binary encoding; Normal count; non-quadrature mode */
 574                 outb(0x20, base_offset + 1);
 575                 /* Disable A and B inputs; preset on index; FLG1 as Carry */
 576                 outb(0x40, base_offset + 1);
 577                 /* Disable index function; negative index polarity */
 578                 outb(0x60, base_offset + 1);
 579         }
 580         /* Enable all counters */
 581         outb(0x00, base[id] + 0x11);
 582
 583         return devm_iio_device_register(dev, indio_dev);
 584 }
 585
 586 static struct isa_driver quad8_driver = {
 587         .probe = quad8_probe,
 588         .driver = {
 589                 .name = "104-quad-8"
 590         }
 591 };
 592
 593 module_isa_driver(quad8_driver, num_quad8);
 594
 595 MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
 596 MODULE_DESCRIPTION("ACCES 104-QUAD-8 IIO driver");
 597 MODULE_LICENSE("GPL v2");