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ipc: optimize semget/shmget/msgget for lots of keys
[linux/fpc-iii.git] / drivers / pinctrl / pinctrl-amd.c
blob38af1ec2df0c2b9c172915906f0a63864b65f1b5
1 /*
2 * GPIO driver for AMD
3 *
4 * Copyright (c) 2014,2015 AMD Corporation.
5 * Authors: Ken Xue <Ken.Xue@amd.com>
6 * Wu, Jeff <Jeff.Wu@amd.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * Contact Information: Nehal Shah <Nehal-bakulchandra.Shah@amd.com>
13 * Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
14 *
15 */
16
17 #include <linux/err.h>
18 #include <linux/bug.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/spinlock.h>
22 #include <linux/compiler.h>
23 #include <linux/types.h>
24 #include <linux/errno.h>
25 #include <linux/log2.h>
26 #include <linux/io.h>
27 #include <linux/gpio.h>
28 #include <linux/slab.h>
29 #include <linux/platform_device.h>
30 #include <linux/mutex.h>
31 #include <linux/acpi.h>
32 #include <linux/seq_file.h>
33 #include <linux/interrupt.h>
34 #include <linux/list.h>
35 #include <linux/bitops.h>
36 #include <linux/pinctrl/pinconf.h>
37 #include <linux/pinctrl/pinconf-generic.h>
38
39 #include "pinctrl-utils.h"
40 #include "pinctrl-amd.h"
41
42 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
43 {
44 unsigned long flags;
45 u32 pin_reg;
46 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
47
48 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
49 pin_reg = readl(gpio_dev->base + offset * 4);
50 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
51 writel(pin_reg, gpio_dev->base + offset * 4);
52 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
53
54 return 0;
55 }
56
57 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
58 int value)
59 {
60 u32 pin_reg;
61 unsigned long flags;
62 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
63
64 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
65 pin_reg = readl(gpio_dev->base + offset * 4);
66 pin_reg |= BIT(OUTPUT_ENABLE_OFF);
67 if (value)
68 pin_reg |= BIT(OUTPUT_VALUE_OFF);
69 else
70 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
71 writel(pin_reg, gpio_dev->base + offset * 4);
72 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
73
74 return 0;
75 }
76
77 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
78 {
79 u32 pin_reg;
80 unsigned long flags;
81 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
82
83 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
84 pin_reg = readl(gpio_dev->base + offset * 4);
85 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
86
87 return !!(pin_reg & BIT(PIN_STS_OFF));
88 }
89
90 static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
91 {
92 u32 pin_reg;
93 unsigned long flags;
94 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
95
96 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
97 pin_reg = readl(gpio_dev->base + offset * 4);
98 if (value)
99 pin_reg |= BIT(OUTPUT_VALUE_OFF);
100 else
101 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
102 writel(pin_reg, gpio_dev->base + offset * 4);
103 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
104 }
105
106 static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
107 unsigned debounce)
108 {
109 u32 time;
110 u32 pin_reg;
111 int ret = 0;
112 unsigned long flags;
113 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
114
115 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
116 pin_reg = readl(gpio_dev->base + offset * 4);
117
118 if (debounce) {
119 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
120 pin_reg &= ~DB_TMR_OUT_MASK;
121 /*
122 Debounce Debounce Timer Max
123 TmrLarge TmrOutUnit Unit Debounce
124 Time
125 0 0 61 usec (2 RtcClk) 976 usec
126 0 1 244 usec (8 RtcClk) 3.9 msec
127 1 0 15.6 msec (512 RtcClk) 250 msec
128 1 1 62.5 msec (2048 RtcClk) 1 sec
129 */
130
131 if (debounce < 61) {
132 pin_reg |= 1;
133 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
134 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
135 } else if (debounce < 976) {
136 time = debounce / 61;
137 pin_reg |= time & DB_TMR_OUT_MASK;
138 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
139 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
140 } else if (debounce < 3900) {
141 time = debounce / 244;
142 pin_reg |= time & DB_TMR_OUT_MASK;
143 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
144 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
145 } else if (debounce < 250000) {
146 time = debounce / 15600;
147 pin_reg |= time & DB_TMR_OUT_MASK;
148 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
149 pin_reg |= BIT(DB_TMR_LARGE_OFF);
150 } else if (debounce < 1000000) {
151 time = debounce / 62500;
152 pin_reg |= time & DB_TMR_OUT_MASK;
153 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
154 pin_reg |= BIT(DB_TMR_LARGE_OFF);
155 } else {
156 pin_reg &= ~DB_CNTRl_MASK;
157 ret = -EINVAL;
158 }
159 } else {
160 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
161 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
162 pin_reg &= ~DB_TMR_OUT_MASK;
163 pin_reg &= ~DB_CNTRl_MASK;
164 }
165 writel(pin_reg, gpio_dev->base + offset * 4);
166 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
167
168 return ret;
169 }
170
171 static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset,
172 unsigned long config)
173 {
174 u32 debounce;
175
176 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
177 return -ENOTSUPP;
178
179 debounce = pinconf_to_config_argument(config);
180 return amd_gpio_set_debounce(gc, offset, debounce);
181 }
182
183 #ifdef CONFIG_DEBUG_FS
184 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
185 {
186 u32 pin_reg;
187 unsigned long flags;
188 unsigned int bank, i, pin_num;
189 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
190
191 char *level_trig;
192 char *active_level;
193 char *interrupt_enable;
194 char *interrupt_mask;
195 char *wake_cntrl0;
196 char *wake_cntrl1;
197 char *wake_cntrl2;
198 char *pin_sts;
199 char *pull_up_sel;
200 char *pull_up_enable;
201 char *pull_down_enable;
202 char *output_value;
203 char *output_enable;
204
205 for (bank = 0; bank < gpio_dev->hwbank_num; bank++) {
206 seq_printf(s, "GPIO bank%d\t", bank);
207
208 switch (bank) {
209 case 0:
210 i = 0;
211 pin_num = AMD_GPIO_PINS_BANK0;
212 break;
213 case 1:
214 i = 64;
215 pin_num = AMD_GPIO_PINS_BANK1 + i;
216 break;
217 case 2:
218 i = 128;
219 pin_num = AMD_GPIO_PINS_BANK2 + i;
220 break;
221 case 3:
222 i = 192;
223 pin_num = AMD_GPIO_PINS_BANK3 + i;
224 break;
225 default:
226 /* Illegal bank number, ignore */
227 continue;
228 }
229 for (; i < pin_num; i++) {
230 seq_printf(s, "pin%d\t", i);
231 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
232 pin_reg = readl(gpio_dev->base + i * 4);
233 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
234
235 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
236 interrupt_enable = "interrupt is enabled|";
237
238 if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) &&
239 !(pin_reg & BIT(ACTIVE_LEVEL_OFF + 1)))
240 active_level = "Active low|";
241 else if (pin_reg & BIT(ACTIVE_LEVEL_OFF) &&
242 !(pin_reg & BIT(ACTIVE_LEVEL_OFF + 1)))
243 active_level = "Active high|";
244 else if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) &&
245 pin_reg & BIT(ACTIVE_LEVEL_OFF + 1))
246 active_level = "Active on both|";
247 else
248 active_level = "Unknown Active level|";
249
250 if (pin_reg & BIT(LEVEL_TRIG_OFF))
251 level_trig = "Level trigger|";
252 else
253 level_trig = "Edge trigger|";
254
255 } else {
256 interrupt_enable =
257 "interrupt is disabled|";
258 active_level = " ";
259 level_trig = " ";
260 }
261
262 if (pin_reg & BIT(INTERRUPT_MASK_OFF))
263 interrupt_mask =
264 "interrupt is unmasked|";
265 else
266 interrupt_mask =
267 "interrupt is masked|";
268
269 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3))
270 wake_cntrl0 = "enable wakeup in S0i3 state|";
271 else
272 wake_cntrl0 = "disable wakeup in S0i3 state|";
273
274 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3))
275 wake_cntrl1 = "enable wakeup in S3 state|";
276 else
277 wake_cntrl1 = "disable wakeup in S3 state|";
278
279 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4))
280 wake_cntrl2 = "enable wakeup in S4/S5 state|";
281 else
282 wake_cntrl2 = "disable wakeup in S4/S5 state|";
283
284 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
285 pull_up_enable = "pull-up is enabled|";
286 if (pin_reg & BIT(PULL_UP_SEL_OFF))
287 pull_up_sel = "8k pull-up|";
288 else
289 pull_up_sel = "4k pull-up|";
290 } else {
291 pull_up_enable = "pull-up is disabled|";
292 pull_up_sel = " ";
293 }
294
295 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF))
296 pull_down_enable = "pull-down is enabled|";
297 else
298 pull_down_enable = "Pull-down is disabled|";
299
300 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
301 pin_sts = " ";
302 output_enable = "output is enabled|";
303 if (pin_reg & BIT(OUTPUT_VALUE_OFF))
304 output_value = "output is high|";
305 else
306 output_value = "output is low|";
307 } else {
308 output_enable = "output is disabled|";
309 output_value = " ";
310
311 if (pin_reg & BIT(PIN_STS_OFF))
312 pin_sts = "input is high|";
313 else
314 pin_sts = "input is low|";
315 }
316
317 seq_printf(s, "%s %s %s %s %s %s\n"
318 " %s %s %s %s %s %s %s 0x%x\n",
319 level_trig, active_level, interrupt_enable,
320 interrupt_mask, wake_cntrl0, wake_cntrl1,
321 wake_cntrl2, pin_sts, pull_up_sel,
322 pull_up_enable, pull_down_enable,
323 output_value, output_enable, pin_reg);
324 }
325 }
326 }
327 #else
328 #define amd_gpio_dbg_show NULL
329 #endif
330
331 static void amd_gpio_irq_enable(struct irq_data *d)
332 {
333 u32 pin_reg;
334 unsigned long flags;
335 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
336 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
337
338 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
339 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
340 pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
341 pin_reg |= BIT(INTERRUPT_MASK_OFF);
342 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
343 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
344 }
345
346 static void amd_gpio_irq_disable(struct irq_data *d)
347 {
348 u32 pin_reg;
349 unsigned long flags;
350 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
351 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
352
353 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
354 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
355 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
356 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
357 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
358 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
359 }
360
361 static void amd_gpio_irq_mask(struct irq_data *d)
362 {
363 u32 pin_reg;
364 unsigned long flags;
365 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
366 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
367
368 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
369 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
370 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
371 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
372 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
373 }
374
375 static void amd_gpio_irq_unmask(struct irq_data *d)
376 {
377 u32 pin_reg;
378 unsigned long flags;
379 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
380 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
381
382 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
383 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
384 pin_reg |= BIT(INTERRUPT_MASK_OFF);
385 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
386 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
387 }
388
389 static void amd_gpio_irq_eoi(struct irq_data *d)
390 {
391 u32 reg;
392 unsigned long flags;
393 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
394 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
395
396 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
397 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
398 reg |= EOI_MASK;
399 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
400 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
401 }
402
403 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
404 {
405 int ret = 0;
406 u32 pin_reg;
407 unsigned long flags, irq_flags;
408 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
409 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
410
411 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
412 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
413
414 /* Ignore the settings coming from the client and
415 * read the values from the ACPI tables
416 * while setting the trigger type
417 */
418
419 irq_flags = irq_get_trigger_type(d->irq);
420 if (irq_flags != IRQ_TYPE_NONE)
421 type = irq_flags;
422
423 switch (type & IRQ_TYPE_SENSE_MASK) {
424 case IRQ_TYPE_EDGE_RISING:
425 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
426 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
427 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
428 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
429 irq_set_handler_locked(d, handle_edge_irq);
430 break;
431
432 case IRQ_TYPE_EDGE_FALLING:
433 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
434 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
435 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
436 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
437 irq_set_handler_locked(d, handle_edge_irq);
438 break;
439
440 case IRQ_TYPE_EDGE_BOTH:
441 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
442 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
443 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
444 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
445 irq_set_handler_locked(d, handle_edge_irq);
446 break;
447
448 case IRQ_TYPE_LEVEL_HIGH:
449 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
450 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
451 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
452 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
453 pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF;
454 irq_set_handler_locked(d, handle_level_irq);
455 break;
456
457 case IRQ_TYPE_LEVEL_LOW:
458 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
459 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
460 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
461 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
462 pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF;
463 irq_set_handler_locked(d, handle_level_irq);
464 break;
465
466 case IRQ_TYPE_NONE:
467 break;
468
469 default:
470 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n");
471 ret = -EINVAL;
472 }
473
474 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
475 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
476 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
477
478 return ret;
479 }
480
481 static void amd_irq_ack(struct irq_data *d)
482 {
483 /*
484 * based on HW design,there is no need to ack HW
485 * before handle current irq. But this routine is
486 * necessary for handle_edge_irq
487 */
488 }
489
490 static struct irq_chip amd_gpio_irqchip = {
491 .name = "amd_gpio",
492 .irq_ack = amd_irq_ack,
493 .irq_enable = amd_gpio_irq_enable,
494 .irq_disable = amd_gpio_irq_disable,
495 .irq_mask = amd_gpio_irq_mask,
496 .irq_unmask = amd_gpio_irq_unmask,
497 .irq_eoi = amd_gpio_irq_eoi,
498 .irq_set_type = amd_gpio_irq_set_type,
499 .flags = IRQCHIP_SKIP_SET_WAKE,
500 };
501
502 #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF))
503
504 static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id)
505 {
506 struct amd_gpio *gpio_dev = dev_id;
507 struct gpio_chip *gc = &gpio_dev->gc;
508 irqreturn_t ret = IRQ_NONE;
509 unsigned int i, irqnr;
510 unsigned long flags;
511 u32 *regs, regval;
512 u64 status, mask;
513
514 /* Read the wake status */
515 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
516 status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
517 status <<= 32;
518 status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
519 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
520
521 /* Bit 0-45 contain the relevant status bits */
522 status &= (1ULL << 46) - 1;
523 regs = gpio_dev->base;
524 for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) {
525 if (!(status & mask))
526 continue;
527 status &= ~mask;
528
529 /* Each status bit covers four pins */
530 for (i = 0; i < 4; i++) {
531 regval = readl(regs + i);
532 if (!(regval & PIN_IRQ_PENDING))
533 continue;
534 irq = irq_find_mapping(gc->irqdomain, irqnr + i);
535 generic_handle_irq(irq);
536 /* Clear interrupt */
537 writel(regval, regs + i);
538 ret = IRQ_HANDLED;
539 }
540 }
541
542 /* Signal EOI to the GPIO unit */
543 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
544 regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
545 regval |= EOI_MASK;
546 writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG);
547 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
548
549 return ret;
550 }
551
552 static int amd_get_groups_count(struct pinctrl_dev *pctldev)
553 {
554 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
555
556 return gpio_dev->ngroups;
557 }
558
559 static const char *amd_get_group_name(struct pinctrl_dev *pctldev,
560 unsigned group)
561 {
562 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
563
564 return gpio_dev->groups[group].name;
565 }
566
567 static int amd_get_group_pins(struct pinctrl_dev *pctldev,
568 unsigned group,
569 const unsigned **pins,
570 unsigned *num_pins)
571 {
572 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
573
574 *pins = gpio_dev->groups[group].pins;
575 *num_pins = gpio_dev->groups[group].npins;
576 return 0;
577 }
578
579 static const struct pinctrl_ops amd_pinctrl_ops = {
580 .get_groups_count = amd_get_groups_count,
581 .get_group_name = amd_get_group_name,
582 .get_group_pins = amd_get_group_pins,
583 #ifdef CONFIG_OF
584 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
585 .dt_free_map = pinctrl_utils_free_map,
586 #endif
587 };
588
589 static int amd_pinconf_get(struct pinctrl_dev *pctldev,
590 unsigned int pin,
591 unsigned long *config)
592 {
593 u32 pin_reg;
594 unsigned arg;
595 unsigned long flags;
596 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
597 enum pin_config_param param = pinconf_to_config_param(*config);
598
599 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
600 pin_reg = readl(gpio_dev->base + pin*4);
601 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
602 switch (param) {
603 case PIN_CONFIG_INPUT_DEBOUNCE:
604 arg = pin_reg & DB_TMR_OUT_MASK;
605 break;
606
607 case PIN_CONFIG_BIAS_PULL_DOWN:
608 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
609 break;
610
611 case PIN_CONFIG_BIAS_PULL_UP:
612 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1));
613 break;
614
615 case PIN_CONFIG_DRIVE_STRENGTH:
616 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
617 break;
618
619 default:
620 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
621 param);
622 return -ENOTSUPP;
623 }
624
625 *config = pinconf_to_config_packed(param, arg);
626
627 return 0;
628 }
629
630 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
631 unsigned long *configs, unsigned num_configs)
632 {
633 int i;
634 u32 arg;
635 int ret = 0;
636 u32 pin_reg;
637 unsigned long flags;
638 enum pin_config_param param;
639 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
640
641 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
642 for (i = 0; i < num_configs; i++) {
643 param = pinconf_to_config_param(configs[i]);
644 arg = pinconf_to_config_argument(configs[i]);
645 pin_reg = readl(gpio_dev->base + pin*4);
646
647 switch (param) {
648 case PIN_CONFIG_INPUT_DEBOUNCE:
649 pin_reg &= ~DB_TMR_OUT_MASK;
650 pin_reg |= arg & DB_TMR_OUT_MASK;
651 break;
652
653 case PIN_CONFIG_BIAS_PULL_DOWN:
654 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
655 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
656 break;
657
658 case PIN_CONFIG_BIAS_PULL_UP:
659 pin_reg &= ~BIT(PULL_UP_SEL_OFF);
660 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF;
661 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
662 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF;
663 break;
664
665 case PIN_CONFIG_DRIVE_STRENGTH:
666 pin_reg &= ~(DRV_STRENGTH_SEL_MASK
667 << DRV_STRENGTH_SEL_OFF);
668 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
669 << DRV_STRENGTH_SEL_OFF;
670 break;
671
672 default:
673 dev_err(&gpio_dev->pdev->dev,
674 "Invalid config param %04x\n", param);
675 ret = -ENOTSUPP;
676 }
677
678 writel(pin_reg, gpio_dev->base + pin*4);
679 }
680 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
681
682 return ret;
683 }
684
685 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev,
686 unsigned int group,
687 unsigned long *config)
688 {
689 const unsigned *pins;
690 unsigned npins;
691 int ret;
692
693 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
694 if (ret)
695 return ret;
696
697 if (amd_pinconf_get(pctldev, pins[0], config))
698 return -ENOTSUPP;
699
700 return 0;
701 }
702
703 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev,
704 unsigned group, unsigned long *configs,
705 unsigned num_configs)
706 {
707 const unsigned *pins;
708 unsigned npins;
709 int i, ret;
710
711 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
712 if (ret)
713 return ret;
714 for (i = 0; i < npins; i++) {
715 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs))
716 return -ENOTSUPP;
717 }
718 return 0;
719 }
720
721 static const struct pinconf_ops amd_pinconf_ops = {
722 .pin_config_get = amd_pinconf_get,
723 .pin_config_set = amd_pinconf_set,
724 .pin_config_group_get = amd_pinconf_group_get,
725 .pin_config_group_set = amd_pinconf_group_set,
726 };
727
728 static struct pinctrl_desc amd_pinctrl_desc = {
729 .pins = kerncz_pins,
730 .npins = ARRAY_SIZE(kerncz_pins),
731 .pctlops = &amd_pinctrl_ops,
732 .confops = &amd_pinconf_ops,
733 .owner = THIS_MODULE,
734 };
735
736 static int amd_gpio_probe(struct platform_device *pdev)
737 {
738 int ret = 0;
739 int irq_base;
740 struct resource *res;
741 struct amd_gpio *gpio_dev;
742
743 gpio_dev = devm_kzalloc(&pdev->dev,
744 sizeof(struct amd_gpio), GFP_KERNEL);
745 if (!gpio_dev)
746 return -ENOMEM;
747
748 raw_spin_lock_init(&gpio_dev->lock);
749
750 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
751 if (!res) {
752 dev_err(&pdev->dev, "Failed to get gpio io resource.\n");
753 return -EINVAL;
754 }
755
756 gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start,
757 resource_size(res));
758 if (!gpio_dev->base)
759 return -ENOMEM;
760
761 irq_base = platform_get_irq(pdev, 0);
762 if (irq_base < 0) {
763 dev_err(&pdev->dev, "Failed to get gpio IRQ: %d\n", irq_base);
764 return irq_base;
765 }
766
767 gpio_dev->pdev = pdev;
768 gpio_dev->gc.direction_input = amd_gpio_direction_input;
769 gpio_dev->gc.direction_output = amd_gpio_direction_output;
770 gpio_dev->gc.get = amd_gpio_get_value;
771 gpio_dev->gc.set = amd_gpio_set_value;
772 gpio_dev->gc.set_config = amd_gpio_set_config;
773 gpio_dev->gc.dbg_show = amd_gpio_dbg_show;
774
775 gpio_dev->gc.base = -1;
776 gpio_dev->gc.label = pdev->name;
777 gpio_dev->gc.owner = THIS_MODULE;
778 gpio_dev->gc.parent = &pdev->dev;
779 gpio_dev->gc.ngpio = resource_size(res) / 4;
780 #if defined(CONFIG_OF_GPIO)
781 gpio_dev->gc.of_node = pdev->dev.of_node;
782 #endif
783
784 gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64;
785 gpio_dev->groups = kerncz_groups;
786 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
787
788 amd_pinctrl_desc.name = dev_name(&pdev->dev);
789 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc,
790 gpio_dev);
791 if (IS_ERR(gpio_dev->pctrl)) {
792 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
793 return PTR_ERR(gpio_dev->pctrl);
794 }
795
796 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev);
797 if (ret)
798 return ret;
799
800 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev),
801 0, 0, gpio_dev->gc.ngpio);
802 if (ret) {
803 dev_err(&pdev->dev, "Failed to add pin range\n");
804 goto out2;
805 }
806
807 ret = gpiochip_irqchip_add(&gpio_dev->gc,
808 &amd_gpio_irqchip,
809 0,
810 handle_simple_irq,
811 IRQ_TYPE_NONE);
812 if (ret) {
813 dev_err(&pdev->dev, "could not add irqchip\n");
814 ret = -ENODEV;
815 goto out2;
816 }
817
818 ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler, 0,
819 KBUILD_MODNAME, gpio_dev);
820 if (ret)
821 goto out2;
822
823 platform_set_drvdata(pdev, gpio_dev);
824
825 dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
826 return ret;
827
828 out2:
829 gpiochip_remove(&gpio_dev->gc);
830
831 return ret;
832 }
833
834 static int amd_gpio_remove(struct platform_device *pdev)
835 {
836 struct amd_gpio *gpio_dev;
837
838 gpio_dev = platform_get_drvdata(pdev);
839
840 gpiochip_remove(&gpio_dev->gc);
841
842 return 0;
843 }
844
845 static const struct acpi_device_id amd_gpio_acpi_match[] = {
846 { "AMD0030", 0 },
847 { "AMDI0030", 0},
848 { },
849 };
850 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
851
852 static struct platform_driver amd_gpio_driver = {
853 .driver = {
854 .name = "amd_gpio",
855 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match),
856 },
857 .probe = amd_gpio_probe,
858 .remove = amd_gpio_remove,
859 };
860
861 module_platform_driver(amd_gpio_driver);
862
863 MODULE_LICENSE("GPL v2");
864 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>");
865 MODULE_DESCRIPTION("AMD GPIO pinctrl driver");
Linux with added FPC-III support