1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/kernel/xscale-cp0.c
5 * XScale DSP and iWMMXt coprocessor context switching and handling
8 #include <linux/types.h>
9 #include <linux/kernel.h>
10 #include <linux/signal.h>
11 #include <linux/sched.h>
12 #include <linux/init.h>
14 #include <asm/thread_notify.h>
15 #include <asm/cputype.h>
17 asm(" .arch armv5te\n");
19 static inline void dsp_save_state(u32
*state
)
21 __asm__
__volatile__ (
22 "mrrc p0, 0, %0, %1, c0\n"
23 : "=r" (state
[0]), "=r" (state
[1]));
26 static inline void dsp_load_state(u32
*state
)
28 __asm__
__volatile__ (
29 "mcrr p0, 0, %0, %1, c0\n"
30 : : "r" (state
[0]), "r" (state
[1]));
33 static int dsp_do(struct notifier_block
*self
, unsigned long cmd
, void *t
)
35 struct thread_info
*thread
= t
;
38 case THREAD_NOTIFY_FLUSH
:
39 thread
->cpu_context
.extra
[0] = 0;
40 thread
->cpu_context
.extra
[1] = 0;
43 case THREAD_NOTIFY_SWITCH
:
44 dsp_save_state(current_thread_info()->cpu_context
.extra
);
45 dsp_load_state(thread
->cpu_context
.extra
);
52 static struct notifier_block dsp_notifier_block
= {
53 .notifier_call
= dsp_do
,
58 static int iwmmxt_do(struct notifier_block
*self
, unsigned long cmd
, void *t
)
60 struct thread_info
*thread
= t
;
63 case THREAD_NOTIFY_FLUSH
:
65 * flush_thread() zeroes thread->fpstate, so no need
66 * to do anything here.
68 * FALLTHROUGH: Ensure we don't try to overwrite our newly
69 * initialised state information on the first fault.
72 case THREAD_NOTIFY_EXIT
:
73 iwmmxt_task_release(thread
);
76 case THREAD_NOTIFY_SWITCH
:
77 iwmmxt_task_switch(thread
);
84 static struct notifier_block iwmmxt_notifier_block
= {
85 .notifier_call
= iwmmxt_do
,
90 static u32 __init
xscale_cp_access_read(void)
94 __asm__
__volatile__ (
95 "mrc p15, 0, %0, c15, c1, 0\n\t"
101 static void __init
xscale_cp_access_write(u32 value
)
105 __asm__
__volatile__ (
106 "mcr p15, 0, %1, c15, c1, 0\n\t"
107 "mrc p15, 0, %0, c15, c1, 0\n\t"
110 : "=r" (temp
) : "r" (value
));
114 * Detect whether we have a MAC coprocessor (40 bit register) or an
115 * iWMMXt coprocessor (64 bit registers) by loading 00000100:00000000
116 * into a coprocessor register and reading it back, and checking
117 * whether the upper word survived intact.
119 static int __init
cpu_has_iwmmxt(void)
125 * This sequence is interpreted by the DSP coprocessor as:
129 * And by the iWMMXt coprocessor as:
133 __asm__
__volatile__ (
134 "mcrr p0, 0, %2, %3, c0\n"
135 "mrrc p0, 0, %0, %1, c0\n"
136 : "=r" (lo
), "=r" (hi
)
137 : "r" (0), "r" (0x100));
144 * If we detect that the CPU has iWMMXt (and CONFIG_IWMMXT=y), we
145 * disable CP0/CP1 on boot, and let call_fpe() and the iWMMXt lazy
146 * switch code handle iWMMXt context switching. If on the other
147 * hand the CPU has a DSP coprocessor, we keep access to CP0 enabled
148 * all the time, and save/restore acc0 on context switch in non-lazy
151 static int __init
xscale_cp0_init(void)
155 /* do not attempt to probe iwmmxt on non-xscale family CPUs */
156 if (!cpu_is_xscale_family())
159 cp_access
= xscale_cp_access_read() & ~3;
160 xscale_cp_access_write(cp_access
| 1);
162 if (cpu_has_iwmmxt()) {
163 #ifndef CONFIG_IWMMXT
164 pr_warn("CAUTION: XScale iWMMXt coprocessor detected, but kernel support is missing.\n");
166 pr_info("XScale iWMMXt coprocessor detected.\n");
167 elf_hwcap
|= HWCAP_IWMMXT
;
168 thread_register_notifier(&iwmmxt_notifier_block
);
171 pr_info("XScale DSP coprocessor detected.\n");
172 thread_register_notifier(&dsp_notifier_block
);
176 xscale_cp_access_write(cp_access
);
181 late_initcall(xscale_cp0_init
);