1 // SPDX-License-Identifier: GPL-2.0
3 * arch/arm/mach-ixp4xx/ixdp425-setup.c
5 * IXDP425/IXCDP1100 board-setup
7 * Copyright (C) 2003-2005 MontaVista Software, Inc.
9 * Author: Deepak Saxena <dsaxena@plexity.net>
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/device.h>
15 #include <linux/serial.h>
16 #include <linux/tty.h>
17 #include <linux/serial_8250.h>
18 #include <linux/gpio/machine.h>
20 #include <linux/mtd/mtd.h>
21 #include <linux/mtd/rawnand.h>
22 #include <linux/mtd/partitions.h>
23 #include <linux/mtd/platnand.h>
24 #include <linux/delay.h>
25 #include <linux/gpio.h>
26 #include <asm/types.h>
27 #include <asm/setup.h>
28 #include <asm/memory.h>
29 #include <mach/hardware.h>
30 #include <asm/mach-types.h>
32 #include <asm/mach/arch.h>
33 #include <asm/mach/flash.h>
37 #define IXDP425_SDA_PIN 7
38 #define IXDP425_SCL_PIN 6
41 #define IXDP425_NAND_NCE_PIN 12
43 #define IXDP425_NAND_CMD_BYTE 0x01
44 #define IXDP425_NAND_ADDR_BYTE 0x02
46 static struct flash_platform_data ixdp425_flash_data
= {
47 .map_name
= "cfi_probe",
51 static struct resource ixdp425_flash_resource
= {
52 .flags
= IORESOURCE_MEM
,
55 static struct platform_device ixdp425_flash
= {
56 .name
= "IXP4XX-Flash",
59 .platform_data
= &ixdp425_flash_data
,
62 .resource
= &ixdp425_flash_resource
,
65 #if defined(CONFIG_MTD_NAND_PLATFORM) || \
66 defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
68 static struct mtd_partition ixdp425_partitions
[] = {
70 .name
= "ixp400 NAND FS 0",
74 .name
= "ixp400 NAND FS 1",
75 .offset
= MTDPART_OFS_APPEND
,
76 .size
= MTDPART_SIZ_FULL
81 ixdp425_flash_nand_cmd_ctrl(struct nand_chip
*this, int cmd
, unsigned int ctrl
)
83 int offset
= (int)nand_get_controller_data(this);
85 if (ctrl
& NAND_CTRL_CHANGE
) {
86 if (ctrl
& NAND_NCE
) {
87 gpio_set_value(IXDP425_NAND_NCE_PIN
, 0);
90 gpio_set_value(IXDP425_NAND_NCE_PIN
, 1);
92 offset
= (ctrl
& NAND_CLE
) ? IXDP425_NAND_CMD_BYTE
: 0;
93 offset
|= (ctrl
& NAND_ALE
) ? IXDP425_NAND_ADDR_BYTE
: 0;
94 nand_set_controller_data(this, (void *)offset
);
97 if (cmd
!= NAND_CMD_NONE
)
98 writeb(cmd
, this->legacy
.IO_ADDR_W
+ offset
);
101 static struct platform_nand_data ixdp425_flash_nand_data
= {
105 .partitions
= ixdp425_partitions
,
106 .nr_partitions
= ARRAY_SIZE(ixdp425_partitions
),
109 .cmd_ctrl
= ixdp425_flash_nand_cmd_ctrl
113 static struct resource ixdp425_flash_nand_resource
= {
114 .flags
= IORESOURCE_MEM
,
117 static struct platform_device ixdp425_flash_nand
= {
121 .platform_data
= &ixdp425_flash_nand_data
,
124 .resource
= &ixdp425_flash_nand_resource
,
126 #endif /* CONFIG_MTD_NAND_PLATFORM */
128 static struct gpiod_lookup_table ixdp425_i2c_gpiod_table
= {
129 .dev_id
= "i2c-gpio.0",
131 GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", IXDP425_SDA_PIN
,
132 NULL
, 0, GPIO_ACTIVE_HIGH
| GPIO_OPEN_DRAIN
),
133 GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", IXDP425_SCL_PIN
,
134 NULL
, 1, GPIO_ACTIVE_HIGH
| GPIO_OPEN_DRAIN
),
138 static struct platform_device ixdp425_i2c_gpio
= {
142 .platform_data
= NULL
,
146 static struct resource ixdp425_uart_resources
[] = {
148 .start
= IXP4XX_UART1_BASE_PHYS
,
149 .end
= IXP4XX_UART1_BASE_PHYS
+ 0x0fff,
150 .flags
= IORESOURCE_MEM
153 .start
= IXP4XX_UART2_BASE_PHYS
,
154 .end
= IXP4XX_UART2_BASE_PHYS
+ 0x0fff,
155 .flags
= IORESOURCE_MEM
159 static struct plat_serial8250_port ixdp425_uart_data
[] = {
161 .mapbase
= IXP4XX_UART1_BASE_PHYS
,
162 .membase
= (char *)IXP4XX_UART1_BASE_VIRT
+ REG_OFFSET
,
163 .irq
= IRQ_IXP4XX_UART1
,
164 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
,
167 .uartclk
= IXP4XX_UART_XTAL
,
170 .mapbase
= IXP4XX_UART2_BASE_PHYS
,
171 .membase
= (char *)IXP4XX_UART2_BASE_VIRT
+ REG_OFFSET
,
172 .irq
= IRQ_IXP4XX_UART2
,
173 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
,
176 .uartclk
= IXP4XX_UART_XTAL
,
181 static struct platform_device ixdp425_uart
= {
182 .name
= "serial8250",
183 .id
= PLAT8250_DEV_PLATFORM
,
184 .dev
.platform_data
= ixdp425_uart_data
,
186 .resource
= ixdp425_uart_resources
189 /* Built-in 10/100 Ethernet MAC interfaces */
190 static struct resource ixp425_npeb_resources
[] = {
192 .start
= IXP4XX_EthB_BASE_PHYS
,
193 .end
= IXP4XX_EthB_BASE_PHYS
+ 0x0fff,
194 .flags
= IORESOURCE_MEM
,
198 static struct resource ixp425_npec_resources
[] = {
200 .start
= IXP4XX_EthC_BASE_PHYS
,
201 .end
= IXP4XX_EthC_BASE_PHYS
+ 0x0fff,
202 .flags
= IORESOURCE_MEM
,
206 static struct eth_plat_info ixdp425_plat_eth
[] = {
218 static struct platform_device ixdp425_eth
[] = {
220 .name
= "ixp4xx_eth",
221 .id
= IXP4XX_ETH_NPEB
,
222 .dev
.platform_data
= ixdp425_plat_eth
,
223 .num_resources
= ARRAY_SIZE(ixp425_npeb_resources
),
224 .resource
= ixp425_npeb_resources
,
226 .name
= "ixp4xx_eth",
227 .id
= IXP4XX_ETH_NPEC
,
228 .dev
.platform_data
= ixdp425_plat_eth
+ 1,
229 .num_resources
= ARRAY_SIZE(ixp425_npec_resources
),
230 .resource
= ixp425_npec_resources
,
234 static struct platform_device
*ixdp425_devices
[] __initdata
= {
237 #if defined(CONFIG_MTD_NAND_PLATFORM) || \
238 defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
246 static void __init
ixdp425_init(void)
250 ixdp425_flash_resource
.start
= IXP4XX_EXP_BUS_BASE(0);
251 ixdp425_flash_resource
.end
=
252 IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size
- 1;
254 #if defined(CONFIG_MTD_NAND_PLATFORM) || \
255 defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
256 ixdp425_flash_nand_resource
.start
= IXP4XX_EXP_BUS_BASE(3),
257 ixdp425_flash_nand_resource
.end
= IXP4XX_EXP_BUS_BASE(3) + 0x10 - 1;
259 gpio_request(IXDP425_NAND_NCE_PIN
, "NAND NCE pin");
260 gpio_direction_output(IXDP425_NAND_NCE_PIN
, 0);
262 /* Configure expansion bus for NAND Flash */
263 *IXP4XX_EXP_CS3
= IXP4XX_EXP_BUS_CS_EN
|
264 IXP4XX_EXP_BUS_STROBE_T(1) | /* extend by 1 clock */
265 IXP4XX_EXP_BUS_CYCLES(0) | /* Intel cycles */
266 IXP4XX_EXP_BUS_SIZE(0) | /* 512bytes addr space*/
267 IXP4XX_EXP_BUS_WR_EN
|
268 IXP4XX_EXP_BUS_BYTE_EN
; /* 8 bit data bus */
271 if (cpu_is_ixp43x()) {
272 ixdp425_uart
.num_resources
= 1;
273 ixdp425_uart_data
[1].flags
= 0;
276 gpiod_add_lookup_table(&ixdp425_i2c_gpiod_table
);
277 platform_add_devices(ixdp425_devices
, ARRAY_SIZE(ixdp425_devices
));
280 #ifdef CONFIG_ARCH_IXDP425
281 MACHINE_START(IXDP425
, "Intel IXDP425 Development Platform")
282 /* Maintainer: MontaVista Software, Inc. */
283 .map_io
= ixp4xx_map_io
,
284 .init_early
= ixp4xx_init_early
,
285 .init_irq
= ixp4xx_init_irq
,
286 .init_time
= ixp4xx_timer_init
,
287 .atag_offset
= 0x100,
288 .init_machine
= ixdp425_init
,
289 #if defined(CONFIG_PCI)
290 .dma_zone_size
= SZ_64M
,
292 .restart
= ixp4xx_restart
,
296 #ifdef CONFIG_MACH_IXDP465
297 MACHINE_START(IXDP465
, "Intel IXDP465 Development Platform")
298 /* Maintainer: MontaVista Software, Inc. */
299 .map_io
= ixp4xx_map_io
,
300 .init_early
= ixp4xx_init_early
,
301 .init_irq
= ixp4xx_init_irq
,
302 .init_time
= ixp4xx_timer_init
,
303 .atag_offset
= 0x100,
304 .init_machine
= ixdp425_init
,
305 #if defined(CONFIG_PCI)
306 .dma_zone_size
= SZ_64M
,
311 #ifdef CONFIG_ARCH_PRPMC1100
312 MACHINE_START(IXCDP1100
, "Intel IXCDP1100 Development Platform")
313 /* Maintainer: MontaVista Software, Inc. */
314 .map_io
= ixp4xx_map_io
,
315 .init_early
= ixp4xx_init_early
,
316 .init_irq
= ixp4xx_init_irq
,
317 .init_time
= ixp4xx_timer_init
,
318 .atag_offset
= 0x100,
319 .init_machine
= ixdp425_init
,
320 #if defined(CONFIG_PCI)
321 .dma_zone_size
= SZ_64M
,
326 #ifdef CONFIG_MACH_KIXRP435
327 MACHINE_START(KIXRP435
, "Intel KIXRP435 Reference Platform")
328 /* Maintainer: MontaVista Software, Inc. */
329 .map_io
= ixp4xx_map_io
,
330 .init_early
= ixp4xx_init_early
,
331 .init_irq
= ixp4xx_init_irq
,
332 .init_time
= ixp4xx_timer_init
,
333 .atag_offset
= 0x100,
334 .init_machine
= ixdp425_init
,
335 #if defined(CONFIG_PCI)
336 .dma_zone_size
= SZ_64M
,