arm64: dts: Revert "specify console via command line"
[linux/fpc-iii.git] / arch / arm / mach-meson / platsmp.c
blob4b8ad728bb42aa68b852e3dfee0b1c656e388426
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2015 Carlo Caione <carlo@endlessm.com>
4 * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
5 */
7 #include <linux/delay.h>
8 #include <linux/init.h>
9 #include <linux/io.h>
10 #include <linux/of.h>
11 #include <linux/of_address.h>
12 #include <linux/regmap.h>
13 #include <linux/reset.h>
14 #include <linux/smp.h>
15 #include <linux/mfd/syscon.h>
17 #include <asm/cacheflush.h>
18 #include <asm/cp15.h>
19 #include <asm/smp_scu.h>
20 #include <asm/smp_plat.h>
22 #define MESON_SMP_SRAM_CPU_CTRL_REG (0x00)
23 #define MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(c) (0x04 + ((c - 1) << 2))
25 #define MESON_CPU_AO_RTI_PWR_A9_CNTL0 (0x00)
26 #define MESON_CPU_AO_RTI_PWR_A9_CNTL1 (0x04)
27 #define MESON_CPU_AO_RTI_PWR_A9_MEM_PD0 (0x14)
29 #define MESON_CPU_PWR_A9_CNTL0_M(c) (0x03 << ((c * 2) + 16))
30 #define MESON_CPU_PWR_A9_CNTL1_M(c) (0x03 << ((c + 1) << 1))
31 #define MESON_CPU_PWR_A9_MEM_PD0_M(c) (0x0f << (32 - (c * 4)))
32 #define MESON_CPU_PWR_A9_CNTL1_ST(c) (0x01 << (c + 16))
34 static void __iomem *sram_base;
35 static void __iomem *scu_base;
36 static struct regmap *pmu;
38 static struct reset_control *meson_smp_get_core_reset(int cpu)
40 struct device_node *np = of_get_cpu_node(cpu, 0);
42 return of_reset_control_get_exclusive(np, NULL);
45 static void meson_smp_set_cpu_ctrl(int cpu, bool on_off)
47 u32 val = readl(sram_base + MESON_SMP_SRAM_CPU_CTRL_REG);
49 if (on_off)
50 val |= BIT(cpu);
51 else
52 val &= ~BIT(cpu);
54 /* keep bit 0 always enabled */
55 val |= BIT(0);
57 writel(val, sram_base + MESON_SMP_SRAM_CPU_CTRL_REG);
60 static void __init meson_smp_prepare_cpus(const char *scu_compatible,
61 const char *pmu_compatible,
62 const char *sram_compatible)
64 static struct device_node *node;
66 /* SMP SRAM */
67 node = of_find_compatible_node(NULL, NULL, sram_compatible);
68 if (!node) {
69 pr_err("Missing SRAM node\n");
70 return;
73 sram_base = of_iomap(node, 0);
74 if (!sram_base) {
75 pr_err("Couldn't map SRAM registers\n");
76 return;
79 /* PMU */
80 pmu = syscon_regmap_lookup_by_compatible(pmu_compatible);
81 if (IS_ERR(pmu)) {
82 pr_err("Couldn't map PMU registers\n");
83 return;
86 /* SCU */
87 node = of_find_compatible_node(NULL, NULL, scu_compatible);
88 if (!node) {
89 pr_err("Missing SCU node\n");
90 return;
93 scu_base = of_iomap(node, 0);
94 if (!scu_base) {
95 pr_err("Couldn't map SCU registers\n");
96 return;
99 scu_enable(scu_base);
102 static void __init meson8b_smp_prepare_cpus(unsigned int max_cpus)
104 meson_smp_prepare_cpus("arm,cortex-a5-scu", "amlogic,meson8b-pmu",
105 "amlogic,meson8b-smp-sram");
108 static void __init meson8_smp_prepare_cpus(unsigned int max_cpus)
110 meson_smp_prepare_cpus("arm,cortex-a9-scu", "amlogic,meson8-pmu",
111 "amlogic,meson8-smp-sram");
114 static void meson_smp_begin_secondary_boot(unsigned int cpu)
117 * Set the entry point before powering on the CPU through the SCU. This
118 * is needed if the CPU is in "warm" state (= after rebooting the
119 * system without power-cycling, or when taking the CPU offline and
120 * then taking it online again.
122 writel(__pa_symbol(secondary_startup),
123 sram_base + MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(cpu));
126 * SCU Power on CPU (needs to be done before starting the CPU,
127 * otherwise the secondary CPU will not start).
129 scu_cpu_power_enable(scu_base, cpu);
132 static int meson_smp_finalize_secondary_boot(unsigned int cpu)
134 unsigned long timeout;
136 timeout = jiffies + (10 * HZ);
137 while (readl(sram_base + MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(cpu))) {
138 if (!time_before(jiffies, timeout)) {
139 pr_err("Timeout while waiting for CPU%d status\n",
140 cpu);
141 return -ETIMEDOUT;
145 writel(__pa_symbol(secondary_startup),
146 sram_base + MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(cpu));
148 meson_smp_set_cpu_ctrl(cpu, true);
150 return 0;
153 static int meson8_smp_boot_secondary(unsigned int cpu,
154 struct task_struct *idle)
156 struct reset_control *rstc;
157 int ret;
159 rstc = meson_smp_get_core_reset(cpu);
160 if (IS_ERR(rstc)) {
161 pr_err("Couldn't get the reset controller for CPU%d\n", cpu);
162 return PTR_ERR(rstc);
165 meson_smp_begin_secondary_boot(cpu);
167 /* Reset enable */
168 ret = reset_control_assert(rstc);
169 if (ret) {
170 pr_err("Failed to assert CPU%d reset\n", cpu);
171 goto out;
174 /* CPU power ON */
175 ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1,
176 MESON_CPU_PWR_A9_CNTL1_M(cpu), 0);
177 if (ret < 0) {
178 pr_err("Couldn't wake up CPU%d\n", cpu);
179 goto out;
182 udelay(10);
184 /* Isolation disable */
185 ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu),
187 if (ret < 0) {
188 pr_err("Error when disabling isolation of CPU%d\n", cpu);
189 goto out;
192 /* Reset disable */
193 ret = reset_control_deassert(rstc);
194 if (ret) {
195 pr_err("Failed to de-assert CPU%d reset\n", cpu);
196 goto out;
199 ret = meson_smp_finalize_secondary_boot(cpu);
200 if (ret)
201 goto out;
203 out:
204 reset_control_put(rstc);
206 return 0;
209 static int meson8b_smp_boot_secondary(unsigned int cpu,
210 struct task_struct *idle)
212 struct reset_control *rstc;
213 int ret;
214 u32 val;
216 rstc = meson_smp_get_core_reset(cpu);
217 if (IS_ERR(rstc)) {
218 pr_err("Couldn't get the reset controller for CPU%d\n", cpu);
219 return PTR_ERR(rstc);
222 meson_smp_begin_secondary_boot(cpu);
224 /* CPU power UP */
225 ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0,
226 MESON_CPU_PWR_A9_CNTL0_M(cpu), 0);
227 if (ret < 0) {
228 pr_err("Couldn't power up CPU%d\n", cpu);
229 goto out;
232 udelay(5);
234 /* Reset enable */
235 ret = reset_control_assert(rstc);
236 if (ret) {
237 pr_err("Failed to assert CPU%d reset\n", cpu);
238 goto out;
241 /* Memory power UP */
242 ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_MEM_PD0,
243 MESON_CPU_PWR_A9_MEM_PD0_M(cpu), 0);
244 if (ret < 0) {
245 pr_err("Couldn't power up the memory for CPU%d\n", cpu);
246 goto out;
249 /* Wake up CPU */
250 ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1,
251 MESON_CPU_PWR_A9_CNTL1_M(cpu), 0);
252 if (ret < 0) {
253 pr_err("Couldn't wake up CPU%d\n", cpu);
254 goto out;
257 udelay(10);
259 ret = regmap_read_poll_timeout(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1, val,
260 val & MESON_CPU_PWR_A9_CNTL1_ST(cpu),
261 10, 10000);
262 if (ret) {
263 pr_err("Timeout while polling PMU for CPU%d status\n", cpu);
264 goto out;
267 /* Isolation disable */
268 ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu),
270 if (ret < 0) {
271 pr_err("Error when disabling isolation of CPU%d\n", cpu);
272 goto out;
275 /* Reset disable */
276 ret = reset_control_deassert(rstc);
277 if (ret) {
278 pr_err("Failed to de-assert CPU%d reset\n", cpu);
279 goto out;
282 ret = meson_smp_finalize_secondary_boot(cpu);
283 if (ret)
284 goto out;
286 out:
287 reset_control_put(rstc);
289 return 0;
292 #ifdef CONFIG_HOTPLUG_CPU
293 static void meson8_smp_cpu_die(unsigned int cpu)
295 meson_smp_set_cpu_ctrl(cpu, false);
297 v7_exit_coherency_flush(louis);
299 scu_power_mode(scu_base, SCU_PM_POWEROFF);
301 dsb();
302 wfi();
304 /* we should never get here */
305 WARN_ON(1);
308 static int meson8_smp_cpu_kill(unsigned int cpu)
310 int ret, power_mode;
311 unsigned long timeout;
313 timeout = jiffies + (50 * HZ);
314 do {
315 power_mode = scu_get_cpu_power_mode(scu_base, cpu);
317 if (power_mode == SCU_PM_POWEROFF)
318 break;
320 usleep_range(10000, 15000);
321 } while (time_before(jiffies, timeout));
323 if (power_mode != SCU_PM_POWEROFF) {
324 pr_err("Error while waiting for SCU power-off on CPU%d\n",
325 cpu);
326 return -ETIMEDOUT;
329 msleep(30);
331 /* Isolation enable */
332 ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu),
333 0x3);
334 if (ret < 0) {
335 pr_err("Error when enabling isolation for CPU%d\n", cpu);
336 return ret;
339 udelay(10);
341 /* CPU power OFF */
342 ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1,
343 MESON_CPU_PWR_A9_CNTL1_M(cpu), 0x3);
344 if (ret < 0) {
345 pr_err("Couldn't change sleep status of CPU%d\n", cpu);
346 return ret;
349 return 1;
352 static int meson8b_smp_cpu_kill(unsigned int cpu)
354 int ret, power_mode, count = 5000;
356 do {
357 power_mode = scu_get_cpu_power_mode(scu_base, cpu);
359 if (power_mode == SCU_PM_POWEROFF)
360 break;
362 udelay(10);
363 } while (++count);
365 if (power_mode != SCU_PM_POWEROFF) {
366 pr_err("Error while waiting for SCU power-off on CPU%d\n",
367 cpu);
368 return -ETIMEDOUT;
371 udelay(10);
373 /* CPU power DOWN */
374 ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0,
375 MESON_CPU_PWR_A9_CNTL0_M(cpu), 0x3);
376 if (ret < 0) {
377 pr_err("Couldn't power down CPU%d\n", cpu);
378 return ret;
381 /* Isolation enable */
382 ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu),
383 0x3);
384 if (ret < 0) {
385 pr_err("Error when enabling isolation for CPU%d\n", cpu);
386 return ret;
389 udelay(10);
391 /* Sleep status */
392 ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1,
393 MESON_CPU_PWR_A9_CNTL1_M(cpu), 0x3);
394 if (ret < 0) {
395 pr_err("Couldn't change sleep status of CPU%d\n", cpu);
396 return ret;
399 /* Memory power DOWN */
400 ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_MEM_PD0,
401 MESON_CPU_PWR_A9_MEM_PD0_M(cpu), 0xf);
402 if (ret < 0) {
403 pr_err("Couldn't power down the memory of CPU%d\n", cpu);
404 return ret;
407 return 1;
409 #endif
411 static struct smp_operations meson8_smp_ops __initdata = {
412 .smp_prepare_cpus = meson8_smp_prepare_cpus,
413 .smp_boot_secondary = meson8_smp_boot_secondary,
414 #ifdef CONFIG_HOTPLUG_CPU
415 .cpu_die = meson8_smp_cpu_die,
416 .cpu_kill = meson8_smp_cpu_kill,
417 #endif
420 static struct smp_operations meson8b_smp_ops __initdata = {
421 .smp_prepare_cpus = meson8b_smp_prepare_cpus,
422 .smp_boot_secondary = meson8b_smp_boot_secondary,
423 #ifdef CONFIG_HOTPLUG_CPU
424 .cpu_die = meson8_smp_cpu_die,
425 .cpu_kill = meson8b_smp_cpu_kill,
426 #endif
429 CPU_METHOD_OF_DECLARE(meson8_smp, "amlogic,meson8-smp", &meson8_smp_ops);
430 CPU_METHOD_OF_DECLARE(meson8b_smp, "amlogic,meson8b-smp", &meson8b_smp_ops);