1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * linux/arch/arm/mach-omap1/mux.c
5 * OMAP1 pin multiplexing configurations
7 * Copyright (C) 2003 - 2008 Nokia Corporation
9 * Written by Tony Lindgren
11 #include <linux/module.h>
12 #include <linux/init.h>
14 #include <linux/spinlock.h>
16 #include <mach/hardware.h>
20 #ifdef CONFIG_OMAP_MUX
22 static struct omap_mux_cfg arch_mux_cfg
;
24 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
25 static struct pin_config omap7xx_pins
[] = {
26 MUX_CFG_7XX("E2_7XX_KBR0", 12, 21, 0, 20, 1, 0)
27 MUX_CFG_7XX("J7_7XX_KBR1", 12, 25, 0, 24, 1, 0)
28 MUX_CFG_7XX("E1_7XX_KBR2", 12, 29, 0, 28, 1, 0)
29 MUX_CFG_7XX("F3_7XX_KBR3", 13, 1, 0, 0, 1, 0)
30 MUX_CFG_7XX("D2_7XX_KBR4", 13, 5, 0, 4, 1, 0)
31 MUX_CFG_7XX("C2_7XX_KBC0", 13, 9, 0, 8, 1, 0)
32 MUX_CFG_7XX("D3_7XX_KBC1", 13, 13, 0, 12, 1, 0)
33 MUX_CFG_7XX("E4_7XX_KBC2", 13, 17, 0, 16, 1, 0)
34 MUX_CFG_7XX("F4_7XX_KBC3", 13, 21, 0, 20, 1, 0)
35 MUX_CFG_7XX("E3_7XX_KBC4", 13, 25, 0, 24, 1, 0)
37 MUX_CFG_7XX("AA17_7XX_USB_DM", 2, 21, 0, 20, 0, 0)
38 MUX_CFG_7XX("W16_7XX_USB_PU_EN", 2, 25, 0, 24, 0, 0)
39 MUX_CFG_7XX("W17_7XX_USB_VBUSI", 2, 29, 6, 28, 1, 0)
40 MUX_CFG_7XX("W18_7XX_USB_DMCK_OUT",3, 3, 1, 2, 0, 0)
41 MUX_CFG_7XX("W19_7XX_USB_DCRST", 3, 7, 1, 6, 0, 0)
44 MUX_CFG_7XX("MMC_7XX_CMD", 2, 9, 0, 8, 1, 0)
45 MUX_CFG_7XX("MMC_7XX_CLK", 2, 13, 0, 12, 1, 0)
46 MUX_CFG_7XX("MMC_7XX_DAT0", 2, 17, 0, 16, 1, 0)
49 MUX_CFG_7XX("I2C_7XX_SCL", 5, 1, 0, 0, 1, 0)
50 MUX_CFG_7XX("I2C_7XX_SDA", 5, 5, 0, 0, 1, 0)
53 MUX_CFG_7XX("SPI_7XX_1", 6, 5, 4, 4, 1, 0)
54 MUX_CFG_7XX("SPI_7XX_2", 6, 9, 4, 8, 1, 0)
55 MUX_CFG_7XX("SPI_7XX_3", 6, 13, 4, 12, 1, 0)
56 MUX_CFG_7XX("SPI_7XX_4", 6, 17, 4, 16, 1, 0)
57 MUX_CFG_7XX("SPI_7XX_5", 8, 25, 0, 24, 0, 0)
58 MUX_CFG_7XX("SPI_7XX_6", 9, 5, 0, 4, 0, 0)
61 MUX_CFG_7XX("UART_7XX_1", 3, 21, 0, 20, 0, 0)
62 MUX_CFG_7XX("UART_7XX_2", 8, 1, 6, 0, 0, 0)
64 #define OMAP7XX_PINS_SZ ARRAY_SIZE(omap7xx_pins)
66 #define omap7xx_pins NULL
67 #define OMAP7XX_PINS_SZ 0
68 #endif /* CONFIG_ARCH_OMAP730 || CONFIG_ARCH_OMAP850 */
70 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
71 static struct pin_config omap1xxx_pins
[] = {
73 * description mux mode mux pull pull pull pu_pd pu dbg
74 * reg offset mode reg bit ena reg
76 MUX_CFG("UART1_TX", 9, 21, 1, 2, 3, 0, NA
, 0, 0)
77 MUX_CFG("UART1_RTS", 9, 12, 1, 2, 0, 0, NA
, 0, 0)
79 /* UART2 (COM_UART_GATING), conflicts with USB2 */
80 MUX_CFG("UART2_TX", C
, 27, 1, 3, 3, 0, NA
, 0, 0)
81 MUX_CFG("UART2_RX", C
, 18, 0, 3, 1, 1, NA
, 0, 0)
82 MUX_CFG("UART2_CTS", C
, 21, 0, 3, 1, 1, NA
, 0, 0)
83 MUX_CFG("UART2_RTS", C
, 24, 1, 3, 2, 0, NA
, 0, 0)
85 /* UART3 (GIGA_UART_GATING) */
86 MUX_CFG("UART3_TX", 6, 0, 1, 0, 30, 0, NA
, 0, 0)
87 MUX_CFG("UART3_RX", 6, 3, 0, 0, 31, 1, NA
, 0, 0)
88 MUX_CFG("UART3_CTS", 5, 12, 2, 0, 24, 0, NA
, 0, 0)
89 MUX_CFG("UART3_RTS", 5, 15, 2, 0, 25, 0, NA
, 0, 0)
90 MUX_CFG("UART3_CLKREQ", 9, 27, 0, 2, 5, 0, NA
, 0, 0)
91 MUX_CFG("UART3_BCLK", A
, 0, 0, 2, 6, 0, NA
, 0, 0)
92 MUX_CFG("Y15_1610_UART3_RTS", A
, 0, 1, 2, 6, 0, NA
, 0, 0)
94 /* PWT & PWL, conflicts with UART3 */
95 MUX_CFG("PWT", 6, 0, 2, 0, 30, 0, NA
, 0, 0)
96 MUX_CFG("PWL", 6, 3, 1, 0, 31, 1, NA
, 0, 0)
98 /* USB internal master generic */
99 MUX_CFG("R18_USB_VBUS", 7, 9, 2, 1, 11, 0, NA
, 0, 1)
100 MUX_CFG("R18_1510_USB_GPIO0", 7, 9, 0, 1, 11, 1, NA
, 0, 1)
101 /* works around erratum: W4_USB_PUEN and W4_USB_PUDIS are switched! */
102 MUX_CFG("W4_USB_PUEN", D
, 3, 3, 3, 5, 1, NA
, 0, 1)
103 MUX_CFG("W4_USB_CLKO", D
, 3, 1, 3, 5, 0, NA
, 0, 1)
104 MUX_CFG("W4_USB_HIGHZ", D
, 3, 4, 3, 5, 0, 3, 0, 1)
105 MUX_CFG("W4_GPIO58", D
, 3, 7, 3, 5, 0, 3, 0, 1)
108 MUX_CFG("USB1_SUSP", 8, 27, 2, 1, 27, 0, NA
, 0, 1)
109 MUX_CFG("USB1_SE0", 9, 0, 2, 1, 28, 0, NA
, 0, 1)
110 MUX_CFG("W13_1610_USB1_SE0", 9, 0, 4, 1, 28, 0, NA
, 0, 1)
111 MUX_CFG("USB1_TXEN", 9, 3, 2, 1, 29, 0, NA
, 0, 1)
112 MUX_CFG("USB1_TXD", 9, 24, 1, 2, 4, 0, NA
, 0, 1)
113 MUX_CFG("USB1_VP", A
, 3, 1, 2, 7, 0, NA
, 0, 1)
114 MUX_CFG("USB1_VM", A
, 6, 1, 2, 8, 0, NA
, 0, 1)
115 MUX_CFG("USB1_RCV", A
, 9, 1, 2, 9, 0, NA
, 0, 1)
116 MUX_CFG("USB1_SPEED", A
, 12, 2, 2, 10, 0, NA
, 0, 1)
117 MUX_CFG("R13_1610_USB1_SPEED", A
, 12, 5, 2, 10, 0, NA
, 0, 1)
118 MUX_CFG("R13_1710_USB1_SEO", A
, 12, 5, 2, 10, 0, NA
, 0, 1)
121 MUX_CFG("USB2_SUSP", B
, 3, 1, 2, 17, 0, NA
, 0, 1)
122 MUX_CFG("USB2_VP", B
, 6, 1, 2, 18, 0, NA
, 0, 1)
123 MUX_CFG("USB2_TXEN", B
, 9, 1, 2, 19, 0, NA
, 0, 1)
124 MUX_CFG("USB2_VM", C
, 18, 1, 3, 0, 0, NA
, 0, 1)
125 MUX_CFG("USB2_RCV", C
, 21, 1, 3, 1, 0, NA
, 0, 1)
126 MUX_CFG("USB2_SE0", C
, 24, 2, 3, 2, 0, NA
, 0, 1)
127 MUX_CFG("USB2_TXD", C
, 27, 2, 3, 3, 0, NA
, 0, 1)
130 MUX_CFG("R18_1510_GPIO0", 7, 9, 0, 1, 11, 1, 0, 0, 1)
131 MUX_CFG("R19_1510_GPIO1", 7, 6, 0, 1, 10, 1, 0, 0, 1)
132 MUX_CFG("M14_1510_GPIO2", 7, 3, 0, 1, 9, 1, 0, 0, 1)
135 MUX_CFG("P18_1610_GPIO3", 7, 0, 0, 1, 8, 0, NA
, 0, 1)
136 MUX_CFG("Y15_1610_GPIO17", A
, 0, 7, 2, 6, 0, NA
, 0, 1)
139 MUX_CFG("R18_1710_GPIO0", 7, 9, 0, 1, 11, 1, 1, 1, 1)
140 MUX_CFG("V2_1710_GPIO10", F
, 27, 1, 4, 3, 1, 4, 1, 1)
141 MUX_CFG("N21_1710_GPIO14", 6, 9, 0, 1, 1, 1, 1, 1, 1)
142 MUX_CFG("W15_1710_GPIO40", 9, 27, 7, 2, 5, 1, 2, 1, 1)
145 MUX_CFG("MPUIO2", 7, 18, 0, 1, 14, 1, NA
, 0, 1)
146 MUX_CFG("N15_1610_MPUIO2", 7, 18, 0, 1, 14, 1, 1, 0, 1)
147 MUX_CFG("MPUIO4", 7, 15, 0, 1, 13, 1, NA
, 0, 1)
148 MUX_CFG("MPUIO5", 7, 12, 0, 1, 12, 1, NA
, 0, 1)
150 MUX_CFG("T20_1610_MPUIO5", 7, 12, 0, 1, 12, 0, 3, 0, 1)
151 MUX_CFG("W11_1610_MPUIO6", 10, 15, 2, 3, 8, 0, 3, 0, 1)
152 MUX_CFG("V10_1610_MPUIO7", A
, 24, 2, 2, 14, 0, 2, 0, 1)
153 MUX_CFG("W11_1610_MPUIO9", 10, 15, 1, 3, 8, 0, 3, 0, 1)
154 MUX_CFG("V10_1610_MPUIO10", A
, 24, 1, 2, 14, 0, 2, 0, 1)
155 MUX_CFG("W10_1610_MPUIO11", A
, 18, 2, 2, 11, 0, 2, 0, 1)
156 MUX_CFG("E20_1610_MPUIO13", 3, 21, 1, 0, 7, 0, 0, 0, 1)
157 MUX_CFG("U20_1610_MPUIO14", 9, 6, 6, 0, 30, 0, 0, 0, 1)
158 MUX_CFG("E19_1610_MPUIO15", 3, 18, 1, 0, 6, 0, 0, 0, 1)
161 MUX_CFG("MCBSP2_CLKR", C
, 6, 0, 2, 27, 1, NA
, 0, 1)
162 MUX_CFG("MCBSP2_CLKX", C
, 9, 0, 2, 29, 1, NA
, 0, 1)
163 MUX_CFG("MCBSP2_DR", C
, 0, 0, 2, 26, 1, NA
, 0, 1)
164 MUX_CFG("MCBSP2_DX", C
, 15, 0, 2, 31, 1, NA
, 0, 1)
165 MUX_CFG("MCBSP2_FSR", C
, 12, 0, 2, 30, 1, NA
, 0, 1)
166 MUX_CFG("MCBSP2_FSX", C
, 3, 0, 2, 27, 1, NA
, 0, 1)
168 /* MCBSP3 NOTE: Mode must 1 for clock */
169 MUX_CFG("MCBSP3_CLKX", 9, 3, 1, 1, 29, 0, NA
, 0, 1)
172 MUX_CFG("BALLOUT_V8_ARMIO3", B
, 18, 0, 2, 25, 1, NA
, 0, 1)
173 MUX_CFG("N20_HDQ", 6, 18, 1, 1, 4, 0, 1, 4, 0)
176 MUX_CFG("W8_1610_MMC2_DAT0", B
, 21, 6, 2, 23, 1, 2, 1, 1)
177 MUX_CFG("V8_1610_MMC2_DAT1", B
, 27, 6, 2, 25, 1, 2, 1, 1)
178 MUX_CFG("W15_1610_MMC2_DAT2", 9, 12, 6, 2, 5, 1, 2, 1, 1)
179 MUX_CFG("R10_1610_MMC2_DAT3", B
, 18, 6, 2, 22, 1, 2, 1, 1)
180 MUX_CFG("Y10_1610_MMC2_CLK", B
, 3, 6, 2, 17, 0, 2, 0, 1)
181 MUX_CFG("Y8_1610_MMC2_CMD", B
, 24, 6, 2, 24, 1, 2, 1, 1)
182 MUX_CFG("V9_1610_MMC2_CMDDIR", B
, 12, 6, 2, 20, 0, 2, 1, 1)
183 MUX_CFG("V5_1610_MMC2_DATDIR0", B
, 15, 6, 2, 21, 0, 2, 1, 1)
184 MUX_CFG("W19_1610_MMC2_DATDIR1", 8, 15, 6, 1, 23, 0, 1, 1, 1)
185 MUX_CFG("R18_1610_MMC2_CLKIN", 7, 9, 6, 1, 11, 0, 1, 11, 1)
187 /* OMAP-1610 External Trace Interface */
188 MUX_CFG("M19_1610_ETM_PSTAT0", 5, 27, 1, 0, 29, 0, 0, 0, 1)
189 MUX_CFG("L15_1610_ETM_PSTAT1", 5, 24, 1, 0, 28, 0, 0, 0, 1)
190 MUX_CFG("L18_1610_ETM_PSTAT2", 5, 21, 1, 0, 27, 0, 0, 0, 1)
191 MUX_CFG("L19_1610_ETM_D0", 5, 18, 1, 0, 26, 0, 0, 0, 1)
192 MUX_CFG("J19_1610_ETM_D6", 5, 0, 1, 0, 20, 0, 0, 0, 1)
193 MUX_CFG("J18_1610_ETM_D7", 5, 27, 1, 0, 19, 0, 0, 0, 1)
196 MUX_CFG("P20_1610_GPIO4", 6, 27, 0, 1, 7, 0, 1, 1, 1)
197 MUX_CFG("V9_1610_GPIO7", B
, 12, 1, 2, 20, 0, 2, 1, 1)
198 MUX_CFG("W8_1610_GPIO9", B
, 21, 0, 2, 23, 0, 2, 1, 1)
199 MUX_CFG("N20_1610_GPIO11", 6, 18, 0, 1, 4, 0, 1, 1, 1)
200 MUX_CFG("N19_1610_GPIO13", 6, 12, 0, 1, 2, 0, 1, 1, 1)
201 MUX_CFG("P10_1610_GPIO22", C
, 0, 7, 2, 26, 0, 2, 1, 1)
202 MUX_CFG("V5_1610_GPIO24", B
, 15, 7, 2, 21, 0, 2, 1, 1)
203 MUX_CFG("AA20_1610_GPIO_41", 9, 9, 7, 1, 31, 0, 1, 1, 1)
204 MUX_CFG("W19_1610_GPIO48", 8, 15, 7, 1, 23, 1, 1, 0, 1)
205 MUX_CFG("M7_1610_GPIO62", 10, 0, 0, 4, 24, 0, 4, 0, 1)
206 MUX_CFG("V14_16XX_GPIO37", 9, 18, 7, 2, 2, 0, 2, 2, 0)
207 MUX_CFG("R9_16XX_GPIO18", C
, 18, 7, 3, 0, 0, 3, 0, 0)
208 MUX_CFG("L14_16XX_GPIO49", 6, 3, 7, 0, 31, 0, 0, 31, 0)
210 /* OMAP-1610 uWire */
211 MUX_CFG("V19_1610_UWIRE_SCLK", 8, 6, 0, 1, 20, 0, 1, 1, 1)
212 MUX_CFG("U18_1610_UWIRE_SDI", 8, 0, 0, 1, 18, 0, 1, 1, 1)
213 MUX_CFG("W21_1610_UWIRE_SDO", 8, 3, 0, 1, 19, 0, 1, 1, 1)
214 MUX_CFG("N14_1610_UWIRE_CS0", 8, 9, 1, 1, 21, 0, 1, 1, 1)
215 MUX_CFG("P15_1610_UWIRE_CS3", 8, 12, 1, 1, 22, 0, 1, 1, 1)
216 MUX_CFG("N15_1610_UWIRE_CS1", 7, 18, 2, 1, 14, 0, NA
, 0, 1)
219 MUX_CFG("U19_1610_SPIF_SCK", 7, 21, 6, 1, 15, 0, 1, 1, 1)
220 MUX_CFG("U18_1610_SPIF_DIN", 8, 0, 6, 1, 18, 1, 1, 0, 1)
221 MUX_CFG("P20_1610_SPIF_DIN", 6, 27, 4, 1, 7, 1, 1, 0, 1)
222 MUX_CFG("W21_1610_SPIF_DOUT", 8, 3, 6, 1, 19, 0, 1, 0, 1)
223 MUX_CFG("R18_1610_SPIF_DOUT", 7, 9, 3, 1, 11, 0, 1, 0, 1)
224 MUX_CFG("N14_1610_SPIF_CS0", 8, 9, 6, 1, 21, 0, 1, 1, 1)
225 MUX_CFG("N15_1610_SPIF_CS1", 7, 18, 6, 1, 14, 0, 1, 1, 1)
226 MUX_CFG("T19_1610_SPIF_CS2", 7, 15, 4, 1, 13, 0, 1, 1, 1)
227 MUX_CFG("P15_1610_SPIF_CS3", 8, 12, 3, 1, 22, 0, 1, 1, 1)
229 /* OMAP-1610 Flash */
230 MUX_CFG("L3_1610_FLASH_CS2B_OE",10, 6, 1, NA
, 0, 0, NA
, 0, 1)
231 MUX_CFG("M8_1610_FLASH_CS2B_WE",10, 3, 1, NA
, 0, 0, NA
, 0, 1)
233 /* First MMC interface, same on 1510, 1610 and 1710 */
234 MUX_CFG("MMC_CMD", A
, 27, 0, 2, 15, 1, 2, 1, 1)
235 MUX_CFG("MMC_DAT1", A
, 24, 0, 2, 14, 1, 2, 1, 1)
236 MUX_CFG("MMC_DAT2", A
, 18, 0, 2, 12, 1, 2, 1, 1)
237 MUX_CFG("MMC_DAT0", B
, 0, 0, 2, 16, 1, 2, 1, 1)
238 MUX_CFG("MMC_CLK", A
, 21, 0, NA
, 0, 0, NA
, 0, 1)
239 MUX_CFG("MMC_DAT3", 10, 15, 0, 3, 8, 1, 3, 1, 1)
240 MUX_CFG("M15_1710_MMC_CLKI", 6, 21, 2, 0, 0, 0, NA
, 0, 1)
241 MUX_CFG("P19_1710_MMC_CMDDIR", 6, 24, 6, 0, 0, 0, NA
, 0, 1)
242 MUX_CFG("P20_1710_MMC_DATDIR0", 6, 27, 5, 0, 0, 0, NA
, 0, 1)
244 /* OMAP-1610 USB0 alternate configuration */
245 MUX_CFG("W9_USB0_TXEN", B
, 9, 5, 2, 19, 0, 2, 0, 1)
246 MUX_CFG("AA9_USB0_VP", B
, 6, 5, 2, 18, 0, 2, 0, 1)
247 MUX_CFG("Y5_USB0_RCV", C
, 21, 5, 3, 1, 0, 1, 0, 1)
248 MUX_CFG("R9_USB0_VM", C
, 18, 5, 3, 0, 0, 3, 0, 1)
249 MUX_CFG("V6_USB0_TXD", C
, 27, 5, 3, 3, 0, 3, 0, 1)
250 MUX_CFG("W5_USB0_SE0", C
, 24, 5, 3, 2, 0, 3, 0, 1)
251 MUX_CFG("V9_USB0_SPEED", B
, 12, 5, 2, 20, 0, 2, 0, 1)
252 MUX_CFG("Y10_USB0_SUSP", B
, 3, 5, 2, 17, 0, 2, 0, 1)
255 MUX_CFG("W9_USB2_TXEN", B
, 9, 1, NA
, 0, 0, NA
, 0, 1)
256 MUX_CFG("AA9_USB2_VP", B
, 6, 1, NA
, 0, 0, NA
, 0, 1)
257 MUX_CFG("Y5_USB2_RCV", C
, 21, 1, NA
, 0, 0, NA
, 0, 1)
258 MUX_CFG("R9_USB2_VM", C
, 18, 1, NA
, 0, 0, NA
, 0, 1)
259 MUX_CFG("V6_USB2_TXD", C
, 27, 2, NA
, 0, 0, NA
, 0, 1)
260 MUX_CFG("W5_USB2_SE0", C
, 24, 2, NA
, 0, 0, NA
, 0, 1)
263 MUX_CFG("R13_1610_UART1_TX", A
, 12, 6, 2, 10, 0, 2, 10, 1)
264 MUX_CFG("V14_16XX_UART1_RX", 9, 18, 0, 2, 2, 0, 2, 2, 1)
265 MUX_CFG("R14_1610_UART1_CTS", 9, 15, 0, 2, 1, 0, 2, 1, 1)
266 MUX_CFG("AA15_1610_UART1_RTS", 9, 12, 1, 2, 0, 0, 2, 0, 1)
267 MUX_CFG("R9_16XX_UART2_RX", C
, 18, 0, 3, 0, 0, 3, 0, 1)
268 MUX_CFG("L14_16XX_UART3_RX", 6, 3, 0, 0, 31, 0, 0, 31, 1)
271 MUX_CFG("I2C_SCL", 7, 24, 0, NA
, 0, 0, NA
, 0, 0)
272 MUX_CFG("I2C_SDA", 7, 27, 0, NA
, 0, 0, NA
, 0, 0)
275 MUX_CFG("F18_1610_KBC0", 3, 15, 0, 0, 5, 1, 0, 0, 0)
276 MUX_CFG("D20_1610_KBC1", 3, 12, 0, 0, 4, 1, 0, 0, 0)
277 MUX_CFG("D19_1610_KBC2", 3, 9, 0, 0, 3, 1, 0, 0, 0)
278 MUX_CFG("E18_1610_KBC3", 3, 6, 0, 0, 2, 1, 0, 0, 0)
279 MUX_CFG("C21_1610_KBC4", 3, 3, 0, 0, 1, 1, 0, 0, 0)
280 MUX_CFG("G18_1610_KBR0", 4, 0, 0, 0, 10, 1, 0, 1, 0)
281 MUX_CFG("F19_1610_KBR1", 3, 27, 0, 0, 9, 1, 0, 1, 0)
282 MUX_CFG("H14_1610_KBR2", 3, 24, 0, 0, 8, 1, 0, 1, 0)
283 MUX_CFG("E20_1610_KBR3", 3, 21, 0, 0, 7, 1, 0, 1, 0)
284 MUX_CFG("E19_1610_KBR4", 3, 18, 0, 0, 6, 1, 0, 1, 0)
285 MUX_CFG("N19_1610_KBR5", 6, 12, 1, 1, 2, 1, 1, 1, 0)
287 /* Power management */
288 MUX_CFG("T20_1610_LOW_PWR", 7, 12, 1, NA
, 0, 0, NA
, 0, 0)
291 MUX_CFG("V5_1710_MCLK_ON", B
, 15, 0, NA
, 0, 0, NA
, 0, 0)
292 MUX_CFG("V5_1710_MCLK_OFF", B
, 15, 6, NA
, 0, 0, NA
, 0, 0)
293 MUX_CFG("R10_1610_MCLK_ON", B
, 18, 0, NA
, 22, 0, NA
, 1, 0)
294 MUX_CFG("R10_1610_MCLK_OFF", B
, 18, 6, 2, 22, 1, 2, 1, 1)
296 /* CompactFlash controller, conflicts with MMC1 */
297 MUX_CFG("P11_1610_CF_CD2", A
, 27, 3, 2, 15, 1, 2, 1, 1)
298 MUX_CFG("R11_1610_CF_IOIS16", B
, 0, 3, 2, 16, 1, 2, 1, 1)
299 MUX_CFG("V10_1610_CF_IREQ", A
, 24, 3, 2, 14, 0, 2, 0, 1)
300 MUX_CFG("W10_1610_CF_RESET", A
, 18, 3, 2, 12, 1, 2, 1, 1)
301 MUX_CFG("W11_1610_CF_CD1", 10, 15, 3, 3, 8, 1, 3, 1, 1)
303 /* parallel camera */
304 MUX_CFG("J15_1610_CAM_LCLK", 4, 24, 0, 0, 18, 1, 0, 0, 0)
305 MUX_CFG("J18_1610_CAM_D7", 4, 27, 0, 0, 19, 1, 0, 0, 0)
306 MUX_CFG("J19_1610_CAM_D6", 5, 0, 0, 0, 20, 1, 0, 0, 0)
307 MUX_CFG("J14_1610_CAM_D5", 5, 3, 0, 0, 21, 1, 0, 0, 0)
308 MUX_CFG("K18_1610_CAM_D4", 5, 6, 0, 0, 22, 1, 0, 0, 0)
309 MUX_CFG("K19_1610_CAM_D3", 5, 9, 0, 0, 23, 1, 0, 0, 0)
310 MUX_CFG("K15_1610_CAM_D2", 5, 12, 0, 0, 24, 1, 0, 0, 0)
311 MUX_CFG("K14_1610_CAM_D1", 5, 15, 0, 0, 25, 1, 0, 0, 0)
312 MUX_CFG("L19_1610_CAM_D0", 5, 18, 0, 0, 26, 1, 0, 0, 0)
313 MUX_CFG("L18_1610_CAM_VS", 5, 21, 0, 0, 27, 1, 0, 0, 0)
314 MUX_CFG("L15_1610_CAM_HS", 5, 24, 0, 0, 28, 1, 0, 0, 0)
315 MUX_CFG("M19_1610_CAM_RSTZ", 5, 27, 0, 0, 29, 0, 0, 0, 0)
316 MUX_CFG("Y15_1610_CAM_OUTCLK", A
, 0, 6, 2, 6, 0, 2, 0, 0)
319 MUX_CFG("H19_1610_CAM_EXCLK", 4, 21, 0, 0, 17, 0, 0, 0, 0)
320 /* REVISIT 5912 spec sez CCP_* can't pullup or pulldown ... ? */
321 MUX_CFG("Y12_1610_CCP_CLKP", 8, 18, 6, 1, 24, 1, 1, 0, 0)
322 MUX_CFG("W13_1610_CCP_CLKM", 9, 0, 6, 1, 28, 1, 1, 0, 0)
323 MUX_CFG("W14_1610_CCP_DATAP", 9, 24, 6, 2, 4, 1, 2, 0, 0)
324 MUX_CFG("Y14_1610_CCP_DATAM", 9, 21, 6, 2, 3, 1, 2, 0, 0)
326 #define OMAP1XXX_PINS_SZ ARRAY_SIZE(omap1xxx_pins)
328 #define omap1xxx_pins NULL
329 #define OMAP1XXX_PINS_SZ 0
330 #endif /* CONFIG_ARCH_OMAP15XX || CONFIG_ARCH_OMAP16XX */
332 static int omap1_cfg_reg(const struct pin_config
*cfg
)
334 static DEFINE_SPINLOCK(mux_spin_lock
);
336 unsigned int reg_orig
= 0, reg
= 0, pu_pd_orig
= 0, pu_pd
= 0,
337 pull_orig
= 0, pull
= 0;
338 unsigned int mask
, warn
= 0;
340 /* Check the mux register in question */
344 spin_lock_irqsave(&mux_spin_lock
, flags
);
345 reg_orig
= omap_readl(cfg
->mux_reg
);
347 /* The mux registers always seem to be 3 bits long */
348 mask
= (0x7 << cfg
->mask_offset
);
349 tmp1
= reg_orig
& mask
;
350 reg
= reg_orig
& ~mask
;
352 tmp2
= (cfg
->mask
<< cfg
->mask_offset
);
358 omap_writel(reg
, cfg
->mux_reg
);
359 spin_unlock_irqrestore(&mux_spin_lock
, flags
);
362 /* Check for pull up or pull down selection on 1610 */
363 if (!cpu_is_omap15xx()) {
364 if (cfg
->pu_pd_reg
&& cfg
->pull_val
) {
365 spin_lock_irqsave(&mux_spin_lock
, flags
);
366 pu_pd_orig
= omap_readl(cfg
->pu_pd_reg
);
367 mask
= 1 << cfg
->pull_bit
;
369 if (cfg
->pu_pd_val
) {
370 if (!(pu_pd_orig
& mask
))
373 pu_pd
= pu_pd_orig
| mask
;
375 if (pu_pd_orig
& mask
)
378 pu_pd
= pu_pd_orig
& ~mask
;
380 omap_writel(pu_pd
, cfg
->pu_pd_reg
);
381 spin_unlock_irqrestore(&mux_spin_lock
, flags
);
385 /* Check for an associated pull down register */
387 spin_lock_irqsave(&mux_spin_lock
, flags
);
388 pull_orig
= omap_readl(cfg
->pull_reg
);
389 mask
= 1 << cfg
->pull_bit
;
392 if (pull_orig
& mask
)
394 /* Low bit = pull enabled */
395 pull
= pull_orig
& ~mask
;
397 if (!(pull_orig
& mask
))
399 /* High bit = pull disabled */
400 pull
= pull_orig
| mask
;
403 omap_writel(pull
, cfg
->pull_reg
);
404 spin_unlock_irqrestore(&mux_spin_lock
, flags
);
408 #ifdef CONFIG_OMAP_MUX_WARNINGS
409 printk(KERN_WARNING
"MUX: initialized %s\n", cfg
->name
);
413 #ifdef CONFIG_OMAP_MUX_DEBUG
414 if (cfg
->debug
|| warn
) {
415 printk("MUX: Setting register %s\n", cfg
->name
);
416 printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
417 cfg
->mux_reg_name
, cfg
->mux_reg
, reg_orig
, reg
);
419 if (!cpu_is_omap15xx()) {
420 if (cfg
->pu_pd_reg
&& cfg
->pull_val
) {
421 printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
422 cfg
->pu_pd_name
, cfg
->pu_pd_reg
,
428 printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
429 cfg
->pull_name
, cfg
->pull_reg
, pull_orig
, pull
);
433 #ifdef CONFIG_OMAP_MUX_WARNINGS
434 return warn
? -ETXTBSY
: 0;
440 static struct omap_mux_cfg
*mux_cfg
;
442 int __init
omap_mux_register(struct omap_mux_cfg
*arch_mux_cfg
)
444 if (!arch_mux_cfg
|| !arch_mux_cfg
->pins
|| arch_mux_cfg
->size
== 0
445 || !arch_mux_cfg
->cfg_reg
) {
446 printk(KERN_ERR
"Invalid pin table\n");
450 mux_cfg
= arch_mux_cfg
;
456 * Sets the Omap MUX and PULL_DWN registers based on the table
458 int omap_cfg_reg(const unsigned long index
)
460 struct pin_config
*reg
;
462 if (!cpu_class_is_omap1()) {
463 printk(KERN_ERR
"mux: Broken omap_cfg_reg(%lu) entry\n",
469 if (mux_cfg
== NULL
) {
470 printk(KERN_ERR
"Pin mux table not initialized\n");
474 if (index
>= mux_cfg
->size
) {
475 printk(KERN_ERR
"Invalid pin mux index: %lu (%lu)\n",
476 index
, mux_cfg
->size
);
481 reg
= &mux_cfg
->pins
[index
];
483 if (!mux_cfg
->cfg_reg
)
486 return mux_cfg
->cfg_reg(reg
);
488 EXPORT_SYMBOL(omap_cfg_reg
);
490 int __init
omap1_mux_init(void)
492 if (cpu_is_omap7xx()) {
493 arch_mux_cfg
.pins
= omap7xx_pins
;
494 arch_mux_cfg
.size
= OMAP7XX_PINS_SZ
;
495 arch_mux_cfg
.cfg_reg
= omap1_cfg_reg
;
498 if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
499 arch_mux_cfg
.pins
= omap1xxx_pins
;
500 arch_mux_cfg
.size
= OMAP1XXX_PINS_SZ
;
501 arch_mux_cfg
.cfg_reg
= omap1_cfg_reg
;
504 return omap_mux_register(&arch_mux_cfg
);
508 #define omap_mux_init() do {} while(0)
509 #define omap_cfg_reg(x) do {} while(0)
510 #endif /* CONFIG_OMAP_MUX */