arm64: dts: Revert "specify console via command line"
[linux/fpc-iii.git] / arch / arm / mach-omap2 / cm1_54xx.h
blob7be363a27a40e4357aad864c828cbcc234ef6573
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * OMAP54xx CM1 instance offset macros
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
18 #ifndef __ARCH_ARM_MACH_OMAP2_CM1_54XX_H
19 #define __ARCH_ARM_MACH_OMAP2_CM1_54XX_H
21 /* CM1 base address */
22 #define OMAP54XX_CM_CORE_AON_BASE 0x4a004000
24 #define OMAP54XX_CM_CORE_AON_REGADDR(inst, reg) \
25 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE + (inst) + (reg))
27 /* CM_CORE_AON instances */
28 #define OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST 0x0000
29 #define OMAP54XX_CM_CORE_AON_CKGEN_INST 0x0100
30 #define OMAP54XX_CM_CORE_AON_MPU_INST 0x0300
31 #define OMAP54XX_CM_CORE_AON_DSP_INST 0x0400
32 #define OMAP54XX_CM_CORE_AON_ABE_INST 0x0500
33 #define OMAP54XX_CM_CORE_AON_RESTORE_INST 0x0e00
34 #define OMAP54XX_CM_CORE_AON_INSTR_INST 0x0f00
36 /* CM_CORE_AON clockdomain register offsets (from instance start) */
37 #define OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS 0x0000
38 #define OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS 0x0000
39 #define OMAP54XX_CM_CORE_AON_ABE_ABE_CDOFFS 0x0000
41 /* CM_CORE_AON */
43 /* CM_CORE_AON.OCP_SOCKET_CM_CORE_AON register offsets */
44 #define OMAP54XX_REVISION_CM_CORE_AON_OFFSET 0x0000
45 #define OMAP54XX_CM_CM_CORE_AON_PROFILING_CLKCTRL_OFFSET 0x0040
46 #define OMAP54XX_CM_CM_CORE_AON_PROFILING_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST, 0x0040)
47 #define OMAP54XX_CM_CORE_AON_DEBUG_CFG_OFFSET 0x0080
48 #define OMAP54XX_CM_CORE_AON_DEBUG_OUT_OFFSET 0x0084
49 #define OMAP54XX_CM_CORE_AON_DEBUG_MPU_FD_TRANS_OFFSET 0x0090
50 #define OMAP54XX_CM_CORE_AON_DEBUG_DSP_FD_TRANS_OFFSET 0x0094
51 #define OMAP54XX_CM_CORE_AON_DEBUG_ABE_FD_TRANS_OFFSET 0x0098
52 #define OMAP54XX_CM_CORE_AON_DEBUG_ABE_FD_TRANS2_OFFSET 0x009c
53 #define OMAP54XX_CM_CORE_AON_DEBUG_CM_CORE_AON_FD_TRANS_OFFSET 0x00a0
54 #define OMAP54XX_CM_CORE_AON_DEBUG_C2C_FD_TRANS_OFFSET 0x00a4
55 #define OMAP54XX_CM_CORE_AON_DEBUG_CAM_FD_TRANS_OFFSET 0x00a8
56 #define OMAP54XX_CM_CORE_AON_DEBUG_COREAON_FD_TRANS_OFFSET 0x00ac
57 #define OMAP54XX_CM_CORE_AON_DEBUG_CUSTEFUSE_FD_TRANS_OFFSET 0x00b0
58 #define OMAP54XX_CM_CORE_AON_DEBUG_DMA_FD_TRANS_OFFSET 0x00b4
59 #define OMAP54XX_CM_CORE_AON_DEBUG_DSS_FD_TRANS_OFFSET 0x00b8
60 #define OMAP54XX_CM_CORE_AON_DEBUG_EMIF_FD_TRANS_OFFSET 0x00bc
61 #define OMAP54XX_CM_CORE_AON_DEBUG_GPU_FD_TRANS_OFFSET 0x00c0
62 #define OMAP54XX_CM_CORE_AON_DEBUG_IPU_FD_TRANS_OFFSET 0x00c4
63 #define OMAP54XX_CM_CORE_AON_DEBUG_IVA_FD_TRANS_OFFSET 0x00c8
64 #define OMAP54XX_CM_CORE_AON_DEBUG_L3INIT_FD_TRANS_OFFSET 0x00cc
65 #define OMAP54XX_CM_CORE_AON_DEBUG_L3INIT_FD_TRANS2_OFFSET 0x00d0
66 #define OMAP54XX_CM_CORE_AON_DEBUG_L3INSTR_FD_TRANS_OFFSET 0x00d4
67 #define OMAP54XX_CM_CORE_AON_DEBUG_L3MAIN1_FD_TRANS_OFFSET 0x00d8
68 #define OMAP54XX_CM_CORE_AON_DEBUG_L3MAIN2_FD_TRANS_OFFSET 0x00dc
69 #define OMAP54XX_CM_CORE_AON_DEBUG_L4CFG_FD_TRANS_OFFSET 0x00e0
70 #define OMAP54XX_CM_CORE_AON_DEBUG_L4PER_FD_TRANS_OFFSET 0x00e4
71 #define OMAP54XX_CM_CORE_AON_DEBUG_L4PER_FD_TRANS2_OFFSET 0x00e8
72 #define OMAP54XX_CM_CORE_AON_DEBUG_L4SEC_FD_TRANS_OFFSET 0x00ec
73 #define OMAP54XX_CM_CORE_AON_DEBUG_MIPIEXT_FD_TRANS_OFFSET 0x00f0
75 /* CM_CORE_AON.CKGEN_CM_CORE_AON register offsets */
76 #define OMAP54XX_CM_CLKSEL_CORE_OFFSET 0x0000
77 #define OMAP54XX_CM_CLKSEL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0000)
78 #define OMAP54XX_CM_CLKSEL_ABE_OFFSET 0x0008
79 #define OMAP54XX_CM_CLKSEL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0008)
80 #define OMAP54XX_CM_DLL_CTRL_OFFSET 0x0010
81 #define OMAP54XX_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020
82 #define OMAP54XX_CM_CLKMODE_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0020)
83 #define OMAP54XX_CM_IDLEST_DPLL_CORE_OFFSET 0x0024
84 #define OMAP54XX_CM_IDLEST_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0024)
85 #define OMAP54XX_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028
86 #define OMAP54XX_CM_AUTOIDLE_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0028)
87 #define OMAP54XX_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c
88 #define OMAP54XX_CM_CLKSEL_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x002c)
89 #define OMAP54XX_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030
90 #define OMAP54XX_CM_DIV_M2_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0030)
91 #define OMAP54XX_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034
92 #define OMAP54XX_CM_DIV_M3_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0034)
93 #define OMAP54XX_CM_DIV_H11_DPLL_CORE_OFFSET 0x0038
94 #define OMAP54XX_CM_DIV_H11_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0038)
95 #define OMAP54XX_CM_DIV_H12_DPLL_CORE_OFFSET 0x003c
96 #define OMAP54XX_CM_DIV_H12_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x003c)
97 #define OMAP54XX_CM_DIV_H13_DPLL_CORE_OFFSET 0x0040
98 #define OMAP54XX_CM_DIV_H13_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0040)
99 #define OMAP54XX_CM_DIV_H14_DPLL_CORE_OFFSET 0x0044
100 #define OMAP54XX_CM_DIV_H14_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0044)
101 #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048
102 #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c
103 #define OMAP54XX_CM_DIV_H21_DPLL_CORE_OFFSET 0x0050
104 #define OMAP54XX_CM_DIV_H21_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0050)
105 #define OMAP54XX_CM_DIV_H22_DPLL_CORE_OFFSET 0x0054
106 #define OMAP54XX_CM_DIV_H22_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0054)
107 #define OMAP54XX_CM_DIV_H23_DPLL_CORE_OFFSET 0x0058
108 #define OMAP54XX_CM_DIV_H23_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0058)
109 #define OMAP54XX_CM_DIV_H24_DPLL_CORE_OFFSET 0x005c
110 #define OMAP54XX_CM_DIV_H24_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x005c)
111 #define OMAP54XX_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060
112 #define OMAP54XX_CM_CLKMODE_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0060)
113 #define OMAP54XX_CM_IDLEST_DPLL_MPU_OFFSET 0x0064
114 #define OMAP54XX_CM_IDLEST_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0064)
115 #define OMAP54XX_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068
116 #define OMAP54XX_CM_AUTOIDLE_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0068)
117 #define OMAP54XX_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c
118 #define OMAP54XX_CM_CLKSEL_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x006c)
119 #define OMAP54XX_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070
120 #define OMAP54XX_CM_DIV_M2_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0070)
121 #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088
122 #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c
123 #define OMAP54XX_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c
124 #define OMAP54XX_CM_BYPCLK_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x009c)
125 #define OMAP54XX_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0
126 #define OMAP54XX_CM_CLKMODE_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a0)
127 #define OMAP54XX_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4
128 #define OMAP54XX_CM_IDLEST_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a4)
129 #define OMAP54XX_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8
130 #define OMAP54XX_CM_AUTOIDLE_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a8)
131 #define OMAP54XX_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac
132 #define OMAP54XX_CM_CLKSEL_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00ac)
133 #define OMAP54XX_CM_DIV_H11_DPLL_IVA_OFFSET 0x00b8
134 #define OMAP54XX_CM_DIV_H11_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00b8)
135 #define OMAP54XX_CM_DIV_H12_DPLL_IVA_OFFSET 0x00bc
136 #define OMAP54XX_CM_DIV_H12_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00bc)
137 #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8
138 #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc
139 #define OMAP54XX_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc
140 #define OMAP54XX_CM_BYPCLK_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00dc)
141 #define OMAP54XX_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0
142 #define OMAP54XX_CM_CLKMODE_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e0)
143 #define OMAP54XX_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4
144 #define OMAP54XX_CM_IDLEST_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e4)
145 #define OMAP54XX_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8
146 #define OMAP54XX_CM_AUTOIDLE_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e8)
147 #define OMAP54XX_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec
148 #define OMAP54XX_CM_CLKSEL_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00ec)
149 #define OMAP54XX_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0
150 #define OMAP54XX_CM_DIV_M2_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00f0)
151 #define OMAP54XX_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4
152 #define OMAP54XX_CM_DIV_M3_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00f4)
153 #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108
154 #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c
155 #define OMAP54XX_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160
156 #define OMAP54XX_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164
157 #define OMAP54XX_CM_DYN_DEP_PRESCAL_OFFSET 0x0170
158 #define OMAP54XX_CM_RESTORE_ST_OFFSET 0x0180
160 /* CM_CORE_AON.MPU_CM_CORE_AON register offsets */
161 #define OMAP54XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000
162 #define OMAP54XX_CM_MPU_STATICDEP_OFFSET 0x0004
163 #define OMAP54XX_CM_MPU_DYNAMICDEP_OFFSET 0x0008
164 #define OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020
165 #define OMAP54XX_CM_MPU_MPU_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_MPU_INST, 0x0020)
166 #define OMAP54XX_CM_MPU_MPU_MPU_DBG_CLKCTRL_OFFSET 0x0028
167 #define OMAP54XX_CM_MPU_MPU_MPU_DBG_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_MPU_INST, 0x0028)
169 /* CM_CORE_AON.DSP_CM_CORE_AON register offsets */
170 #define OMAP54XX_CM_DSP_CLKSTCTRL_OFFSET 0x0000
171 #define OMAP54XX_CM_DSP_STATICDEP_OFFSET 0x0004
172 #define OMAP54XX_CM_DSP_DYNAMICDEP_OFFSET 0x0008
173 #define OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET 0x0020
174 #define OMAP54XX_CM_DSP_DSP_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_DSP_INST, 0x0020)
176 /* CM_CORE_AON.ABE_CM_CORE_AON register offsets */
177 #define OMAP54XX_CM_ABE_CLKSTCTRL_OFFSET 0x0000
178 #define OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET 0x0020
179 #define OMAP54XX_CM_ABE_L4_ABE_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0020)
180 #define OMAP54XX_CM_ABE_AESS_CLKCTRL_OFFSET 0x0028
181 #define OMAP54XX_CM_ABE_AESS_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0028)
182 #define OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET 0x0030
183 #define OMAP54XX_CM_ABE_MCPDM_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0030)
184 #define OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET 0x0038
185 #define OMAP54XX_CM_ABE_DMIC_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0038)
186 #define OMAP54XX_CM_ABE_MCASP_CLKCTRL_OFFSET 0x0040
187 #define OMAP54XX_CM_ABE_MCASP_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0040)
188 #define OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET 0x0048
189 #define OMAP54XX_CM_ABE_MCBSP1_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0048)
190 #define OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET 0x0050
191 #define OMAP54XX_CM_ABE_MCBSP2_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0050)
192 #define OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET 0x0058
193 #define OMAP54XX_CM_ABE_MCBSP3_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0058)
194 #define OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL_OFFSET 0x0060
195 #define OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0060)
196 #define OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET 0x0068
197 #define OMAP54XX_CM_ABE_TIMER5_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0068)
198 #define OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET 0x0070
199 #define OMAP54XX_CM_ABE_TIMER6_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0070)
200 #define OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET 0x0078
201 #define OMAP54XX_CM_ABE_TIMER7_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0078)
202 #define OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET 0x0080
203 #define OMAP54XX_CM_ABE_TIMER8_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0080)
204 #define OMAP54XX_CM_ABE_WD_TIMER3_CLKCTRL_OFFSET 0x0088
205 #define OMAP54XX_CM_ABE_WD_TIMER3_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0088)
207 #endif