1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * DRA7xx CM1 instance offset macros
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
7 * Generated by code originally written by:
8 * Paul Walmsley (paul@pwsan.com)
9 * Rajendra Nayak (rnayak@ti.com)
10 * Benoit Cousson (b-cousson@ti.com)
12 * This file is automatically generated from the OMAP hardware databases.
13 * We respectfully ask that any modifications to this file be coordinated
14 * with the public linux-omap@vger.kernel.org mailing list and the
15 * authors above to ensure that the autogeneration scripts are kept
16 * up-to-date with the file contents.
19 #ifndef __ARCH_ARM_MACH_OMAP2_CM1_7XX_H
20 #define __ARCH_ARM_MACH_OMAP2_CM1_7XX_H
22 /* CM1 base address */
23 #define DRA7XX_CM_CORE_AON_BASE 0x4a005000
25 #define DRA7XX_CM_CORE_AON_REGADDR(inst, reg) \
26 OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE + (inst) + (reg))
28 /* CM_CORE_AON instances */
29 #define DRA7XX_CM_CORE_AON_OCP_SOCKET_INST 0x0000
30 #define DRA7XX_CM_CORE_AON_CKGEN_INST 0x0100
31 #define DRA7XX_CM_CORE_AON_MPU_INST 0x0300
32 #define DRA7XX_CM_CORE_AON_DSP1_INST 0x0400
33 #define DRA7XX_CM_CORE_AON_IPU_INST 0x0500
34 #define DRA7XX_CM_CORE_AON_DSP2_INST 0x0600
35 #define DRA7XX_CM_CORE_AON_EVE1_INST 0x0640
36 #define DRA7XX_CM_CORE_AON_EVE2_INST 0x0680
37 #define DRA7XX_CM_CORE_AON_EVE3_INST 0x06c0
38 #define DRA7XX_CM_CORE_AON_EVE4_INST 0x0700
39 #define DRA7XX_CM_CORE_AON_RTC_INST 0x0740
40 #define DRA7XX_CM_CORE_AON_VPE_INST 0x0760
41 #define DRA7XX_CM_CORE_AON_RESTORE_INST 0x0e00
42 #define DRA7XX_CM_CORE_AON_INSTR_INST 0x0f00
44 /* CM_CORE_AON clockdomain register offsets (from instance start) */
45 #define DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS 0x0000
46 #define DRA7XX_CM_CORE_AON_DSP1_DSP1_CDOFFS 0x0000
47 #define DRA7XX_CM_CORE_AON_IPU_IPU1_CDOFFS 0x0000
48 #define DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS 0x0040
49 #define DRA7XX_CM_CORE_AON_DSP2_DSP2_CDOFFS 0x0000
50 #define DRA7XX_CM_CORE_AON_EVE1_EVE1_CDOFFS 0x0000
51 #define DRA7XX_CM_CORE_AON_EVE2_EVE2_CDOFFS 0x0000
52 #define DRA7XX_CM_CORE_AON_EVE3_EVE3_CDOFFS 0x0000
53 #define DRA7XX_CM_CORE_AON_EVE4_EVE4_CDOFFS 0x0000
54 #define DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS 0x0000
55 #define DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS 0x0000
59 /* CM_CORE_AON.OCP_SOCKET_CM_CORE_AON register offsets */
60 #define DRA7XX_REVISION_CM_CORE_AON_OFFSET 0x0000
61 #define DRA7XX_CM_CM_CORE_AON_PROFILING_CLKCTRL_OFFSET 0x0040
62 #define DRA7XX_CM_CM_CORE_AON_PROFILING_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_OCP_SOCKET_INST, 0x0040)
63 #define DRA7XX_CM_CORE_AON_DEBUG_OUT_OFFSET 0x00ec
64 #define DRA7XX_CM_CORE_AON_DEBUG_CFG0_OFFSET 0x00f0
65 #define DRA7XX_CM_CORE_AON_DEBUG_CFG1_OFFSET 0x00f4
66 #define DRA7XX_CM_CORE_AON_DEBUG_CFG2_OFFSET 0x00f8
67 #define DRA7XX_CM_CORE_AON_DEBUG_CFG3_OFFSET 0x00fc
69 /* CM_CORE_AON.CKGEN_CM_CORE_AON register offsets */
70 #define DRA7XX_CM_CLKSEL_CORE_OFFSET 0x0000
71 #define DRA7XX_CM_CLKSEL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0000)
72 #define DRA7XX_CM_CLKSEL_ABE_OFFSET 0x0008
73 #define DRA7XX_CM_CLKSEL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0008)
74 #define DRA7XX_CM_DLL_CTRL_OFFSET 0x0010
75 #define DRA7XX_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020
76 #define DRA7XX_CM_CLKMODE_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0020)
77 #define DRA7XX_CM_IDLEST_DPLL_CORE_OFFSET 0x0024
78 #define DRA7XX_CM_IDLEST_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0024)
79 #define DRA7XX_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028
80 #define DRA7XX_CM_AUTOIDLE_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0028)
81 #define DRA7XX_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c
82 #define DRA7XX_CM_CLKSEL_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x002c)
83 #define DRA7XX_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030
84 #define DRA7XX_CM_DIV_M2_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0030)
85 #define DRA7XX_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034
86 #define DRA7XX_CM_DIV_M3_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0034)
87 #define DRA7XX_CM_DIV_H11_DPLL_CORE_OFFSET 0x0038
88 #define DRA7XX_CM_DIV_H11_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0038)
89 #define DRA7XX_CM_DIV_H12_DPLL_CORE_OFFSET 0x003c
90 #define DRA7XX_CM_DIV_H12_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x003c)
91 #define DRA7XX_CM_DIV_H13_DPLL_CORE_OFFSET 0x0040
92 #define DRA7XX_CM_DIV_H13_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0040)
93 #define DRA7XX_CM_DIV_H14_DPLL_CORE_OFFSET 0x0044
94 #define DRA7XX_CM_DIV_H14_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0044)
95 #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048
96 #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c
97 #define DRA7XX_CM_DIV_H21_DPLL_CORE_OFFSET 0x0050
98 #define DRA7XX_CM_DIV_H21_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0050)
99 #define DRA7XX_CM_DIV_H22_DPLL_CORE_OFFSET 0x0054
100 #define DRA7XX_CM_DIV_H22_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0054)
101 #define DRA7XX_CM_DIV_H23_DPLL_CORE_OFFSET 0x0058
102 #define DRA7XX_CM_DIV_H23_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0058)
103 #define DRA7XX_CM_DIV_H24_DPLL_CORE_OFFSET 0x005c
104 #define DRA7XX_CM_DIV_H24_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x005c)
105 #define DRA7XX_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060
106 #define DRA7XX_CM_CLKMODE_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0060)
107 #define DRA7XX_CM_IDLEST_DPLL_MPU_OFFSET 0x0064
108 #define DRA7XX_CM_IDLEST_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0064)
109 #define DRA7XX_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068
110 #define DRA7XX_CM_AUTOIDLE_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0068)
111 #define DRA7XX_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c
112 #define DRA7XX_CM_CLKSEL_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x006c)
113 #define DRA7XX_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070
114 #define DRA7XX_CM_DIV_M2_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0070)
115 #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088
116 #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c
117 #define DRA7XX_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c
118 #define DRA7XX_CM_BYPCLK_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x009c)
119 #define DRA7XX_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0
120 #define DRA7XX_CM_CLKMODE_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a0)
121 #define DRA7XX_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4
122 #define DRA7XX_CM_IDLEST_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a4)
123 #define DRA7XX_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8
124 #define DRA7XX_CM_AUTOIDLE_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a8)
125 #define DRA7XX_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac
126 #define DRA7XX_CM_CLKSEL_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00ac)
127 #define DRA7XX_CM_DIV_M2_DPLL_IVA_OFFSET 0x00b0
128 #define DRA7XX_CM_DIV_M2_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00b0)
129 #define DRA7XX_CM_DIV_M3_DPLL_IVA_OFFSET 0x00b4
130 #define DRA7XX_CM_DIV_M3_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00b4)
131 #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8
132 #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc
133 #define DRA7XX_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc
134 #define DRA7XX_CM_BYPCLK_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00dc)
135 #define DRA7XX_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0
136 #define DRA7XX_CM_CLKMODE_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e0)
137 #define DRA7XX_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4
138 #define DRA7XX_CM_IDLEST_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e4)
139 #define DRA7XX_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8
140 #define DRA7XX_CM_AUTOIDLE_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e8)
141 #define DRA7XX_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec
142 #define DRA7XX_CM_CLKSEL_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00ec)
143 #define DRA7XX_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0
144 #define DRA7XX_CM_DIV_M2_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00f0)
145 #define DRA7XX_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4
146 #define DRA7XX_CM_DIV_M3_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00f4)
147 #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108
148 #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c
149 #define DRA7XX_CM_CLKMODE_DPLL_DDR_OFFSET 0x0110
150 #define DRA7XX_CM_CLKMODE_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0110)
151 #define DRA7XX_CM_IDLEST_DPLL_DDR_OFFSET 0x0114
152 #define DRA7XX_CM_IDLEST_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0114)
153 #define DRA7XX_CM_AUTOIDLE_DPLL_DDR_OFFSET 0x0118
154 #define DRA7XX_CM_AUTOIDLE_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0118)
155 #define DRA7XX_CM_CLKSEL_DPLL_DDR_OFFSET 0x011c
156 #define DRA7XX_CM_CLKSEL_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x011c)
157 #define DRA7XX_CM_DIV_M2_DPLL_DDR_OFFSET 0x0120
158 #define DRA7XX_CM_DIV_M2_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0120)
159 #define DRA7XX_CM_DIV_M3_DPLL_DDR_OFFSET 0x0124
160 #define DRA7XX_CM_DIV_M3_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0124)
161 #define DRA7XX_CM_DIV_H11_DPLL_DDR_OFFSET 0x0128
162 #define DRA7XX_CM_DIV_H11_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0128)
163 #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_DDR_OFFSET 0x012c
164 #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_DDR_OFFSET 0x0130
165 #define DRA7XX_CM_CLKMODE_DPLL_DSP_OFFSET 0x0134
166 #define DRA7XX_CM_CLKMODE_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0134)
167 #define DRA7XX_CM_IDLEST_DPLL_DSP_OFFSET 0x0138
168 #define DRA7XX_CM_IDLEST_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0138)
169 #define DRA7XX_CM_AUTOIDLE_DPLL_DSP_OFFSET 0x013c
170 #define DRA7XX_CM_AUTOIDLE_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x013c)
171 #define DRA7XX_CM_CLKSEL_DPLL_DSP_OFFSET 0x0140
172 #define DRA7XX_CM_CLKSEL_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0140)
173 #define DRA7XX_CM_DIV_M2_DPLL_DSP_OFFSET 0x0144
174 #define DRA7XX_CM_DIV_M2_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0144)
175 #define DRA7XX_CM_DIV_M3_DPLL_DSP_OFFSET 0x0148
176 #define DRA7XX_CM_DIV_M3_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0148)
177 #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_DSP_OFFSET 0x014c
178 #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_DSP_OFFSET 0x0150
179 #define DRA7XX_CM_BYPCLK_DPLL_DSP_OFFSET 0x0154
180 #define DRA7XX_CM_BYPCLK_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0154)
181 #define DRA7XX_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160
182 #define DRA7XX_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164
183 #define DRA7XX_CM_DYN_DEP_PRESCAL_OFFSET 0x0170
184 #define DRA7XX_CM_RESTORE_ST_OFFSET 0x0180
185 #define DRA7XX_CM_CLKMODE_DPLL_EVE_OFFSET 0x0184
186 #define DRA7XX_CM_CLKMODE_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0184)
187 #define DRA7XX_CM_IDLEST_DPLL_EVE_OFFSET 0x0188
188 #define DRA7XX_CM_IDLEST_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0188)
189 #define DRA7XX_CM_AUTOIDLE_DPLL_EVE_OFFSET 0x018c
190 #define DRA7XX_CM_AUTOIDLE_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x018c)
191 #define DRA7XX_CM_CLKSEL_DPLL_EVE_OFFSET 0x0190
192 #define DRA7XX_CM_CLKSEL_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0190)
193 #define DRA7XX_CM_DIV_M2_DPLL_EVE_OFFSET 0x0194
194 #define DRA7XX_CM_DIV_M2_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0194)
195 #define DRA7XX_CM_DIV_M3_DPLL_EVE_OFFSET 0x0198
196 #define DRA7XX_CM_DIV_M3_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0198)
197 #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_EVE_OFFSET 0x019c
198 #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_EVE_OFFSET 0x01a0
199 #define DRA7XX_CM_BYPCLK_DPLL_EVE_OFFSET 0x01a4
200 #define DRA7XX_CM_BYPCLK_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01a4)
201 #define DRA7XX_CM_CLKMODE_DPLL_GMAC_OFFSET 0x01a8
202 #define DRA7XX_CM_CLKMODE_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01a8)
203 #define DRA7XX_CM_IDLEST_DPLL_GMAC_OFFSET 0x01ac
204 #define DRA7XX_CM_IDLEST_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01ac)
205 #define DRA7XX_CM_AUTOIDLE_DPLL_GMAC_OFFSET 0x01b0
206 #define DRA7XX_CM_AUTOIDLE_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b0)
207 #define DRA7XX_CM_CLKSEL_DPLL_GMAC_OFFSET 0x01b4
208 #define DRA7XX_CM_CLKSEL_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b4)
209 #define DRA7XX_CM_DIV_M2_DPLL_GMAC_OFFSET 0x01b8
210 #define DRA7XX_CM_DIV_M2_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b8)
211 #define DRA7XX_CM_DIV_M3_DPLL_GMAC_OFFSET 0x01bc
212 #define DRA7XX_CM_DIV_M3_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01bc)
213 #define DRA7XX_CM_DIV_H11_DPLL_GMAC_OFFSET 0x01c0
214 #define DRA7XX_CM_DIV_H11_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c0)
215 #define DRA7XX_CM_DIV_H12_DPLL_GMAC_OFFSET 0x01c4
216 #define DRA7XX_CM_DIV_H12_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c4)
217 #define DRA7XX_CM_DIV_H13_DPLL_GMAC_OFFSET 0x01c8
218 #define DRA7XX_CM_DIV_H13_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c8)
219 #define DRA7XX_CM_DIV_H14_DPLL_GMAC_OFFSET 0x01cc
220 #define DRA7XX_CM_DIV_H14_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01cc)
221 #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_GMAC_OFFSET 0x01d0
222 #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_GMAC_OFFSET 0x01d4
223 #define DRA7XX_CM_CLKMODE_DPLL_GPU_OFFSET 0x01d8
224 #define DRA7XX_CM_CLKMODE_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01d8)
225 #define DRA7XX_CM_IDLEST_DPLL_GPU_OFFSET 0x01dc
226 #define DRA7XX_CM_IDLEST_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01dc)
227 #define DRA7XX_CM_AUTOIDLE_DPLL_GPU_OFFSET 0x01e0
228 #define DRA7XX_CM_AUTOIDLE_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e0)
229 #define DRA7XX_CM_CLKSEL_DPLL_GPU_OFFSET 0x01e4
230 #define DRA7XX_CM_CLKSEL_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e4)
231 #define DRA7XX_CM_DIV_M2_DPLL_GPU_OFFSET 0x01e8
232 #define DRA7XX_CM_DIV_M2_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e8)
233 #define DRA7XX_CM_DIV_M3_DPLL_GPU_OFFSET 0x01ec
234 #define DRA7XX_CM_DIV_M3_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01ec)
235 #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_GPU_OFFSET 0x01f0
236 #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_GPU_OFFSET 0x01f4
238 /* CM_CORE_AON.MPU_CM_CORE_AON register offsets */
239 #define DRA7XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000
240 #define DRA7XX_CM_MPU_STATICDEP_OFFSET 0x0004
241 #define DRA7XX_CM_MPU_DYNAMICDEP_OFFSET 0x0008
242 #define DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020
243 #define DRA7XX_CM_MPU_MPU_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_MPU_INST, 0x0020)
244 #define DRA7XX_CM_MPU_MPU_MPU_DBG_CLKCTRL_OFFSET 0x0028
245 #define DRA7XX_CM_MPU_MPU_MPU_DBG_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_MPU_INST, 0x0028)
247 /* CM_CORE_AON.DSP1_CM_CORE_AON register offsets */
248 #define DRA7XX_CM_DSP1_CLKSTCTRL_OFFSET 0x0000
249 #define DRA7XX_CM_DSP1_STATICDEP_OFFSET 0x0004
250 #define DRA7XX_CM_DSP1_DYNAMICDEP_OFFSET 0x0008
251 #define DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET 0x0020
252 #define DRA7XX_CM_DSP1_DSP1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_DSP1_INST, 0x0020)
254 /* CM_CORE_AON.IPU_CM_CORE_AON register offsets */
255 #define DRA7XX_CM_IPU1_CLKSTCTRL_OFFSET 0x0000
256 #define DRA7XX_CM_IPU1_STATICDEP_OFFSET 0x0004
257 #define DRA7XX_CM_IPU1_DYNAMICDEP_OFFSET 0x0008
258 #define DRA7XX_CM_IPU1_IPU1_CLKCTRL_OFFSET 0x0020
259 #define DRA7XX_CM_IPU1_IPU1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0020)
260 #define DRA7XX_CM_IPU_CLKSTCTRL_OFFSET 0x0040
261 #define DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET 0x0050
262 #define DRA7XX_CM_IPU_MCASP1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0050)
263 #define DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET 0x0058
264 #define DRA7XX_CM_IPU_TIMER5_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0058)
265 #define DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET 0x0060
266 #define DRA7XX_CM_IPU_TIMER6_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0060)
267 #define DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET 0x0068
268 #define DRA7XX_CM_IPU_TIMER7_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0068)
269 #define DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET 0x0070
270 #define DRA7XX_CM_IPU_TIMER8_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0070)
271 #define DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET 0x0078
272 #define DRA7XX_CM_IPU_I2C5_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0078)
273 #define DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET 0x0080
274 #define DRA7XX_CM_IPU_UART6_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0080)
276 /* CM_CORE_AON.DSP2_CM_CORE_AON register offsets */
277 #define DRA7XX_CM_DSP2_CLKSTCTRL_OFFSET 0x0000
278 #define DRA7XX_CM_DSP2_STATICDEP_OFFSET 0x0004
279 #define DRA7XX_CM_DSP2_DYNAMICDEP_OFFSET 0x0008
280 #define DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET 0x0020
281 #define DRA7XX_CM_DSP2_DSP2_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_DSP2_INST, 0x0020)
283 /* CM_CORE_AON.EVE1_CM_CORE_AON register offsets */
284 #define DRA7XX_CM_EVE1_CLKSTCTRL_OFFSET 0x0000
285 #define DRA7XX_CM_EVE1_STATICDEP_OFFSET 0x0004
286 #define DRA7XX_CM_EVE1_EVE1_CLKCTRL_OFFSET 0x0020
287 #define DRA7XX_CM_EVE1_EVE1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE1_INST, 0x0020)
289 /* CM_CORE_AON.EVE2_CM_CORE_AON register offsets */
290 #define DRA7XX_CM_EVE2_CLKSTCTRL_OFFSET 0x0000
291 #define DRA7XX_CM_EVE2_STATICDEP_OFFSET 0x0004
292 #define DRA7XX_CM_EVE2_EVE2_CLKCTRL_OFFSET 0x0020
293 #define DRA7XX_CM_EVE2_EVE2_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE2_INST, 0x0020)
295 /* CM_CORE_AON.EVE3_CM_CORE_AON register offsets */
296 #define DRA7XX_CM_EVE3_CLKSTCTRL_OFFSET 0x0000
297 #define DRA7XX_CM_EVE3_STATICDEP_OFFSET 0x0004
298 #define DRA7XX_CM_EVE3_EVE3_CLKCTRL_OFFSET 0x0020
299 #define DRA7XX_CM_EVE3_EVE3_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE3_INST, 0x0020)
301 /* CM_CORE_AON.EVE4_CM_CORE_AON register offsets */
302 #define DRA7XX_CM_EVE4_CLKSTCTRL_OFFSET 0x0000
303 #define DRA7XX_CM_EVE4_STATICDEP_OFFSET 0x0004
304 #define DRA7XX_CM_EVE4_EVE4_CLKCTRL_OFFSET 0x0020
305 #define DRA7XX_CM_EVE4_EVE4_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE4_INST, 0x0020)
307 /* CM_CORE_AON.RTC_CM_CORE_AON register offsets */
308 #define DRA7XX_CM_RTC_CLKSTCTRL_OFFSET 0x0000
309 #define DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET 0x0004
310 #define DRA7XX_CM_RTC_RTCSS_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_RTC_INST, 0x0004)
312 /* CM_CORE_AON.VPE_CM_CORE_AON register offsets */
313 #define DRA7XX_CM_VPE_CLKSTCTRL_OFFSET 0x0000
314 #define DRA7XX_CM_VPE_VPE_CLKCTRL_OFFSET 0x0004
315 #define DRA7XX_CM_VPE_VPE_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_VPE_INST, 0x0004)
316 #define DRA7XX_CM_VPE_STATICDEP_OFFSET 0x0008