arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
   4  *
   5  * Copyright (C) 2011 Nokia Corporation
   6  * Paul Walmsley
   7  */
   8
   9 #include <linux/types.h>
  10
  11 #include "omap_hwmod.h"
  12 #include "omap_hwmod_common_data.h"
  13 #include "cm-regbits-24xx.h"
  14 #include "prm-regbits-24xx.h"
  15 #include "wd_timer.h"
  16
  17 /*
  18  * 'dispc' class
  19  * display controller
  20  */
  21
  22 static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
  23         .rev_offs       = 0x0000,
  24         .sysc_offs      = 0x0010,
  25         .syss_offs      = 0x0014,
  26         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
  27                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
  28         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  29                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
  30         .sysc_fields    = &omap_hwmod_sysc_type1,
  31 };
  32
  33 struct omap_hwmod_class omap2_dispc_hwmod_class = {
  34         .name   = "dispc",
  35         .sysc   = &omap2_dispc_sysc,
  36 };
  37
  38 /* OMAP2xxx Timer Common */
  39 static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
  40         .rev_offs       = 0x0000,
  41         .sysc_offs      = 0x0010,
  42         .syss_offs      = 0x0014,
  43         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
  44                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
  45                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
  46         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  47         .sysc_fields    = &omap_hwmod_sysc_type1,
  48 };
  49
  50 struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
  51         .name   = "timer",
  52         .sysc   = &omap2xxx_timer_sysc,
  53 };
  54
  55 /*
  56  * 'wd_timer' class
  57  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
  58  * overflow condition
  59  */
  60
  61 static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
  62         .rev_offs       = 0x0000,
  63         .sysc_offs      = 0x0010,
  64         .syss_offs      = 0x0014,
  65         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
  66                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
  67         .sysc_fields    = &omap_hwmod_sysc_type1,
  68 };
  69
  70 struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
  71         .name           = "wd_timer",
  72         .sysc           = &omap2xxx_wd_timer_sysc,
  73         .pre_shutdown   = &omap2_wd_timer_disable,
  74         .reset          = &omap2_wd_timer_reset,
  75 };
  76
  77 /*
  78  * 'gpio' class
  79  * general purpose io module
  80  */
  81 static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
  82         .rev_offs       = 0x0000,
  83         .sysc_offs      = 0x0010,
  84         .syss_offs      = 0x0014,
  85         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
  86                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
  87                            SYSS_HAS_RESET_STATUS),
  88         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  89         .sysc_fields    = &omap_hwmod_sysc_type1,
  90 };
  91
  92 struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
  93         .name = "gpio",
  94         .sysc = &omap2xxx_gpio_sysc,
  95 };
  96
  97 /*
  98  * 'mailbox' class
  99  * mailbox module allowing communication between the on-chip processors
 100  * using a queued mailbox-interrupt mechanism.
 101  */
 102
 103 static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
 104         .rev_offs       = 0x000,
 105         .sysc_offs      = 0x010,
 106         .syss_offs      = 0x014,
 107         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 108                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 109         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 110         .sysc_fields    = &omap_hwmod_sysc_type1,
 111 };
 112
 113 struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
 114         .name   = "mailbox",
 115         .sysc   = &omap2xxx_mailbox_sysc,
 116 };
 117
 118 /*
 119  * 'mcspi' class
 120  * multichannel serial port interface (mcspi) / master/slave synchronous serial
 121  * bus
 122  */
 123
 124 static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
 125         .rev_offs       = 0x0000,
 126         .sysc_offs      = 0x0010,
 127         .syss_offs      = 0x0014,
 128         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 129                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 130                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 131         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 132         .sysc_fields    = &omap_hwmod_sysc_type1,
 133 };
 134
 135 struct omap_hwmod_class omap2xxx_mcspi_class = {
 136         .name   = "mcspi",
 137         .sysc   = &omap2xxx_mcspi_sysc,
 138 };
 139
 140 /*
 141  * 'gpmc' class
 142  * general purpose memory controller
 143  */
 144
 145 static struct omap_hwmod_class_sysconfig omap2xxx_gpmc_sysc = {
 146         .rev_offs       = 0x0000,
 147         .sysc_offs      = 0x0010,
 148         .syss_offs      = 0x0014,
 149         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 150                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 151         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 152         .sysc_fields    = &omap_hwmod_sysc_type1,
 153 };
 154
 155 static struct omap_hwmod_class omap2xxx_gpmc_hwmod_class = {
 156         .name   = "gpmc",
 157         .sysc   = &omap2xxx_gpmc_sysc,
 158 };
 159
 160 /*
 161  * IP blocks
 162  */
 163
 164 /* L3 */
 165 struct omap_hwmod omap2xxx_l3_main_hwmod = {
 166         .name           = "l3_main",
 167         .class          = &l3_hwmod_class,
 168         .flags          = HWMOD_NO_IDLEST,
 169 };
 170
 171 /* L4 CORE */
 172 struct omap_hwmod omap2xxx_l4_core_hwmod = {
 173         .name           = "l4_core",
 174         .class          = &l4_hwmod_class,
 175         .flags          = HWMOD_NO_IDLEST,
 176 };
 177
 178 /* L4 WKUP */
 179 struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
 180         .name           = "l4_wkup",
 181         .class          = &l4_hwmod_class,
 182         .flags          = HWMOD_NO_IDLEST,
 183 };
 184
 185 /* MPU */
 186 struct omap_hwmod omap2xxx_mpu_hwmod = {
 187         .name           = "mpu",
 188         .class          = &mpu_hwmod_class,
 189         .main_clk       = "mpu_ck",
 190 };
 191
 192 /* IVA2 */
 193 struct omap_hwmod omap2xxx_iva_hwmod = {
 194         .name           = "iva",
 195         .class          = &iva_hwmod_class,
 196 };
 197
 198 /* timer1 */
 199 struct omap_hwmod omap2xxx_timer1_hwmod = {
 200         .name           = "timer1",
 201         .main_clk       = "gpt1_fck",
 202         .prcm           = {
 203                 .omap2 = {
 204                         .module_offs = WKUP_MOD,
 205                         .idlest_reg_id = 1,
 206                         .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
 207                 },
 208         },
 209         .class          = &omap2xxx_timer_hwmod_class,
 210         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 211 };
 212
 213 /* timer2 */
 214 struct omap_hwmod omap2xxx_timer2_hwmod = {
 215         .name           = "timer2",
 216         .main_clk       = "gpt2_fck",
 217         .prcm           = {
 218                 .omap2 = {
 219                         .module_offs = CORE_MOD,
 220                         .idlest_reg_id = 1,
 221                         .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
 222                 },
 223         },
 224         .class          = &omap2xxx_timer_hwmod_class,
 225         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 226 };
 227
 228 /* timer3 */
 229 struct omap_hwmod omap2xxx_timer3_hwmod = {
 230         .name           = "timer3",
 231         .main_clk       = "gpt3_fck",
 232         .prcm           = {
 233                 .omap2 = {
 234                         .module_offs = CORE_MOD,
 235                         .idlest_reg_id = 1,
 236                         .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
 237                 },
 238         },
 239         .class          = &omap2xxx_timer_hwmod_class,
 240         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 241 };
 242
 243 /* timer4 */
 244 struct omap_hwmod omap2xxx_timer4_hwmod = {
 245         .name           = "timer4",
 246         .main_clk       = "gpt4_fck",
 247         .prcm           = {
 248                 .omap2 = {
 249                         .module_offs = CORE_MOD,
 250                         .idlest_reg_id = 1,
 251                         .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
 252                 },
 253         },
 254         .class          = &omap2xxx_timer_hwmod_class,
 255         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 256 };
 257
 258 /* timer5 */
 259 struct omap_hwmod omap2xxx_timer5_hwmod = {
 260         .name           = "timer5",
 261         .main_clk       = "gpt5_fck",
 262         .prcm           = {
 263                 .omap2 = {
 264                         .module_offs = CORE_MOD,
 265                         .idlest_reg_id = 1,
 266                         .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
 267                 },
 268         },
 269         .class          = &omap2xxx_timer_hwmod_class,
 270         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 271 };
 272
 273 /* timer6 */
 274 struct omap_hwmod omap2xxx_timer6_hwmod = {
 275         .name           = "timer6",
 276         .main_clk       = "gpt6_fck",
 277         .prcm           = {
 278                 .omap2 = {
 279                         .module_offs = CORE_MOD,
 280                         .idlest_reg_id = 1,
 281                         .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
 282                 },
 283         },
 284         .class          = &omap2xxx_timer_hwmod_class,
 285         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 286 };
 287
 288 /* timer7 */
 289 struct omap_hwmod omap2xxx_timer7_hwmod = {
 290         .name           = "timer7",
 291         .main_clk       = "gpt7_fck",
 292         .prcm           = {
 293                 .omap2 = {
 294                         .module_offs = CORE_MOD,
 295                         .idlest_reg_id = 1,
 296                         .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
 297                 },
 298         },
 299         .class          = &omap2xxx_timer_hwmod_class,
 300         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 301 };
 302
 303 /* timer8 */
 304 struct omap_hwmod omap2xxx_timer8_hwmod = {
 305         .name           = "timer8",
 306         .main_clk       = "gpt8_fck",
 307         .prcm           = {
 308                 .omap2 = {
 309                         .module_offs = CORE_MOD,
 310                         .idlest_reg_id = 1,
 311                         .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
 312                 },
 313         },
 314         .class          = &omap2xxx_timer_hwmod_class,
 315         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 316 };
 317
 318 /* timer9 */
 319 struct omap_hwmod omap2xxx_timer9_hwmod = {
 320         .name           = "timer9",
 321         .main_clk       = "gpt9_fck",
 322         .prcm           = {
 323                 .omap2 = {
 324                         .module_offs = CORE_MOD,
 325                         .idlest_reg_id = 1,
 326                         .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
 327                 },
 328         },
 329         .class          = &omap2xxx_timer_hwmod_class,
 330         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 331 };
 332
 333 /* timer10 */
 334 struct omap_hwmod omap2xxx_timer10_hwmod = {
 335         .name           = "timer10",
 336         .main_clk       = "gpt10_fck",
 337         .prcm           = {
 338                 .omap2 = {
 339                         .module_offs = CORE_MOD,
 340                         .idlest_reg_id = 1,
 341                         .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
 342                 },
 343         },
 344         .class          = &omap2xxx_timer_hwmod_class,
 345         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 346 };
 347
 348 /* timer11 */
 349 struct omap_hwmod omap2xxx_timer11_hwmod = {
 350         .name           = "timer11",
 351         .main_clk       = "gpt11_fck",
 352         .prcm           = {
 353                 .omap2 = {
 354                         .module_offs = CORE_MOD,
 355                         .idlest_reg_id = 1,
 356                         .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
 357                 },
 358         },
 359         .class          = &omap2xxx_timer_hwmod_class,
 360         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 361 };
 362
 363 /* timer12 */
 364 struct omap_hwmod omap2xxx_timer12_hwmod = {
 365         .name           = "timer12",
 366         .main_clk       = "gpt12_fck",
 367         .prcm           = {
 368                 .omap2 = {
 369                         .module_offs = CORE_MOD,
 370                         .idlest_reg_id = 1,
 371                         .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
 372                 },
 373         },
 374         .class          = &omap2xxx_timer_hwmod_class,
 375         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 376 };
 377
 378 /* wd_timer2 */
 379 struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
 380         .name           = "wd_timer2",
 381         .class          = &omap2xxx_wd_timer_hwmod_class,
 382         .main_clk       = "mpu_wdt_fck",
 383         .prcm           = {
 384                 .omap2 = {
 385                         .module_offs = WKUP_MOD,
 386                         .idlest_reg_id = 1,
 387                         .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
 388                 },
 389         },
 390 };
 391
 392 /* UART1 */
 393
 394 struct omap_hwmod omap2xxx_uart1_hwmod = {
 395         .name           = "uart1",
 396         .main_clk       = "uart1_fck",
 397         .flags          = DEBUG_OMAP2UART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
 398         .prcm           = {
 399                 .omap2 = {
 400                         .module_offs = CORE_MOD,
 401                         .idlest_reg_id = 1,
 402                         .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
 403                 },
 404         },
 405         .class          = &omap2_uart_class,
 406 };
 407
 408 /* UART2 */
 409
 410 struct omap_hwmod omap2xxx_uart2_hwmod = {
 411         .name           = "uart2",
 412         .main_clk       = "uart2_fck",
 413         .flags          = DEBUG_OMAP2UART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
 414         .prcm           = {
 415                 .omap2 = {
 416                         .module_offs = CORE_MOD,
 417                         .idlest_reg_id = 1,
 418                         .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
 419                 },
 420         },
 421         .class          = &omap2_uart_class,
 422 };
 423
 424 /* UART3 */
 425
 426 struct omap_hwmod omap2xxx_uart3_hwmod = {
 427         .name           = "uart3",
 428         .main_clk       = "uart3_fck",
 429         .flags          = DEBUG_OMAP2UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
 430         .prcm           = {
 431                 .omap2 = {
 432                         .module_offs = CORE_MOD,
 433                         .idlest_reg_id = 2,
 434                         .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
 435                 },
 436         },
 437         .class          = &omap2_uart_class,
 438 };
 439
 440 /* dss */
 441
 442 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 443         /*
 444          * The DSS HW needs all DSS clocks enabled during reset. The dss_core
 445          * driver does not use these clocks.
 446          */
 447         { .role = "tv_clk", .clk = "dss_54m_fck" },
 448         { .role = "sys_clk", .clk = "dss2_fck" },
 449 };
 450
 451 struct omap_hwmod omap2xxx_dss_core_hwmod = {
 452         .name           = "dss_core",
 453         .class          = &omap2_dss_hwmod_class,
 454         .main_clk       = "dss1_fck", /* instead of dss_fck */
 455         .prcm           = {
 456                 .omap2 = {
 457                         .module_offs = CORE_MOD,
 458                         .idlest_reg_id = 1,
 459                 },
 460         },
 461         .opt_clks       = dss_opt_clks,
 462         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 463         .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 464 };
 465
 466 struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
 467         .name           = "dss_dispc",
 468         .class          = &omap2_dispc_hwmod_class,
 469         .main_clk       = "dss1_fck",
 470         .prcm           = {
 471                 .omap2 = {
 472                         .module_offs = CORE_MOD,
 473                         .idlest_reg_id = 1,
 474                 },
 475         },
 476         .flags          = HWMOD_NO_IDLEST,
 477         .dev_attr       = &omap2_3_dss_dispc_dev_attr,
 478 };
 479
 480 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 481         { .role = "ick", .clk = "dss_ick" },
 482 };
 483
 484 struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
 485         .name           = "dss_rfbi",
 486         .class          = &omap2_rfbi_hwmod_class,
 487         .main_clk       = "dss1_fck",
 488         .prcm           = {
 489                 .omap2 = {
 490                         .module_offs = CORE_MOD,
 491                 },
 492         },
 493         .opt_clks       = dss_rfbi_opt_clks,
 494         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 495         .flags          = HWMOD_NO_IDLEST,
 496 };
 497
 498 struct omap_hwmod omap2xxx_dss_venc_hwmod = {
 499         .name           = "dss_venc",
 500         .class          = &omap2_venc_hwmod_class,
 501         .main_clk       = "dss_54m_fck",
 502         .prcm           = {
 503                 .omap2 = {
 504                         .module_offs = CORE_MOD,
 505                 },
 506         },
 507         .flags          = HWMOD_NO_IDLEST,
 508 };
 509
 510 /* gpio1 */
 511 struct omap_hwmod omap2xxx_gpio1_hwmod = {
 512         .name           = "gpio1",
 513         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 514         .main_clk       = "gpios_fck",
 515         .prcm           = {
 516                 .omap2 = {
 517                         .module_offs = WKUP_MOD,
 518                         .idlest_reg_id = 1,
 519                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 520                 },
 521         },
 522         .class          = &omap2xxx_gpio_hwmod_class,
 523 };
 524
 525 /* gpio2 */
 526 struct omap_hwmod omap2xxx_gpio2_hwmod = {
 527         .name           = "gpio2",
 528         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 529         .main_clk       = "gpios_fck",
 530         .prcm           = {
 531                 .omap2 = {
 532                         .module_offs = WKUP_MOD,
 533                         .idlest_reg_id = 1,
 534                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 535                 },
 536         },
 537         .class          = &omap2xxx_gpio_hwmod_class,
 538 };
 539
 540 /* gpio3 */
 541 struct omap_hwmod omap2xxx_gpio3_hwmod = {
 542         .name           = "gpio3",
 543         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 544         .main_clk       = "gpios_fck",
 545         .prcm           = {
 546                 .omap2 = {
 547                         .module_offs = WKUP_MOD,
 548                         .idlest_reg_id = 1,
 549                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 550                 },
 551         },
 552         .class          = &omap2xxx_gpio_hwmod_class,
 553 };
 554
 555 /* gpio4 */
 556 struct omap_hwmod omap2xxx_gpio4_hwmod = {
 557         .name           = "gpio4",
 558         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 559         .main_clk       = "gpios_fck",
 560         .prcm           = {
 561                 .omap2 = {
 562                         .module_offs = WKUP_MOD,
 563                         .idlest_reg_id = 1,
 564                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 565                 },
 566         },
 567         .class          = &omap2xxx_gpio_hwmod_class,
 568 };
 569
 570 /* mcspi1 */
 571 struct omap_hwmod omap2xxx_mcspi1_hwmod = {
 572         .name           = "mcspi1",
 573         .main_clk       = "mcspi1_fck",
 574         .prcm           = {
 575                 .omap2 = {
 576                         .module_offs = CORE_MOD,
 577                         .idlest_reg_id = 1,
 578                         .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
 579                 },
 580         },
 581         .class          = &omap2xxx_mcspi_class,
 582 };
 583
 584 /* mcspi2 */
 585 struct omap_hwmod omap2xxx_mcspi2_hwmod = {
 586         .name           = "mcspi2",
 587         .main_clk       = "mcspi2_fck",
 588         .prcm           = {
 589                 .omap2 = {
 590                         .module_offs = CORE_MOD,
 591                         .idlest_reg_id = 1,
 592                         .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
 593                 },
 594         },
 595         .class          = &omap2xxx_mcspi_class,
 596 };
 597
 598 static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
 599         .name   = "counter",
 600 };
 601
 602 struct omap_hwmod omap2xxx_counter_32k_hwmod = {
 603         .name           = "counter_32k",
 604         .main_clk       = "func_32k_ck",
 605         .prcm           = {
 606                 .omap2  = {
 607                         .module_offs = WKUP_MOD,
 608                         .idlest_reg_id = 1,
 609                         .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
 610                 },
 611         },
 612         .class          = &omap2xxx_counter_hwmod_class,
 613 };
 614
 615 /* gpmc */
 616 struct omap_hwmod omap2xxx_gpmc_hwmod = {
 617         .name           = "gpmc",
 618         .class          = &omap2xxx_gpmc_hwmod_class,
 619         .main_clk       = "gpmc_fck",
 620         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
 621         .flags          = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
 622         .prcm           = {
 623                 .omap2  = {
 624                         .module_offs = CORE_MOD,
 625                 },
 626         },
 627 };
 628
 629 /* RNG */
 630
 631 static struct omap_hwmod_class_sysconfig omap2_rng_sysc = {
 632         .rev_offs       = 0x3c,
 633         .sysc_offs      = 0x40,
 634         .syss_offs      = 0x44,
 635         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 636                            SYSS_HAS_RESET_STATUS),
 637         .sysc_fields    = &omap_hwmod_sysc_type1,
 638 };
 639
 640 static struct omap_hwmod_class omap2_rng_hwmod_class = {
 641         .name           = "rng",
 642         .sysc           = &omap2_rng_sysc,
 643 };
 644
 645 struct omap_hwmod omap2xxx_rng_hwmod = {
 646         .name           = "rng",
 647         .main_clk       = "l4_ck",
 648         .prcm           = {
 649                 .omap2 = {
 650                         .module_offs = CORE_MOD,
 651                         .idlest_reg_id = 4,
 652                         .idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT,
 653                 },
 654         },
 655         /*
 656          * XXX The first read from the SYSSTATUS register of the RNG
 657          * after the SYSCONFIG SOFTRESET bit is set triggers an
 658          * imprecise external abort.  It's unclear why this happens.
 659          * Until this is analyzed, skip the IP block reset.
 660          */
 661         .flags          = HWMOD_INIT_NO_RESET,
 662         .class          = &omap2_rng_hwmod_class,
 663 };
 664
 665 /* SHAM */
 666
 667 static struct omap_hwmod_class_sysconfig omap2_sham_sysc = {
 668         .rev_offs       = 0x5c,
 669         .sysc_offs      = 0x60,
 670         .syss_offs      = 0x64,
 671         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 672                            SYSS_HAS_RESET_STATUS),
 673         .sysc_fields    = &omap_hwmod_sysc_type1,
 674 };
 675
 676 static struct omap_hwmod_class omap2xxx_sham_class = {
 677         .name   = "sham",
 678         .sysc   = &omap2_sham_sysc,
 679 };
 680
 681 struct omap_hwmod omap2xxx_sham_hwmod = {
 682         .name           = "sham",
 683         .main_clk       = "l4_ck",
 684         .prcm           = {
 685                 .omap2 = {
 686                         .module_offs = CORE_MOD,
 687                         .idlest_reg_id = 4,
 688                         .idlest_idle_bit = OMAP24XX_ST_SHA_SHIFT,
 689                 },
 690         },
 691         .class          = &omap2xxx_sham_class,
 692 };
 693
 694 /* AES */
 695
 696 static struct omap_hwmod_class_sysconfig omap2_aes_sysc = {
 697         .rev_offs       = 0x44,
 698         .sysc_offs      = 0x48,
 699         .syss_offs      = 0x4c,
 700         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 701                            SYSS_HAS_RESET_STATUS),
 702         .sysc_fields    = &omap_hwmod_sysc_type1,
 703 };
 704
 705 static struct omap_hwmod_class omap2xxx_aes_class = {
 706         .name   = "aes",
 707         .sysc   = &omap2_aes_sysc,
 708 };
 709
 710 struct omap_hwmod omap2xxx_aes_hwmod = {
 711         .name           = "aes",
 712         .main_clk       = "l4_ck",
 713         .prcm           = {
 714                 .omap2 = {
 715                         .module_offs = CORE_MOD,
 716                         .idlest_reg_id = 4,
 717                         .idlest_idle_bit = OMAP24XX_ST_AES_SHIFT,
 718                 },
 719         },
 720         .class          = &omap2xxx_aes_class,
 721 };