arch/arm/mach-omap2/omap_hwmod_43xx_data.c

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated
   3  *
   4  * Hwmod present only in AM43x and those that differ other than register
   5  * offsets as compared to AM335x.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include "omap_hwmod.h"
  18 #include "omap_hwmod_33xx_43xx_common_data.h"
  19 #include "prcm43xx.h"
  20 #include "omap_hwmod_common_data.h"
  21
  22 /* IP blocks */
  23 static struct omap_hwmod am43xx_emif_hwmod = {
  24         .name           = "emif",
  25         .class          = &am33xx_emif_hwmod_class,
  26         .clkdm_name     = "emif_clkdm",
  27         .flags          = HWMOD_INIT_NO_IDLE,
  28         .main_clk       = "dpll_ddr_m2_ck",
  29         .prcm           = {
  30                 .omap4  = {
  31                         .clkctrl_offs   = AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET,
  32                         .modulemode     = MODULEMODE_SWCTRL,
  33                 },
  34         },
  35 };
  36
  37 static struct omap_hwmod am43xx_l4_hs_hwmod = {
  38         .name           = "l4_hs",
  39         .class          = &am33xx_l4_hwmod_class,
  40         .clkdm_name     = "l3_clkdm",
  41         .flags          = HWMOD_INIT_NO_IDLE,
  42         .main_clk       = "l4hs_gclk",
  43         .prcm           = {
  44                 .omap4  = {
  45                         .clkctrl_offs   = AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET,
  46                         .modulemode     = MODULEMODE_SWCTRL,
  47                 },
  48         },
  49 };
  50
  51 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
  52         { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
  53 };
  54
  55 static struct omap_hwmod am43xx_wkup_m3_hwmod = {
  56         .name           = "wkup_m3",
  57         .class          = &am33xx_wkup_m3_hwmod_class,
  58         .clkdm_name     = "l4_wkup_aon_clkdm",
  59         /* Keep hardreset asserted */
  60         .flags          = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
  61         .main_clk       = "sys_clkin_ck",
  62         .prcm           = {
  63                 .omap4  = {
  64                         .clkctrl_offs   = AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
  65                         .rstctrl_offs   = AM43XX_RM_WKUP_RSTCTRL_OFFSET,
  66                         .rstst_offs     = AM43XX_RM_WKUP_RSTST_OFFSET,
  67                         .modulemode     = MODULEMODE_SWCTRL,
  68                 },
  69         },
  70         .rst_lines      = am33xx_wkup_m3_resets,
  71         .rst_lines_cnt  = ARRAY_SIZE(am33xx_wkup_m3_resets),
  72 };
  73
  74 static struct omap_hwmod am43xx_control_hwmod = {
  75         .name           = "control",
  76         .class          = &am33xx_control_hwmod_class,
  77         .clkdm_name     = "l4_wkup_clkdm",
  78         .flags          = HWMOD_INIT_NO_IDLE,
  79         .main_clk       = "sys_clkin_ck",
  80         .prcm           = {
  81                 .omap4  = {
  82                         .clkctrl_offs   = AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
  83                         .modulemode     = MODULEMODE_SWCTRL,
  84                 },
  85         },
  86 };
  87
  88 static struct omap_hwmod_class_sysconfig am43xx_synctimer_sysc = {
  89         .rev_offs       = 0x0,
  90         .sysc_offs      = 0x4,
  91         .sysc_flags     = SYSC_HAS_SIDLEMODE,
  92         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
  93         .sysc_fields    = &omap_hwmod_sysc_type1,
  94 };
  95
  96 static struct omap_hwmod_class am43xx_synctimer_hwmod_class = {
  97         .name   = "synctimer",
  98         .sysc   = &am43xx_synctimer_sysc,
  99 };
 100
 101 static struct omap_hwmod am43xx_synctimer_hwmod = {
 102         .name           = "counter_32k",
 103         .class          = &am43xx_synctimer_hwmod_class,
 104         .clkdm_name     = "l4_wkup_aon_clkdm",
 105         .flags          = HWMOD_SWSUP_SIDLE,
 106         .main_clk       = "synctimer_32kclk",
 107         .prcm = {
 108                 .omap4 = {
 109                         .clkctrl_offs = AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 110                         .modulemode   = MODULEMODE_SWCTRL,
 111                 },
 112         },
 113 };
 114
 115
 116 static struct omap_hwmod_class_sysconfig am43xx_usb_otg_ss_sysc = {
 117         .rev_offs       = 0x0000,
 118         .sysc_offs      = 0x0010,
 119         .sysc_flags     = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
 120                                 SYSC_HAS_SIDLEMODE),
 121         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 122                                 SIDLE_SMART_WKUP | MSTANDBY_FORCE |
 123                                 MSTANDBY_NO | MSTANDBY_SMART |
 124                                 MSTANDBY_SMART_WKUP),
 125         .sysc_fields    = &omap_hwmod_sysc_type2,
 126 };
 127
 128 static struct omap_hwmod_class am43xx_usb_otg_ss_hwmod_class = {
 129         .name   = "usb_otg_ss",
 130         .sysc   = &am43xx_usb_otg_ss_sysc,
 131 };
 132
 133 static struct omap_hwmod am43xx_usb_otg_ss0_hwmod = {
 134         .name           = "usb_otg_ss0",
 135         .class          = &am43xx_usb_otg_ss_hwmod_class,
 136         .clkdm_name     = "l3s_clkdm",
 137         .main_clk       = "l3s_gclk",
 138         .prcm = {
 139                 .omap4 = {
 140                         .clkctrl_offs   = AM43XX_CM_PER_USB_OTG_SS0_CLKCTRL_OFFSET,
 141                         .modulemode     = MODULEMODE_SWCTRL,
 142                 },
 143         },
 144 };
 145
 146 static struct omap_hwmod am43xx_usb_otg_ss1_hwmod = {
 147         .name           = "usb_otg_ss1",
 148         .class          = &am43xx_usb_otg_ss_hwmod_class,
 149         .clkdm_name     = "l3s_clkdm",
 150         .main_clk       = "l3s_gclk",
 151         .prcm = {
 152                 .omap4 = {
 153                         .clkctrl_offs   = AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET,
 154                         .modulemode     = MODULEMODE_SWCTRL,
 155                 },
 156         },
 157 };
 158
 159 /* dss */
 160
 161 static struct omap_hwmod am43xx_dss_core_hwmod = {
 162         .name           = "dss_core",
 163         .class          = &omap2_dss_hwmod_class,
 164         .clkdm_name     = "dss_clkdm",
 165         .main_clk       = "disp_clk",
 166         .prcm = {
 167                 .omap4 = {
 168                         .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
 169                         .modulemode   = MODULEMODE_SWCTRL,
 170                 },
 171         },
 172 };
 173
 174 /* dispc */
 175
 176 static struct omap_dss_dispc_dev_attr am43xx_dss_dispc_dev_attr = {
 177         .manager_count          = 1,
 178         .has_framedonetv_irq    = 0
 179 };
 180
 181 static struct omap_hwmod_class_sysconfig am43xx_dispc_sysc = {
 182         .rev_offs       = 0x0000,
 183         .sysc_offs      = 0x0010,
 184         .syss_offs      = 0x0014,
 185         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
 186                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 187                            SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_MIDLEMODE),
 188         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 189                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 190         .sysc_fields    = &omap_hwmod_sysc_type1,
 191 };
 192
 193 static struct omap_hwmod_class am43xx_dispc_hwmod_class = {
 194         .name   = "dispc",
 195         .sysc   = &am43xx_dispc_sysc,
 196 };
 197
 198 static struct omap_hwmod am43xx_dss_dispc_hwmod = {
 199         .name           = "dss_dispc",
 200         .class          = &am43xx_dispc_hwmod_class,
 201         .clkdm_name     = "dss_clkdm",
 202         .main_clk       = "disp_clk",
 203         .prcm = {
 204                 .omap4 = {
 205                         .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
 206                 },
 207         },
 208         .dev_attr       = &am43xx_dss_dispc_dev_attr,
 209         .parent_hwmod   = &am43xx_dss_core_hwmod,
 210 };
 211
 212 /* rfbi */
 213
 214 static struct omap_hwmod am43xx_dss_rfbi_hwmod = {
 215         .name           = "dss_rfbi",
 216         .class          = &omap2_rfbi_hwmod_class,
 217         .clkdm_name     = "dss_clkdm",
 218         .main_clk       = "disp_clk",
 219         .prcm = {
 220                 .omap4 = {
 221                         .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
 222                 },
 223         },
 224         .parent_hwmod   = &am43xx_dss_core_hwmod,
 225 };
 226
 227
 228 /* Interfaces */
 229 static struct omap_hwmod_ocp_if am43xx_l3_main__emif = {
 230         .master         = &am33xx_l3_main_hwmod,
 231         .slave          = &am43xx_emif_hwmod,
 232         .clk            = "dpll_core_m4_ck",
 233         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 234 };
 235
 236 static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = {
 237         .master         = &am33xx_l3_main_hwmod,
 238         .slave          = &am43xx_l4_hs_hwmod,
 239         .clk            = "l3s_gclk",
 240         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 241 };
 242
 243 static struct omap_hwmod_ocp_if am43xx_wkup_m3__l4_wkup = {
 244         .master         = &am43xx_wkup_m3_hwmod,
 245         .slave          = &am33xx_l4_wkup_hwmod,
 246         .clk            = "sys_clkin_ck",
 247         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 248 };
 249
 250 static struct omap_hwmod_ocp_if am43xx_l4_wkup__wkup_m3 = {
 251         .master         = &am33xx_l4_wkup_hwmod,
 252         .slave          = &am43xx_wkup_m3_hwmod,
 253         .clk            = "sys_clkin_ck",
 254         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 255 };
 256
 257 static struct omap_hwmod_ocp_if am43xx_l3_main__pruss = {
 258         .master         = &am33xx_l3_main_hwmod,
 259         .slave          = &am33xx_pruss_hwmod,
 260         .clk            = "dpll_core_m4_ck",
 261         .user           = OCP_USER_MPU,
 262 };
 263
 264 static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex0 = {
 265         .master         = &am33xx_l4_wkup_hwmod,
 266         .slave          = &am33xx_smartreflex0_hwmod,
 267         .clk            = "sys_clkin_ck",
 268         .user           = OCP_USER_MPU,
 269 };
 270
 271 static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex1 = {
 272         .master         = &am33xx_l4_wkup_hwmod,
 273         .slave          = &am33xx_smartreflex1_hwmod,
 274         .clk            = "sys_clkin_ck",
 275         .user           = OCP_USER_MPU,
 276 };
 277
 278 static struct omap_hwmod_ocp_if am43xx_l4_wkup__control = {
 279         .master         = &am33xx_l4_wkup_hwmod,
 280         .slave          = &am43xx_control_hwmod,
 281         .clk            = "sys_clkin_ck",
 282         .user           = OCP_USER_MPU,
 283 };
 284
 285 static struct omap_hwmod_ocp_if am43xx_l4_wkup__timer1 = {
 286         .master         = &am33xx_l4_wkup_hwmod,
 287         .slave          = &am33xx_timer1_hwmod,
 288         .clk            = "sys_clkin_ck",
 289         .user           = OCP_USER_MPU,
 290 };
 291
 292 static struct omap_hwmod_ocp_if am33xx_l4_wkup__synctimer = {
 293         .master         = &am33xx_l4_wkup_hwmod,
 294         .slave          = &am43xx_synctimer_hwmod,
 295         .clk            = "sys_clkin_ck",
 296         .user           = OCP_USER_MPU,
 297 };
 298
 299 static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss0 = {
 300         .master         = &am33xx_l3_s_hwmod,
 301         .slave          = &am43xx_usb_otg_ss0_hwmod,
 302         .clk            = "l3s_gclk",
 303         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 304 };
 305
 306 static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss1 = {
 307         .master         = &am33xx_l3_s_hwmod,
 308         .slave          = &am43xx_usb_otg_ss1_hwmod,
 309         .clk            = "l3s_gclk",
 310         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 311 };
 312
 313 static struct omap_hwmod_ocp_if am43xx_dss__l3_main = {
 314         .master         = &am43xx_dss_core_hwmod,
 315         .slave          = &am33xx_l3_main_hwmod,
 316         .clk            = "l3_gclk",
 317         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 318 };
 319
 320 static struct omap_hwmod_ocp_if am43xx_l4_ls__dss = {
 321         .master         = &am33xx_l4_ls_hwmod,
 322         .slave          = &am43xx_dss_core_hwmod,
 323         .clk            = "l4ls_gclk",
 324         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 325 };
 326
 327 static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_dispc = {
 328         .master         = &am33xx_l4_ls_hwmod,
 329         .slave          = &am43xx_dss_dispc_hwmod,
 330         .clk            = "l4ls_gclk",
 331         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 332 };
 333
 334 static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_rfbi = {
 335         .master         = &am33xx_l4_ls_hwmod,
 336         .slave          = &am43xx_dss_rfbi_hwmod,
 337         .clk            = "l4ls_gclk",
 338         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 339 };
 340
 341 static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
 342         &am33xx_l4_wkup__synctimer,
 343         &am43xx_l3_main__pruss,
 344         &am33xx_mpu__l3_main,
 345         &am33xx_mpu__prcm,
 346         &am33xx_l3_s__l4_ls,
 347         &am33xx_l3_s__l4_wkup,
 348         &am43xx_l3_main__l4_hs,
 349         &am33xx_l3_main__l3_s,
 350         &am33xx_l3_main__l3_instr,
 351         &am33xx_l3_main__gfx,
 352         &am33xx_l3_s__l3_main,
 353         &am43xx_l3_main__emif,
 354         &am33xx_pruss__l3_main,
 355         &am43xx_wkup_m3__l4_wkup,
 356         &am33xx_gfx__l3_main,
 357         &am43xx_l4_wkup__wkup_m3,
 358         &am43xx_l4_wkup__control,
 359         &am43xx_l4_wkup__smartreflex0,
 360         &am43xx_l4_wkup__smartreflex1,
 361         &am43xx_l4_wkup__timer1,
 362         &am33xx_l4_ls__timer2,
 363         &am33xx_l3_main__tpcc,
 364         &am33xx_l3_s__gpmc,
 365         &am33xx_l3_main__tptc0,
 366         &am33xx_l3_main__tptc1,
 367         &am33xx_l3_main__tptc2,
 368         &am33xx_l3_main__ocmc,
 369         &am43xx_l3_s__usbotgss0,
 370         &am43xx_l3_s__usbotgss1,
 371         &am43xx_dss__l3_main,
 372         &am43xx_l4_ls__dss,
 373         &am43xx_l4_ls__dss_dispc,
 374         &am43xx_l4_ls__dss_rfbi,
 375         NULL,
 376 };
 377
 378 static struct omap_hwmod_ocp_if *am43xx_rtc_hwmod_ocp_ifs[] __initdata = {
 379         &am33xx_l4_wkup__rtc,
 380         NULL,
 381 };
 382
 383 int __init am43xx_hwmod_init(void)
 384 {
 385         int ret;
 386
 387         omap_hwmod_am43xx_reg();
 388         omap_hwmod_init();
 389         ret = omap_hwmod_register_links(am43xx_hwmod_ocp_ifs);
 390
 391         if (!ret && of_machine_is_compatible("ti,am4372"))
 392                 ret = omap_hwmod_register_links(am43xx_rtc_hwmod_ocp_ifs);
 393
 394         return ret;
 395 }