arch/arm/mach-omap2/omap_hwmod_54xx_data.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Hardware modules present on the OMAP54xx chips
   4  *
   5  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <linux/power/smartreflex.h>
  19
  20 #include "omap_hwmod.h"
  21 #include "omap_hwmod_common_data.h"
  22 #include "cm1_54xx.h"
  23 #include "cm2_54xx.h"
  24 #include "prm54xx.h"
  25
  26 /* Base offset for all OMAP5 interrupts external to MPUSS */
  27 #define OMAP54XX_IRQ_GIC_START  32
  28
  29 /*
  30  * IP blocks
  31  */
  32
  33 /*
  34  * 'dmm' class
  35  * instance(s): dmm
  36  */
  37 static struct omap_hwmod_class omap54xx_dmm_hwmod_class = {
  38         .name   = "dmm",
  39 };
  40
  41 /* dmm */
  42 static struct omap_hwmod omap54xx_dmm_hwmod = {
  43         .name           = "dmm",
  44         .class          = &omap54xx_dmm_hwmod_class,
  45         .clkdm_name     = "emif_clkdm",
  46         .prcm = {
  47                 .omap4 = {
  48                         .clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
  49                         .context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET,
  50                 },
  51         },
  52 };
  53
  54 /*
  55  * 'l3' class
  56  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
  57  */
  58 static struct omap_hwmod_class omap54xx_l3_hwmod_class = {
  59         .name   = "l3",
  60 };
  61
  62 /* l3_instr */
  63 static struct omap_hwmod omap54xx_l3_instr_hwmod = {
  64         .name           = "l3_instr",
  65         .class          = &omap54xx_l3_hwmod_class,
  66         .clkdm_name     = "l3instr_clkdm",
  67         .prcm = {
  68                 .omap4 = {
  69                         .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  70                         .context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  71                         .modulemode   = MODULEMODE_HWCTRL,
  72                 },
  73         },
  74 };
  75
  76 /* l3_main_1 */
  77 static struct omap_hwmod omap54xx_l3_main_1_hwmod = {
  78         .name           = "l3_main_1",
  79         .class          = &omap54xx_l3_hwmod_class,
  80         .clkdm_name     = "l3main1_clkdm",
  81         .prcm = {
  82                 .omap4 = {
  83                         .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
  84                         .context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
  85                 },
  86         },
  87 };
  88
  89 /* l3_main_2 */
  90 static struct omap_hwmod omap54xx_l3_main_2_hwmod = {
  91         .name           = "l3_main_2",
  92         .class          = &omap54xx_l3_hwmod_class,
  93         .clkdm_name     = "l3main2_clkdm",
  94         .prcm = {
  95                 .omap4 = {
  96                         .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
  97                         .context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET,
  98                 },
  99         },
 100 };
 101
 102 /* l3_main_3 */
 103 static struct omap_hwmod omap54xx_l3_main_3_hwmod = {
 104         .name           = "l3_main_3",
 105         .class          = &omap54xx_l3_hwmod_class,
 106         .clkdm_name     = "l3instr_clkdm",
 107         .prcm = {
 108                 .omap4 = {
 109                         .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
 110                         .context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET,
 111                         .modulemode   = MODULEMODE_HWCTRL,
 112                 },
 113         },
 114 };
 115
 116 /*
 117  * 'l4' class
 118  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 119  */
 120 static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
 121         .name   = "l4",
 122 };
 123
 124 /* l4_abe */
 125 static struct omap_hwmod omap54xx_l4_abe_hwmod = {
 126         .name           = "l4_abe",
 127         .class          = &omap54xx_l4_hwmod_class,
 128         .clkdm_name     = "abe_clkdm",
 129         .prcm = {
 130                 .omap4 = {
 131                         .clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET,
 132                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 133                 },
 134         },
 135 };
 136
 137 /* l4_cfg */
 138 static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
 139         .name           = "l4_cfg",
 140         .class          = &omap54xx_l4_hwmod_class,
 141         .clkdm_name     = "l4cfg_clkdm",
 142         .prcm = {
 143                 .omap4 = {
 144                         .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 145                         .context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 146                 },
 147         },
 148 };
 149
 150 /* l4_per */
 151 static struct omap_hwmod omap54xx_l4_per_hwmod = {
 152         .name           = "l4_per",
 153         .class          = &omap54xx_l4_hwmod_class,
 154         .clkdm_name     = "l4per_clkdm",
 155         .prcm = {
 156                 .omap4 = {
 157                         .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
 158                         .context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 159                 },
 160         },
 161 };
 162
 163 /* l4_wkup */
 164 static struct omap_hwmod omap54xx_l4_wkup_hwmod = {
 165         .name           = "l4_wkup",
 166         .class          = &omap54xx_l4_hwmod_class,
 167         .clkdm_name     = "wkupaon_clkdm",
 168         .prcm = {
 169                 .omap4 = {
 170                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
 171                         .context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
 172                 },
 173         },
 174 };
 175
 176 /*
 177  * 'mpu_bus' class
 178  * instance(s): mpu_private
 179  */
 180 static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = {
 181         .name   = "mpu_bus",
 182 };
 183
 184 /* mpu_private */
 185 static struct omap_hwmod omap54xx_mpu_private_hwmod = {
 186         .name           = "mpu_private",
 187         .class          = &omap54xx_mpu_bus_hwmod_class,
 188         .clkdm_name     = "mpu_clkdm",
 189         .prcm = {
 190                 .omap4 = {
 191                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 192                 },
 193         },
 194 };
 195
 196 /*
 197  * 'counter' class
 198  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 199  */
 200
 201 static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = {
 202         .rev_offs       = 0x0000,
 203         .sysc_offs      = 0x0010,
 204         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 205         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 206         .sysc_fields    = &omap_hwmod_sysc_type1,
 207 };
 208
 209 static struct omap_hwmod_class omap54xx_counter_hwmod_class = {
 210         .name   = "counter",
 211         .sysc   = &omap54xx_counter_sysc,
 212 };
 213
 214 /* counter_32k */
 215 static struct omap_hwmod omap54xx_counter_32k_hwmod = {
 216         .name           = "counter_32k",
 217         .class          = &omap54xx_counter_hwmod_class,
 218         .clkdm_name     = "wkupaon_clkdm",
 219         .flags          = HWMOD_SWSUP_SIDLE,
 220         .main_clk       = "wkupaon_iclk_mux",
 221         .prcm = {
 222                 .omap4 = {
 223                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
 224                         .context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
 225                 },
 226         },
 227 };
 228
 229 /*
 230  * 'dss' class
 231  * display sub-system
 232  */
 233 static struct omap_hwmod_class_sysconfig omap54xx_dss_sysc = {
 234         .rev_offs       = 0x0000,
 235         .syss_offs      = 0x0014,
 236         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 237 };
 238
 239 static struct omap_hwmod_class omap54xx_dss_hwmod_class = {
 240         .name   = "dss",
 241         .sysc   = &omap54xx_dss_sysc,
 242         .reset  = omap_dss_reset,
 243 };
 244
 245 /* dss */
 246 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 247         { .role = "32khz_clk", .clk = "dss_32khz_clk" },
 248         { .role = "sys_clk", .clk = "dss_sys_clk" },
 249         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 250 };
 251
 252 static struct omap_hwmod omap54xx_dss_hwmod = {
 253         .name           = "dss_core",
 254         .class          = &omap54xx_dss_hwmod_class,
 255         .clkdm_name     = "dss_clkdm",
 256         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 257         .main_clk       = "dss_dss_clk",
 258         .prcm = {
 259                 .omap4 = {
 260                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 261                         .context_offs = OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET,
 262                         .modulemode   = MODULEMODE_SWCTRL,
 263                 },
 264         },
 265         .opt_clks       = dss_opt_clks,
 266         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 267 };
 268
 269 /*
 270  * 'dispc' class
 271  * display controller
 272  */
 273
 274 static struct omap_hwmod_class_sysconfig omap54xx_dispc_sysc = {
 275         .rev_offs       = 0x0000,
 276         .sysc_offs      = 0x0010,
 277         .syss_offs      = 0x0014,
 278         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 279                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 280                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 281                            SYSS_HAS_RESET_STATUS),
 282         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 283                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 284         .sysc_fields    = &omap_hwmod_sysc_type1,
 285 };
 286
 287 static struct omap_hwmod_class omap54xx_dispc_hwmod_class = {
 288         .name   = "dispc",
 289         .sysc   = &omap54xx_dispc_sysc,
 290 };
 291
 292 /* dss_dispc */
 293 static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
 294         { .role = "sys_clk", .clk = "dss_sys_clk" },
 295 };
 296
 297 /* dss_dispc dev_attr */
 298 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
 299         .has_framedonetv_irq    = 1,
 300         .manager_count          = 4,
 301 };
 302
 303 static struct omap_hwmod omap54xx_dss_dispc_hwmod = {
 304         .name           = "dss_dispc",
 305         .class          = &omap54xx_dispc_hwmod_class,
 306         .clkdm_name     = "dss_clkdm",
 307         .main_clk       = "dss_dss_clk",
 308         .prcm = {
 309                 .omap4 = {
 310                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 311                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 312                 },
 313         },
 314         .opt_clks       = dss_dispc_opt_clks,
 315         .opt_clks_cnt   = ARRAY_SIZE(dss_dispc_opt_clks),
 316         .dev_attr       = &dss_dispc_dev_attr,
 317         .parent_hwmod   = &omap54xx_dss_hwmod,
 318 };
 319
 320 /*
 321  * 'dsi1' class
 322  * display serial interface controller
 323  */
 324
 325 static struct omap_hwmod_class_sysconfig omap54xx_dsi1_sysc = {
 326         .rev_offs       = 0x0000,
 327         .sysc_offs      = 0x0010,
 328         .syss_offs      = 0x0014,
 329         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 330                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 331                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 332         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 333         .sysc_fields    = &omap_hwmod_sysc_type1,
 334 };
 335
 336 static struct omap_hwmod_class omap54xx_dsi1_hwmod_class = {
 337         .name   = "dsi1",
 338         .sysc   = &omap54xx_dsi1_sysc,
 339 };
 340
 341 /* dss_dsi1_a */
 342 static struct omap_hwmod_opt_clk dss_dsi1_a_opt_clks[] = {
 343         { .role = "sys_clk", .clk = "dss_sys_clk" },
 344 };
 345
 346 static struct omap_hwmod omap54xx_dss_dsi1_a_hwmod = {
 347         .name           = "dss_dsi1",
 348         .class          = &omap54xx_dsi1_hwmod_class,
 349         .clkdm_name     = "dss_clkdm",
 350         .main_clk       = "dss_dss_clk",
 351         .prcm = {
 352                 .omap4 = {
 353                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 354                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 355                 },
 356         },
 357         .opt_clks       = dss_dsi1_a_opt_clks,
 358         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_a_opt_clks),
 359         .parent_hwmod   = &omap54xx_dss_hwmod,
 360 };
 361
 362 /* dss_dsi1_c */
 363 static struct omap_hwmod_opt_clk dss_dsi1_c_opt_clks[] = {
 364         { .role = "sys_clk", .clk = "dss_sys_clk" },
 365 };
 366
 367 static struct omap_hwmod omap54xx_dss_dsi1_c_hwmod = {
 368         .name           = "dss_dsi2",
 369         .class          = &omap54xx_dsi1_hwmod_class,
 370         .clkdm_name     = "dss_clkdm",
 371         .main_clk       = "dss_dss_clk",
 372         .prcm = {
 373                 .omap4 = {
 374                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 375                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 376                 },
 377         },
 378         .opt_clks       = dss_dsi1_c_opt_clks,
 379         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_c_opt_clks),
 380         .parent_hwmod   = &omap54xx_dss_hwmod,
 381 };
 382
 383 /*
 384  * 'hdmi' class
 385  * hdmi controller
 386  */
 387
 388 static struct omap_hwmod_class_sysconfig omap54xx_hdmi_sysc = {
 389         .rev_offs       = 0x0000,
 390         .sysc_offs      = 0x0010,
 391         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 392                            SYSC_HAS_SOFTRESET),
 393         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 394                            SIDLE_SMART_WKUP),
 395         .sysc_fields    = &omap_hwmod_sysc_type2,
 396 };
 397
 398 static struct omap_hwmod_class omap54xx_hdmi_hwmod_class = {
 399         .name   = "hdmi",
 400         .sysc   = &omap54xx_hdmi_sysc,
 401 };
 402
 403 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 404         { .role = "sys_clk", .clk = "dss_sys_clk" },
 405 };
 406
 407 static struct omap_hwmod omap54xx_dss_hdmi_hwmod = {
 408         .name           = "dss_hdmi",
 409         .class          = &omap54xx_hdmi_hwmod_class,
 410         .clkdm_name     = "dss_clkdm",
 411         .main_clk       = "dss_48mhz_clk",
 412         .prcm = {
 413                 .omap4 = {
 414                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 415                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 416                 },
 417         },
 418         .opt_clks       = dss_hdmi_opt_clks,
 419         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 420         .parent_hwmod   = &omap54xx_dss_hwmod,
 421 };
 422
 423 /*
 424  * 'rfbi' class
 425  * remote frame buffer interface
 426  */
 427
 428 static struct omap_hwmod_class_sysconfig omap54xx_rfbi_sysc = {
 429         .rev_offs       = 0x0000,
 430         .sysc_offs      = 0x0010,
 431         .syss_offs      = 0x0014,
 432         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 433                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 434         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 435         .sysc_fields    = &omap_hwmod_sysc_type1,
 436 };
 437
 438 static struct omap_hwmod_class omap54xx_rfbi_hwmod_class = {
 439         .name   = "rfbi",
 440         .sysc   = &omap54xx_rfbi_sysc,
 441 };
 442
 443 /* dss_rfbi */
 444 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 445         { .role = "ick", .clk = "l3_iclk_div" },
 446 };
 447
 448 static struct omap_hwmod omap54xx_dss_rfbi_hwmod = {
 449         .name           = "dss_rfbi",
 450         .class          = &omap54xx_rfbi_hwmod_class,
 451         .clkdm_name     = "dss_clkdm",
 452         .prcm = {
 453                 .omap4 = {
 454                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 455                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 456                 },
 457         },
 458         .opt_clks       = dss_rfbi_opt_clks,
 459         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 460         .parent_hwmod   = &omap54xx_dss_hwmod,
 461 };
 462
 463 /*
 464  * 'emif' class
 465  * external memory interface no1 (wrapper)
 466  */
 467
 468 static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = {
 469         .rev_offs       = 0x0000,
 470 };
 471
 472 static struct omap_hwmod_class omap54xx_emif_hwmod_class = {
 473         .name   = "emif",
 474         .sysc   = &omap54xx_emif_sysc,
 475 };
 476
 477 /* emif1 */
 478 static struct omap_hwmod omap54xx_emif1_hwmod = {
 479         .name           = "emif1",
 480         .class          = &omap54xx_emif_hwmod_class,
 481         .clkdm_name     = "emif_clkdm",
 482         .flags          = HWMOD_INIT_NO_IDLE,
 483         .main_clk       = "dpll_core_h11x2_ck",
 484         .prcm = {
 485                 .omap4 = {
 486                         .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
 487                         .context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
 488                         .modulemode   = MODULEMODE_HWCTRL,
 489                 },
 490         },
 491 };
 492
 493 /* emif2 */
 494 static struct omap_hwmod omap54xx_emif2_hwmod = {
 495         .name           = "emif2",
 496         .class          = &omap54xx_emif_hwmod_class,
 497         .clkdm_name     = "emif_clkdm",
 498         .flags          = HWMOD_INIT_NO_IDLE,
 499         .main_clk       = "dpll_core_h11x2_ck",
 500         .prcm = {
 501                 .omap4 = {
 502                         .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
 503                         .context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
 504                         .modulemode   = MODULEMODE_HWCTRL,
 505                 },
 506         },
 507 };
 508
 509
 510
 511
 512 /*
 513  * 'mpu' class
 514  * mpu sub-system
 515  */
 516
 517 static struct omap_hwmod_class omap54xx_mpu_hwmod_class = {
 518         .name   = "mpu",
 519 };
 520
 521 /* mpu */
 522 static struct omap_hwmod omap54xx_mpu_hwmod = {
 523         .name           = "mpu",
 524         .class          = &omap54xx_mpu_hwmod_class,
 525         .clkdm_name     = "mpu_clkdm",
 526         .flags          = HWMOD_INIT_NO_IDLE,
 527         .main_clk       = "dpll_mpu_m2_ck",
 528         .prcm = {
 529                 .omap4 = {
 530                         .clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET,
 531                         .context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET,
 532                 },
 533         },
 534 };
 535
 536
 537 /*
 538  * 'timer' class
 539  * general purpose timer module with accurate 1ms tick
 540  * This class contains several variants: ['timer_1ms', 'timer']
 541  */
 542
 543 static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = {
 544         .rev_offs       = 0x0000,
 545         .sysc_offs      = 0x0010,
 546         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 547                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 548         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 549                            SIDLE_SMART_WKUP),
 550         .sysc_fields    = &omap_hwmod_sysc_type2,
 551 };
 552
 553 static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = {
 554         .name   = "timer",
 555         .sysc   = &omap54xx_timer_1ms_sysc,
 556 };
 557
 558 /* timer1 */
 559 static struct omap_hwmod omap54xx_timer1_hwmod = {
 560         .name           = "timer1",
 561         .class          = &omap54xx_timer_1ms_hwmod_class,
 562         .clkdm_name     = "wkupaon_clkdm",
 563         .main_clk       = "timer1_gfclk_mux",
 564         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 565         .prcm = {
 566                 .omap4 = {
 567                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
 568                         .context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
 569                         .modulemode   = MODULEMODE_SWCTRL,
 570                 },
 571         },
 572 };
 573
 574 /*
 575  * 'usb_host_hs' class
 576  * high-speed multi-port usb host controller
 577  */
 578
 579 static struct omap_hwmod_class_sysconfig omap54xx_usb_host_hs_sysc = {
 580         .rev_offs       = 0x0000,
 581         .sysc_offs      = 0x0010,
 582         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
 583                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 584         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 585                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 586                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 587         .sysc_fields    = &omap_hwmod_sysc_type2,
 588 };
 589
 590 static struct omap_hwmod_class omap54xx_usb_host_hs_hwmod_class = {
 591         .name   = "usb_host_hs",
 592         .sysc   = &omap54xx_usb_host_hs_sysc,
 593 };
 594
 595 static struct omap_hwmod omap54xx_usb_host_hs_hwmod = {
 596         .name           = "usb_host_hs",
 597         .class          = &omap54xx_usb_host_hs_hwmod_class,
 598         .clkdm_name     = "l3init_clkdm",
 599         /*
 600          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
 601          * id: i660
 602          *
 603          * Description:
 604          * In the following configuration :
 605          * - USBHOST module is set to smart-idle mode
 606          * - PRCM asserts idle_req to the USBHOST module ( This typically
 607          *   happens when the system is going to a low power mode : all ports
 608          *   have been suspended, the master part of the USBHOST module has
 609          *   entered the standby state, and SW has cut the functional clocks)
 610          * - an USBHOST interrupt occurs before the module is able to answer
 611          *   idle_ack, typically a remote wakeup IRQ.
 612          * Then the USB HOST module will enter a deadlock situation where it
 613          * is no more accessible nor functional.
 614          *
 615          * Workaround:
 616          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
 617          */
 618
 619         /*
 620          * Errata: USB host EHCI may stall when entering smart-standby mode
 621          * Id: i571
 622          *
 623          * Description:
 624          * When the USBHOST module is set to smart-standby mode, and when it is
 625          * ready to enter the standby state (i.e. all ports are suspended and
 626          * all attached devices are in suspend mode), then it can wrongly assert
 627          * the Mstandby signal too early while there are still some residual OCP
 628          * transactions ongoing. If this condition occurs, the internal state
 629          * machine may go to an undefined state and the USB link may be stuck
 630          * upon the next resume.
 631          *
 632          * Workaround:
 633          * Don't use smart standby; use only force standby,
 634          * hence HWMOD_SWSUP_MSTANDBY
 635          */
 636
 637         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 638         .main_clk       = "l3init_60m_fclk",
 639         .prcm = {
 640                 .omap4 = {
 641                         .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET,
 642                         .context_offs = OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET,
 643                         .modulemode   = MODULEMODE_SWCTRL,
 644                 },
 645         },
 646 };
 647
 648 /*
 649  * 'usb_tll_hs' class
 650  * usb_tll_hs module is the adapter on the usb_host_hs ports
 651  */
 652
 653 static struct omap_hwmod_class_sysconfig omap54xx_usb_tll_hs_sysc = {
 654         .rev_offs       = 0x0000,
 655         .sysc_offs      = 0x0010,
 656         .syss_offs      = 0x0014,
 657         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 658                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 659                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 660         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 661         .sysc_fields    = &omap_hwmod_sysc_type1,
 662 };
 663
 664 static struct omap_hwmod_class omap54xx_usb_tll_hs_hwmod_class = {
 665         .name   = "usb_tll_hs",
 666         .sysc   = &omap54xx_usb_tll_hs_sysc,
 667 };
 668
 669 static struct omap_hwmod omap54xx_usb_tll_hs_hwmod = {
 670         .name           = "usb_tll_hs",
 671         .class          = &omap54xx_usb_tll_hs_hwmod_class,
 672         .clkdm_name     = "l3init_clkdm",
 673         .main_clk       = "l4_root_clk_div",
 674         .prcm = {
 675                 .omap4 = {
 676                         .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET,
 677                         .context_offs = OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET,
 678                         .modulemode   = MODULEMODE_HWCTRL,
 679                 },
 680         },
 681 };
 682
 683 /*
 684  * 'usb_otg_ss' class
 685  * 2.0 super speed (usb_otg_ss) controller
 686  */
 687
 688 static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc = {
 689         .rev_offs       = 0x0000,
 690         .sysc_offs      = 0x0010,
 691         .sysc_flags     = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
 692                            SYSC_HAS_SIDLEMODE),
 693         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 694                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 695                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 696         .sysc_fields    = &omap_hwmod_sysc_type2,
 697 };
 698
 699 static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class = {
 700         .name   = "usb_otg_ss",
 701         .sysc   = &omap54xx_usb_otg_ss_sysc,
 702 };
 703
 704 /* usb_otg_ss */
 705 static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks[] = {
 706         { .role = "refclk960m", .clk = "usb_otg_ss_refclk960m" },
 707 };
 708
 709 static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = {
 710         .name           = "usb_otg_ss",
 711         .class          = &omap54xx_usb_otg_ss_hwmod_class,
 712         .clkdm_name     = "l3init_clkdm",
 713         .flags          = HWMOD_SWSUP_SIDLE,
 714         .main_clk       = "dpll_core_h13x2_ck",
 715         .prcm = {
 716                 .omap4 = {
 717                         .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET,
 718                         .context_offs = OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET,
 719                         .modulemode   = MODULEMODE_HWCTRL,
 720                 },
 721         },
 722         .opt_clks       = usb_otg_ss_opt_clks,
 723         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss_opt_clks),
 724 };
 725
 726 /*
 727  * 'sata' class
 728  * sata:  serial ata interface  gen2 compliant   ( 1 rx/ 1 tx)
 729  */
 730
 731 static struct omap_hwmod_class_sysconfig omap54xx_sata_sysc = {
 732         .rev_offs       = 0x00fc,
 733         .sysc_offs      = 0x0000,
 734         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 735         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 736                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 737                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 738         .sysc_fields    = &omap_hwmod_sysc_type2,
 739 };
 740
 741 static struct omap_hwmod_class omap54xx_sata_hwmod_class = {
 742         .name   = "sata",
 743         .sysc   = &omap54xx_sata_sysc,
 744 };
 745
 746 /* sata */
 747 static struct omap_hwmod omap54xx_sata_hwmod = {
 748         .name           = "sata",
 749         .class          = &omap54xx_sata_hwmod_class,
 750         .clkdm_name     = "l3init_clkdm",
 751         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 752         .main_clk       = "func_48m_fclk",
 753         .mpu_rt_idx     = 1,
 754         .prcm = {
 755                 .omap4 = {
 756                         .clkctrl_offs = OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
 757                         .context_offs = OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
 758                         .modulemode   = MODULEMODE_SWCTRL,
 759                 },
 760         },
 761 };
 762
 763 /* l4_cfg -> sata */
 764 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__sata = {
 765         .master         = &omap54xx_l4_cfg_hwmod,
 766         .slave          = &omap54xx_sata_hwmod,
 767         .clk            = "l3_iclk_div",
 768         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 769 };
 770
 771 /*
 772  * Interfaces
 773  */
 774
 775 /* l3_main_1 -> dmm */
 776 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm = {
 777         .master         = &omap54xx_l3_main_1_hwmod,
 778         .slave          = &omap54xx_dmm_hwmod,
 779         .clk            = "l3_iclk_div",
 780         .user           = OCP_USER_SDMA,
 781 };
 782
 783 /* l3_main_3 -> l3_instr */
 784 static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = {
 785         .master         = &omap54xx_l3_main_3_hwmod,
 786         .slave          = &omap54xx_l3_instr_hwmod,
 787         .clk            = "l3_iclk_div",
 788         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 789 };
 790
 791 /* l3_main_2 -> l3_main_1 */
 792 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = {
 793         .master         = &omap54xx_l3_main_2_hwmod,
 794         .slave          = &omap54xx_l3_main_1_hwmod,
 795         .clk            = "l3_iclk_div",
 796         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 797 };
 798
 799 /* l4_cfg -> l3_main_1 */
 800 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
 801         .master         = &omap54xx_l4_cfg_hwmod,
 802         .slave          = &omap54xx_l3_main_1_hwmod,
 803         .clk            = "l3_iclk_div",
 804         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 805 };
 806
 807 /* mpu -> l3_main_1 */
 808 static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
 809         .master         = &omap54xx_mpu_hwmod,
 810         .slave          = &omap54xx_l3_main_1_hwmod,
 811         .clk            = "l3_iclk_div",
 812         .user           = OCP_USER_MPU,
 813 };
 814
 815 /* l3_main_1 -> l3_main_2 */
 816 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = {
 817         .master         = &omap54xx_l3_main_1_hwmod,
 818         .slave          = &omap54xx_l3_main_2_hwmod,
 819         .clk            = "l3_iclk_div",
 820         .user           = OCP_USER_MPU,
 821 };
 822
 823 /* l4_cfg -> l3_main_2 */
 824 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
 825         .master         = &omap54xx_l4_cfg_hwmod,
 826         .slave          = &omap54xx_l3_main_2_hwmod,
 827         .clk            = "l3_iclk_div",
 828         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 829 };
 830
 831 /* l3_main_1 -> l3_main_3 */
 832 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
 833         .master         = &omap54xx_l3_main_1_hwmod,
 834         .slave          = &omap54xx_l3_main_3_hwmod,
 835         .clk            = "l3_iclk_div",
 836         .user           = OCP_USER_MPU,
 837 };
 838
 839 /* l3_main_2 -> l3_main_3 */
 840 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = {
 841         .master         = &omap54xx_l3_main_2_hwmod,
 842         .slave          = &omap54xx_l3_main_3_hwmod,
 843         .clk            = "l3_iclk_div",
 844         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 845 };
 846
 847 /* l4_cfg -> l3_main_3 */
 848 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = {
 849         .master         = &omap54xx_l4_cfg_hwmod,
 850         .slave          = &omap54xx_l3_main_3_hwmod,
 851         .clk            = "l3_iclk_div",
 852         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 853 };
 854
 855 /* l3_main_1 -> l4_abe */
 856 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe = {
 857         .master         = &omap54xx_l3_main_1_hwmod,
 858         .slave          = &omap54xx_l4_abe_hwmod,
 859         .clk            = "abe_iclk",
 860         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 861 };
 862
 863 /* mpu -> l4_abe */
 864 static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe = {
 865         .master         = &omap54xx_mpu_hwmod,
 866         .slave          = &omap54xx_l4_abe_hwmod,
 867         .clk            = "abe_iclk",
 868         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 869 };
 870
 871 /* l3_main_1 -> l4_cfg */
 872 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
 873         .master         = &omap54xx_l3_main_1_hwmod,
 874         .slave          = &omap54xx_l4_cfg_hwmod,
 875         .clk            = "l4_root_clk_div",
 876         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 877 };
 878
 879 /* l3_main_2 -> l4_per */
 880 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = {
 881         .master         = &omap54xx_l3_main_2_hwmod,
 882         .slave          = &omap54xx_l4_per_hwmod,
 883         .clk            = "l4_root_clk_div",
 884         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 885 };
 886
 887 /* l3_main_1 -> l4_wkup */
 888 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = {
 889         .master         = &omap54xx_l3_main_1_hwmod,
 890         .slave          = &omap54xx_l4_wkup_hwmod,
 891         .clk            = "wkupaon_iclk_mux",
 892         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 893 };
 894
 895 /* mpu -> mpu_private */
 896 static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = {
 897         .master         = &omap54xx_mpu_hwmod,
 898         .slave          = &omap54xx_mpu_private_hwmod,
 899         .clk            = "l3_iclk_div",
 900         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 901 };
 902
 903 /* l4_wkup -> counter_32k */
 904 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = {
 905         .master         = &omap54xx_l4_wkup_hwmod,
 906         .slave          = &omap54xx_counter_32k_hwmod,
 907         .clk            = "wkupaon_iclk_mux",
 908         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 909 };
 910
 911 /* l3_main_2 -> dss */
 912 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss = {
 913         .master         = &omap54xx_l3_main_2_hwmod,
 914         .slave          = &omap54xx_dss_hwmod,
 915         .clk            = "l3_iclk_div",
 916         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 917 };
 918
 919 /* l3_main_2 -> dss_dispc */
 920 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dispc = {
 921         .master         = &omap54xx_l3_main_2_hwmod,
 922         .slave          = &omap54xx_dss_dispc_hwmod,
 923         .clk            = "l3_iclk_div",
 924         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 925 };
 926
 927 /* l3_main_2 -> dss_dsi1_a */
 928 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_a = {
 929         .master         = &omap54xx_l3_main_2_hwmod,
 930         .slave          = &omap54xx_dss_dsi1_a_hwmod,
 931         .clk            = "l3_iclk_div",
 932         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 933 };
 934
 935 /* l3_main_2 -> dss_dsi1_c */
 936 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_c = {
 937         .master         = &omap54xx_l3_main_2_hwmod,
 938         .slave          = &omap54xx_dss_dsi1_c_hwmod,
 939         .clk            = "l3_iclk_div",
 940         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 941 };
 942
 943 /* l3_main_2 -> dss_hdmi */
 944 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_hdmi = {
 945         .master         = &omap54xx_l3_main_2_hwmod,
 946         .slave          = &omap54xx_dss_hdmi_hwmod,
 947         .clk            = "l3_iclk_div",
 948         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 949 };
 950
 951 /* l3_main_2 -> dss_rfbi */
 952 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_rfbi = {
 953         .master         = &omap54xx_l3_main_2_hwmod,
 954         .slave          = &omap54xx_dss_rfbi_hwmod,
 955         .clk            = "l3_iclk_div",
 956         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 957 };
 958
 959 /* mpu -> emif1 */
 960 static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
 961         .master         = &omap54xx_mpu_hwmod,
 962         .slave          = &omap54xx_emif1_hwmod,
 963         .clk            = "dpll_core_h11x2_ck",
 964         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 965 };
 966
 967 /* mpu -> emif2 */
 968 static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = {
 969         .master         = &omap54xx_mpu_hwmod,
 970         .slave          = &omap54xx_emif2_hwmod,
 971         .clk            = "dpll_core_h11x2_ck",
 972         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 973 };
 974
 975 /* l4_cfg -> mpu */
 976 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
 977         .master         = &omap54xx_l4_cfg_hwmod,
 978         .slave          = &omap54xx_mpu_hwmod,
 979         .clk            = "l4_root_clk_div",
 980         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 981 };
 982
 983 /* l4_wkup -> timer1 */
 984 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = {
 985         .master         = &omap54xx_l4_wkup_hwmod,
 986         .slave          = &omap54xx_timer1_hwmod,
 987         .clk            = "wkupaon_iclk_mux",
 988         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 989 };
 990
 991 /* l4_cfg -> usb_host_hs */
 992 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_host_hs = {
 993         .master         = &omap54xx_l4_cfg_hwmod,
 994         .slave          = &omap54xx_usb_host_hs_hwmod,
 995         .clk            = "l3_iclk_div",
 996         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 997 };
 998
 999 /* l4_cfg -> usb_tll_hs */
1000 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_tll_hs = {
1001         .master         = &omap54xx_l4_cfg_hwmod,
1002         .slave          = &omap54xx_usb_tll_hs_hwmod,
1003         .clk            = "l4_root_clk_div",
1004         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1005 };
1006
1007 /* l4_cfg -> usb_otg_ss */
1008 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = {
1009         .master         = &omap54xx_l4_cfg_hwmod,
1010         .slave          = &omap54xx_usb_otg_ss_hwmod,
1011         .clk            = "dpll_core_h13x2_ck",
1012         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1013 };
1014
1015 static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
1016         &omap54xx_l3_main_1__dmm,
1017         &omap54xx_l3_main_3__l3_instr,
1018         &omap54xx_l3_main_2__l3_main_1,
1019         &omap54xx_l4_cfg__l3_main_1,
1020         &omap54xx_mpu__l3_main_1,
1021         &omap54xx_l3_main_1__l3_main_2,
1022         &omap54xx_l4_cfg__l3_main_2,
1023         &omap54xx_l3_main_1__l3_main_3,
1024         &omap54xx_l3_main_2__l3_main_3,
1025         &omap54xx_l4_cfg__l3_main_3,
1026         &omap54xx_l3_main_1__l4_abe,
1027         &omap54xx_mpu__l4_abe,
1028         &omap54xx_l3_main_1__l4_cfg,
1029         &omap54xx_l3_main_2__l4_per,
1030         &omap54xx_l3_main_1__l4_wkup,
1031         &omap54xx_mpu__mpu_private,
1032         &omap54xx_l4_wkup__counter_32k,
1033         &omap54xx_l3_main_2__dss,
1034         &omap54xx_l3_main_2__dss_dispc,
1035         &omap54xx_l3_main_2__dss_dsi1_a,
1036         &omap54xx_l3_main_2__dss_dsi1_c,
1037         &omap54xx_l3_main_2__dss_hdmi,
1038         &omap54xx_l3_main_2__dss_rfbi,
1039         &omap54xx_mpu__emif1,
1040         &omap54xx_mpu__emif2,
1041         &omap54xx_l4_cfg__mpu,
1042         &omap54xx_l4_wkup__timer1,
1043         &omap54xx_l4_cfg__usb_host_hs,
1044         &omap54xx_l4_cfg__usb_tll_hs,
1045         &omap54xx_l4_cfg__usb_otg_ss,
1046         &omap54xx_l4_cfg__sata,
1047         NULL,
1048 };
1049
1050 int __init omap54xx_hwmod_init(void)
1051 {
1052         omap_hwmod_init();
1053         return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs);
1054 }