arch/arm/mach-s3c64xx/common.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright (c) 2011 Samsung Electronics Co., Ltd.
   4 //              http://www.samsung.com
   5 //
   6 // Copyright 2008 Openmoko, Inc.
   7 // Copyright 2008 Simtec Electronics
   8 //      Ben Dooks <ben@simtec.co.uk>
   9 //      http://armlinux.simtec.co.uk/
  10 //
  11 // Common Codes for S3C64XX machines
  12
  13 /*
  14  * NOTE: Code in this file is not used when booting with Device Tree support.
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/module.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/ioport.h>
  22 #include <linux/serial_core.h>
  23 #include <linux/serial_s3c.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/reboot.h>
  26 #include <linux/io.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/irq.h>
  29 #include <linux/gpio.h>
  30 #include <linux/irqchip/arm-vic.h>
  31 #include <clocksource/samsung_pwm.h>
  32
  33 #include <asm/mach/arch.h>
  34 #include <asm/mach/map.h>
  35 #include <asm/system_misc.h>
  36
  37 #include <mach/map.h>
  38 #include <mach/irqs.h>
  39 #include <mach/hardware.h>
  40 #include <mach/regs-gpio.h>
  41 #include <mach/gpio-samsung.h>
  42
  43 #include <plat/cpu.h>
  44 #include <plat/devs.h>
  45 #include <plat/pm.h>
  46 #include <plat/gpio-cfg.h>
  47 #include <plat/pwm-core.h>
  48 #include <plat/regs-irqtype.h>
  49
  50 #include "common.h"
  51 #include "irq-uart.h"
  52 #include "watchdog-reset.h"
  53
  54 /* External clock frequency */
  55 static unsigned long xtal_f __ro_after_init = 12000000;
  56 static unsigned long xusbxti_f __ro_after_init = 48000000;
  57
  58 void __init s3c64xx_set_xtal_freq(unsigned long freq)
  59 {
  60         xtal_f = freq;
  61 }
  62
  63 void __init s3c64xx_set_xusbxti_freq(unsigned long freq)
  64 {
  65         xusbxti_f = freq;
  66 }
  67
  68 /* uart registration process */
  69
  70 static void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
  71 {
  72         s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no);
  73 }
  74
  75 /* table of supported CPUs */
  76
  77 static const char name_s3c6400[] = "S3C6400";
  78 static const char name_s3c6410[] = "S3C6410";
  79
  80 static struct cpu_table cpu_ids[] __initdata = {
  81         {
  82                 .idcode         = S3C6400_CPU_ID,
  83                 .idmask         = S3C64XX_CPU_MASK,
  84                 .map_io         = s3c6400_map_io,
  85                 .init_uarts     = s3c64xx_init_uarts,
  86                 .init           = s3c6400_init,
  87                 .name           = name_s3c6400,
  88         }, {
  89                 .idcode         = S3C6410_CPU_ID,
  90                 .idmask         = S3C64XX_CPU_MASK,
  91                 .map_io         = s3c6410_map_io,
  92                 .init_uarts     = s3c64xx_init_uarts,
  93                 .init           = s3c6410_init,
  94                 .name           = name_s3c6410,
  95         },
  96 };
  97
  98 /* minimal IO mapping */
  99
 100 /* see notes on uart map in arch/arm/mach-s3c64xx/include/mach/debug-macro.S */
 101 #define UART_OFFS (S3C_PA_UART & 0xfffff)
 102
 103 static struct map_desc s3c_iodesc[] __initdata = {
 104         {
 105                 .virtual        = (unsigned long)S3C_VA_SYS,
 106                 .pfn            = __phys_to_pfn(S3C64XX_PA_SYSCON),
 107                 .length         = SZ_4K,
 108                 .type           = MT_DEVICE,
 109         }, {
 110                 .virtual        = (unsigned long)S3C_VA_MEM,
 111                 .pfn            = __phys_to_pfn(S3C64XX_PA_SROM),
 112                 .length         = SZ_4K,
 113                 .type           = MT_DEVICE,
 114         }, {
 115                 .virtual        = (unsigned long)(S3C_VA_UART + UART_OFFS),
 116                 .pfn            = __phys_to_pfn(S3C_PA_UART),
 117                 .length         = SZ_4K,
 118                 .type           = MT_DEVICE,
 119         }, {
 120                 .virtual        = (unsigned long)VA_VIC0,
 121                 .pfn            = __phys_to_pfn(S3C64XX_PA_VIC0),
 122                 .length         = SZ_16K,
 123                 .type           = MT_DEVICE,
 124         }, {
 125                 .virtual        = (unsigned long)VA_VIC1,
 126                 .pfn            = __phys_to_pfn(S3C64XX_PA_VIC1),
 127                 .length         = SZ_16K,
 128                 .type           = MT_DEVICE,
 129         }, {
 130                 .virtual        = (unsigned long)S3C_VA_TIMER,
 131                 .pfn            = __phys_to_pfn(S3C_PA_TIMER),
 132                 .length         = SZ_16K,
 133                 .type           = MT_DEVICE,
 134         }, {
 135                 .virtual        = (unsigned long)S3C64XX_VA_GPIO,
 136                 .pfn            = __phys_to_pfn(S3C64XX_PA_GPIO),
 137                 .length         = SZ_4K,
 138                 .type           = MT_DEVICE,
 139         }, {
 140                 .virtual        = (unsigned long)S3C64XX_VA_MODEM,
 141                 .pfn            = __phys_to_pfn(S3C64XX_PA_MODEM),
 142                 .length         = SZ_4K,
 143                 .type           = MT_DEVICE,
 144         }, {
 145                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 146                 .pfn            = __phys_to_pfn(S3C64XX_PA_WATCHDOG),
 147                 .length         = SZ_4K,
 148                 .type           = MT_DEVICE,
 149         }, {
 150                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
 151                 .pfn            = __phys_to_pfn(S3C64XX_PA_USB_HSPHY),
 152                 .length         = SZ_1K,
 153                 .type           = MT_DEVICE,
 154         },
 155 };
 156
 157 static struct bus_type s3c64xx_subsys = {
 158         .name           = "s3c64xx-core",
 159         .dev_name       = "s3c64xx-core",
 160 };
 161
 162 static struct device s3c64xx_dev = {
 163         .bus    = &s3c64xx_subsys,
 164 };
 165
 166 static struct samsung_pwm_variant s3c64xx_pwm_variant = {
 167         .bits           = 32,
 168         .div_base       = 0,
 169         .has_tint_cstat = true,
 170         .tclk_mask      = (1 << 7) | (1 << 6) | (1 << 5),
 171 };
 172
 173 void __init samsung_set_timer_source(unsigned int event, unsigned int source)
 174 {
 175         s3c64xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
 176         s3c64xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
 177 }
 178
 179 void __init samsung_timer_init(void)
 180 {
 181         unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
 182                 IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
 183                 IRQ_TIMER3_VIC, IRQ_TIMER4_VIC,
 184         };
 185
 186         samsung_pwm_clocksource_init(S3C_VA_TIMER,
 187                                         timer_irqs, &s3c64xx_pwm_variant);
 188 }
 189
 190 /* read cpu identification code */
 191
 192 void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
 193 {
 194         /* initialise the io descriptors we need for initialisation */
 195         iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
 196         iotable_init(mach_desc, size);
 197
 198         /* detect cpu id */
 199         s3c64xx_init_cpu();
 200
 201         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 202
 203         samsung_pwm_set_platdata(&s3c64xx_pwm_variant);
 204 }
 205
 206 static __init int s3c64xx_dev_init(void)
 207 {
 208         /* Not applicable when using DT. */
 209         if (of_have_populated_dt() || !soc_is_s3c64xx())
 210                 return 0;
 211
 212         subsys_system_register(&s3c64xx_subsys, NULL);
 213         return device_register(&s3c64xx_dev);
 214 }
 215 core_initcall(s3c64xx_dev_init);
 216
 217 /*
 218  * setup the sources the vic should advertise resume
 219  * for, even though it is not doing the wake
 220  * (set_irq_wake needs to be valid)
 221  */
 222 #define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE))
 223 #define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) | \
 224                          1 << (IRQ_PENDN - IRQ_VIC1_BASE) |     \
 225                          1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) |    \
 226                          1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) |    \
 227                          1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE))
 228
 229 void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
 230 {
 231         /*
 232          * FIXME: there is no better place to put this at the moment
 233          * (s3c64xx_clk_init needs ioremap and must happen before init_time
 234          * samsung_wdt_reset_init needs clocks)
 235          */
 236         s3c64xx_clk_init(NULL, xtal_f, xusbxti_f, soc_is_s3c6400(), S3C_VA_SYS);
 237         samsung_wdt_reset_init(S3C_VA_WATCHDOG);
 238
 239         printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
 240
 241         /* initialise the pair of VICs */
 242         vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
 243         vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);
 244 }
 245
 246 #define eint_offset(irq)        ((irq) - IRQ_EINT(0))
 247 #define eint_irq_to_bit(irq)    ((u32)(1 << eint_offset(irq)))
 248
 249 static inline void s3c_irq_eint_mask(struct irq_data *data)
 250 {
 251         u32 mask;
 252
 253         mask = __raw_readl(S3C64XX_EINT0MASK);
 254         mask |= (u32)data->chip_data;
 255         __raw_writel(mask, S3C64XX_EINT0MASK);
 256 }
 257
 258 static void s3c_irq_eint_unmask(struct irq_data *data)
 259 {
 260         u32 mask;
 261
 262         mask = __raw_readl(S3C64XX_EINT0MASK);
 263         mask &= ~((u32)data->chip_data);
 264         __raw_writel(mask, S3C64XX_EINT0MASK);
 265 }
 266
 267 static inline void s3c_irq_eint_ack(struct irq_data *data)
 268 {
 269         __raw_writel((u32)data->chip_data, S3C64XX_EINT0PEND);
 270 }
 271
 272 static void s3c_irq_eint_maskack(struct irq_data *data)
 273 {
 274         /* compiler should in-line these */
 275         s3c_irq_eint_mask(data);
 276         s3c_irq_eint_ack(data);
 277 }
 278
 279 static int s3c_irq_eint_set_type(struct irq_data *data, unsigned int type)
 280 {
 281         int offs = eint_offset(data->irq);
 282         int pin, pin_val;
 283         int shift;
 284         u32 ctrl, mask;
 285         u32 newvalue = 0;
 286         void __iomem *reg;
 287
 288         if (offs > 27)
 289                 return -EINVAL;
 290
 291         if (offs <= 15)
 292                 reg = S3C64XX_EINT0CON0;
 293         else
 294                 reg = S3C64XX_EINT0CON1;
 295
 296         switch (type) {
 297         case IRQ_TYPE_NONE:
 298                 printk(KERN_WARNING "No edge setting!\n");
 299                 break;
 300
 301         case IRQ_TYPE_EDGE_RISING:
 302                 newvalue = S3C2410_EXTINT_RISEEDGE;
 303                 break;
 304
 305         case IRQ_TYPE_EDGE_FALLING:
 306                 newvalue = S3C2410_EXTINT_FALLEDGE;
 307                 break;
 308
 309         case IRQ_TYPE_EDGE_BOTH:
 310                 newvalue = S3C2410_EXTINT_BOTHEDGE;
 311                 break;
 312
 313         case IRQ_TYPE_LEVEL_LOW:
 314                 newvalue = S3C2410_EXTINT_LOWLEV;
 315                 break;
 316
 317         case IRQ_TYPE_LEVEL_HIGH:
 318                 newvalue = S3C2410_EXTINT_HILEV;
 319                 break;
 320
 321         default:
 322                 printk(KERN_ERR "No such irq type %d", type);
 323                 return -1;
 324         }
 325
 326         if (offs <= 15)
 327                 shift = (offs / 2) * 4;
 328         else
 329                 shift = ((offs - 16) / 2) * 4;
 330         mask = 0x7 << shift;
 331
 332         ctrl = __raw_readl(reg);
 333         ctrl &= ~mask;
 334         ctrl |= newvalue << shift;
 335         __raw_writel(ctrl, reg);
 336
 337         /* set the GPIO pin appropriately */
 338
 339         if (offs < 16) {
 340                 pin = S3C64XX_GPN(offs);
 341                 pin_val = S3C_GPIO_SFN(2);
 342         } else if (offs < 23) {
 343                 pin = S3C64XX_GPL(offs + 8 - 16);
 344                 pin_val = S3C_GPIO_SFN(3);
 345         } else {
 346                 pin = S3C64XX_GPM(offs - 23);
 347                 pin_val = S3C_GPIO_SFN(3);
 348         }
 349
 350         s3c_gpio_cfgpin(pin, pin_val);
 351
 352         return 0;
 353 }
 354
 355 static struct irq_chip s3c_irq_eint = {
 356         .name           = "s3c-eint",
 357         .irq_mask       = s3c_irq_eint_mask,
 358         .irq_unmask     = s3c_irq_eint_unmask,
 359         .irq_mask_ack   = s3c_irq_eint_maskack,
 360         .irq_ack        = s3c_irq_eint_ack,
 361         .irq_set_type   = s3c_irq_eint_set_type,
 362         .irq_set_wake   = s3c_irqext_wake,
 363 };
 364
 365 /* s3c_irq_demux_eint
 366  *
 367  * This function demuxes the IRQ from the group0 external interrupts,
 368  * from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into
 369  * the specific handlers s3c_irq_demux_eintX_Y.
 370  */
 371 static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
 372 {
 373         u32 status = __raw_readl(S3C64XX_EINT0PEND);
 374         u32 mask = __raw_readl(S3C64XX_EINT0MASK);
 375         unsigned int irq;
 376
 377         status &= ~mask;
 378         status >>= start;
 379         status &= (1 << (end - start + 1)) - 1;
 380
 381         for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
 382                 if (status & 1)
 383                         generic_handle_irq(irq);
 384
 385                 status >>= 1;
 386         }
 387 }
 388
 389 static void s3c_irq_demux_eint0_3(struct irq_desc *desc)
 390 {
 391         s3c_irq_demux_eint(0, 3);
 392 }
 393
 394 static void s3c_irq_demux_eint4_11(struct irq_desc *desc)
 395 {
 396         s3c_irq_demux_eint(4, 11);
 397 }
 398
 399 static void s3c_irq_demux_eint12_19(struct irq_desc *desc)
 400 {
 401         s3c_irq_demux_eint(12, 19);
 402 }
 403
 404 static void s3c_irq_demux_eint20_27(struct irq_desc *desc)
 405 {
 406         s3c_irq_demux_eint(20, 27);
 407 }
 408
 409 static int __init s3c64xx_init_irq_eint(void)
 410 {
 411         int irq;
 412
 413         /* On DT-enabled systems EINTs are handled by pinctrl-s3c64xx driver. */
 414         if (of_have_populated_dt() || !soc_is_s3c64xx())
 415                 return -ENODEV;
 416
 417         for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
 418                 irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq);
 419                 irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq));
 420                 irq_clear_status_flags(irq, IRQ_NOREQUEST);
 421         }
 422
 423         irq_set_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
 424         irq_set_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
 425         irq_set_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
 426         irq_set_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);
 427
 428         return 0;
 429 }
 430 arch_initcall(s3c64xx_init_irq_eint);
 431
 432 void s3c64xx_restart(enum reboot_mode mode, const char *cmd)
 433 {
 434         if (mode != REBOOT_SOFT)
 435                 samsung_wdt_reset();
 436
 437         /* if all else fails, or mode was for soft, jump to 0 */
 438         soft_restart(0);
 439 }