arch/arm/mach-s3c64xx/mach-anw6410.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright 2008 Openmoko, Inc.
   4 // Copyright 2008 Simtec Electronics
   5 //      Ben Dooks <ben@simtec.co.uk>
   6 //      http://armlinux.simtec.co.uk/
   7 // Copyright 2009 Kwangwoo Lee
   8 //      Kwangwoo Lee <kwangwoo.lee@gmail.com>
   9
  10 #include <linux/kernel.h>
  11 #include <linux/types.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/list.h>
  14 #include <linux/timer.h>
  15 #include <linux/init.h>
  16 #include <linux/serial_core.h>
  17 #include <linux/serial_s3c.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/io.h>
  20 #include <linux/i2c.h>
  21 #include <linux/fb.h>
  22 #include <linux/gpio.h>
  23 #include <linux/delay.h>
  24 #include <linux/dm9000.h>
  25
  26 #include <video/platform_lcd.h>
  27 #include <video/samsung_fimd.h>
  28
  29 #include <asm/mach/arch.h>
  30 #include <asm/mach/map.h>
  31 #include <asm/mach/irq.h>
  32
  33 #include <mach/hardware.h>
  34 #include <mach/map.h>
  35
  36 #include <asm/irq.h>
  37 #include <asm/mach-types.h>
  38
  39 #include <linux/platform_data/i2c-s3c2410.h>
  40 #include <plat/fb.h>
  41
  42 #include <plat/devs.h>
  43 #include <plat/cpu.h>
  44 #include <mach/irqs.h>
  45 #include <mach/regs-gpio.h>
  46 #include <mach/gpio-samsung.h>
  47 #include <plat/samsung-time.h>
  48
  49 #include "common.h"
  50 #include "regs-modem.h"
  51
  52 /* DM9000 */
  53 #define ANW6410_PA_DM9000       (0x18000000)
  54
  55 /* A hardware buffer to control external devices is mapped at 0x30000000.
  56  * It can not be read. So current status must be kept in anw6410_extdev_status.
  57  */
  58 #define ANW6410_VA_EXTDEV       S3C_ADDR(0x02000000)
  59 #define ANW6410_PA_EXTDEV       (0x30000000)
  60
  61 #define ANW6410_EN_DM9000       (1<<11)
  62 #define ANW6410_EN_LCD          (1<<14)
  63
  64 static __u32 anw6410_extdev_status;
  65
  66 static struct s3c2410_uartcfg anw6410_uartcfgs[] __initdata = {
  67         [0] = {
  68                 .hwport      = 0,
  69                 .flags       = 0,
  70                 .ucon        = 0x3c5,
  71                 .ulcon       = 0x03,
  72                 .ufcon       = 0x51,
  73         },
  74         [1] = {
  75                 .hwport      = 1,
  76                 .flags       = 0,
  77                 .ucon        = 0x3c5,
  78                 .ulcon       = 0x03,
  79                 .ufcon       = 0x51,
  80         },
  81 };
  82
  83 /* framebuffer and LCD setup. */
  84 static void __init anw6410_lcd_mode_set(void)
  85 {
  86         u32 tmp;
  87
  88         /* set the LCD type */
  89         tmp = __raw_readl(S3C64XX_SPCON);
  90         tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
  91         tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
  92         __raw_writel(tmp, S3C64XX_SPCON);
  93
  94         /* remove the LCD bypass */
  95         tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
  96         tmp &= ~MIFPCON_LCD_BYPASS;
  97         __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
  98 }
  99
 100 /* GPF1 = LCD panel power
 101  * GPF4 = LCD backlight control
 102  */
 103 static void anw6410_lcd_power_set(struct plat_lcd_data *pd,
 104                                    unsigned int power)
 105 {
 106         if (power) {
 107                 anw6410_extdev_status |= (ANW6410_EN_LCD << 16);
 108                 __raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
 109
 110                 gpio_direction_output(S3C64XX_GPF(1), 1);
 111                 gpio_direction_output(S3C64XX_GPF(4), 1);
 112         } else {
 113                 anw6410_extdev_status &= ~(ANW6410_EN_LCD << 16);
 114                 __raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
 115
 116                 gpio_direction_output(S3C64XX_GPF(1), 0);
 117                 gpio_direction_output(S3C64XX_GPF(4), 0);
 118         }
 119 }
 120
 121 static struct plat_lcd_data anw6410_lcd_power_data = {
 122         .set_power      = anw6410_lcd_power_set,
 123 };
 124
 125 static struct platform_device anw6410_lcd_powerdev = {
 126         .name                   = "platform-lcd",
 127         .dev.parent             = &s3c_device_fb.dev,
 128         .dev.platform_data      = &anw6410_lcd_power_data,
 129 };
 130
 131 static struct s3c_fb_pd_win anw6410_fb_win0 = {
 132         .max_bpp        = 32,
 133         .default_bpp    = 16,
 134         .xres           = 800,
 135         .yres           = 480,
 136 };
 137
 138 static struct fb_videomode anw6410_lcd_timing = {
 139         .left_margin    = 8,
 140         .right_margin   = 13,
 141         .upper_margin   = 7,
 142         .lower_margin   = 5,
 143         .hsync_len      = 3,
 144         .vsync_len      = 1,
 145         .xres           = 800,
 146         .yres           = 480,
 147 };
 148
 149 /* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
 150 static struct s3c_fb_platdata anw6410_lcd_pdata __initdata = {
 151         .setup_gpio     = s3c64xx_fb_gpio_setup_24bpp,
 152         .vtiming        = &anw6410_lcd_timing,
 153         .win[0]         = &anw6410_fb_win0,
 154         .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 155         .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
 156 };
 157
 158 /* DM9000AEP 10/100 ethernet controller */
 159 static void __init anw6410_dm9000_enable(void)
 160 {
 161         anw6410_extdev_status |= (ANW6410_EN_DM9000 << 16);
 162         __raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
 163 }
 164
 165 static struct resource anw6410_dm9000_resource[] = {
 166         [0] = DEFINE_RES_MEM(ANW6410_PA_DM9000, 4),
 167         [1] = DEFINE_RES_MEM(ANW6410_PA_DM9000 + 4, 501),
 168         [2] = DEFINE_RES_NAMED(IRQ_EINT(15), 1, NULL, IORESOURCE_IRQ \
 169                                         | IRQF_TRIGGER_HIGH),
 170 };
 171
 172 static struct dm9000_plat_data anw6410_dm9000_pdata = {
 173         .flags    = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
 174         /* dev_addr can be set to provide hwaddr. */
 175 };
 176
 177 static struct platform_device anw6410_device_eth = {
 178         .name   = "dm9000",
 179         .id     = -1,
 180         .num_resources  = ARRAY_SIZE(anw6410_dm9000_resource),
 181         .resource       = anw6410_dm9000_resource,
 182         .dev    = {
 183                 .platform_data  = &anw6410_dm9000_pdata,
 184         },
 185 };
 186
 187 static struct map_desc anw6410_iodesc[] __initdata = {
 188         {
 189                 .virtual        = (unsigned long)ANW6410_VA_EXTDEV,
 190                 .pfn            = __phys_to_pfn(ANW6410_PA_EXTDEV),
 191                 .length         = SZ_64K,
 192                 .type           = MT_DEVICE,
 193         },
 194 };
 195
 196 static struct platform_device *anw6410_devices[] __initdata = {
 197         &s3c_device_fb,
 198         &anw6410_lcd_powerdev,
 199         &anw6410_device_eth,
 200 };
 201
 202 static void __init anw6410_map_io(void)
 203 {
 204         s3c64xx_init_io(anw6410_iodesc, ARRAY_SIZE(anw6410_iodesc));
 205         s3c64xx_set_xtal_freq(12000000);
 206         s3c24xx_init_uarts(anw6410_uartcfgs, ARRAY_SIZE(anw6410_uartcfgs));
 207         samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 208
 209         anw6410_lcd_mode_set();
 210 }
 211
 212 static void __init anw6410_machine_init(void)
 213 {
 214         s3c_fb_set_platdata(&anw6410_lcd_pdata);
 215
 216         gpio_request(S3C64XX_GPF(1), "panel power");
 217         gpio_request(S3C64XX_GPF(4), "LCD backlight");
 218
 219         anw6410_dm9000_enable();
 220
 221         platform_add_devices(anw6410_devices, ARRAY_SIZE(anw6410_devices));
 222 }
 223
 224 MACHINE_START(ANW6410, "A&W6410")
 225         /* Maintainer: Kwangwoo Lee <kwangwoo.lee@gmail.com> */
 226         .atag_offset    = 0x100,
 227         .nr_irqs        = S3C64XX_NR_IRQS,
 228         .init_irq       = s3c6410_init_irq,
 229         .map_io         = anw6410_map_io,
 230         .init_machine   = anw6410_machine_init,
 231         .init_time      = samsung_timer_init,
 232         .restart        = s3c64xx_restart,
 233 MACHINE_END