1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/arm740.S: utility functions for ARM740
5 * Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com)
7 #include <linux/linkage.h>
8 #include <linux/init.h>
9 #include <asm/assembler.h>
10 #include <asm/asm-offsets.h>
11 #include <asm/hwcap.h>
12 #include <asm/pgtable-hwdef.h>
13 #include <asm/pgtable.h>
14 #include <asm/ptrace.h>
16 #include "proc-macros.S"
20 * cpu_arm740_proc_init()
21 * cpu_arm740_do_idle()
22 * cpu_arm740_dcache_clean_area()
23 * cpu_arm740_switch_mm()
25 * These are not required.
27 ENTRY(cpu_arm740_proc_init)
28 ENTRY(cpu_arm740_do_idle)
29 ENTRY(cpu_arm740_dcache_clean_area)
30 ENTRY(cpu_arm740_switch_mm)
34 * cpu_arm740_proc_fin()
36 ENTRY(cpu_arm740_proc_fin)
37 mrc p15, 0, r0, c1, c0, 0
38 bic r0, r0, #0x3f000000 @ bank/f/lock/s
39 bic r0, r0, #0x0000000c @ w-buffer/cache
40 mcr p15, 0, r0, c1, c0, 0 @ disable caches
44 * cpu_arm740_reset(loc)
45 * Params : r0 = address to jump to
46 * Notes : This sets up everything for a reset
48 .pushsection .idmap.text, "ax"
49 ENTRY(cpu_arm740_reset)
51 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache
52 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
53 bic ip, ip, #0x0000000c @ ............wc..
54 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
56 ENDPROC(cpu_arm740_reset)
59 .type __arm740_setup, #function
62 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
64 mcr p15, 0, r0, c6, c3 @ disable area 3~7
65 mcr p15, 0, r0, c6, c4
66 mcr p15, 0, r0, c6, c5
67 mcr p15, 0, r0, c6, c6
68 mcr p15, 0, r0, c6, c7
70 mov r0, #0x0000003F @ base = 0, size = 4GB
71 mcr p15, 0, r0, c6, c0 @ set area 0, default
73 ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
74 ldr r3, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB)
75 mov r4, #10 @ 11 is the minimum (4KB)
76 1: add r4, r4, #1 @ area size *= 2
78 bne 1b @ count not zero r-shift
79 orr r0, r0, r4, lsl #1 @ the area register value
80 orr r0, r0, #1 @ set enable bit
81 mcr p15, 0, r0, c6, c1 @ set area 1, RAM
83 ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
84 ldr r3, =(CONFIG_FLASH_SIZE >> 12) @ size of FLASH (must be >= 4KB)
88 mov r4, #10 @ 11 is the minimum (4KB)
89 1: add r4, r4, #1 @ area size *= 2
91 bne 1b @ count not zero r-shift
92 orr r0, r0, r4, lsl #1 @ the area register value
93 orr r0, r0, #1 @ set enable bit
94 2: mcr p15, 0, r0, c6, c2 @ set area 2, ROM/FLASH
97 mcr p15, 0, r0, c2, c0 @ Region 1&2 cacheable
98 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
99 mov r0, #0x00 @ disable whole write buffer
101 mov r0, #0x02 @ Region 1 write bufferred
103 mcr p15, 0, r0, c3, c0
106 sub r0, r0, #1 @ r0 = 0xffff
107 mcr p15, 0, r0, c5, c0 @ all read/write access
109 mrc p15, 0, r0, c1, c0 @ get control register
110 bic r0, r0, #0x3F000000 @ set to standard caching mode
111 @ need some benchmark
112 orr r0, r0, #0x0000000d @ MPU/Cache/WB
116 .size __arm740_setup, . - __arm740_setup
120 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
121 define_processor_functions arm740, dabort=v4t_late_abort, pabort=legacy_pabort, nommu=1
125 string cpu_arch_name, "armv4"
126 string cpu_elf_name, "v4"
127 string cpu_arm740_name, "ARM740T"
131 .section ".proc.info.init", "a"
132 .type __arm740_proc_info,#object
138 initfn __arm740_setup, __arm740_proc_info
141 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_26BIT
142 .long cpu_arm740_name
143 .long arm740_processor_functions
146 .long v4_cache_fns @ cache model
147 .size __arm740_proc_info, . - __arm740_proc_info