1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/arch/arm/mm/proc-arm926.S: MMU functions for ARM926EJ-S
5 * Copyright (C) 1999-2001 ARM Limited
6 * Copyright (C) 2000 Deep Blue Solutions Ltd.
7 * hacked for non-paged-MM by Hyok S. Choi, 2003.
9 * These are the low level assembler for performing cache and TLB
10 * functions on the arm926.
12 * CONFIG_CPU_ARM926_CPU_IDLE -> nohlt
14 #include <linux/linkage.h>
15 #include <linux/init.h>
16 #include <asm/assembler.h>
17 #include <asm/hwcap.h>
18 #include <asm/pgtable-hwdef.h>
19 #include <asm/pgtable.h>
21 #include <asm/ptrace.h>
22 #include "proc-macros.S"
25 * This is the maximum size of an area which will be invalidated
26 * using the single invalidate entry instructions. Anything larger
27 * than this, and we go for the whole cache.
29 * This value should be chosen such that we choose the cheapest
32 #define CACHE_DLIMIT 16384
35 * the cache line size of the I and D cache
37 #define CACHE_DLINESIZE 32
41 * cpu_arm926_proc_init()
43 ENTRY(cpu_arm926_proc_init)
47 * cpu_arm926_proc_fin()
49 ENTRY(cpu_arm926_proc_fin)
50 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
51 bic r0, r0, #0x1000 @ ...i............
52 bic r0, r0, #0x000e @ ............wca.
53 mcr p15, 0, r0, c1, c0, 0 @ disable caches
57 * cpu_arm926_reset(loc)
59 * Perform a soft reset of the system. Put the CPU into the
60 * same state as it would be if it had been reset, and branch
61 * to what would be the reset vector.
63 * loc: location to jump to for soft reset
66 .pushsection .idmap.text, "ax"
67 ENTRY(cpu_arm926_reset)
69 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
70 mcr p15, 0, ip, c7, c10, 4 @ drain WB
72 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
74 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
75 bic ip, ip, #0x000f @ ............wcam
76 bic ip, ip, #0x1100 @ ...i...s........
77 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
79 ENDPROC(cpu_arm926_reset)
83 * cpu_arm926_do_idle()
85 * Called with IRQs disabled
88 ENTRY(cpu_arm926_do_idle)
90 mrc p15, 0, r1, c1, c0, 0 @ Read control register
91 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
93 mrs r3, cpsr @ Disable FIQs while Icache
94 orr ip, r3, #PSR_F_BIT @ is disabled
96 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
97 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
98 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
99 msr cpsr_c, r3 @ Restore FIQ state
105 * Unconditionally clean and invalidate the entire icache.
107 ENTRY(arm926_flush_icache_all)
109 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
111 ENDPROC(arm926_flush_icache_all)
114 * flush_user_cache_all()
116 * Clean and invalidate all cache entries in a particular
119 ENTRY(arm926_flush_user_cache_all)
123 * flush_kern_cache_all()
125 * Clean and invalidate the entire cache.
127 ENTRY(arm926_flush_kern_cache_all)
131 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
132 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
134 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate
138 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
139 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
143 * flush_user_cache_range(start, end, flags)
145 * Clean and invalidate a range of cache entries in the
146 * specified address range.
148 * - start - start address (inclusive)
149 * - end - end address (exclusive)
150 * - flags - vm_flags describing address space
152 ENTRY(arm926_flush_user_cache_range)
154 sub r3, r1, r0 @ calculate total size
155 cmp r3, #CACHE_DLIMIT
156 bgt __flush_whole_cache
158 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
159 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
160 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
161 add r0, r0, #CACHE_DLINESIZE
162 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
163 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
164 add r0, r0, #CACHE_DLINESIZE
166 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
167 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
168 add r0, r0, #CACHE_DLINESIZE
169 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
170 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
171 add r0, r0, #CACHE_DLINESIZE
176 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
180 * coherent_kern_range(start, end)
182 * Ensure coherency between the Icache and the Dcache in the
183 * region described by start, end. If you have non-snooping
184 * Harvard caches, you need to implement this function.
186 * - start - virtual start address
187 * - end - virtual end address
189 ENTRY(arm926_coherent_kern_range)
193 * coherent_user_range(start, end)
195 * Ensure coherency between the Icache and the Dcache in the
196 * region described by start, end. If you have non-snooping
197 * Harvard caches, you need to implement this function.
199 * - start - virtual start address
200 * - end - virtual end address
202 ENTRY(arm926_coherent_user_range)
203 bic r0, r0, #CACHE_DLINESIZE - 1
204 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
205 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
206 add r0, r0, #CACHE_DLINESIZE
209 mcr p15, 0, r0, c7, c10, 4 @ drain WB
214 * flush_kern_dcache_area(void *addr, size_t size)
216 * Ensure no D cache aliasing occurs, either with itself or
219 * - addr - kernel address
220 * - size - region size
222 ENTRY(arm926_flush_kern_dcache_area)
224 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
225 add r0, r0, #CACHE_DLINESIZE
229 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
230 mcr p15, 0, r0, c7, c10, 4 @ drain WB
234 * dma_inv_range(start, end)
236 * Invalidate (discard) the specified virtual address range.
237 * May not write back any entries. If 'start' or 'end'
238 * are not cache line aligned, those lines must be written
241 * - start - virtual start address
242 * - end - virtual end address
246 arm926_dma_inv_range:
247 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
248 tst r0, #CACHE_DLINESIZE - 1
249 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
250 tst r1, #CACHE_DLINESIZE - 1
251 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
253 bic r0, r0, #CACHE_DLINESIZE - 1
254 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
255 add r0, r0, #CACHE_DLINESIZE
258 mcr p15, 0, r0, c7, c10, 4 @ drain WB
262 * dma_clean_range(start, end)
264 * Clean the specified virtual address range.
266 * - start - virtual start address
267 * - end - virtual end address
271 arm926_dma_clean_range:
272 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
273 bic r0, r0, #CACHE_DLINESIZE - 1
274 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
275 add r0, r0, #CACHE_DLINESIZE
279 mcr p15, 0, r0, c7, c10, 4 @ drain WB
283 * dma_flush_range(start, end)
285 * Clean and invalidate the specified virtual address range.
287 * - start - virtual start address
288 * - end - virtual end address
290 ENTRY(arm926_dma_flush_range)
291 bic r0, r0, #CACHE_DLINESIZE - 1
293 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
294 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
296 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
298 add r0, r0, #CACHE_DLINESIZE
301 mcr p15, 0, r0, c7, c10, 4 @ drain WB
305 * dma_map_area(start, size, dir)
306 * - start - kernel virtual start address
307 * - size - size of region
308 * - dir - DMA direction
310 ENTRY(arm926_dma_map_area)
312 cmp r2, #DMA_TO_DEVICE
313 beq arm926_dma_clean_range
314 bcs arm926_dma_inv_range
315 b arm926_dma_flush_range
316 ENDPROC(arm926_dma_map_area)
319 * dma_unmap_area(start, size, dir)
320 * - start - kernel virtual start address
321 * - size - size of region
322 * - dir - DMA direction
324 ENTRY(arm926_dma_unmap_area)
326 ENDPROC(arm926_dma_unmap_area)
328 .globl arm926_flush_kern_cache_louis
329 .equ arm926_flush_kern_cache_louis, arm926_flush_kern_cache_all
331 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
332 define_cache_functions arm926
334 ENTRY(cpu_arm926_dcache_clean_area)
335 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
336 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
337 add r0, r0, #CACHE_DLINESIZE
338 subs r1, r1, #CACHE_DLINESIZE
341 mcr p15, 0, r0, c7, c10, 4 @ drain WB
344 /* =============================== PageTable ============================== */
347 * cpu_arm926_switch_mm(pgd)
349 * Set the translation base pointer to be as described by pgd.
351 * pgd: new page tables
354 ENTRY(cpu_arm926_switch_mm)
357 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
358 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
360 @ && 'Clean & Invalidate whole DCache'
361 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate
364 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
365 mcr p15, 0, ip, c7, c10, 4 @ drain WB
366 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
367 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
372 * cpu_arm926_set_pte_ext(ptep, pte, ext)
374 * Set a PTE and flush it out
377 ENTRY(cpu_arm926_set_pte_ext)
381 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
382 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
384 mcr p15, 0, r0, c7, c10, 4 @ drain WB
388 /* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
389 .globl cpu_arm926_suspend_size
390 .equ cpu_arm926_suspend_size, 4 * 3
391 #ifdef CONFIG_ARM_CPU_SUSPEND
392 ENTRY(cpu_arm926_do_suspend)
393 stmfd sp!, {r4 - r6, lr}
394 mrc p15, 0, r4, c13, c0, 0 @ PID
395 mrc p15, 0, r5, c3, c0, 0 @ Domain ID
396 mrc p15, 0, r6, c1, c0, 0 @ Control register
398 ldmfd sp!, {r4 - r6, pc}
399 ENDPROC(cpu_arm926_do_suspend)
401 ENTRY(cpu_arm926_do_resume)
403 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
404 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
406 mcr p15, 0, r4, c13, c0, 0 @ PID
407 mcr p15, 0, r5, c3, c0, 0 @ Domain ID
408 mcr p15, 0, r1, c2, c0, 0 @ TTB address
409 mov r0, r6 @ control register
411 ENDPROC(cpu_arm926_do_resume)
414 .type __arm926_setup, #function
417 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
418 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
420 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
424 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
425 mov r0, #4 @ disable write-back on caches explicitly
426 mcr p15, 7, r0, c15, c0, 0
431 mrc p15, 0, r0, c1, c0 @ get control register v4
434 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
435 orr r0, r0, #0x4000 @ .1.. .... .... ....
438 .size __arm926_setup, . - __arm926_setup
442 * .RVI ZFRS BLDP WCAM
443 * .011 0001 ..11 0101
446 .type arm926_crval, #object
448 crval clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134
452 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
453 define_processor_functions arm926, dabort=v5tj_early_abort, pabort=legacy_pabort, suspend=1
457 string cpu_arch_name, "armv5tej"
458 string cpu_elf_name, "v5"
459 string cpu_arm926_name, "ARM926EJ-S"
463 .section ".proc.info.init", "a"
465 .type __arm926_proc_info,#object
467 .long 0x41069260 @ ARM926EJ-S (v5TEJ)
469 .long PMD_TYPE_SECT | \
470 PMD_SECT_BUFFERABLE | \
471 PMD_SECT_CACHEABLE | \
473 PMD_SECT_AP_WRITE | \
475 .long PMD_TYPE_SECT | \
477 PMD_SECT_AP_WRITE | \
479 initfn __arm926_setup, __arm926_proc_info
482 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
483 .long cpu_arm926_name
484 .long arm926_processor_functions
487 .long arm926_cache_fns
488 .size __arm926_proc_info, . - __arm926_proc_info