1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/arch/arm/mm/proc-fa526.S: MMU functions for FA526
5 * Written by : Luke Lee
6 * Copyright (C) 2005 Faraday Corp.
7 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
9 * These are the low level assembler for performing cache and TLB
10 * functions on the fa526.
12 #include <linux/linkage.h>
13 #include <linux/init.h>
14 #include <asm/assembler.h>
15 #include <asm/hwcap.h>
16 #include <asm/pgtable-hwdef.h>
17 #include <asm/pgtable.h>
19 #include <asm/ptrace.h>
21 #include "proc-macros.S"
23 #define CACHE_DLINESIZE 16
27 * cpu_fa526_proc_init()
29 ENTRY(cpu_fa526_proc_init)
33 * cpu_fa526_proc_fin()
35 ENTRY(cpu_fa526_proc_fin)
36 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
37 bic r0, r0, #0x1000 @ ...i............
38 bic r0, r0, #0x000e @ ............wca.
39 mcr p15, 0, r0, c1, c0, 0 @ disable caches
45 * cpu_fa526_reset(loc)
47 * Perform a soft reset of the system. Put the CPU into the
48 * same state as it would be if it had been reset, and branch
49 * to what would be the reset vector.
51 * loc: location to jump to for soft reset
54 .pushsection .idmap.text, "ax"
55 ENTRY(cpu_fa526_reset)
56 /* TODO: Use CP8 if possible... */
58 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
59 mcr p15, 0, ip, c7, c10, 4 @ drain WB
61 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
63 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
64 bic ip, ip, #0x000f @ ............wcam
65 bic ip, ip, #0x1100 @ ...i...s........
66 bic ip, ip, #0x0800 @ BTB off
67 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
71 ENDPROC(cpu_fa526_reset)
78 ENTRY(cpu_fa526_do_idle)
82 ENTRY(cpu_fa526_dcache_clean_area)
83 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
84 add r0, r0, #CACHE_DLINESIZE
85 subs r1, r1, #CACHE_DLINESIZE
87 mcr p15, 0, r0, c7, c10, 4 @ drain WB
90 /* =============================== PageTable ============================== */
93 * cpu_fa526_switch_mm(pgd)
95 * Set the translation base pointer to be as described by pgd.
97 * pgd: new page tables
100 ENTRY(cpu_fa526_switch_mm)
103 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
104 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
106 mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache
108 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
109 mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed
110 mcr p15, 0, ip, c7, c10, 4 @ data write barrier
111 mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
112 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
113 mcr p15, 0, ip, c8, c7, 0 @ invalidate UTLB
118 * cpu_fa526_set_pte_ext(ptep, pte, ext)
120 * Set a PTE and flush it out
123 ENTRY(cpu_fa526_set_pte_ext)
127 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
129 mcr p15, 0, r0, c7, c10, 4 @ drain WB
133 .type __fa526_setup, #function
135 /* On return of this routine, r0 must carry correct flags for CFG register */
137 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
138 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
140 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
142 mcr p15, 0, r0, c7, c5, 5 @ invalidate IScratchpad RAM
145 mcr p15, 0, r0, c1, c1, 0 @ turn-on ECR
148 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB All
149 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
150 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
152 mov r0, #0x1f @ Domains 0, 1 = manager, 2 = client
153 mcr p15, 0, r0, c3, c0 @ load domain access register
155 mrc p15, 0, r0, c1, c0 @ get control register v4
156 ldr r5, fa526_cr1_clear
158 ldr r5, fa526_cr1_set
161 .size __fa526_setup, . - __fa526_setup
164 * .RVI ZFRS BLDP WCAM
165 * ..11 1001 .111 1101
168 .type fa526_cr1_clear, #object
169 .type fa526_cr1_set, #object
177 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
178 define_processor_functions fa526, dabort=v4_early_abort, pabort=legacy_pabort
182 string cpu_arch_name, "armv4"
183 string cpu_elf_name, "v4"
184 string cpu_fa526_name, "FA526"
188 .section ".proc.info.init", "a"
190 .type __fa526_proc_info,#object
194 .long PMD_TYPE_SECT | \
195 PMD_SECT_BUFFERABLE | \
196 PMD_SECT_CACHEABLE | \
198 PMD_SECT_AP_WRITE | \
200 .long PMD_TYPE_SECT | \
202 PMD_SECT_AP_WRITE | \
204 initfn __fa526_setup, __fa526_proc_info
207 .long HWCAP_SWP | HWCAP_HALF
209 .long fa526_processor_functions
213 .size __fa526_proc_info, . - __fa526_proc_info