arm64: dts: Revert "specify console via command line"
[linux/fpc-iii.git] / arch / arm / mm / proc-v7.S
blob48e0ef6f0dccfe02e25045a455c6fea3701c50ab
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  *  linux/arch/arm/mm/proc-v7.S
4  *
5  *  Copyright (C) 2001 Deep Blue Solutions Ltd.
6  *
7  *  This is the "shell" of the ARMv7 processor support.
8  */
9 #include <linux/arm-smccc.h>
10 #include <linux/init.h>
11 #include <linux/linkage.h>
12 #include <asm/assembler.h>
13 #include <asm/asm-offsets.h>
14 #include <asm/hwcap.h>
15 #include <asm/pgtable-hwdef.h>
16 #include <asm/pgtable.h>
17 #include <asm/memory.h>
19 #include "proc-macros.S"
21 #ifdef CONFIG_ARM_LPAE
22 #include "proc-v7-3level.S"
23 #else
24 #include "proc-v7-2level.S"
25 #endif
27 ENTRY(cpu_v7_proc_init)
28         ret     lr
29 ENDPROC(cpu_v7_proc_init)
31 ENTRY(cpu_v7_proc_fin)
32         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
33         bic     r0, r0, #0x1000                 @ ...i............
34         bic     r0, r0, #0x0006                 @ .............ca.
35         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
36         ret     lr
37 ENDPROC(cpu_v7_proc_fin)
40  *      cpu_v7_reset(loc, hyp)
41  *
42  *      Perform a soft reset of the system.  Put the CPU into the
43  *      same state as it would be if it had been reset, and branch
44  *      to what would be the reset vector.
45  *
46  *      - loc   - location to jump to for soft reset
47  *      - hyp   - indicate if restart occurs in HYP mode
48  *
49  *      This code must be executed using a flat identity mapping with
50  *      caches disabled.
51  */
52         .align  5
53         .pushsection    .idmap.text, "ax"
54 ENTRY(cpu_v7_reset)
55         mrc     p15, 0, r2, c1, c0, 0           @ ctrl register
56         bic     r2, r2, #0x1                    @ ...............m
57  THUMB( bic     r2, r2, #1 << 30 )              @ SCTLR.TE (Thumb exceptions)
58         mcr     p15, 0, r2, c1, c0, 0           @ disable MMU
59         isb
60 #ifdef CONFIG_ARM_VIRT_EXT
61         teq     r1, #0
62         bne     __hyp_soft_restart
63 #endif
64         bx      r0
65 ENDPROC(cpu_v7_reset)
66         .popsection
69  *      cpu_v7_do_idle()
70  *
71  *      Idle the processor (eg, wait for interrupt).
72  *
73  *      IRQs are already disabled.
74  */
75 ENTRY(cpu_v7_do_idle)
76         dsb                                     @ WFI may enter a low-power mode
77         wfi
78         ret     lr
79 ENDPROC(cpu_v7_do_idle)
81 ENTRY(cpu_v7_dcache_clean_area)
82         ALT_SMP(W(nop))                 @ MP extensions imply L1 PTW
83         ALT_UP_B(1f)
84         ret     lr
85 1:      dcache_line_size r2, r3
86 2:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
87         add     r0, r0, r2
88         subs    r1, r1, r2
89         bhi     2b
90         dsb     ishst
91         ret     lr
92 ENDPROC(cpu_v7_dcache_clean_area)
94 #ifdef CONFIG_ARM_PSCI
95         .arch_extension sec
96 ENTRY(cpu_v7_smc_switch_mm)
97         stmfd   sp!, {r0 - r3}
98         movw    r0, #:lower16:ARM_SMCCC_ARCH_WORKAROUND_1
99         movt    r0, #:upper16:ARM_SMCCC_ARCH_WORKAROUND_1
100         smc     #0
101         ldmfd   sp!, {r0 - r3}
102         b       cpu_v7_switch_mm
103 ENDPROC(cpu_v7_smc_switch_mm)
104         .arch_extension virt
105 ENTRY(cpu_v7_hvc_switch_mm)
106         stmfd   sp!, {r0 - r3}
107         movw    r0, #:lower16:ARM_SMCCC_ARCH_WORKAROUND_1
108         movt    r0, #:upper16:ARM_SMCCC_ARCH_WORKAROUND_1
109         hvc     #0
110         ldmfd   sp!, {r0 - r3}
111         b       cpu_v7_switch_mm
112 ENDPROC(cpu_v7_hvc_switch_mm)
113 #endif
114 ENTRY(cpu_v7_iciallu_switch_mm)
115         mov     r3, #0
116         mcr     p15, 0, r3, c7, c5, 0           @ ICIALLU
117         b       cpu_v7_switch_mm
118 ENDPROC(cpu_v7_iciallu_switch_mm)
119 ENTRY(cpu_v7_bpiall_switch_mm)
120         mov     r3, #0
121         mcr     p15, 0, r3, c7, c5, 6           @ flush BTAC/BTB
122         b       cpu_v7_switch_mm
123 ENDPROC(cpu_v7_bpiall_switch_mm)
125         string  cpu_v7_name, "ARMv7 Processor"
126         .align
128 /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
129 .globl  cpu_v7_suspend_size
130 .equ    cpu_v7_suspend_size, 4 * 9
131 #ifdef CONFIG_ARM_CPU_SUSPEND
132 ENTRY(cpu_v7_do_suspend)
133         stmfd   sp!, {r4 - r11, lr}
134         mrc     p15, 0, r4, c13, c0, 0  @ FCSE/PID
135         mrc     p15, 0, r5, c13, c0, 3  @ User r/o thread ID
136         stmia   r0!, {r4 - r5}
137 #ifdef CONFIG_MMU
138         mrc     p15, 0, r6, c3, c0, 0   @ Domain ID
139 #ifdef CONFIG_ARM_LPAE
140         mrrc    p15, 1, r5, r7, c2      @ TTB 1
141 #else
142         mrc     p15, 0, r7, c2, c0, 1   @ TTB 1
143 #endif
144         mrc     p15, 0, r11, c2, c0, 2  @ TTB control register
145 #endif
146         mrc     p15, 0, r8, c1, c0, 0   @ Control register
147         mrc     p15, 0, r9, c1, c0, 1   @ Auxiliary control register
148         mrc     p15, 0, r10, c1, c0, 2  @ Co-processor access control
149         stmia   r0, {r5 - r11}
150         ldmfd   sp!, {r4 - r11, pc}
151 ENDPROC(cpu_v7_do_suspend)
153 ENTRY(cpu_v7_do_resume)
154         mov     ip, #0
155         mcr     p15, 0, ip, c7, c5, 0   @ invalidate I cache
156         mcr     p15, 0, ip, c13, c0, 1  @ set reserved context ID
157         ldmia   r0!, {r4 - r5}
158         mcr     p15, 0, r4, c13, c0, 0  @ FCSE/PID
159         mcr     p15, 0, r5, c13, c0, 3  @ User r/o thread ID
160         ldmia   r0, {r5 - r11}
161 #ifdef CONFIG_MMU
162         mcr     p15, 0, ip, c8, c7, 0   @ invalidate TLBs
163         mcr     p15, 0, r6, c3, c0, 0   @ Domain ID
164 #ifdef CONFIG_ARM_LPAE
165         mcrr    p15, 0, r1, ip, c2      @ TTB 0
166         mcrr    p15, 1, r5, r7, c2      @ TTB 1
167 #else
168         ALT_SMP(orr     r1, r1, #TTB_FLAGS_SMP)
169         ALT_UP(orr      r1, r1, #TTB_FLAGS_UP)
170         mcr     p15, 0, r1, c2, c0, 0   @ TTB 0
171         mcr     p15, 0, r7, c2, c0, 1   @ TTB 1
172 #endif
173         mcr     p15, 0, r11, c2, c0, 2  @ TTB control register
174         ldr     r4, =PRRR               @ PRRR
175         ldr     r5, =NMRR               @ NMRR
176         mcr     p15, 0, r4, c10, c2, 0  @ write PRRR
177         mcr     p15, 0, r5, c10, c2, 1  @ write NMRR
178 #endif  /* CONFIG_MMU */
179         mrc     p15, 0, r4, c1, c0, 1   @ Read Auxiliary control register
180         teq     r4, r9                  @ Is it already set?
181         mcrne   p15, 0, r9, c1, c0, 1   @ No, so write it
182         mcr     p15, 0, r10, c1, c0, 2  @ Co-processor access control
183         isb
184         dsb
185         mov     r0, r8                  @ control register
186         b       cpu_resume_mmu
187 ENDPROC(cpu_v7_do_resume)
188 #endif
190 .globl  cpu_ca9mp_suspend_size
191 .equ    cpu_ca9mp_suspend_size, cpu_v7_suspend_size + 4 * 2
192 #ifdef CONFIG_ARM_CPU_SUSPEND
193 ENTRY(cpu_ca9mp_do_suspend)
194         stmfd   sp!, {r4 - r5}
195         mrc     p15, 0, r4, c15, c0, 1          @ Diagnostic register
196         mrc     p15, 0, r5, c15, c0, 0          @ Power register
197         stmia   r0!, {r4 - r5}
198         ldmfd   sp!, {r4 - r5}
199         b       cpu_v7_do_suspend
200 ENDPROC(cpu_ca9mp_do_suspend)
202 ENTRY(cpu_ca9mp_do_resume)
203         ldmia   r0!, {r4 - r5}
204         mrc     p15, 0, r10, c15, c0, 1         @ Read Diagnostic register
205         teq     r4, r10                         @ Already restored?
206         mcrne   p15, 0, r4, c15, c0, 1          @ No, so restore it
207         mrc     p15, 0, r10, c15, c0, 0         @ Read Power register
208         teq     r5, r10                         @ Already restored?
209         mcrne   p15, 0, r5, c15, c0, 0          @ No, so restore it
210         b       cpu_v7_do_resume
211 ENDPROC(cpu_ca9mp_do_resume)
212 #endif
214 #ifdef CONFIG_CPU_PJ4B
215         globl_equ       cpu_pj4b_switch_mm,     cpu_v7_switch_mm
216         globl_equ       cpu_pj4b_set_pte_ext,   cpu_v7_set_pte_ext
217         globl_equ       cpu_pj4b_proc_init,     cpu_v7_proc_init
218         globl_equ       cpu_pj4b_proc_fin,      cpu_v7_proc_fin
219         globl_equ       cpu_pj4b_reset,         cpu_v7_reset
220 #ifdef CONFIG_PJ4B_ERRATA_4742
221 ENTRY(cpu_pj4b_do_idle)
222         dsb                                     @ WFI may enter a low-power mode
223         wfi
224         dsb                                     @barrier
225         ret     lr
226 ENDPROC(cpu_pj4b_do_idle)
227 #else
228         globl_equ       cpu_pj4b_do_idle,       cpu_v7_do_idle
229 #endif
230         globl_equ       cpu_pj4b_dcache_clean_area,     cpu_v7_dcache_clean_area
231 #ifdef CONFIG_ARM_CPU_SUSPEND
232 ENTRY(cpu_pj4b_do_suspend)
233         stmfd   sp!, {r6 - r10}
234         mrc     p15, 1, r6, c15, c1, 0  @ save CP15 - extra features
235         mrc     p15, 1, r7, c15, c2, 0  @ save CP15 - Aux Func Modes Ctrl 0
236         mrc     p15, 1, r8, c15, c1, 2  @ save CP15 - Aux Debug Modes Ctrl 2
237         mrc     p15, 1, r9, c15, c1, 1  @ save CP15 - Aux Debug Modes Ctrl 1
238         mrc     p15, 0, r10, c9, c14, 0  @ save CP15 - PMC
239         stmia   r0!, {r6 - r10}
240         ldmfd   sp!, {r6 - r10}
241         b cpu_v7_do_suspend
242 ENDPROC(cpu_pj4b_do_suspend)
244 ENTRY(cpu_pj4b_do_resume)
245         ldmia   r0!, {r6 - r10}
246         mcr     p15, 1, r6, c15, c1, 0  @ restore CP15 - extra features
247         mcr     p15, 1, r7, c15, c2, 0  @ restore CP15 - Aux Func Modes Ctrl 0
248         mcr     p15, 1, r8, c15, c1, 2  @ restore CP15 - Aux Debug Modes Ctrl 2
249         mcr     p15, 1, r9, c15, c1, 1  @ restore CP15 - Aux Debug Modes Ctrl 1
250         mcr     p15, 0, r10, c9, c14, 0  @ restore CP15 - PMC
251         b cpu_v7_do_resume
252 ENDPROC(cpu_pj4b_do_resume)
253 #endif
254 .globl  cpu_pj4b_suspend_size
255 .equ    cpu_pj4b_suspend_size, cpu_v7_suspend_size + 4 * 5
257 #endif
260  *      __v7_setup
262  *      Initialise TLB, Caches, and MMU state ready to switch the MMU
263  *      on.  Return in r0 the new CP15 C1 control register setting.
265  *      r1, r2, r4, r5, r9, r13 must be preserved - r13 is not a stack
266  *      r4: TTBR0 (low word)
267  *      r5: TTBR0 (high word if LPAE)
268  *      r8: TTBR1
269  *      r9: Main ID register
271  *      This should be able to cover all ARMv7 cores.
273  *      It is assumed that:
274  *      - cache type register is implemented
275  */
276 __v7_ca5mp_setup:
277 __v7_ca9mp_setup:
278 __v7_cr7mp_setup:
279 __v7_cr8mp_setup:
280         mov     r10, #(1 << 0)                  @ Cache/TLB ops broadcasting
281         b       1f
282 __v7_ca7mp_setup:
283 __v7_ca12mp_setup:
284 __v7_ca15mp_setup:
285 __v7_b15mp_setup:
286 __v7_ca17mp_setup:
287         mov     r10, #0
288 1:      adr     r0, __v7_setup_stack_ptr
289         ldr     r12, [r0]
290         add     r12, r12, r0                    @ the local stack
291         stmia   r12, {r1-r6, lr}                @ v7_invalidate_l1 touches r0-r6
292         bl      v7_invalidate_l1
293         ldmia   r12, {r1-r6, lr}
294 #ifdef CONFIG_SMP
295         orr     r10, r10, #(1 << 6)             @ Enable SMP/nAMP mode
296         ALT_SMP(mrc     p15, 0, r0, c1, c0, 1)
297         ALT_UP(mov      r0, r10)                @ fake it for UP
298         orr     r10, r10, r0                    @ Set required bits
299         teq     r10, r0                         @ Were they already set?
300         mcrne   p15, 0, r10, c1, c0, 1          @ No, update register
301 #endif
302         b       __v7_setup_cont
305  * Errata:
306  *  r0, r10 available for use
307  *  r1, r2, r4, r5, r9, r13: must be preserved
308  *  r3: contains MIDR rX number in bits 23-20
309  *  r6: contains MIDR rXpY as 8-bit XY number
310  *  r9: MIDR
311  */
312 __ca8_errata:
313 #if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)
314         teq     r3, #0x00100000                 @ only present in r1p*
315         mrceq   p15, 0, r0, c1, c0, 1           @ read aux control register
316         orreq   r0, r0, #(1 << 6)               @ set IBE to 1
317         mcreq   p15, 0, r0, c1, c0, 1           @ write aux control register
318 #endif
319 #ifdef CONFIG_ARM_ERRATA_458693
320         teq     r6, #0x20                       @ only present in r2p0
321         mrceq   p15, 0, r0, c1, c0, 1           @ read aux control register
322         orreq   r0, r0, #(1 << 5)               @ set L1NEON to 1
323         orreq   r0, r0, #(1 << 9)               @ set PLDNOP to 1
324         mcreq   p15, 0, r0, c1, c0, 1           @ write aux control register
325 #endif
326 #ifdef CONFIG_ARM_ERRATA_460075
327         teq     r6, #0x20                       @ only present in r2p0
328         mrceq   p15, 1, r0, c9, c0, 2           @ read L2 cache aux ctrl register
329         tsteq   r0, #1 << 22
330         orreq   r0, r0, #(1 << 22)              @ set the Write Allocate disable bit
331         mcreq   p15, 1, r0, c9, c0, 2           @ write the L2 cache aux ctrl register
332 #endif
333         b       __errata_finish
335 __ca9_errata:
336 #ifdef CONFIG_ARM_ERRATA_742230
337         cmp     r6, #0x22                       @ only present up to r2p2
338         mrcle   p15, 0, r0, c15, c0, 1          @ read diagnostic register
339         orrle   r0, r0, #1 << 4                 @ set bit #4
340         mcrle   p15, 0, r0, c15, c0, 1          @ write diagnostic register
341 #endif
342 #ifdef CONFIG_ARM_ERRATA_742231
343         teq     r6, #0x20                       @ present in r2p0
344         teqne   r6, #0x21                       @ present in r2p1
345         teqne   r6, #0x22                       @ present in r2p2
346         mrceq   p15, 0, r0, c15, c0, 1          @ read diagnostic register
347         orreq   r0, r0, #1 << 12                @ set bit #12
348         orreq   r0, r0, #1 << 22                @ set bit #22
349         mcreq   p15, 0, r0, c15, c0, 1          @ write diagnostic register
350 #endif
351 #ifdef CONFIG_ARM_ERRATA_743622
352         teq     r3, #0x00200000                 @ only present in r2p*
353         mrceq   p15, 0, r0, c15, c0, 1          @ read diagnostic register
354         orreq   r0, r0, #1 << 6                 @ set bit #6
355         mcreq   p15, 0, r0, c15, c0, 1          @ write diagnostic register
356 #endif
357 #if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
358         ALT_SMP(cmp r6, #0x30)                  @ present prior to r3p0
359         ALT_UP_B(1f)
360         mrclt   p15, 0, r0, c15, c0, 1          @ read diagnostic register
361         orrlt   r0, r0, #1 << 11                @ set bit #11
362         mcrlt   p15, 0, r0, c15, c0, 1          @ write diagnostic register
364 #endif
365         b       __errata_finish
367 __ca15_errata:
368 #ifdef CONFIG_ARM_ERRATA_773022
369         cmp     r6, #0x4                        @ only present up to r0p4
370         mrcle   p15, 0, r0, c1, c0, 1           @ read aux control register
371         orrle   r0, r0, #1 << 1                 @ disable loop buffer
372         mcrle   p15, 0, r0, c1, c0, 1           @ write aux control register
373 #endif
374         b       __errata_finish
376 __ca12_errata:
377 #ifdef CONFIG_ARM_ERRATA_818325_852422
378         mrc     p15, 0, r10, c15, c0, 1         @ read diagnostic register
379         orr     r10, r10, #1 << 12              @ set bit #12
380         mcr     p15, 0, r10, c15, c0, 1         @ write diagnostic register
381 #endif
382 #ifdef CONFIG_ARM_ERRATA_821420
383         mrc     p15, 0, r10, c15, c0, 2         @ read internal feature reg
384         orr     r10, r10, #1 << 1               @ set bit #1
385         mcr     p15, 0, r10, c15, c0, 2         @ write internal feature reg
386 #endif
387 #ifdef CONFIG_ARM_ERRATA_825619
388         mrc     p15, 0, r10, c15, c0, 1         @ read diagnostic register
389         orr     r10, r10, #1 << 24              @ set bit #24
390         mcr     p15, 0, r10, c15, c0, 1         @ write diagnostic register
391 #endif
392 #ifdef CONFIG_ARM_ERRATA_857271
393         mrc     p15, 0, r10, c15, c0, 1         @ read diagnostic register
394         orr     r10, r10, #3 << 10              @ set bits #10 and #11
395         mcr     p15, 0, r10, c15, c0, 1         @ write diagnostic register
396 #endif
397         b       __errata_finish
399 __ca17_errata:
400 #ifdef CONFIG_ARM_ERRATA_852421
401         cmp     r6, #0x12                       @ only present up to r1p2
402         mrcle   p15, 0, r10, c15, c0, 1         @ read diagnostic register
403         orrle   r10, r10, #1 << 24              @ set bit #24
404         mcrle   p15, 0, r10, c15, c0, 1         @ write diagnostic register
405 #endif
406 #ifdef CONFIG_ARM_ERRATA_852423
407         cmp     r6, #0x12                       @ only present up to r1p2
408         mrcle   p15, 0, r10, c15, c0, 1         @ read diagnostic register
409         orrle   r10, r10, #1 << 12              @ set bit #12
410         mcrle   p15, 0, r10, c15, c0, 1         @ write diagnostic register
411 #endif
412 #ifdef CONFIG_ARM_ERRATA_857272
413         mrc     p15, 0, r10, c15, c0, 1         @ read diagnostic register
414         orr     r10, r10, #3 << 10              @ set bits #10 and #11
415         mcr     p15, 0, r10, c15, c0, 1         @ write diagnostic register
416 #endif
417         b       __errata_finish
419 __v7_pj4b_setup:
420 #ifdef CONFIG_CPU_PJ4B
422 /* Auxiliary Debug Modes Control 1 Register */
423 #define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
424 #define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
425 #define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
427 /* Auxiliary Debug Modes Control 2 Register */
428 #define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */
429 #define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */
430 #define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */
431 #define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */
432 #define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
433 #define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\
434                             PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR)
436 /* Auxiliary Functional Modes Control Register 0 */
437 #define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */
438 #define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
439 #define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */
441 /* Auxiliary Debug Modes Control 0 Register */
442 #define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */
444         /* Auxiliary Debug Modes Control 1 Register */
445         mrc     p15, 1, r0, c15, c1, 1
446         orr     r0, r0, #PJ4B_CLEAN_LINE
447         orr     r0, r0, #PJ4B_INTER_PARITY
448         bic     r0, r0, #PJ4B_STATIC_BP
449         mcr     p15, 1, r0, c15, c1, 1
451         /* Auxiliary Debug Modes Control 2 Register */
452         mrc     p15, 1, r0, c15, c1, 2
453         bic     r0, r0, #PJ4B_FAST_LDR
454         orr     r0, r0, #PJ4B_AUX_DBG_CTRL2
455         mcr     p15, 1, r0, c15, c1, 2
457         /* Auxiliary Functional Modes Control Register 0 */
458         mrc     p15, 1, r0, c15, c2, 0
459 #ifdef CONFIG_SMP
460         orr     r0, r0, #PJ4B_SMP_CFB
461 #endif
462         orr     r0, r0, #PJ4B_L1_PAR_CHK
463         orr     r0, r0, #PJ4B_BROADCAST_CACHE
464         mcr     p15, 1, r0, c15, c2, 0
466         /* Auxiliary Debug Modes Control 0 Register */
467         mrc     p15, 1, r0, c15, c1, 0
468         orr     r0, r0, #PJ4B_WFI_WFE
469         mcr     p15, 1, r0, c15, c1, 0
471 #endif /* CONFIG_CPU_PJ4B */
473 __v7_setup:
474         adr     r0, __v7_setup_stack_ptr
475         ldr     r12, [r0]
476         add     r12, r12, r0                    @ the local stack
477         stmia   r12, {r1-r6, lr}                @ v7_invalidate_l1 touches r0-r6
478         bl      v7_invalidate_l1
479         ldmia   r12, {r1-r6, lr}
481 __v7_setup_cont:
482         and     r0, r9, #0xff000000             @ ARM?
483         teq     r0, #0x41000000
484         bne     __errata_finish
485         and     r3, r9, #0x00f00000             @ variant
486         and     r6, r9, #0x0000000f             @ revision
487         orr     r6, r6, r3, lsr #20-4           @ combine variant and revision
488         ubfx    r0, r9, #4, #12                 @ primary part number
490         /* Cortex-A8 Errata */
491         ldr     r10, =0x00000c08                @ Cortex-A8 primary part number
492         teq     r0, r10
493         beq     __ca8_errata
495         /* Cortex-A9 Errata */
496         ldr     r10, =0x00000c09                @ Cortex-A9 primary part number
497         teq     r0, r10
498         beq     __ca9_errata
500         /* Cortex-A12 Errata */
501         ldr     r10, =0x00000c0d                @ Cortex-A12 primary part number
502         teq     r0, r10
503         beq     __ca12_errata
505         /* Cortex-A17 Errata */
506         ldr     r10, =0x00000c0e                @ Cortex-A17 primary part number
507         teq     r0, r10
508         beq     __ca17_errata
510         /* Cortex-A15 Errata */
511         ldr     r10, =0x00000c0f                @ Cortex-A15 primary part number
512         teq     r0, r10
513         beq     __ca15_errata
515 __errata_finish:
516         mov     r10, #0
517         mcr     p15, 0, r10, c7, c5, 0          @ I+BTB cache invalidate
518 #ifdef CONFIG_MMU
519         mcr     p15, 0, r10, c8, c7, 0          @ invalidate I + D TLBs
520         v7_ttb_setup r10, r4, r5, r8, r3        @ TTBCR, TTBRx setup
521         ldr     r3, =PRRR                       @ PRRR
522         ldr     r6, =NMRR                       @ NMRR
523         mcr     p15, 0, r3, c10, c2, 0          @ write PRRR
524         mcr     p15, 0, r6, c10, c2, 1          @ write NMRR
525 #endif
526         dsb                                     @ Complete invalidations
527 #ifndef CONFIG_ARM_THUMBEE
528         mrc     p15, 0, r0, c0, c1, 0           @ read ID_PFR0 for ThumbEE
529         and     r0, r0, #(0xf << 12)            @ ThumbEE enabled field
530         teq     r0, #(1 << 12)                  @ check if ThumbEE is present
531         bne     1f
532         mov     r3, #0
533         mcr     p14, 6, r3, c1, c0, 0           @ Initialize TEEHBR to 0
534         mrc     p14, 6, r0, c0, c0, 0           @ load TEECR
535         orr     r0, r0, #1                      @ set the 1st bit in order to
536         mcr     p14, 6, r0, c0, c0, 0           @ stop userspace TEEHBR access
538 #endif
539         adr     r3, v7_crval
540         ldmia   r3, {r3, r6}
541  ARM_BE8(orr    r6, r6, #1 << 25)               @ big-endian page tables
542 #ifdef CONFIG_SWP_EMULATE
543         orr     r3, r3, #(1 << 10)              @ set SW bit in "clear"
544         bic     r6, r6, #(1 << 10)              @ clear it in "mmuset"
545 #endif
546         mrc     p15, 0, r0, c1, c0, 0           @ read control register
547         bic     r0, r0, r3                      @ clear bits them
548         orr     r0, r0, r6                      @ set them
549  THUMB( orr     r0, r0, #1 << 30        )       @ Thumb exceptions
550         ret     lr                              @ return to head.S:__ret
552         .align  2
553 __v7_setup_stack_ptr:
554         .word   PHYS_RELATIVE(__v7_setup_stack, .)
555 ENDPROC(__v7_setup)
557         .bss
558         .align  2
559 __v7_setup_stack:
560         .space  4 * 7                           @ 7 registers
562         __INITDATA
564         .weak cpu_v7_bugs_init
566         @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
567         define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_bugs_init
569 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
570         @ generic v7 bpiall on context switch
571         globl_equ       cpu_v7_bpiall_proc_init,        cpu_v7_proc_init
572         globl_equ       cpu_v7_bpiall_proc_fin,         cpu_v7_proc_fin
573         globl_equ       cpu_v7_bpiall_reset,            cpu_v7_reset
574         globl_equ       cpu_v7_bpiall_do_idle,          cpu_v7_do_idle
575         globl_equ       cpu_v7_bpiall_dcache_clean_area, cpu_v7_dcache_clean_area
576         globl_equ       cpu_v7_bpiall_set_pte_ext,      cpu_v7_set_pte_ext
577         globl_equ       cpu_v7_bpiall_suspend_size,     cpu_v7_suspend_size
578 #ifdef CONFIG_ARM_CPU_SUSPEND
579         globl_equ       cpu_v7_bpiall_do_suspend,       cpu_v7_do_suspend
580         globl_equ       cpu_v7_bpiall_do_resume,        cpu_v7_do_resume
581 #endif
582         define_processor_functions v7_bpiall, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_bugs_init
584 #define HARDENED_BPIALL_PROCESSOR_FUNCTIONS v7_bpiall_processor_functions
585 #else
586 #define HARDENED_BPIALL_PROCESSOR_FUNCTIONS v7_processor_functions
587 #endif
589 #ifndef CONFIG_ARM_LPAE
590         @ Cortex-A8 - always needs bpiall switch_mm implementation
591         globl_equ       cpu_ca8_proc_init,      cpu_v7_proc_init
592         globl_equ       cpu_ca8_proc_fin,       cpu_v7_proc_fin
593         globl_equ       cpu_ca8_reset,          cpu_v7_reset
594         globl_equ       cpu_ca8_do_idle,        cpu_v7_do_idle
595         globl_equ       cpu_ca8_dcache_clean_area, cpu_v7_dcache_clean_area
596         globl_equ       cpu_ca8_set_pte_ext,    cpu_v7_set_pte_ext
597         globl_equ       cpu_ca8_switch_mm,      cpu_v7_bpiall_switch_mm
598         globl_equ       cpu_ca8_suspend_size,   cpu_v7_suspend_size
599 #ifdef CONFIG_ARM_CPU_SUSPEND
600         globl_equ       cpu_ca8_do_suspend,     cpu_v7_do_suspend
601         globl_equ       cpu_ca8_do_resume,      cpu_v7_do_resume
602 #endif
603         define_processor_functions ca8, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_ca8_ibe
605         @ Cortex-A9 - needs more registers preserved across suspend/resume
606         @ and bpiall switch_mm for hardening
607         globl_equ       cpu_ca9mp_proc_init,    cpu_v7_proc_init
608         globl_equ       cpu_ca9mp_proc_fin,     cpu_v7_proc_fin
609         globl_equ       cpu_ca9mp_reset,        cpu_v7_reset
610         globl_equ       cpu_ca9mp_do_idle,      cpu_v7_do_idle
611         globl_equ       cpu_ca9mp_dcache_clean_area, cpu_v7_dcache_clean_area
612 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
613         globl_equ       cpu_ca9mp_switch_mm,    cpu_v7_bpiall_switch_mm
614 #else
615         globl_equ       cpu_ca9mp_switch_mm,    cpu_v7_switch_mm
616 #endif
617         globl_equ       cpu_ca9mp_set_pte_ext,  cpu_v7_set_pte_ext
618         define_processor_functions ca9mp, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_bugs_init
619 #endif
621         @ Cortex-A15 - needs iciallu switch_mm for hardening
622         globl_equ       cpu_ca15_proc_init,     cpu_v7_proc_init
623         globl_equ       cpu_ca15_proc_fin,      cpu_v7_proc_fin
624         globl_equ       cpu_ca15_reset,         cpu_v7_reset
625         globl_equ       cpu_ca15_do_idle,       cpu_v7_do_idle
626         globl_equ       cpu_ca15_dcache_clean_area, cpu_v7_dcache_clean_area
627 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
628         globl_equ       cpu_ca15_switch_mm,     cpu_v7_iciallu_switch_mm
629 #else
630         globl_equ       cpu_ca15_switch_mm,     cpu_v7_switch_mm
631 #endif
632         globl_equ       cpu_ca15_set_pte_ext,   cpu_v7_set_pte_ext
633         globl_equ       cpu_ca15_suspend_size,  cpu_v7_suspend_size
634         globl_equ       cpu_ca15_do_suspend,    cpu_v7_do_suspend
635         globl_equ       cpu_ca15_do_resume,     cpu_v7_do_resume
636         define_processor_functions ca15, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_ca15_ibe
637 #ifdef CONFIG_CPU_PJ4B
638         define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
639 #endif
641         .section ".rodata"
643         string  cpu_arch_name, "armv7"
644         string  cpu_elf_name, "v7"
645         .align
647         .section ".proc.info.init", "a"
649         /*
650          * Standard v7 proc info content
651          */
652 .macro __v7_proc name, initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions, cache_fns = v7_cache_fns
653         ALT_SMP(.long   PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
654                         PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
655         ALT_UP(.long    PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
656                         PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
657         .long   PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
658                 PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
659         initfn  \initfunc, \name
660         .long   cpu_arch_name
661         .long   cpu_elf_name
662         .long   HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
663                 HWCAP_EDSP | HWCAP_TLS | \hwcaps
664         .long   cpu_v7_name
665         .long   \proc_fns
666         .long   v7wbi_tlb_fns
667         .long   v6_user_fns
668         .long   \cache_fns
669 .endm
671 #ifndef CONFIG_ARM_LPAE
672         /*
673          * ARM Ltd. Cortex A5 processor.
674          */
675         .type   __v7_ca5mp_proc_info, #object
676 __v7_ca5mp_proc_info:
677         .long   0x410fc050
678         .long   0xff0ffff0
679         __v7_proc __v7_ca5mp_proc_info, __v7_ca5mp_setup
680         .size   __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
682         /*
683          * ARM Ltd. Cortex A9 processor.
684          */
685         .type   __v7_ca9mp_proc_info, #object
686 __v7_ca9mp_proc_info:
687         .long   0x410fc090
688         .long   0xff0ffff0
689         __v7_proc __v7_ca9mp_proc_info, __v7_ca9mp_setup, proc_fns = ca9mp_processor_functions
690         .size   __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
692         /*
693          * ARM Ltd. Cortex A8 processor.
694          */
695         .type   __v7_ca8_proc_info, #object
696 __v7_ca8_proc_info:
697         .long   0x410fc080
698         .long   0xff0ffff0
699         __v7_proc __v7_ca8_proc_info, __v7_setup, proc_fns = ca8_processor_functions
700         .size   __v7_ca8_proc_info, . - __v7_ca8_proc_info
702 #endif  /* CONFIG_ARM_LPAE */
704         /*
705          * Marvell PJ4B processor.
706          */
707 #ifdef CONFIG_CPU_PJ4B
708         .type   __v7_pj4b_proc_info, #object
709 __v7_pj4b_proc_info:
710         .long   0x560f5800
711         .long   0xff0fff00
712         __v7_proc __v7_pj4b_proc_info, __v7_pj4b_setup, proc_fns = pj4b_processor_functions
713         .size   __v7_pj4b_proc_info, . - __v7_pj4b_proc_info
714 #endif
716         /*
717          * ARM Ltd. Cortex R7 processor.
718          */
719         .type   __v7_cr7mp_proc_info, #object
720 __v7_cr7mp_proc_info:
721         .long   0x410fc170
722         .long   0xff0ffff0
723         __v7_proc __v7_cr7mp_proc_info, __v7_cr7mp_setup
724         .size   __v7_cr7mp_proc_info, . - __v7_cr7mp_proc_info
726         /*
727          * ARM Ltd. Cortex R8 processor.
728          */
729         .type   __v7_cr8mp_proc_info, #object
730 __v7_cr8mp_proc_info:
731         .long   0x410fc180
732         .long   0xff0ffff0
733         __v7_proc __v7_cr8mp_proc_info, __v7_cr8mp_setup
734         .size   __v7_cr8mp_proc_info, . - __v7_cr8mp_proc_info
736         /*
737          * ARM Ltd. Cortex A7 processor.
738          */
739         .type   __v7_ca7mp_proc_info, #object
740 __v7_ca7mp_proc_info:
741         .long   0x410fc070
742         .long   0xff0ffff0
743         __v7_proc __v7_ca7mp_proc_info, __v7_ca7mp_setup
744         .size   __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
746         /*
747          * ARM Ltd. Cortex A12 processor.
748          */
749         .type   __v7_ca12mp_proc_info, #object
750 __v7_ca12mp_proc_info:
751         .long   0x410fc0d0
752         .long   0xff0ffff0
753         __v7_proc __v7_ca12mp_proc_info, __v7_ca12mp_setup, proc_fns = HARDENED_BPIALL_PROCESSOR_FUNCTIONS
754         .size   __v7_ca12mp_proc_info, . - __v7_ca12mp_proc_info
756         /*
757          * ARM Ltd. Cortex A15 processor.
758          */
759         .type   __v7_ca15mp_proc_info, #object
760 __v7_ca15mp_proc_info:
761         .long   0x410fc0f0
762         .long   0xff0ffff0
763         __v7_proc __v7_ca15mp_proc_info, __v7_ca15mp_setup, proc_fns = ca15_processor_functions
764         .size   __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
766         /*
767          * Broadcom Corporation Brahma-B15 processor.
768          */
769         .type   __v7_b15mp_proc_info, #object
770 __v7_b15mp_proc_info:
771         .long   0x420f00f0
772         .long   0xff0ffff0
773         __v7_proc __v7_b15mp_proc_info, __v7_b15mp_setup, proc_fns = ca15_processor_functions, cache_fns = b15_cache_fns
774         .size   __v7_b15mp_proc_info, . - __v7_b15mp_proc_info
776         /*
777          * ARM Ltd. Cortex A17 processor.
778          */
779         .type   __v7_ca17mp_proc_info, #object
780 __v7_ca17mp_proc_info:
781         .long   0x410fc0e0
782         .long   0xff0ffff0
783         __v7_proc __v7_ca17mp_proc_info, __v7_ca17mp_setup, proc_fns = HARDENED_BPIALL_PROCESSOR_FUNCTIONS
784         .size   __v7_ca17mp_proc_info, . - __v7_ca17mp_proc_info
786         /* ARM Ltd. Cortex A73 processor */
787         .type   __v7_ca73_proc_info, #object
788 __v7_ca73_proc_info:
789         .long   0x410fd090
790         .long   0xff0ffff0
791         __v7_proc __v7_ca73_proc_info, __v7_setup, proc_fns = HARDENED_BPIALL_PROCESSOR_FUNCTIONS
792         .size   __v7_ca73_proc_info, . - __v7_ca73_proc_info
794         /* ARM Ltd. Cortex A75 processor */
795         .type   __v7_ca75_proc_info, #object
796 __v7_ca75_proc_info:
797         .long   0x410fd0a0
798         .long   0xff0ffff0
799         __v7_proc __v7_ca75_proc_info, __v7_setup, proc_fns = HARDENED_BPIALL_PROCESSOR_FUNCTIONS
800         .size   __v7_ca75_proc_info, . - __v7_ca75_proc_info
802         /*
803          * Qualcomm Inc. Krait processors.
804          */
805         .type   __krait_proc_info, #object
806 __krait_proc_info:
807         .long   0x510f0400              @ Required ID value
808         .long   0xff0ffc00              @ Mask for ID
809         /*
810          * Some Krait processors don't indicate support for SDIV and UDIV
811          * instructions in the ARM instruction set, even though they actually
812          * do support them. They also don't indicate support for fused multiply
813          * instructions even though they actually do support them.
814          */
815         __v7_proc __krait_proc_info, __v7_setup, hwcaps = HWCAP_IDIV | HWCAP_VFPv4
816         .size   __krait_proc_info, . - __krait_proc_info
818         /*
819          * Match any ARMv7 processor core.
820          */
821         .type   __v7_proc_info, #object
822 __v7_proc_info:
823         .long   0x000f0000              @ Required ID value
824         .long   0x000f0000              @ Mask for ID
825         __v7_proc __v7_proc_info, __v7_setup
826         .size   __v7_proc_info, . - __v7_proc_info